drivers/intel/fsp2_0: Add saving MRC data after FSP-S option

When Kconfig SAVE_MRC_AFTER_FSPS is selected, save MRC training
data after FSP-S instead of FSP-M. For now only SPR-SP server
FSP supports this.
This issue surfaces with SPR-SP, because of the memory type
(DDR5 support) and memory capacity (more memory controllers, bigger
DRAM capacity). Therefore Intel decided to save MRC training data after
FSP-S with SPR-SP FSP.

Change-Id: I3bab0c5004e717e842b484c89187e8c0b9c2b3eb
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71950
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/drivers/intel/fsp2_0/Kconfig

@@ -381,4 +381,12 @@ config FSP_ENABLE_SERIAL_DEBUG
 	  coreboot native debug driver when coreboot has integrated the debug FSP
 	  binaries. coreboot disables serial messages when this config is not enabled.
 
+config SAVE_MRC_AFTER_FSPS
+	bool
+	default n
+	depends on XEON_SP_COMMON_BASE
+	help
+	  Save MRC training data after FSP-S. Select this on platforms that generate MRC
+	  cache HOB data as part of FSP-S rather than FSP-M.
+
 endif

src/drivers/intel/fsp2_0/save_mrc_data.c

@@ -43,4 +43,8 @@ static void save_mrc_data(void *unused)
  * Should be done before ramstage_cse_fw_sync() to avoid traning memory twice on
  * a cold boot after a full firmware update.
  */
+#if !CONFIG(SAVE_MRC_AFTER_FSPS)
 BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, save_mrc_data, NULL);
+#elif CONFIG(SAVE_MRC_AFTER_FSPS)
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, save_mrc_data, NULL);
+#endif