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mb/google/dedede: Configure I2C ports

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Enable I2C ports that are used. Add GPIO configuration for the I2C
ports. Enable config items that are required for I2C HID & Generic devices.

BUG=None
TEST=Build the mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I12e974530fb5f61fae5d12cadbb3f928e617d73a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
This commit is contained in:
Karthikeyan Ramasubramanian
2020-02-11 11:53:47 -07:00
committed by Patrick Georgi
parent 95ea799019
commit 55c8702324
3 changed files with 53 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/dedede/Kconfig
View File

@@ -1,5 +1,7 @@
config BOARD_GOOGLE_BASEBOARD_DEDEDE
def_bool n
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID
select DRIVERS_SPI_ACPI
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_BOARDID

40
src/mainboard/google/dedede/variants/baseboard/devicetree.cb
View File

@@ -20,11 +20,11 @@ chip soc/intel/tigerlake
register "pmc_gpe0_dw2" = "GPP_H"
register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
}"
@@ -60,12 +60,32 @@ chip soc/intel/tigerlake
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C0 | Trackpad |
#| I2C1 | Digitizer |
#| I2C2 | Touchscreen |
#| I2C3 | Camera |
#| I2C4 | Audio |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
},
}"
device domain 0 on
@@ -80,16 +100,16 @@ chip soc/intel/tigerlake
device pci 14.2 off end # PMC SRAM
device pci 14.3 off end # CNVi wifi
device pci 14.5 off end # SDCard
device pci 15.0 off end # I2C 0
device pci 15.1 off end # I2C 1
device pci 15.2 off end # I2C 2
device pci 15.3 off end # I2C 3
device pci 15.0 on end # I2C 0
device pci 15.1 on end # I2C 1
device pci 15.2 on end # I2C 2
device pci 15.3 on end # I2C 3
device pci 16.0 off end # HECI 1
device pci 16.1 off end # HECI 2
device pci 16.4 off end # HECI 3
device pci 16.5 off end # HECI 4
device pci 17.0 off end # SATA
device pci 19.0 off end # I2C 4
device pci 19.0 on end # I2C 4
device pci 19.1 off end # I2C 5
device pci 19.2 on end # UART 2
device pci 1a.0 off end # eMMC

21
src/mainboard/google/dedede/variants/baseboard/gpio.c
View File

@@ -33,6 +33,14 @@ static const struct pad_config gpio_table[] = {
/* B18 : H1_SLAVE_SPI_MOSI_R */
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
/* C16 : AP_I2C_TRACKPAD_SDA_3V3 */
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
/* C17 : AP_I2C_TRACKPAD_SCL_3V3 */
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
/* C18 : AP_I2C_EMR_SDA */
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
/* C19 : AP_I2C_EMR_SCL */
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
/* C20 : UART_DBG_TX_AP_RX */
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
/* C21 : UART_AP_TX_DBG_RX */
@@ -41,6 +49,19 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_C22, DN_20K),
/* C23 : UART2_CTS_N */
PAD_NC(GPP_C23, DN_20K),
/* H4 : AP_I2C_TS_SDA */
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
/* H5 : AP_I2C_TS_SCL */
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
/* H6 : AP_I2C_CAM_SDA */
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
/* H7 : AP_I2C_CAM_SCL */
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
/* H8 : AP_I2C_AUDIO_SDA */
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
/* H9 : AP_I2C_AUDIO_SCL */
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
};
/* Early pad configuration in bootblock */