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Allow per-board setting of HT clock and width so

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less than optimal PCB designs can still work reliably
with reduced clock.

Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5179 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Timothy Pearson
2010-03-01 10:30:08 +00:00
committed by Patrick Georgi
parent 72f75b1c8b
commit 55cf7bcbeb
2 changed files with 115 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

44
src/northbridge/amd/amdht/h3finit.c
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@@ -1327,9 +1327,51 @@ void selectOptimalWidthAndFrequency(sMainData *pDat)
for (i = 0; i < pDat->TotalLinks*2; i += 2)
{
cbPCBFreqLimit = 0xFFFF;
#if CONFIG_LIMIT_HT_SPEED_200
cbPCBFreqLimit = 0x0001;
#elif CONFIG_LIMIT_HT_SPEED_300
cbPCBFreqLimit = 0x0003;
#elif CONFIG_LIMIT_HT_SPEED_400
cbPCBFreqLimit = 0x0007;
#elif CONFIG_LIMIT_HT_SPEED_500
cbPCBFreqLimit = 0x000F;
#elif CONFIG_LIMIT_HT_SPEED_600
cbPCBFreqLimit = 0x001F;
#elif CONFIG_LIMIT_HT_SPEED_800
cbPCBFreqLimit = 0x003F;
#elif CONFIG_LIMIT_HT_SPEED_1000
cbPCBFreqLimit = 0x007F;
#elif CONFIG_LIMIT_HT_SPEED_1200
cbPCBFreqLimit = 0x00FF;
#elif CONFIG_LIMIT_HT_SPEED_1400
cbPCBFreqLimit = 0x01FF;
#elif CONFIG_LIMIT_HT_SPEED_1600
cbPCBFreqLimit = 0x03FF;
#elif CONFIG_LIMIT_HT_SPEED_1800
cbPCBFreqLimit = 0x07FF;
#elif CONFIG_LIMIT_HT_SPEED_2000
cbPCBFreqLimit = 0x0FFF;
#elif CONFIG_LIMIT_HT_SPEED_2200
cbPCBFreqLimit = 0x1FFF;
#elif CONFIG_LIMIT_HT_SPEED_2400
cbPCBFreqLimit = 0x3FFF;
#elif CONFIG_LIMIT_HT_SPEED_2600
cbPCBFreqLimit = 0x7FFF;
#else
cbPCBFreqLimit = 0xFFFF; // Maximum allowed by autoconfiguration
#endif
#if CONFIG_LIMIT_HT_DOWN_WIDTH_8
cbPCBABDownstreamWidth = 8;
#else
cbPCBABDownstreamWidth = 16;
#endif
#if CONFIG_LIMIT_HT_UP_WIDTH_8
cbPCBBAUpstreamWidth = 8;
#else
cbPCBBAUpstreamWidth = 16;
#endif
if ( (pDat->PortList[i].Type == PORTLIST_TYPE_CPU) && (pDat->PortList[i+1].Type == PORTLIST_TYPE_CPU))
{