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aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG

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Both SMM_ASEG and SMM_TSEG choices work.

There is periodic TCO timeout occurring.
At least with DEBUG_SMI kernel reports low memory corruption.

Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki
2022-01-18 04:25:48 +02:00
parent 0c745347d0
commit 560c3f5ccf
15 changed files with 240 additions and 76 deletions
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2
src/southbridge/intel/i82801dx/Kconfig
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@@ -3,7 +3,9 @@
config SOUTHBRIDGE_INTEL_I82801DX
bool
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select HAVE_SMI_HANDLER
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SMM
select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_RTC
select SOUTHBRIDGE_INTEL_COMMON_RESET

2
src/southbridge/intel/i82801dx/Makefile.inc
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@@ -15,4 +15,6 @@ ramstage-y += lpc.c
ramstage-y += usb.c
ramstage-y += usb2.c
smm-y += smihandler.c
endif

21
src/southbridge/intel/i82801dx/fadt.c
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@@ -1,20 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/pci_ops.h>
#include <acpi/acpi.h>
#include <version.h>
/* FIXME: This needs to go into a separate .h file
* to be included by the ich7 smi handler, ich7 smi init
* code and the mainboard fadt.
*/
#define APM_CNT 0x0 /* ACPI mode only */
#define CST_CONTROL 0x85
#define PST_CONTROL 0x0
#define ACPI_DISABLE 0xAA
#define ACPI_ENABLE 0x55
#define S4_BIOS 0x77
#define GNVS_UPDATE 0xea
#include <cpu/x86/smm.h>
#include <device/pci_ops.h>
void acpi_fill_fadt(acpi_fadt_t *fadt)
{
@@ -24,9 +12,8 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = ACPI_ENABLE;
fadt->acpi_disable = ACPI_DISABLE;
fadt->pstate_cnt = PST_CONTROL;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
}
fadt->pm1a_evt_blk = pmbase;

4
src/southbridge/intel/i82801dx/i82801dx.h
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@@ -140,8 +140,8 @@ void i82801dx_lpc_setup(void);
#define DEVACT_STS 0x44
#define SS_CNT 0x50
#define TCOBASE 0x60 /* TCO Base Address Register */
#define TCO1_CNT 0x08 /* TCO1 Control Register */
/* TCO1 Control Register */
#define TCO1_CNT 0x68
#define GEN_PMCON_1 0xa0
#define GEN_PMCON_2 0xa2

12
src/southbridge/intel/i82801dx/lpc.c
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@@ -4,6 +4,7 @@
#include <arch/io.h>
#include <arch/ioapic.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
@@ -162,6 +163,15 @@ static void i82801dx_rtc_init(struct device *dev)
pci_write_config8(dev, RTC_CONF, 0x04);
}
static void i82801dx_set_acpi_mode(struct device *dev)
{
if (!acpi_is_wakeup_s3()) {
apm_control(APM_CNT_ACPI_DISABLE);
} else {
apm_control(APM_CNT_ACPI_ENABLE);
}
}
static void i82801dx_lpc_route_dma(struct device *dev, u8 mask)
{
u16 reg16;
@@ -240,6 +250,8 @@ static void lpc_init(struct device *dev)
enable_hpet(dev);
setup_i8259();
i82801dx_set_acpi_mode(dev);
}
static void i82801dx_lpc_read_resources(struct device *dev)

12
src/southbridge/intel/i82801dx/smihandler.c Normal file
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@@ -0,0 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <southbridge/intel/common/pmutil.h>
#include "i82801dx.h"
void southbridge_smi_monitor(void)
{
}
void southbridge_finalize_all(void)
{
}