src/include: Drop unneeded empty lines

Change-Id: Ie325541547ea10946f41a8f979d144a06a7e80eb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Elyes HAOUAS
2020-08-19 21:51:55 +02:00
committed by Patrick Georgi
parent 7c79d8302b
commit 563fc0889f
27 changed files with 0 additions and 39 deletions

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@@ -66,7 +66,6 @@ typedef struct {
u64 rsi;
u64 rdi;
u64 io_mem_addr;
u32 io_misc_info;

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@@ -6,7 +6,6 @@
#include <types.h>
#include <cpu/x86/smm.h>
/* Intel Revision 30101 SMM State-Save Area
* The following processor architectures use this:
* - Westmere
@@ -83,7 +82,6 @@ typedef struct {
u64 rsi;
u64 rdi;
u64 io_mem_addr;
u32 io_misc_info;

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@@ -51,7 +51,6 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_
bool cpu_has_alternative_smrr(void);
#define MSR_PRMRR_PHYS_BASE 0x1f4
#define MSR_PRMRR_PHYS_MASK 0x1f5
#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4

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@@ -18,7 +18,6 @@
*/
#define PMB1_BASE 0x800
/* Speedstep related MSRs */
#define MSR_THERM2_CTL 0x19D
#define MSR_EBC_FREQUENCY_ID 0x2c

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@@ -299,7 +299,6 @@ static inline enum mca_err_code_types mca_err_type(msr_t reg)
return MCA_ERRTYPE_UNKNOWN;
}
/* Helper for setting single MSR bits */
static inline void msr_set_bit(unsigned int reg, unsigned int bit)
{
@@ -318,6 +317,5 @@ static inline void msr_set_bit(unsigned int reg, unsigned int bit)
wrmsr(reg, msr);
}
#endif /* __ASSEMBLER__ */
#endif /* CPU_X86_MSR_H */

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@@ -27,7 +27,6 @@
#define MTRR_DEF_TYPE_EN (1 << 11)
#define MTRR_DEF_TYPE_FIX_EN (1 << 10)
#define IA32_SMRR_PHYS_BASE 0x1f2
#define IA32_SMRR_PHYS_MASK 0x1f3
#define SMRR_PHYS_MASK_LOCK (1 << 10)

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@@ -3,7 +3,6 @@
#include <console/post_codes.h>
#if CONFIG(POST_IO)
#define post_code(value) \
movb $value, %al; \