src/include: Drop unneeded empty lines
Change-Id: Ie325541547ea10946f41a8f979d144a06a7e80eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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committed by
Patrick Georgi
parent
7c79d8302b
commit
563fc0889f
@@ -66,7 +66,6 @@ typedef struct {
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u64 rsi;
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u64 rdi;
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u64 io_mem_addr;
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u32 io_misc_info;
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@@ -6,7 +6,6 @@
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#include <types.h>
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#include <cpu/x86/smm.h>
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/* Intel Revision 30101 SMM State-Save Area
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* The following processor architectures use this:
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* - Westmere
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@@ -83,7 +82,6 @@ typedef struct {
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u64 rsi;
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u64 rdi;
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u64 io_mem_addr;
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u32 io_misc_info;
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@@ -51,7 +51,6 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_
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bool cpu_has_alternative_smrr(void);
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#define MSR_PRMRR_PHYS_BASE 0x1f4
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#define MSR_PRMRR_PHYS_MASK 0x1f5
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#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4
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@@ -18,7 +18,6 @@
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*/
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#define PMB1_BASE 0x800
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/* Speedstep related MSRs */
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#define MSR_THERM2_CTL 0x19D
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#define MSR_EBC_FREQUENCY_ID 0x2c
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@@ -299,7 +299,6 @@ static inline enum mca_err_code_types mca_err_type(msr_t reg)
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return MCA_ERRTYPE_UNKNOWN;
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}
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/* Helper for setting single MSR bits */
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static inline void msr_set_bit(unsigned int reg, unsigned int bit)
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{
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@@ -318,6 +317,5 @@ static inline void msr_set_bit(unsigned int reg, unsigned int bit)
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wrmsr(reg, msr);
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}
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#endif /* __ASSEMBLER__ */
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#endif /* CPU_X86_MSR_H */
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@@ -27,7 +27,6 @@
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#define MTRR_DEF_TYPE_EN (1 << 11)
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#define MTRR_DEF_TYPE_FIX_EN (1 << 10)
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#define IA32_SMRR_PHYS_BASE 0x1f2
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#define IA32_SMRR_PHYS_MASK 0x1f3
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#define SMRR_PHYS_MASK_LOCK (1 << 10)
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@@ -3,7 +3,6 @@
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#include <console/post_codes.h>
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#if CONFIG(POST_IO)
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#define post_code(value) \
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movb $value, %al; \
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