soc/amd: Do SMM relocation via MSR

AMD CPUs have a convenient MSR that allows to set the SMBASE in the save
state without ever entering SMM (e.g. at the default 0x30000 address).
This has been a feature in all AMD CPUs since at least AMD K8. This
allows to do relocation in parallel in ramstage and without setting up a
relocation handler, which likely results in a speedup. The more cores
the higher the speedup as relocation was happening sequentially. On a 4
core AMD picasso system this results in 33ms boot speedup.

TESTED on google/vilboz (Picasso) with CONFIG_SMI_DEBUG: verify that SMM
is correctly relocated with the BSP correctly entering the smihandler.

Change-Id: I9729fb94ed5c18cfd57b8098c838c08a04490e4b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/include/cpu/x86/mp.h

@@ -57,6 +57,9 @@ struct mp_ops {
 	/*
 	 * Optional function to use to trigger SMM to perform relocation. If
 	 * not provided, smm_initiate_relocation() is used.
+	 * This function is called on each CPU.
+	 * On platforms that select CONFIG(X86_SMM_SKIP_RELOCATION_HANDLER) to
+	 * not relocate in SMM, this function can be used to relocate CPUs.
 	 */
 	void (*per_cpu_smm_trigger)(void);
 	/*
@@ -66,6 +69,7 @@ struct mp_ops {
 	 * running the relocation handler, current SMBASE of relocation handler,
 	 * and the pre-calculated staggered CPU SMBASE address of the permanent
 	 * SMM handler.
+	 * This function is only called with !CONFIG(X86_SMM_SKIP_RELOCATION_HANDLER) set.
 	 */
 	void (*relocation_handler)(int cpu, uintptr_t curr_smbase,
 		uintptr_t staggered_smbase);