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haswell/lynxpoint: Add native DMI init

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Implement native DMI init for Haswell and Lynx Point. This is only
needed on non-ULT platforms, and only when MRC.bin is not used.

TEST=Verify DMI initialises correctly on Asrock B85M Pro4.

Change-Id: I5fb1a2adc4ffbf0ebbf0d2d3a444055c53765faa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons
2022-05-06 21:56:48 +02:00
committed by Felix Held
parent b739fd287d
commit 567ece44ea
10 changed files with 480 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/southbridge/intel/lynxpoint/Makefile.inc
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@@ -35,6 +35,8 @@ bootblock-y += early_pch.c
romstage-y += early_usb.c early_me.c me_status.c early_pch.c
romstage-y += pmutil.c
romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c
ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
romstage-y += lp_gpio.c
ramstage-y += lp_gpio.c

52
src/southbridge/intel/lynxpoint/early_pch_native.c Normal file
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@@ -0,0 +1,52 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <console/console.h>
#include <device/pci_ops.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <types.h>
void pch_dmi_setup_physical_layer(void)
{
/** FIXME: We need to make sure the SA supports Gen2 as well **/
if ((RCBA32(0x21a4) & 0x0f) == 0x02) {
/* Set Gen 2 Common Clock N_FTS */
RCBA32_AND_OR(0x2340, ~0x00ff0000, 0x3a << 16);
/* Set Target Link Speed to DMI Gen2 */
RCBA8_AND_OR(DLCTL2, ~0x07, 0x02);
}
}
#define VC_ACTIVE (1U << 31)
#define VCNEGPND (1 << 1)
void pch_dmi_tc_vc_mapping(const u32 vc0, const u32 vc1, const u32 vcp, const u32 vcm)
{
printk(BIOS_DEBUG, "Programming PCH DMI VC/TC mappings...\n");
RCBA32_AND_OR(CIR0050, ~(0xf << 20), 2 << 20);
if (vcp & VC_ACTIVE)
RCBA32_OR(CIR0050, 1 << 19 | 1 << 17);
RCBA32(CIR0050); /* Ensure posted write hits */
/* Use the same virtual channel mapping on both ends of the DMI link */
RCBA32(V0CTL) = vc0;
RCBA32(V1CTL) = vc1;
RCBA32(V1CTL); /* Ensure posted write hits */
RCBA32(VPCTL) = vcp;
RCBA32(VPCTL); /* Ensure posted write hits */
RCBA32(VMCTL) = vcm;
/* Lock the registers */
RCBA32_OR(CIR0050, 1U << 31);
RCBA32(CIR0050); /* Ensure posted write hits */
printk(BIOS_DEBUG, "Waiting for PCH DMI VC negotiation... ");
do {} while (RCBA16(V0STS) & VCNEGPND);
do {} while (RCBA16(V1STS) & VCNEGPND);
do {} while (RCBA16(VPSTS) & VCNEGPND);
do {} while (RCBA16(VMSTS) & VCNEGPND);
printk(BIOS_DEBUG, "done!\n");
}

20
src/southbridge/intel/lynxpoint/pch.h
View File

@@ -112,6 +112,9 @@ enum pch_platform_type {
PCH_TYPE_ULT = 5,
};
void pch_dmi_setup_physical_layer(void);
void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm);
void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
void usb_ehci_disable(pci_devfn_t dev);
void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
@@ -405,9 +408,10 @@ void mainboard_config_rcba(void);
/* Southbridge IO BARs */
#define PMBASE 0x40
#define GPIOBASE 0x48
#define PMBASE 0x40
#define CIR0050 0x0050 /* 32bit */
#define RPC 0x0400 /* 32bit */
#define RPFN 0x0404 /* 32bit */
@@ -430,6 +434,20 @@ void mainboard_config_rcba(void);
#define IOTR2 0x1e90 /* 64bit */
#define IOTR3 0x1e98 /* 64bit */
#define V0CTL 0x2014 /* 32bit */
#define V0STS 0x201a /* 16bit */
#define V1CTL 0x2020 /* 32bit */
#define V1STS 0x2026 /* 16bit */
#define VPCTL 0x2030 /* 32bit */
#define VPSTS 0x2038 /* 16bit */
#define VMCTL 0x2040 /* 32bit */
#define VMSTS 0x2048 /* 16bit */
#define DLCTL2 0x21b0
#define TCTL 0x3000 /* 8bit */
#define NOINT 0