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cpu/armltd/cortex-a9: Remove stub func dead code

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Change-Id: Ia8246e2bdf346883072a924d8808f14f48d44bb3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7351
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This commit is contained in:
Edward O'Callaghan
2014-11-07 13:27:29 +11:00
committed by Stefan Reinauer
parent 6c90f3334e
commit 569bd3ff60
3 changed files with 1 additions and 53 deletions
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9
src/arch/arm/include/armv7.h
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@@ -66,11 +66,4 @@
#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))
#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))
void v7_outer_cache_enable(void);
void v7_outer_cache_disable(void);
void v7_outer_cache_flush_all(void);
void v7_outer_cache_inval_all(void);
void v7_outer_cache_flush_range(u32 start, u32 end);
void v7_outer_cache_inval_range(u32 start, u32 end);
#endif
#endif /* ARMV7_H */

3
src/cpu/armltd/cortex-a9/Makefile.inc
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@@ -1,3 +0,0 @@
ramstage-y += cache.c
romstage-y += cache.c
bootblock-y += cache.c

42
src/cpu/armltd/cortex-a9/cache.c
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@@ -1,42 +0,0 @@
/*
* Copyright (C) 2013 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <armv7.h>
/*
* Sets L2 cache related parameters before enabling data cache
*/
void v7_outer_cache_enable(void)
{
}
/* stubs so we don't need weak symbols in cache_v7.c */
void v7_outer_cache_disable(void)
{
}
void v7_outer_cache_flush_all(void)
{
}
void v7_outer_cache_inval_all(void)
{
}
void v7_outer_cache_flush_range(u32 start, u32 end)
{
}
void v7_outer_cache_inval_range(u32 start, u32 end)
{
}