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Intel 82371EB: Some code simplifications (trivial).

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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
2007-06-03 16:57:27 +00:00
parent f027280d39
commit 56a9125453
4 changed files with 5 additions and 18 deletions
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1
src/southbridge/intel/i82371eb/i82371eb.h
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@@ -26,7 +26,6 @@
void i82371eb_enable(device_t dev); void i82371eb_enable(device_t dev);
#endif #endif
#define PCICMD 0x04 /* PCI Command Register */
#define XBCS 0x4e /* X-Bus Chip Select register */ #define XBCS 0x4e /* X-Bus Chip Select register */
/* SMBus */ /* SMBus */

4
src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
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@@ -49,9 +49,9 @@ static void enable_smbus(void)
pci_write_config8(dev, SMBHSTCFG, reg8); pci_write_config8(dev, SMBHSTCFG, reg8);
/* Enable access to the SMBus I/O space. */ /* Enable access to the SMBus I/O space. */
reg16 = pci_read_config16(dev, PCICMD); reg16 = pci_read_config16(dev, PCI_COMMAND);
reg16 |= IOSE; reg16 |= IOSE;
pci_write_config16(dev, PCICMD, reg16); pci_write_config16(dev, PCI_COMMAND, reg16);
/* Clear any lingering errors, so the transaction will run. */ /* Clear any lingering errors, so the transaction will run. */
outb(inb(SMBUS_IO_BASE + SMBHST_STATUS), SMBUS_IO_BASE + SMBHST_STATUS); outb(inb(SMBUS_IO_BASE + SMBHST_STATUS), SMBUS_IO_BASE + SMBHST_STATUS);

11
src/southbridge/intel/i82371eb/i82371eb_ide.c
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@@ -35,9 +35,7 @@
static void ide_init(struct device *dev) static void ide_init(struct device *dev)
{ {
uint16_t reg; uint16_t reg;
struct southbridge_intel_i82371eb_config *conf; struct southbridge_intel_i82371eb_config *conf = dev->chip_info;
conf = dev->chip_info;
/* Enable/disable the primary IDE interface. */ /* Enable/disable the primary IDE interface. */
reg = pci_read_config16(dev, IDETIM_PRI); reg = pci_read_config16(dev, IDETIM_PRI);
@@ -62,18 +60,13 @@ static void ide_init(struct device *dev)
pci_write_config16(dev, IDETIM_SEC, reg); pci_write_config16(dev, IDETIM_SEC, reg);
} }
/* There are no subsystem IDs on the Intel 82371EB. */
static struct pci_operations lops_pci = {
// .set_subsystem = 0,
};
static struct device_operations ide_ops = { static struct device_operations ide_ops = {
.read_resources = pci_dev_read_resources, .read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources, .enable_resources = pci_dev_enable_resources,
.init = ide_init, .init = ide_init,
.scan_bus = 0, .scan_bus = 0,
.ops_pci = &lops_pci, .ops_pci = 0, /* No subsystem IDs on 82371EB! */
}; };
static struct pci_driver ide_driver __pci_driver = { static struct pci_driver ide_driver __pci_driver = {

7
src/southbridge/intel/i82371eb/i82371eb_smbus.c
View File

@@ -27,11 +27,6 @@
static struct smbus_bus_operations lops_smbus_bus = { static struct smbus_bus_operations lops_smbus_bus = {
}; };
/* There are no subsystem IDs on the Intel 82371EB. */
static struct pci_operations lops_pci = {
// .set_subsystem = 0,
};
static struct device_operations smbus_ops = { static struct device_operations smbus_ops = {
.read_resources = pci_dev_read_resources, .read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
@@ -39,7 +34,7 @@ static struct device_operations smbus_ops = {
.init = 0, .init = 0,
.scan_bus = scan_static_bus, .scan_bus = scan_static_bus,
// .enable = i82371eb_enable, // TODO: Needed? // .enable = i82371eb_enable, // TODO: Needed?
.ops_pci = &lops_pci, .ops_pci = 0, /* No subsystem IDs on 82371EB! */
.ops_smbus_bus = &lops_smbus_bus, .ops_smbus_bus = &lops_smbus_bus,
}; };