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soc/intel/skylake: Use common cpu/intel/car romstage code

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Setting up the console and entering postcar can be done in a common
place.

Change-Id: I8a8db0fcb4f0fbbb121a8195a8a8b6644c28db07
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32962
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
2019-05-23 15:07:49 +02:00
committed by Patrick Georgi
parent 73ac12196c
commit 56e2d7d21a
4 changed files with 6 additions and 52 deletions
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2
src/soc/intel/skylake/romstage/Makefile.inc
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@@ -1,4 +1,4 @@
romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += car_stage.S
romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += ../../../../cpu/intel/car/romstage.c
romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c
romstage-y += systemagent.c

41
src/soc/intel/skylake/romstage/car_stage.S
View File

@@ -1,41 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cpu/x86/post_code.h>
/* I/O delay between post codes on failure */
#define LHLT_DELAY 0x50000
.text
.global car_stage_entry
car_stage_entry:
call romstage_c_entry
/* we don't return here */
movb $0x69, %ah
jmp .Lhlt
.Lhlt:
xchg %al, %ah
#if CONFIG(POST_IO)
outb %al, $CONFIG_POST_IO_PORT
#else
post_code(POST_DEAD_CODE)
#endif
movl $LHLT_DELAY, %ecx
.Lhlt_Delay:
outb %al, $0xED
loop .Lhlt_Delay
jmp .Lhlt