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soc/intel/cnl: switch to PMC/IPC for HECI disable on SOC_INTEL_COMETLAKE

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Commit d6dbd933 [soc/intel/cannonlake: Use SBI msg to disable HECI1]

switched CNL-based mainboards from using FSP for HECI disablement to SBI
msg, but this causes google/hatch to hang when attempting to unhide p2sb
as part of disabling HECI1 via SBI during SMM, so switch to using
PMC/IPC method. SOC_INTEL_WHISKEYLAKE and SOC_INTEL_COFFEELAKE do not
support PMC disablement method, so they remain using SBI.

Test: build/boot google/hatch, verify HECI1 disabled via console log and
lspci in booted OS.

Change-Id: I06f0eb312b579af4a0fe826403374dcd99689d21
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Matt DeVillier
2022-02-10 17:01:35 -06:00
committed by Felix Held
parent 148b545671
commit 575a2e589d
3 changed files with 11 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
src/soc/intel/cannonlake/Kconfig
View File

@@ -5,15 +5,17 @@ config SOC_INTEL_COFFEELAKE
bool bool
select SOC_INTEL_CANNONLAKE_BASE select SOC_INTEL_CANNONLAKE_BASE
select FSP_USES_CB_STACK select FSP_USES_CB_STACK
select HAVE_INTEL_FSP_REPO
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
select HAVE_EXP_X86_64_SUPPORT select HAVE_EXP_X86_64_SUPPORT
select HAVE_INTEL_FSP_REPO
select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
config SOC_INTEL_WHISKEYLAKE config SOC_INTEL_WHISKEYLAKE
bool bool
select SOC_INTEL_CANNONLAKE_BASE select SOC_INTEL_CANNONLAKE_BASE
select FSP_USES_CB_STACK select FSP_USES_CB_STACK
select HAVE_INTEL_FSP_REPO select HAVE_INTEL_FSP_REPO
select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
config SOC_INTEL_COMETLAKE config SOC_INTEL_COMETLAKE
@@ -21,7 +23,9 @@ config SOC_INTEL_COMETLAKE
select SOC_INTEL_CANNONLAKE_BASE select SOC_INTEL_CANNONLAKE_BASE
select FSP_USES_CB_STACK select FSP_USES_CB_STACK
select HAVE_INTEL_FSP_REPO select HAVE_INTEL_FSP_REPO
select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT
config SOC_INTEL_COMETLAKE_1 config SOC_INTEL_COMETLAKE_1
bool bool
@@ -109,7 +113,6 @@ config CPU_SPECIFIC_OPTIONS
config DISABLE_HECI1_AT_PRE_BOOT config DISABLE_HECI1_AT_PRE_BOOT
default y if MAINBOARD_HAS_CHROMEOS default y if MAINBOARD_HAS_CHROMEOS
select HECI_DISABLE_USING_SMM
config MAX_CPUS config MAX_CPUS
int int

4
src/soc/intel/cannonlake/finalize.c
View File

@@ -7,6 +7,7 @@
#include <device/mmio.h> #include <device/mmio.h>
#include <device/pci.h> #include <device/pci.h>
#include <intelblocks/cpulib.h> #include <intelblocks/cpulib.h>
#include <intelblocks/cse.h>
#include <intelblocks/lpc_lib.h> #include <intelblocks/lpc_lib.h>
#include <intelblocks/pcr.h> #include <intelblocks/pcr.h>
#include <intelblocks/pmclib.h> #include <intelblocks/pmclib.h>
@@ -95,6 +96,9 @@ static void soc_finalize(void *unused)
pch_finalize(); pch_finalize();
apm_control(APM_CNT_FINALIZE); apm_control(APM_CNT_FINALIZE);
sa_finalize(); sa_finalize();
if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) &&
CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC))
heci1_disable();
/* Indicate finalize step with post code */ /* Indicate finalize step with post code */
post_code(POST_OS_BOOT); post_code(POST_OS_BOOT);

2
src/soc/intel/cannonlake/smihandler.c
View File

@@ -16,7 +16,7 @@
*/ */
void smihandler_soc_at_finalize(void) void smihandler_soc_at_finalize(void)
{ {
if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM))
heci1_disable(); heci1_disable();
} }