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sb/amd/sb800: Drop support

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Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which platforms using this code lack.

Change-Id: I1c25837f1ba05ecd58309b63a471001f4aee2fff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36968
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
2019-11-19 17:23:34 +01:00
committed by Kyösti Mälkki
parent 334699d205
commit 57803ba3f5
22 changed files with 0 additions and 3394 deletions
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35
src/cpu/amd/family_10h-family_15h/init_cpus.c
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@@ -30,10 +30,6 @@
#include <southbridge/amd/common/reset.h>
#if CONFIG(SOUTHBRIDGE_AMD_SB800)
#include <southbridge/amd/sb800/sb800.h>
#endif
#include "cpu/amd/car/disable_cache_as_ram.c"
#if CONFIG(PCI_IO_CFG_EXT)
@@ -1041,37 +1037,6 @@ void cpuSetAMDMSR(uint8_t node_id)
}
}
#if CONFIG(SOUTHBRIDGE_AMD_SB800)
if (revision & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) {
/* Set up message triggered C1E */
msr = rdmsr(MSR_INTPEND);
msr.lo &= ~0xffff; /* IOMsgAddr = ACPI_PM_EVT_BLK */
msr.lo |= ACPI_PM_EVT_BLK & 0xffff;
msr.lo |= (0x1 << 29); /* BmStsClrOnHltEn = 1 */
if (revision & AMD_DR_GT_D0) {
msr.lo &= ~(0x1 << 28); /* C1eOnCmpHalt = 0 */
msr.lo &= ~(0x1 << 27); /* SmiOnCmpHalt = 0 */
}
wrmsr(MSR_INTPEND, msr);
msr = rdmsr(HWCR_MSR);
msr.lo |= (0x1 << 12); /* HltXSpCycEn = 1 */
wrmsr(HWCR_MSR, msr);
}
if (revision & (AMD_DR_Ex | AMD_FAM15_ALL)) {
if (CONFIG(HAVE_ACPI_TABLES))
if ((get_option(&nvram, "cpu_c_states") == CB_SUCCESS) &&
(nvram)) {
/* Set up the C-state base address */
msr_t c_state_addr_msr;
c_state_addr_msr = rdmsr(MSR_CSTATE_ADDRESS);
c_state_addr_msr.lo = ACPI_CPU_P_LVL2;
wrmsr(MSR_CSTATE_ADDRESS, c_state_addr_msr);
}
}
#endif
if (revision & AMD_FAM15_ALL) {
enable_cpb = 1;
if (get_option(&nvram, "cpu_core_boost") == CB_SUCCESS)