From 5783ad7a658fbb575a88c2414e9395f8f1d1e39a Mon Sep 17 00:00:00 2001
From: Tim Crawford <tcrawford@system76.com>
Date: Thu, 5 May 2022 11:51:11 -0600
Subject: [PATCH] mb/system76: TGL-U: Disable AER for CPU PCIe RP

Fixes suspend with certain SSDs installed in the PCIe 4 slot.

Change-Id: Ib91b154963aeafe96c8118cbab89f0e70634e8bc
Signed-off-by: Tim Crawford <tcrawford@system76.com>
---
 src/mainboard/system76/galp5/ramstage.c  | 8 +++-----
 src/mainboard/system76/lemp10/ramstage.c | 8 +++-----
 2 files changed, 6 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/system76/galp5/ramstage.c b/src/mainboard/system76/galp5/ramstage.c
index dec2a89ee4..155c097c4c 100644
--- a/src/mainboard/system76/galp5/ramstage.c
+++ b/src/mainboard/system76/galp5/ramstage.c
@@ -3,11 +3,9 @@
 #include <soc/ramstage.h>
 #include "gpio.h"
 
-static void mainboard_init(void *chip_info)
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 {
+	params->CpuPcieRpAdvancedErrorReporting[0] = 0;
+
 	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 }
-
-struct chip_operations mainboard_ops = {
-	.init = mainboard_init,
-};
diff --git a/src/mainboard/system76/lemp10/ramstage.c b/src/mainboard/system76/lemp10/ramstage.c
index a3b12bb1f2..d48b65d959 100644
--- a/src/mainboard/system76/lemp10/ramstage.c
+++ b/src/mainboard/system76/lemp10/ramstage.c
@@ -3,11 +3,9 @@
 #include <mainboard/gpio.h>
 #include <soc/ramstage.h>
 
-static void mainboard_init(void *chip_info)
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 {
+	params->CpuPcieRpAdvancedErrorReporting[0] = 0;
+
 	mainboard_configure_gpios();
 }
-
-struct chip_operations mainboard_ops = {
-	.init = mainboard_init,
-};