diff --git a/.editorconfig b/.editorconfig new file mode 100644 index 0000000000..eb44fcd7e4 --- /dev/null +++ b/.editorconfig @@ -0,0 +1,11 @@ +# EditorConfig: https://EditorConfig.org + +root = true + +[*] +indent_style = tab +tab_width = 8 +charset = utf-8 +insert_final_newline = true +end_of_line = lf +trim_trailing_whitespace = true diff --git a/.gitmodules b/.gitmodules index a656998655..77c74777f6 100644 --- a/.gitmodules +++ b/.gitmodules @@ -34,3 +34,6 @@ url = https://github.com/coreboot/intel-microcode.git update = none ignore = dirty +[submodule "3rdparty/ffs"] + path = 3rdparty/ffs + url = https://github.com/coreboot/ffs.git diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index 693e278e30..42cdeb9308 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit 693e278e308441d716f7f5116c43aa150955da31 +Subproject commit 42cdeb93080f2b54a75be14e4f5ee776872f3f0f diff --git a/3rdparty/chromeec b/3rdparty/chromeec index 11bd4c0f4d..860fe2962d 160000 --- a/3rdparty/chromeec +++ b/3rdparty/chromeec @@ -1 +1 @@ -Subproject commit 11bd4c0f4d11357ab830982d7dec164813c886dd +Subproject commit 860fe2962d40ee901369d1dc67f4aa7a7a42ba4d diff --git a/3rdparty/ffs b/3rdparty/ffs new file mode 160000 index 0000000000..3ec70fbc45 --- /dev/null +++ b/3rdparty/ffs @@ -0,0 +1 @@ +Subproject commit 3ec70fbc458e32eef0d0b1de79688b4dc48cbd57 diff --git a/3rdparty/vboot b/3rdparty/vboot index 9c90611097..e6700f4c70 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 9c906110972f538ee5753845916ebd1f826f54b6 +Subproject commit e6700f4c70fe72850ae4f3f5df19c9281ebcefc8 diff --git a/AUTHORS b/AUTHORS index c5fec189ab..72521a1043 100644 --- a/AUTHORS +++ b/AUTHORS @@ -2,13 +2,100 @@ # # This does not necessarily list everyone who has contributed code, since in # some cases, their employer may be the copyright holder. To see the full list -# of contributors, see the revision history in source control. -# git log --pretty=format:%an | sort | uniq -# +# of contributors, and their email addresses, see the revision history in source +# control. +# Run the below commands in the coreboot repo for additional information. +# To see a list of contributors: git log --pretty=format:%an | sort | uniq +# For patches adding or removing a name: git log -i -S "NAME" --source --all +9elements Agency GmbH +Advanced Micro Devices, Inc. +Alex Züpke Alexander Couzens +Alexandru Gagniuc +Andy Fleming +ARM Limited and Contributors +Arthur Heymans +Carl-Daniel Hailfinger +coresystems GmbH +Damien Zammit +David Hendricks +David Mosberger-Tang +Denis Dowling +DENX Software Engineering +DMP Electronics Inc. +Drew Eckhardt +Egbert Eich +Eric Biederman +Eswar Nallusamy +Facebook, Inc. +Felix Held +Frederic Potter +Free Software Foundation, Inc. +Freescale Semiconductor, Inc. +Gary Jennejohn +Gerd Hoffmann +Google LLC +Greg Watson +Imagination Technologies +Intel Corporation +Jason Zhao +Jordan Crouse +Joseph Smith +Keith Hui +Kshitij +Kyösti Mälkki +Lei Wen +Li-Ta Lo +Libra Li +Linus Torvalds +Linux Networx, Inc. +Marc Jones +Marek Vasut +Marius Gröger +Martin Mares +Marvell Semiconductor Inc. +MediaTek Inc. +MontaVista Software, Inc. +Myles Watson +Nicholas Sielicki +Nick Barker +Nico Huber +Patrick Georgi +Patrick Rudolph +PC Engines GmbH +Per Odlund +Peter Stuge +Raptor Engineering, LLC +Richard Woodruff +Ronald G. Minnich +Rudolf Marek +Russell King +Sage Electronic Engineering, LLC +SciTech Software, Inc. +secunet Security Networks AG +Siemens AG +Silicon Integrated System Corporation +Stefan Reinauer +Steve Magnani +SUSE LINUX AG +Sven Schnelle +Syed Mohammed Khasim +Texas Instruments +The Linux Foundation +Timothy Pearson +Tyan Computer Corp. +Uwe Hermann +VIA Technologies, Inc +Wolfgang Denk +Yinghai Lu # Directories transferred src/acpi +src/arch +src/commonlib +src/console +src/cpu +src/device diff --git a/Documentation/acpi/devicetree.md b/Documentation/acpi/devicetree.md new file mode 100644 index 0000000000..556c9668f6 --- /dev/null +++ b/Documentation/acpi/devicetree.md @@ -0,0 +1,234 @@ +# Adding new devices to a device tree + +## Introduction + +ACPI exposes a platform-independent interface for operating systems to perform +power management and other platform-level functions. Some operating systems +also use ACPI to enumerate devices that are not immediately discoverable, such +as those behind I2C or SPI busses (in contrast to PCI). This document discusses +the way that coreboot uses the concept of a "device tree" to generate ACPI +tables for usage by the operating system. + +## Devicetree and overridetree (if applicable) + +For mainboards that are organized around a "reference board" or "baseboard" +model (see ``src/mainboard/google/octopus`` or ``hatch`` for examples), there is +typically a devicetree.cb file that all boards share, and any differences for a +specific board ("variant") are captured in the overridetree.cb file. Any +settings changed in the overridetree take precedence over those in the main +devicetree. Note, not all mainboards will have the devicetree/overridetree +distinction, and may only have a devicetree.cb file. Or you can always just +write the ASL (ACPI Source Language) code yourself. + +## Device drivers + +Let's take a look at an example entry from +``src/mainboard/google/hatch/variant/hatch/overridetree.cb``: + +``` +device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "wake" = "GPE0_DW0_21" + device i2c 15 on end + end +end # I2C #0 +``` + +When this entry is processed during ramstage, it will create a device in the +ACPI SSDT table (all devices in devicetrees end up in the SSDT table). The ACPI +generation routines in coreboot actually generate the raw bytecode that +represents the device's structure, but looking at ASL code is easier to +understand; see below for what the disassembled bytecode looks like: + +``` +Scope (\_SB.PCI0.I2C0) +{ + Device (D015) + { + Name (_HID, "ELAN0000") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_DDN, "ELAN Touchpad") // _DDN: DOS Device Name + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + I2cSerialBusV2 (0x0015, ControllerInitiated, 400000, + AddressingMode7Bit, "\\_SB.PCI0.I2C0", + 0x00, ResourceConsumer, , Exclusive, ) + Interrupt (ResourceConsumer, Edge, ActiveLow, ExclusiveAndWake, ,, ) + { + 0x0000002D, + } + }) + Name (_S0W, 0x04) // _S0W: S0 Device Wake State + Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake + { + 0x15, // GPE #21 + 0x03 // Sleep state S3 + }) + } +} +``` + +You can see it generates _HID, _UID, _DDN, _STA, _CRS, _S0W, and _PRW +names/methods in the Device's scope. + +## Utilizing a device driver + +The device driver must be enabled for your build. There will be a CONFIG option +in the Kconfig file in the directory that the driver is in (e.g., +``src/drivers/i2c/generic`` contains a Kconfig file; the option here is named +CONFIG_DRIVERS_I2C_GENERIC). The config option will need to be added to your +mainboard's Kconfig file (e.g., ``src/mainboard/google/hatch/Kconfig``) in order +to be compiled into your build. + +## Diving into the above example: + +Let's take a look at how the devicetree language corresponds to the generated +ASL. + +First, note this: + +``` + chip drivers/i2c/generic +``` + +This means that the device driver we're using has a corresponding structure, +located at ``src/drivers/i2c/generic/chip.h``, named **struct +drivers_i2c_generic_config** and it contains many properties you can specify to +be included in the ACPI table. + +### hid + +``` + register "hid" = ""ELAN0000"" +``` + +This corresponds to **const char *hid** in the struct. In the ACPI ASL, it +translates to: + +``` + Name (_HID, "ELAN0000") // _HID: Hardware ID +``` + +under the device. **This property is used to match the device to its driver +during enumeration in the OS.** + +### desc + +``` + register "desc" = ""ELAN Touchpad"" +``` + +corresponds to **const char *desc** and in ASL: + +``` + Name (_DDN, "ELAN Touchpad") // _DDN: DOS Device Name +``` + +### irq + +It also adds the interrupt, + +``` + Interrupt (ResourceConsumer, Edge, ActiveLow, ExclusiveAndWake, ,, ) + { + 0x0000002D, + } +``` + +which comes from: + +``` + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" +``` + +The GPIO pin IRQ settings control the "Edge", "ActiveLow", and +"ExclusiveAndWake" settings seen above (edge means it is an edge-triggered +interrupt as opposed to level-triggered; active low means the interrupt is +triggered on a falling edge). + +Note that the ACPI_IRQ_WAKE_EDGE_LOW macro informs the platform that the GPIO +will be routed through SCI (ACPI's System Control Interrupt) for use as a wake +source. Also note that the IRQ names are SoC-specific, and you will need to +find the names in your SoC's header file. The ACPI_* macros are defined in +``src/arch/x86/include/arch/acpi_device.h``. + +Using a GPIO as an IRQ requires that it is configured in coreboot correctly. +This is often done in a mainboard-specific file named ``gpio.c``. + +### wake + +The last register is: + +``` + register "wake" = "GPE0_DW0_21" +``` + +which indicates that the method of waking the system using the touchpad will be +through a GPE, #21 associated with DW0, which is set up in devicetree.cb from +this example. The "21" indicates GPP_X21, where GPP_X is mapped onto DW0 +elsewhere in the devicetree. + +The last bit of the definition of that device includes: + +``` + device i2c 15 on end +``` + +which means it's an I2C device, with 7-bit address 0x15, and the device is "on", +meaning it will be exposed in the ACPI table. The PCI device that the +controller is located in determines which I2C bus the device is expected to be +found on. In this example, this is I2C bus 0. This also determines the ACPI +"Scope" that the device names and methods will live under, in this case +"\_SB.PCI0.I2C0". + +## Other auto-generated names + +(see [ACPI specification +6.3](https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf) +for more details on ACPI methods) + +### _S0W (S0 Device Wake State) +_S0W indicates the deepest S0 sleep state this device can wake itself from, +which in this case is 4, representing _D3cold_. + +### _PRW (Power Resources for Wake) +_PRW indicates the power resources and events required for wake. There are no +dependent power resources, but the GPE (GPE0_DW0_21) is mentioned here (0x15), +as well as the deepest sleep state supporting waking the system (3), which is +S3. + +### _STA (Status) +The _STA method is generated automatically, and its values, 0xF, indicates the +following: + + Bit [0] – Set if the device is present. + Bit [1] – Set if the device is enabled and decoding its resources. + Bit [2] – Set if the device should be shown in the UI. + Bit [3] – Set if the device is functioning properly (cleared if device failed its diagnostics). + +### _CRS (Current resource settings) +The _CRS method is generated automatically, as the driver knows it is an I2C +controller, and so specifies how to configure the controller for proper +operation with the touchpad. + +``` +Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings +{ + I2cSerialBusV2 (0x0015, ControllerInitiated, 400000, + AddressingMode7Bit, "\\_SB.PCI0.I2C0", + 0x00, ResourceConsumer, , Exclusive, ) +``` + +## Notes + + - **All fields that are left unspecified in the devicetree are initialized to + zero.** + - **All devices in devicetrees end up in the SSDT table, and are generated in + coreboot's ramstage** diff --git a/Documentation/coding_style.md b/Documentation/coding_style.md index 048b8e673e..ac0de4ea9d 100644 --- a/Documentation/coding_style.md +++ b/Documentation/coding_style.md @@ -80,11 +80,11 @@ Get a decent editor and don't leave whitespace at the end of lines. Coding style is all about readability and maintainability using commonly available tools. -The limit on the length of lines is 80 columns and this is a strongly +The limit on the length of lines is 96 columns and this is a strongly preferred limit. -Statements longer than 80 columns will be broken into sensible chunks, -unless exceeding 80 columns significantly increases readability and does +Statements longer than 96 columns will be broken into sensible chunks, +unless exceeding 96 columns significantly increases readability and does not hide information. Descendants are always substantially shorter than the parent and are placed substantially to the right. The same applies to function headers with a long argument list. However, never break diff --git a/Documentation/getting_started/gerrit_guidelines.md b/Documentation/getting_started/gerrit_guidelines.md index 34104d8e55..735ba3ba3d 100644 --- a/Documentation/getting_started/gerrit_guidelines.md +++ b/Documentation/getting_started/gerrit_guidelines.md @@ -46,11 +46,11 @@ clarification, see the Developer's Certificate of Origin in the coreboot * Let non-trivial patches sit in a review state for at least 24 hours before submission. Remember that there are coreboot developers in timezones all over the world, and everyone should have a chance to contribute. -Trivial patches would be things like whitespace changes or spelling fixes. -In general, small changes that don’t impact the final binary output. The +Trivial patches would be things like whitespace changes or spelling fixes, +in general those that don’t impact the final binary output. The 24-hour period would start at submission, and would be restarted at any update which significantly changes any part of the patch. Patches can be -'Fast-tracked' and submitted in under this 24 hour with the agreement of at +'Fast-tracked' and submitted in under 24 hours with the agreement of at least 3 +2 votes. * Do not +2 patches that you authored or own, even for something as trivial diff --git a/Documentation/getting_started/kconfig.md b/Documentation/getting_started/kconfig.md index 852ca08bf9..ecdfe62d4a 100644 --- a/Documentation/getting_started/kconfig.md +++ b/Documentation/getting_started/kconfig.md @@ -73,9 +73,6 @@ These variables are typically set in the makefiles or on the make command line. These variables were added to Kconfig specifically for coreboot and are not included in the Linux version. -- COREBOOT_BUILD_DIR=path for temporary files. This is used by coreboot’s - abuild tool. - - KCONFIG_STRICT=value. Define to enable warnings as errors. This is enabled in coreboot, and should not be changed. diff --git a/Documentation/index.md b/Documentation/index.md index a2c2878ddb..b880c1c4d5 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -161,7 +161,7 @@ for example OpenBSD, is probably the closest cousin of our approach. Contents: * [Getting Started](getting_started/index.md) -* [Rookie Guide](lessons/index.md) +* [Tutorial](tutorial/index.md) * [Coding Style](coding_style.md) * [Project Ideas](contributing/project_ideas.md) * [Code of Conduct](community/code_of_conduct.md) @@ -172,6 +172,7 @@ Contents: * [Intel IFD Binary Extraction](Binary_Extraction.md) * [Dealing with Untrusted Input in SMM](technotes/2017-02-dealing-with-untrusted-input-in-smm.md) * [GPIO toggling in ACPI AML](acpi/gpio.md) +* [Adding devices to a device tree](acpi/devicetree.md) * [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md) * [Display panel-specific documentation](gfx/display-panel.md) * [Architecture-specific documentation](arch/index.md) diff --git a/Documentation/lessons/index.md b/Documentation/lessons/index.md deleted file mode 100644 index 6540e8c4fa..0000000000 --- a/Documentation/lessons/index.md +++ /dev/null @@ -1,4 +0,0 @@ -# Rookie Guide - -* [Lesson 1: Starting from scratch](lesson1.md) -* [Lesson 2: Submitting a patch to coreboot.org](lesson2.md) diff --git a/Documentation/mainboard/emulation/qemu-aarch64.md b/Documentation/mainboard/emulation/qemu-aarch64.md index ee4c9e7a3b..4df36a9944 100644 --- a/Documentation/mainboard/emulation/qemu-aarch64.md +++ b/Documentation/mainboard/emulation/qemu-aarch64.md @@ -7,7 +7,7 @@ as a payload for QEMU/AArch64. ```bash qemu-system-aarch64 -bios ./build/coreboot.rom \ -M virt,secure=on,virtualization=on -cpu cortex-a53 \ - -nographic -m 8912M + -nographic -m 8192M ``` - The default CPU in QEMU for AArch64 is a cortex-a15 which is 32-bit @@ -17,6 +17,7 @@ have the right to access EL3/EL2 registers. You need to enable EL3/EL2 via `-machine secure=on,virtualization=on`. - You need to specify the size of memory more than 544 MiB because 512 MiB is reserved for the kernel. +- The maximum size of memory is 255GiB (-m 261120). ## Building coreboot with an arbitrary FIT payload There are 3 steps to make coreboot.rom for QEMU/AArch64. If you select @@ -30,7 +31,7 @@ You can get the DTB from QEMU with the following command. ``` $ qemu-system-aarch64 \ -M virt,dumpdtb=virt.dtb,secure=on,virtualization=on \ - -cpu cortex-a53 -nographic -m 2048M + -cpu cortex-a53 -nographic -m 8192M ``` ### 2. Build a FIT image with a DTB diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 0f3105f85b..ea476eb59f 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -2,6 +2,11 @@ This section contains documentation about coreboot on specific mainboards. +## ASRock + +- [H81M-HDS](asrock/h81m-hds.md) +- [H110M-DVS](asrock/h110m-dvs.md) + ## ASUS - [F2A85-M](asus/f2a85-m.md) @@ -9,11 +14,6 @@ This section contains documentation about coreboot on specific mainboards. - [P8H61-M Pro](asus/p8h61-m_pro.md) - [P8Z77-M Pro](asus/p8z77-m_pro.md) -## ASRock - -- [H81M-HDS](asrock/h81m-hds.md) -- [H110M-DVS](asrock/h110m-dvs.md) - ## Cavium - [CN81XX EVB SFF](cavium/cn8100_sff_evb.md) @@ -26,12 +26,6 @@ The boards in this section are not real mainboards, but emulators. - [Qemu RISC-V emulator](emulation/qemu-riscv.md) - [Qemu AArch64 emulator](emulation/qemu-aarch64.md) -## Intel - -- [DG43GT](intel/dg43gt.md) -- [IceLake RVP](intel/icelake_rvp.md) -- [KBLRVP11](intel/kblrvp11.md) - ## Facebook - [FBG-1701](facebook/fbg1701.md) @@ -48,11 +42,6 @@ The boards in this section are not real mainboards, but emulators. - [Dragonegg](google/dragonegg.md) -## Open Cellular - -- [Elgon](opencellular/elgon.md) -- [Rotundu](opencellular/rotundu.md) - ## HP - [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md) @@ -63,6 +52,12 @@ The boards in this section are not real mainboards, but emulators. - [EliteBook common](hp/elitebook_series.md) - [EliteBook 8760w](hp/8760w.md) +## Intel + +- [DG43GT](intel/dg43gt.md) +- [IceLake RVP](intel/icelake_rvp.md) +- [KBLRVP11](intel/kblrvp11.md) + ## Lenovo - [Mainboard codenames](lenovo/codenames.md) @@ -70,10 +65,6 @@ The boards in this section are not real mainboards, but emulators. - [T4xx common](lenovo/t4xx_series.md) - [X2xx common](lenovo/x2xx_series.md) -## Portwell - -- [PQ7-M107](portwell/pq7-m107.md) - ### Sandy Bridge series - [T420](lenovo/t420.md) @@ -92,17 +83,23 @@ The boards in this section are not real mainboards, but emulators. - [MS-7707](msi/ms7707/ms7707.md) -## PC Engines +## Open Cellular -- [APU2](pcengines/apu2.md) - -## Roda - -- [RK9 Flash Header](roda/rk9/flash_header.md) +- [Elgon](opencellular/elgon.md) +- [Rotundu](opencellular/rotundu.md) ## PC Engines - [APU1](pcengines/apu1.md) +- [APU2](pcengines/apu2.md) + +## Portwell + +- [PQ7-M107](portwell/pq7-m107.md) + +## Roda + +- [RK9 Flash Header](roda/rk9/flash_header.md) ## SiFive @@ -111,6 +108,7 @@ The boards in this section are not real mainboards, but emulators. ## Supermicro - [X10SLM+-F](supermicro/x10slm-f.md) +- [X11 LGA1151 series](supermicro/x11-lga1151-series/index.md) ## UP diff --git a/Documentation/mainboard/supermicro/x10slm-f.md b/Documentation/mainboard/supermicro/x10slm-f.md index 2c2e6a84cd..7fae61fc5f 100644 --- a/Documentation/mainboard/supermicro/x10slm-f.md +++ b/Documentation/mainboard/supermicro/x10slm-f.md @@ -12,7 +12,7 @@ Please see :doc:`../../northbridge/intel/haswell/mrc.bin`. ```eval_rst If you haven't already, build the coreboot toolchain as described in -:doc:`../../lessons/lesson1`. +:doc:`../../tutorial/part1`. ``` A fully working image should be possible so long as you have the @@ -135,7 +135,7 @@ for caveats. can't be used for temperature readings. - There is no automatic, OS-independent fan control. This is because - the super I/O hardware monitor can only obtain valid CPU temperature + the Super I/O hardware monitor can only obtain valid CPU temperature readings from the PECI agent, but the required driver doesn't exist in coreboot. The `coretemp` driver can still be used for accurate CPU temperature readings from an OS, and hence the OS can do fan control. diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/index.md b/Documentation/mainboard/supermicro/x11-lga1151-series/index.md new file mode 100644 index 0000000000..79d2571009 --- /dev/null +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/index.md @@ -0,0 +1,7 @@ +# X11 LGA1151 series + +The supermicros X11 series with socket LGA1151 are mostly the same boards with some minor +differences in internal and external interfaces like available PCIe slots, 1 GbE, 10 GbE, +IPMI etc. This is why those boards are grouped as "X11 LGA1151 series". + +- [X11SSH-TF](x11ssh-tf/x11ssh-tf.md) diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md new file mode 100644 index 0000000000..79e7f3e5eb --- /dev/null +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md @@ -0,0 +1,73 @@ +# Supermicro X11SSH-TF + +This section details how to run coreboot on the [Supermicro X11SSH-TF]. + +## Required proprietary blobs + +* [Intel FSP2.0] +* Intel ME + +## Flashing coreboot + +The board can be flashed externally using *some* programmers. +The CH341 was found working, while Dediprog won't detect the chip. + +For more details have a look at the [flashing tutorial]. + +The flash IC can be found between the two PCIe slots near the southbridge: +![](x11ssh-tf_flash.jpg) + +## BMC (IPMI) + +This board has an ASPEED [AST2400], which has BMC functionality. The +BMC firmware resides in a 32 MiB SOIC-16 chip in the corner of the +mainboard near the [AST2400]. This chip is an [MX25L25635F]. + +## Known issues + +- Intel SGX causes secondary APs to crash (disabled for now). +- Tianocore doesn't work with Aspeed NGI, as it's text mode only. +- SMBus / I2C does not work (interrupt timeout) + +## Tested and working + +- USB ports +- M.2 2280 NVMe slot +- 2x 10GB Ethernet +- SATA +- RS232 +- VGA on Aspeed +- Super I/O initialisation +- ECC DRAM detection +- PCIe slots +- TPM on TPM expansion header +- BMC (IPMI) + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Kaby Lake | ++------------------+--------------------------------------------------+ +| PCH | Intel C236 | ++------------------+--------------------------------------------------+ +| Super I/O | ASPEED AST2400 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel SPS (server version of the ME) | ++------------------+--------------------------------------------------+ +| Coprocessor | ASPEED AST2400 | ++------------------+--------------------------------------------------+ +``` + +## Extra links + +- [Board manual] + +[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376 +[Board manual]: https://www.supermicro.com/manuals/motherboard/C236/MNL-1783.pdf +[flashrom]: https://flashrom.org/Flashrom +[MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf +[N25Q128A]: https://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/Serial%20NOR/N25Q/n25q_128mb_3v_65nm.pdf +[flashing tutorial]: ../../../../flash_tutorial/ext_power.md +[Intel FSP2.0]: ../../../../soc/intel/fsp/index.md +[Supermicro X11SSH-TF]: https://www.supermicro.com/en/products/motherboard/X11SSH-TF diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf_flash.jpg b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf_flash.jpg new file mode 100644 index 0000000000..8ab07f23c7 Binary files /dev/null and b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf_flash.jpg differ diff --git a/Documentation/security/intel/txt.md b/Documentation/security/intel/txt.md index f67b63942e..f80a731e81 100644 --- a/Documentation/security/intel/txt.md +++ b/Documentation/security/intel/txt.md @@ -90,11 +90,11 @@ correct state. If it's not the SINIT ACM will reset the platform. ## For developers ### Configuring Intel TXT in Kconfig -Enable ``TEE_INTEL_TXT`` and set the following: +Enable ``INTEL_TXT`` and set the following: -``TEE_INTEL_TXT_BIOSACM_FILE`` to the path of the BIOS ACM provided by Intel +``INTEL_TXT_BIOSACM_FILE`` to the path of the BIOS ACM provided by Intel -``TEE_INTEL_TXT_SINITACM_FILE`` to the path of the SINIT ACM provided by Intel +``INTEL_TXT_SINITACM_FILE`` to the path of the SINIT ACM provided by Intel ### Print TXT status as early as possible Add platform code to print the TXT status as early as possible, as the register is cleared on cold reset. diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md index 6269445ff3..cd7fe0b302 100644 --- a/Documentation/soc/intel/fsp/index.md +++ b/Documentation/soc/intel/fsp/index.md @@ -45,6 +45,8 @@ those are fixed. If possible a workaround is described here as well. * [FSP Specification 2.0](https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v2.pdf) +* [FSP Specification 2.1](https://cdrdv2.intel.com/v1/dl/getContent/611786) + ## Additional Features in FSP 2.1 specification - [PPI](ppi/ppi.md) diff --git a/Documentation/superio/common/ssdt.md b/Documentation/superio/common/ssdt.md new file mode 100644 index 0000000000..4353cde3aa --- /dev/null +++ b/Documentation/superio/common/ssdt.md @@ -0,0 +1,56 @@ +# SuperIO SSTD generator + +This page describes the common SSDT ACPI generator for SuperIO chips that can +be found in coreboot. + +## Functional description + +In order to automatically generate ACPI functions you need to add +a new `chip superio/common` and `device pnp xx.0 on` to your devicetree. + +The xx denotes the hexadecimal address of the SuperIO. + +Place the regular LDN pnp devices behind those two entries. + +The code will automatically guess the function based on the decoded +I/O range and ISA IRQ number. + +## Example devicetree.cb + +This example is based on AST2400. + +```code +# Add a "container" for proper ACPI code generation +chip superio/common + device pnp 2e.0 on # just for the base device, not for the LDNs + chip superio/aspeed/ast2400 + device pnp 2e.0 off end + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # SUART2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 on # SWC + io 0x60 = 0xa00 + io 0x62 = 0xa10 + io 0x64 = 0xa20 + io 0x66 = 0xa30 + irq 0x70 = 0 + end + end + end +end +``` + +## TODO + +1) Add ACPI HIDs to every SuperIO driver +2) Don't guess ACPI HID of LDNs if it's known +3) Add "enter config" and "exit config" bytes +4) Generate support methods that allow + * Setting resource settings at runtime + * Getting resource settings at runtime + * Disabling LDNs at runtime diff --git a/Documentation/superio/index.md b/Documentation/superio/index.md index eef4d579ef..39965fde07 100644 --- a/Documentation/superio/index.md +++ b/Documentation/superio/index.md @@ -5,3 +5,6 @@ This section contains documentation about coreboot on specific SuperIOs. ## Nuvoton - [NPCD378](nuvoton/npcd378.md) + +## Common +- [SSDT generator for generic SuperIOs](common/ssdt.md) diff --git a/Documentation/tutorial/index.md b/Documentation/tutorial/index.md new file mode 100644 index 0000000000..48dfbe5da6 --- /dev/null +++ b/Documentation/tutorial/index.md @@ -0,0 +1,4 @@ +# Tutorial + +* [Part 1: Starting from scratch](part1.md) +* [Part 2: Submitting a patch to coreboot.org](part2.md) diff --git a/Documentation/lessons/lesson1.md b/Documentation/tutorial/part1.md similarity index 98% rename from Documentation/lessons/lesson1.md rename to Documentation/tutorial/part1.md index bbb3eb5582..75a9ba375f 100644 --- a/Documentation/lessons/lesson1.md +++ b/Documentation/tutorial/part1.md @@ -1,5 +1,5 @@ -coreboot Lesson 1: Starting from scratch -======================================== +Tutorial, part 1: Starting from scratch +=========================================== From a fresh Ubuntu 16.04 or 18.04 install, here are all the steps required for a very basic build: diff --git a/Documentation/lessons/lesson2.md b/Documentation/tutorial/part2.md similarity index 99% rename from Documentation/lessons/lesson2.md rename to Documentation/tutorial/part2.md index ae70c70cbc..e5322186f9 100644 --- a/Documentation/lessons/lesson2.md +++ b/Documentation/tutorial/part2.md @@ -1,4 +1,4 @@ -# coreboot Lesson 2: Submitting a patch to coreboot.org +# Tutorial, part 2: Submitting a patch to coreboot.org ## Part 1: Setting up an account at coreboot.org diff --git a/Documentation/vendorcode/index.md b/Documentation/vendorcode/index.md index 3374eafc67..ffa5ed5041 100644 --- a/Documentation/vendorcode/index.md +++ b/Documentation/vendorcode/index.md @@ -5,3 +5,4 @@ This section contains documentation about coreboot on specific vendorcode. ## Vendor - [Cavium](cavium/index.md) +- [Eltan](eltan/index.md) diff --git a/Makefile b/Makefile index 317a8eb1cf..35a4b32c2a 100644 --- a/Makefile +++ b/Makefile @@ -30,6 +30,9 @@ ## SUCH DAMAGE. ## +ifneq ($(words $(CURDIR)),1) + $(error Error: Path to the main directory cannot contain spaces) +endif top := $(CURDIR) src := src srck := $(top)/util/kconfig @@ -42,6 +45,12 @@ absobj := $(abspath $(obj)) COREBOOT_EXPORTS := COREBOOT_EXPORTS COREBOOT_EXPORTS += top src srck obj objutil objk +# reproducible builds +LANG:=C +LC_ALL:=C +TZ:=UTC0 +COREBOOT_EXPORTS += LANG LC_ALL TZ + DOTCONFIG ?= $(top)/.config KCONFIG_CONFIG = $(DOTCONFIG) KCONFIG_AUTOADS := $(obj)/cb-config.ads @@ -129,6 +138,12 @@ NOMKDIR:=1 endif endif +.xcompile: util/xcompile/xcompile + rm -f $@ + $< $(XGCCPATH) > $@.tmp + \mv -f $@.tmp $@ 2> /dev/null + rm -f $@.tmp + -include $(TOPLEVEL)/site-local/Makefile.inc ifeq ($(NOCOMPILE),1) @@ -148,12 +163,6 @@ include $(DOTCONFIG) # to silence stupid warnings about a file that would be generated anyway. $(if $(wildcard .xcompile)$(NOCOMPILE),,$(eval $(shell util/xcompile/xcompile $(XGCCPATH) > .xcompile || rm -f .xcompile))) -.xcompile: util/xcompile/xcompile - rm -f $@ - $< $(XGCCPATH) > $@.tmp - \mv -f $@.tmp $@ 2> /dev/null - rm -f $@.tmp - -include .xcompile ifneq ($(XCOMPILE_COMPLETE),1) diff --git a/Makefile.inc b/Makefile.inc index c275d1efa5..86764045a6 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -402,7 +402,7 @@ endif CFLAGS_common += -pipe -g -nostdinc -std=gnu11 CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough -CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits +CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits -Wvla CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie ifeq ($(CONFIG_COMPILER_GCC),y) @@ -497,14 +497,14 @@ build_h_exports := BUILD_TIMELESS KERNELVERSION COREBOOT_EXTRA_VERSION # Report new `build.ht` as dependency if `build.h` differs. build_h_check := \ export $(foreach exp,$(build_h_exports),$(exp)="$($(exp))"); \ - util/genbuild_h/genbuild_h.sh >$(build_h)t 2>/dev/null; \ + util/genbuild_h/genbuild_h.sh .xcompile >$(build_h)t 2>/dev/null; \ cmp -s $(build_h)t $(build_h) >/dev/null 2>&1 || echo $(build_h)t $(build_h): $$(shell $$(build_h_check)) @printf " GEN build.h\n" mv $< $@ -build-dirs: +build-dirs $(objcbfs) $(objgenerated): mkdir -p $(objcbfs) $(objgenerated) ####################################################################### @@ -646,7 +646,7 @@ install-git-commit-clangfmt: include util/crossgcc/Makefile.inc .PHONY: tools -tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) +tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) ########################################################################### # Common recipes for all stages @@ -706,7 +706,7 @@ $(objcbfs)/bootblock.raw.bin: $(objcbfs)/bootblock.raw.elf $(OBJCOPY_bootblock) -O binary $< $@ ifneq ($(CONFIG_HAVE_BOOTBLOCK),y) -$(objcbfs)/bootblock.bin: +$(objcbfs)/bootblock.bin: $(objcbfs) dd if=/dev/zero of=$@ bs=64 count=1 endif diff --git a/configs/config.intel_galileo_gen2.debug b/configs/config.intel_galileo_gen2.debug index ceea7d0af7..f4fdb2d7eb 100644 --- a/configs/config.intel_galileo_gen2.debug +++ b/configs/config.intel_galileo_gen2.debug @@ -3,7 +3,6 @@ CONFIG_VENDOR_INTEL=y CONFIG_BOARD_INTEL_GALILEO=y # CONFIG_FSP_DEBUG_ALL is not set CONFIG_DISPLAY_MTRRS=y -CONFIG_DISPLAY_SMM_MEMORY_MAP=y CONFIG_DISPLAY_ESRAM_LAYOUT=y CONFIG_BOOTBLOCK_NORMAL=y CONFIG_ON_DEVICE_ROM_LOAD=y diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index 1e9eb80d20..34c45d9855 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -83,7 +83,7 @@ OBJCOPY := $(OBJCOPY_$(ARCH-y)) LPCC := CC="$(CC)" $(LIBPAYLOAD_OBJ)/bin/lpgcc LPAS := AS="$(AS)" $(LIBPAYLOAD_OBJ)/bin/lpas -CFLAGS += -Wall -Wextra -Wmissing-prototypes -Werror +CFLAGS += -Wall -Wextra -Wmissing-prototypes -Wvla -Werror CFLAGS += -Os -fno-builtin $(CFLAGS_$(ARCH-y)) $(INCLUDES) ifneq ($(strip $(HAVE_DOTCONFIG)),) diff --git a/payloads/external/LinuxBoot/targets/linux.mk b/payloads/external/LinuxBoot/targets/linux.mk index e32ad1e21b..8be0926eb0 100644 --- a/payloads/external/LinuxBoot/targets/linux.mk +++ b/payloads/external/LinuxBoot/targets/linux.mk @@ -29,11 +29,13 @@ tarball_dir:=$(project_dir)/tarball decompress_flag=.done OBJCOPY:=$(LINUXBOOT_CROSS_COMPILE)objcopy +KERNEL_MAKE_FLAGS = \ + ARCH=$(ARCH-y) ifeq ($(CONFIG_LINUXBOOT_KERNEL_CUSTOM),y) kernel_version:=$(CONFIG_LINUXBOOT_KERNEL_CUSTOM_VERSION) else - kernel_version:=$(shell curl -s -k https://www.kernel.org/feeds/kdist.xml | \ + kernel_version:=$(shell curl -sS -k https://www.kernel.org/feeds/kdist.xml | \ sed -n -e 's@.*\(.*\).*@\1@p' | \ awk -F ',' '/$(TAG-y)/{ print $$3 }' | \ head -n 1) @@ -67,7 +69,7 @@ ifneq ($(shell [[ -d "$(kernel_dir)" && -f "$(kernel_dir)/$(decompress_flag)" ]] if [[ ! -f $(tarball_dir)/$(kernel_tarball).xz && ! -f $(tarball_dir)/$(kernel_tarball).xz ]]; then \ echo " WWW $(kernel_tarball).xz"; \ cd $(tarball_dir); \ - curl -OLs "$(kernel_mirror_path)/$(kernel_tarball).xz"; \ + curl -OLSs "$(kernel_mirror_path)/$(kernel_tarball).xz"; \ cd $(pwd); \ fi endif @@ -90,15 +92,15 @@ ifeq ($(CONFIG_LINUXBOOT_KERNEL_CUSTOM_CONFIG),y) else cp $(ARCH-y)/defconfig $(kernel_dir)/.config endif - $(MAKE) -C $(kernel_dir) olddefconfig ARCH=$(ARCH-y) + $(MAKE) -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) olddefconfig build: $(kernel_dir)/.config @echo " MAKE Linux $(kernel_version)" ifeq ($(CONFIG_LINUXBOOT_KERNEL_BZIMAGE),y) - $(MAKE) -C $(kernel_dir) CROSS_COMPILE=$(LINUXBOOT_CROSS_COMPILE) ARCH=$(ARCH-y) bzImage + $(MAKE) -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) CROSS_COMPILE=$(LINUXBOOT_CROSS_COMPILE) bzImage else ifeq ($(CONFIG_LINUXBOOT_KERNEL_UIMAGE),y) - $(MAKE) -C $(kernel_dir) CROSS_COMPILE=$(LINUXBOOT_CROSS_COMPILE) ARCH=$(ARCH-y) vmlinux + $(MAKE) -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) CROSS_COMPILE=$(LINUXBOOT_CROSS_COMPILE) vmlinux endif endif diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index df168f2bee..f6417fd946 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -29,6 +29,11 @@ endif ifeq ($(CONFIG_PAYLOAD_DEPTHCHARGE),y) PAYLOAD_CONFIG=payloads/external/depthcharge/depthcharge/.config $(PAYLOAD_CONFIG): payloads/external/depthcharge/depthcharge/build/depthcharge.elf +ifneq ($(CONFIG_MAINBOARD_DEPTHCHARGE),) + BOARD=$(CONFIG_MAINBOARD_DEPTHCHARGE) +else + BOARD=$(call ws_to_under,$(call strip_quotes,$(call tolower,$(CONFIG_MAINBOARD_PART_NUMBER)))) +endif #TODO: Figure out version endif @@ -114,7 +119,7 @@ endif payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL) $(MAKE) -C payloads/external/depthcharge \ - BOARD=$(call ws_to_under,$(call strip_quotes,$(call tolower,$(CONFIG_MAINBOARD_PART_NUMBER)))) \ + BOARD=$(BOARD) \ MFLAGS= MAKEFLAGS= \ DEPTHCHARGE_MASTER=$(CONFIG_DEPTHCHARGE_MASTER) \ DEPTHCHARGE_STABLE=$(CONFIG_DEPTHCHARGE_STABLE) \ @@ -128,14 +133,14 @@ payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd tianocore: $(DOTCONFI $(MAKE) -C payloads/external/tianocore all \ HOSTCC="$(HOSTCC)" \ CC="$(HOSTCC)" \ - CONFIG_TIANOCORE_MASTER=$(CONFIG_TIANOCORE_MASTER) \ - CONFIG_TIANOCORE_STABLE=$(CONFIG_TIANOCORE_STABLE) \ - CONFIG_TIANOCORE_REVISION=$(CONFIG_TIANOCORE_REVISION) \ CONFIG_TIANOCORE_REVISION_ID=$(CONFIG_TIANOCORE_REVISION_ID) \ CONFIG_TIANOCORE_DEBUG=$(CONFIG_TIANOCORE_DEBUG) \ CONFIG_TIANOCORE_TARGET_IA32=$(CONFIG_TIANOCORE_TARGET_IA32) \ CONFIG_TIANOCORE_USE_8254_TIMER=$(CONFIG_TIANOCORE_USE_8254_TIMER) \ CONFIG_TIANOCORE_BOOTSPLASH_FILE=$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \ + CONFIG_TIANOCORE_UEFIPAYLOAD=$(CONFIG_TIANOCORE_UEFIPAYLOAD) \ + CONFIG_TIANOCORE_COREBOOTPAYLOAD=$(CONFIG_TIANOCORE_COREBOOTPAYLOAD) \ + CONFIG_MMCONF_BASE_ADDRESS=$(CONFIG_MMCONF_BASE_ADDRESS) \ GCC_CC_x86_32=$(GCC_CC_x86_32) \ GCC_CC_x86_64=$(GCC_CC_x86_64) \ GCC_CC_arm=$(GCC_CC_arm) \ diff --git a/payloads/external/depthcharge/Kconfig b/payloads/external/depthcharge/Kconfig index 9fd1268b91..89c81ef70e 100644 --- a/payloads/external/depthcharge/Kconfig +++ b/payloads/external/depthcharge/Kconfig @@ -35,6 +35,11 @@ config PAYLOAD_FILE string default "payloads/external/depthcharge/depthcharge/build/depthcharge.elf" +config MAINBOARD_DEPTHCHARGE + string "" + help + Override BOARD setting for depthcharge + config LP_DEFCONFIG_OVERRIDE bool "Use default libpayload config" help diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig index d8b7d9251d..7717917f94 100644 --- a/payloads/external/tianocore/Kconfig +++ b/payloads/external/tianocore/Kconfig @@ -7,38 +7,32 @@ config PAYLOAD_FILE The result of a corebootPkg build choice - prompt "Tianocore version" - default TIANOCORE_STABLE + prompt "Tianocore payload" + default TIANOCORE_COREBOOTPAYLOAD help - Select which version of Tianocore to build (default is to build stable) - stable: MrChromebox's customized version of Tianocore which works on most + Select which type of payload Tianocore will build (default is CorebootPayload) + CorebootPayload: MrChromebox's customized version of Tianocore which works on most (all?) x86_64 devices - revision: use specific commit or branch to build Tianocore (specified by user) + UEFIPayload: Use upstream Tianocore payload from https://github.com/tianocore/edk2 -config TIANOCORE_STABLE - bool "stable" +config TIANOCORE_COREBOOTPAYLOAD + bool "CorebootPayload" help Select this option to build using MrChromebox's custom Tianocore tree i.e. a version of Tianocore that builds without any errors and just works. -config TIANOCORE_REVISION - bool "git revision" +config TIANOCORE_UEFIPAYLOAD + bool "UEFIPayload" help - Select this option if you have a specific commit or branch - that you want to use from either MrChromebox's tree or upstream - EDK2 from which to build Tianocore. - - You will be able to specify the name of a branch or a commit id - later. + Select this option if you want to use upstream EDK2 to build Tianocore. endchoice config TIANOCORE_REVISION_ID string "Insert a commit's SHA-1 or a branch name" - depends on TIANOCORE_REVISION - default "upstream/master" help - The commit's SHA-1 or branch name of the revision to use. + The commit's SHA-1 or branch name of the revision to use. Choose "upstream/master" + for master branch of Tianocore release on github. choice prompt "Target architecture" @@ -89,7 +83,7 @@ config TIANOCORE_USE_8254_TIMER config TIANOCORE_BOOTSPLASH_IMAGE bool "Use a custom bootsplash image" - depends on TIANOCORE_STABLE + depends on TIANOCORE_COREBOOTPAYLOAD help Select this option if you have a bootsplash image that you would like to be used. If this option is not selected, the default @@ -98,6 +92,7 @@ config TIANOCORE_BOOTSPLASH_IMAGE config TIANOCORE_BOOTSPLASH_FILE string "Tianocore Bootsplash path and filename" depends on TIANOCORE_BOOTSPLASH_IMAGE + depends on TIANOCORE_COREBOOTPAYLOAD default "bootsplash.bmp" help The path and filename of the file to use as graphical bootsplash diff --git a/payloads/external/tianocore/Kconfig.name b/payloads/external/tianocore/Kconfig.name index a56d248bab..7b0b300351 100644 --- a/payloads/external/tianocore/Kconfig.name +++ b/payloads/external/tianocore/Kconfig.name @@ -1,5 +1,5 @@ config PAYLOAD_TIANOCORE - bool "Tianocore coreboot payload package" + bool "Tianocore payload" depends on ARCH_X86 help Select this option if you want to build a coreboot image diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index f208e5952f..7adb700a6e 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -22,9 +22,19 @@ project_git_repo=https://github.com/mrchromebox/edk2 project_git_branch=coreboot_fb upstream_git_repo=https://github.com/tianocore/edk2 +ifeq ($(CONFIG_TIANOCORE_UEFIPAYLOAD),y) +bootloader=UefiPayloadPkg +build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_MMCONF_BASE_ADDRESS) +TAG=upstream/master +else +bootloader=CorebootPayloadPkg # STABLE revision is MrChromebox's coreboot framebuffer (coreboot_fb) branch -TAG-$(CONFIG_TIANOCORE_STABLE)=origin/$(project_git_branch) -TAG-$(CONFIG_TIANOCORE_REVISION)=$(CONFIG_TIANOCORE_REVISION_ID) +TAG=origin/$(project_git_branch) +endif + +ifneq ($(CONFIG_TIANOCORE_REVISION_ID),) +TAG=$(CONFIG_TIANOCORE_REVISION_ID) +endif export EDK_TOOLS_PATH=$(project_dir)/BaseTools @@ -39,9 +49,9 @@ TIMER=-DUSE_HPET_TIMER endif ifeq ($(CONFIG_TIANOCORE_TARGET_IA32), y) - BUILD_STR=-a IA32 -t COREBOOT -p CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -b $(BUILD_TYPE) $(TIMER) + BUILD_STR=-a IA32 -t COREBOOT -p $(bootloader)/$(bootloader)Ia32.dsc -b $(BUILD_TYPE) $(TIMER) $(build_flavor) else - BUILD_STR=-a IA32 -a X64 -t COREBOOT -p CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -b $(BUILD_TYPE) $(TIMER) + BUILD_STR=-a IA32 -a X64 -t COREBOOT -p $(bootloader)/$(bootloader)Ia32X64.dsc -b $(BUILD_TYPE) $(TIMER) $(build_flavor) endif all: clean build @@ -56,13 +66,13 @@ update: $(project_dir) cd $(project_dir); \ echo " Fetching new commits from the $(project_name) repo"; \ git fetch --multiple origin upstream 2>/dev/null; \ - if ! git rev-parse --verify -q $(TAG-y) >/dev/null; then \ - echo " $(TAG-y) is not a valid git reference"; \ + if ! git rev-parse --verify -q $(TAG) >/dev/null; then \ + echo " $(TAG) is not a valid git reference"; \ exit 1; \ fi; \ if git describe --all --dirty | grep -qv dirty; then \ - echo " Checking out $(project_name) revision $(TAG-y)"; \ - git checkout --detach $(TAG-y); \ + echo " Checking out $(project_name) revision $(TAG)"; \ + git checkout --detach $(TAG); \ else \ echo " Working directory not clean; will not overwrite"; \ fi @@ -80,7 +90,7 @@ checktools: build: update checktools unset CC; $(MAKE) -C $(project_dir)/BaseTools - echo " build $(project_name) $(TAG-y)" + echo " build $(project_name) $(TAG)" if [ -n $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) ]; then \ echo " Copying custom bootsplash image"; \ case "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" in \ @@ -99,7 +109,7 @@ build: update checktools cat ../tools_def.txt >> $(project_dir)/Conf/tools_def.txt; \ fi; \ build $(BUILD_STR); \ - mv $(project_dir)/Build/CorebootPayloadPkg*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd; \ + mv $(project_dir)/Build/$(bootloader)*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd; \ git checkout CorebootPayloadPkg/Logo/Logo.bmp > /dev/null 2>&1 || true clean: diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index f0aaa2727f..4863d3f1da 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -62,7 +62,7 @@ INCLUDES := -Iinclude -Iinclude/$(ARCHDIR-y) -I$(obj) -include include/kconfig.h CFLAGS += $(EXTRA_CFLAGS) $(INCLUDES) -Os -pipe -nostdinc -ggdb3 CFLAGS += -nostdlib -fno-builtin -ffreestanding -fomit-frame-pointer CFLAGS += -ffunction-sections -fdata-sections -CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes +CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wvla CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough CFLAGS += -Wstrict-aliasing -Wshadow -Werror diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index 9c9854da76..4004def9d9 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -265,6 +265,8 @@ usb_decode_mps0(usb_speed speed, u8 bMaxPacketSize0) } return bMaxPacketSize0; case SUPER_SPEED: + /* Intentional fallthrough */ + case SUPER_SPEED_PLUS: if (bMaxPacketSize0 != 9) { usb_debug("Invalid MPS0: 0x%02x\n", bMaxPacketSize0); bMaxPacketSize0 = 9; @@ -284,6 +286,8 @@ int speed_to_default_mps(usb_speed speed) case HIGH_SPEED: return 64; case SUPER_SPEED: + /* Intentional fallthrough */ + case SUPER_SPEED_PLUS: default: return 512; } @@ -319,6 +323,8 @@ usb_decode_interval(usb_speed speed, const endpoint_type type, const unsigned ch return LOG2(bInterval); } case SUPER_SPEED: + /* Intentional fallthrough */ + case SUPER_SPEED_PLUS: switch (type) { case ISOCHRONOUS: case INTERRUPT: return bInterval - 1; @@ -657,7 +663,7 @@ usb_detach_device(hci_t *controller, int devno) int usb_attach_device(hci_t *controller, int hubaddress, int port, usb_speed speed) { - static const char* speeds[] = { "full", "low", "high", "super" }; + static const char *speeds[] = { "full", "low", "high", "super", "ultra" }; usb_debug ("%sspeed device\n", (speed < sizeof(speeds) / sizeof(char*)) ? speeds[speed] : "invalid value - no"); int newdev = set_address (controller, speed, port, hubaddress); @@ -692,6 +698,14 @@ usb_generic_init (usbdev_t *dev) } } +/* + * returns the speed is above SUPER_SPEED or not + */ +_Bool is_usb_speed_ss(usb_speed speed) +{ + return (speed == SUPER_SPEED || speed == SUPER_SPEED_PLUS); +} + /* * returns the address of the closest USB2.0 hub, which is responsible for * split transactions, along with the number of the used downstream port diff --git a/payloads/libpayload/drivers/usb/usbhub.c b/payloads/libpayload/drivers/usb/usbhub.c index 340e47ae3d..87c58169c5 100644 --- a/payloads/libpayload/drivers/usb/usbhub.c +++ b/payloads/libpayload/drivers/usb/usbhub.c @@ -35,15 +35,39 @@ /* assume that host_to_device is overwritten if necessary */ #define DR_PORT gen_bmRequestType(host_to_device, class_type, other_recp) /* status (and status change) bits */ -#define PORT_CONNECTION 0x1 -#define PORT_ENABLE 0x2 -#define PORT_RESET 0x10 +#define PORT_CONNECTION 0x01 +#define PORT_ENABLE 0x02 +#define PORT_SUSPEND 0x04 +#define PORT_OVER_CURRENT 0x08 +#define PORT_RESET 0x10 +#define BH_PORT_RESET 0x20 +#define PORT_LINK_STATE 0x40 +#define PORT_CONFIG_ERROR 0x80 /* feature selectors (for setting / clearing features) */ -#define SEL_PORT_RESET 0x4 -#define SEL_PORT_POWER 0x8 -#define SEL_C_PORT_CONNECTION 0x10 +#define SEL_PORT_RESET 0x04 +#define SEL_PORT_POWER 0x08 +#define SEL_C_PORT_CONNECTION 0x10 +#define SEL_C_PORT_ENABLE 0x11 +#define SEL_C_PORT_SUSPEND 0x12 +#define SEL_C_PORT_OVER_CURRENT 0x13 +#define SEL_C_PORT_RESET 0x14 +#define SEL_C_PORT_LINK_STATE 0x19 +#define SEL_C_PORT_CONFIG_ERROR 0x1a +#define SEL_C_BH_PORT_RESET 0x1d /* request type (USB 3.0 hubs only) */ -#define SET_HUB_DEPTH 12 +#define SET_HUB_DEPTH 12 + +static endpoint_t * +usb_hub_interrupt_ep(usbdev_t *const dev) +{ + int i; + for (i = 0; i < dev->num_endp; ++i) { + if (dev->endpoints[i].type == INTERRUPT && + dev->endpoints[i].direction == IN) + return &dev->endpoints[i]; + } + return NULL; +} static int usb_hub_port_status_changed(usbdev_t *const dev, const int port) @@ -96,8 +120,8 @@ usb_hub_port_speed(usbdev_t *const dev, const int port) int ret = get_status (dev, port, DR_PORT, sizeof(buf), buf); if (ret >= 0 && (buf[0] & PORT_ENABLE)) { /* SuperSpeed hubs can only have SuperSpeed devices. */ - if (dev->speed == SUPER_SPEED) - return SUPER_SPEED; + if (is_usb_speed_ss(dev->speed)) + return dev->speed; /*[bit] 10 9 (USB 2.0 port status word) * 0 0 full speed @@ -169,14 +193,100 @@ usb_hub_port_initialize(usbdev_t *const dev, const int port) return; if (buf[1] & PORT_CONNECTION) clear_feature(dev, port, SEL_C_PORT_CONNECTION, DR_PORT); - if (buf[0] & PORT_CONNECTION) + if (buf[0] & PORT_CONNECTION) { + usb_debug("usbhub: Port coldplug at %d\n", port); generic_hub_scanport(dev, port); + } +} + +static int +usb_hub_handle_port_change(usbdev_t *const dev, const int port) +{ + static const struct { + unsigned short change_bit; + unsigned short clear_sel; + } change_bits[] = { + { PORT_CONNECTION, SEL_C_PORT_CONNECTION }, + { PORT_ENABLE, SEL_C_PORT_ENABLE }, + { PORT_SUSPEND, SEL_C_PORT_SUSPEND }, + { PORT_OVER_CURRENT, SEL_C_PORT_OVER_CURRENT }, + { PORT_RESET, SEL_C_PORT_RESET }, + { BH_PORT_RESET, SEL_C_BH_PORT_RESET }, + { PORT_LINK_STATE, SEL_C_PORT_LINK_STATE }, + { PORT_CONFIG_ERROR, SEL_C_PORT_CONFIG_ERROR }, + }; + int ret = 0; + unsigned int i; + unsigned short checked_bits = 0; + unsigned short buf[2] = { 0, 0 }; + + ret = get_status(dev, port, DR_PORT, sizeof(buf), buf); + if (ret < 0) + return ret; + + /* + * Second word holds the change bits. The interrupt transfer shows + * a logical or of these bits, so we have to clear them all. + */ + for (i = 0; i < ARRAY_SIZE(change_bits); ++i) { + if (buf[1] & change_bits[i].change_bit) + clear_feature(dev, port, change_bits[i].clear_sel, DR_PORT); + checked_bits |= change_bits[i].change_bit; + } + if (buf[1] & ~checked_bits) + usb_debug("usbhub: Spurious change bit at port %d\n", port); + + /* Now, handle connection changes. */ + if (buf[1] & PORT_CONNECTION) { + usb_debug("usbhub: Port change at %d\n", port); + ret = generic_hub_scanport(dev, port); + } + return ret; +} + +static void +usb_hub_poll(usbdev_t *const dev) +{ + unsigned int port, i; + u8 buf[32] = { 0 }; + const u8 *ibuf; + + /* First, gather all change bits from finished interrupt transfers. */ + const size_t port_bytes = MIN(ARRAY_SIZE(buf), + div_round_up(GEN_HUB(dev)->num_ports + 1, 8)); + while ((ibuf = dev->controller->poll_intr_queue(GEN_HUB(dev)->data))) { + for (i = 0; i < port_bytes; ++i) + buf[i] |= ibuf[i]; + } + + for (port = 1; port <= GEN_HUB(dev)->num_ports; ++port) { + /* ports start at bit1; bit0 is hub status change */ + if (buf[port / 8] & (1 << (port % 8))) { + if (usb_hub_handle_port_change(dev, port) < 0) + return; + } + } +} + +static void +usb_hub_destroy(usbdev_t *const dev) +{ + endpoint_t *const intr_ep = usb_hub_interrupt_ep(dev); + dev->controller->destroy_intr_queue(intr_ep, GEN_HUB(dev)->data); + generic_hub_destroy(dev); } void usb_hub_init(usbdev_t *const dev) { - int type = dev->speed == SUPER_SPEED ? 0x2a : 0x29; /* similar enough */ + endpoint_t *const intr_ep = usb_hub_interrupt_ep(dev); + if (!intr_ep) { + usb_debug("usbhub: ERROR: No interrupt-in endpoint found\n"); + return; + } + + /* Get number of ports from hub decriptor */ + int type = is_usb_speed_ss(dev->speed) ? 0x2a : 0x29; /* similar enough */ hub_descriptor_t desc; /* won't fit the whole thing, we don't care */ if (get_descriptor(dev, gen_bmRequestType(device_to_host, class_type, dev_recp), type, 0, &desc, sizeof(desc)) != sizeof(desc)) { @@ -185,12 +295,40 @@ usb_hub_init(usbdev_t *const dev) return; } - if (dev->speed == SUPER_SPEED) + if (is_usb_speed_ss(dev->speed)) usb_hub_set_hub_depth(dev); - if (generic_hub_init(dev, desc.bNbrPorts, &usb_hub_ops) < 0) + + /* + * Register interrupt transfer: + * one bit per port + one bit for the hub, + * 20 transfers in the queue, like our HID driver, + * one transfer per 256ms + */ + void *const intrq = dev->controller->create_intr_queue( + intr_ep, intr_ep->maxpacketsize, 20, 256); + if (!intrq) { + usb_detach_device(dev->controller, dev->address); return; + } + + /* + * Limit the number of ports by the max packet size of + * the interrupt endpoint. This shouldn't be necessary + * but prevents a potential overflow in usb_hub_poll(). + */ + const unsigned int num_ports = + MIN(desc.bNbrPorts, intr_ep->maxpacketsize * 8 - 1); + if (generic_hub_init(dev, num_ports, &usb_hub_ops)) { + dev->controller->destroy_intr_queue(intr_ep, intrq); + usb_detach_device(dev->controller, dev->address); + return; + } int port; - for (port = 1; port <= GEN_HUB(dev)->num_ports; ++port) + for (port = 1; port <= num_ports; ++port) usb_hub_port_initialize(dev, port); + + GEN_HUB(dev)->data = intrq; + dev->poll = usb_hub_poll; + dev->destroy = usb_hub_destroy; } diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c index 2c7cbe5ef2..2412e99af3 100644 --- a/payloads/libpayload/drivers/usb/usbmsc.c +++ b/payloads/libpayload/drivers/usb/usbmsc.c @@ -157,6 +157,9 @@ reset_transport (usbdev_t *dev) dr.wIndex = 0; dr.wLength = 0; + if (MSC_INST (dev)->quirks & USB_MSC_QUIRK_NO_RESET) + return MSC_COMMAND_FAIL; + /* if any of these fails, detach device, as we are lost */ if (dev->controller->control (dev, OUT, sizeof (dr), &dr, 0, 0) < 0 || clear_stall (MSC_INST (dev)->bulk_in) || @@ -185,7 +188,8 @@ initialize_luns (usbdev_t *dev) dr.wValue = 0; dr.wIndex = 0; dr.wLength = 1; - if (dev->controller->control (dev, IN, sizeof (dr), &dr, + if (MSC_INST (dev)->quirks & USB_MSC_QUIRK_NO_LUNS || + dev->controller->control (dev, IN, sizeof (dr), &dr, sizeof (msc->num_luns), &msc->num_luns) < 0) msc->num_luns = 0; /* assume only 1 lun if req fails */ msc->num_luns++; /* Get Max LUN returns number of last LUN */ @@ -218,14 +222,23 @@ wrap_cbw (cbw_t *cbw, int datalen, cbw_direction dir, const u8 *cmd, static int get_csw (endpoint_t *ep, csw_t *csw) { - if (ep->dev->controller->bulk (ep, sizeof (csw_t), (u8 *) csw, 1) < 0) { + hci_t *ctrlr = ep->dev->controller; + int ret = ctrlr->bulk (ep, sizeof (csw_t), (u8 *) csw, 1); + + /* Some broken sticks send a zero-length packet at the end of their data + transfer which would show up here. Skip it to get the actual CSW. */ + if (ret == 0) + ret = ctrlr->bulk (ep, sizeof (csw_t), (u8 *) csw, 1); + + if (ret < 0) { clear_stall (ep); - if (ep->dev->controller->bulk - (ep, sizeof (csw_t), (u8 *) csw, 1) < 0) { + if (ctrlr->bulk (ep, sizeof (csw_t), (u8 *) csw, 1) < 0) { return reset_transport (ep->dev); } } - if (csw->dCSWTag != tag) { + if (ret != sizeof(csw_t) || csw->dCSWTag != tag || + csw->dCSWSignature != csw_signature) { + usb_debug ("MSC: received malformed CSW\n"); return reset_transport (ep->dev); } return MSC_COMMAND_OK; @@ -591,14 +604,6 @@ usb_msc_test_unit_ready (usbdev_t *dev) void usb_msc_init (usbdev_t *dev) { - int i; - - /* init .data before setting .destroy */ - dev->data = NULL; - - dev->destroy = usb_msc_destroy; - dev->poll = usb_msc_poll; - configuration_descriptor_t *cd = (configuration_descriptor_t *) dev->configuration; interface_descriptor_t *interface = @@ -625,6 +630,19 @@ usb_msc_init (usbdev_t *dev) return; } + usb_msc_force_init (dev, 0); +} + +void usb_msc_force_init (usbdev_t *dev, u32 quirks) +{ + int i; + + /* init .data before setting .destroy */ + dev->data = NULL; + + dev->destroy = usb_msc_destroy; + dev->poll = usb_msc_poll; + dev->data = malloc (sizeof (usbmsc_inst_t)); if (!dev->data) fatal("Not enough memory for USB MSC device.\n"); @@ -632,6 +650,7 @@ usb_msc_init (usbdev_t *dev) MSC_INST (dev)->bulk_in = 0; MSC_INST (dev)->bulk_out = 0; MSC_INST (dev)->usbdisk_created = 0; + MSC_INST (dev)->quirks = quirks; for (i = 1; i <= dev->num_endp; i++) { if (dev->endpoints[i].endpoint == 0) diff --git a/payloads/libpayload/drivers/usb/xhci_devconf.c b/payloads/libpayload/drivers/usb/xhci_devconf.c index 99e3037304..3f50caa512 100644 --- a/payloads/libpayload/drivers/usb/xhci_devconf.c +++ b/payloads/libpayload/drivers/usb/xhci_devconf.c @@ -267,7 +267,7 @@ _free_ic_return: static int xhci_finish_hub_config(usbdev_t *const dev, inputctx_t *const ic) { - int type = dev->speed == SUPER_SPEED ? 0x2a : 0x29; /* similar enough */ + int type = is_usb_speed_ss(dev->speed) ? 0x2a : 0x29; /* similar enough */ hub_descriptor_t desc; if (get_descriptor(dev, gen_bmRequestType(device_to_host, class_type, diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 57a3afc6b1..80bfaae6bf 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -445,6 +445,25 @@ static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); } /** @} */ +/** + * @defgroup mmio MMIO helper functions + * @{ + */ +#if !CONFIG(LP_ARCH_MIPS) +void buffer_from_fifo32(void *buffer, size_t size, void *fifo, + int fifo_stride, int fifo_width); +void buffer_to_fifo32_prefix(void *buffer, u32 prefix, int prefsz, size_t size, + void *fifo, int fifo_stride, int fifo_width); +static inline void buffer_to_fifo32(void *buffer, size_t size, void *fifo, + int fifo_stride, int fifo_width) +{ + buffer_to_fifo32_prefix(buffer, size, 0, 0, fifo, + fifo_stride, fifo_width); +} +#endif +/** @} */ + + /** * @defgroup hash Hashing functions * @{ diff --git a/payloads/libpayload/include/usb/usb.h b/payloads/libpayload/include/usb/usb.h index db7ec57d57..8505c4f60b 100644 --- a/payloads/libpayload/include/usb/usb.h +++ b/payloads/libpayload/include/usb/usb.h @@ -210,6 +210,7 @@ typedef enum { LOW_SPEED = 1, HIGH_SPEED = 2, SUPER_SPEED = 3, + SUPER_SPEED_PLUS = 4, } usb_speed; struct usbdev { @@ -293,6 +294,7 @@ int get_descriptor (usbdev_t *dev, int rtype, int descType, int descIdx, int set_configuration (usbdev_t *dev); int clear_feature (usbdev_t *dev, int endp, int feature, int rtype); int clear_stall (endpoint_t *ep); +_Bool is_usb_speed_ss(usb_speed speed); void usb_nop_init (usbdev_t *dev); void usb_hub_init (usbdev_t *dev); diff --git a/payloads/libpayload/include/usb/usbmsc.h b/payloads/libpayload/include/usb/usbmsc.h index f4562a56d5..8786586e51 100644 --- a/payloads/libpayload/include/usb/usbmsc.h +++ b/payloads/libpayload/include/usb/usbmsc.h @@ -34,13 +34,24 @@ typedef struct { unsigned int numblocks; endpoint_t *bulk_in; endpoint_t *bulk_out; - u8 usbdisk_created; + u8 quirks : 7; + u8 usbdisk_created : 1; s8 ready; u8 lun; u8 num_luns; void *data; /* For use by consumers of libpayload. */ } usbmsc_inst_t; +/* Possible values for quirks field. */ +enum { + /* Don't check for LUNs (force assumption that there's only one LUN). */ + USB_MSC_QUIRK_NO_LUNS = 1 << 0, + /* Never do a BULK_ONLY reset, just continue. This means that the device + cannot recover from phase errors and won't detach automatically for + unrecoverable errors. Do not use unless you have to. */ + USB_MSC_QUIRK_NO_RESET = 1 << 1, +}; + /* Possible values for ready field. */ enum { USB_MSC_DETACHED = -1, /* Disk detached or out to lunch. */ @@ -56,4 +67,8 @@ typedef enum { cbw_direction_data_in = 0x80, cbw_direction_data_out = 0 int readwrite_blocks_512 (usbdev_t *dev, int start, int n, cbw_direction dir, u8 *buf); int readwrite_blocks (usbdev_t *dev, int start, int n, cbw_direction dir, u8 *buf); +/* Force a device to enumerate as MSC, without checking class/protocol types. + It must still have a bulk endpoint pair and respond to MSC commands. */ +void usb_msc_force_init (usbdev_t *dev, u32 quirks); + #endif diff --git a/payloads/libpayload/libc/lib.c b/payloads/libpayload/libc/lib.c index bead1f801b..081d7dd0e2 100644 --- a/payloads/libpayload/libc/lib.c +++ b/payloads/libpayload/libc/lib.c @@ -27,6 +27,7 @@ * SUCH DAMAGE. */ +#include #include /* @@ -125,3 +126,54 @@ char *getenv(const char *name) { return NULL; } + +#if !CONFIG(LP_ARCH_MIPS) +/* + * Reads a transfer buffer from 32-bit FIFO registers. fifo_stride is the + * distance in bytes between registers (e.g. pass 4 for a normal array of 32-bit + * registers or 0 to read everything from the same register). fifo_width is + * the amount of bytes read per register (can be 1 through 4). + */ +void buffer_from_fifo32(void *buffer, size_t size, void *fifo, + int fifo_stride, int fifo_width) +{ + u8 *p = buffer; + int i, j; + + assert(fifo_width > 0 && fifo_width <= sizeof(u32) && + fifo_stride % sizeof(u32) == 0); + + for (i = 0; i < size; i += fifo_width, fifo += fifo_stride) { + u32 val = read32(fifo); + for (j = 0; j < MIN(size - i, fifo_width); j++) + *p++ = (u8)(val >> (j * 8)); + } +} + +/* + * Version of buffer_to_fifo32() that can prepend a prefix of up to fifo_width + * size to the transfer. This is often useful for protocols where a command word + * precedes the actual payload data. The prefix must be packed in the low-order + * bytes of the 'prefix' u32 parameter and any high-order bytes exceeding prefsz + * must be 0. Note that 'size' counts total bytes written, including 'prefsz'. + */ +void buffer_to_fifo32_prefix(void *buffer, u32 prefix, int prefsz, size_t size, + void *fifo, int fifo_stride, int fifo_width) +{ + u8 *p = buffer; + int i, j = prefsz; + + assert(fifo_width > 0 && fifo_width <= sizeof(u32) && + fifo_stride % sizeof(u32) == 0 && prefsz <= fifo_width); + + uint32_t val = prefix; + for (i = 0; i < size; i += fifo_width, fifo += fifo_stride) { + for (; j < MIN(size - i, fifo_width); j++) + val |= *p++ << (j * 8); + write32(fifo, val); + val = 0; + j = 0; + } + +} +#endif diff --git a/payloads/linuxcheck/Makefile b/payloads/linuxcheck/Makefile index b967369e1a..838c90df0c 100644 --- a/payloads/linuxcheck/Makefile +++ b/payloads/linuxcheck/Makefile @@ -3,7 +3,7 @@ XCOMPILE=$(LIBPAYLOAD_DIR)/libpayload.xcompile # build libpayload and put .config file in $(CURDIR) instead of ../libpayload # to avoid pollute the libpayload source directory and possible conflicts LPOPTS=obj="$(CURDIR)/build" DESTDIR="$(CURDIR)" DOTCONFIG="$(CURDIR)/.config" -CFLAGS += -Wall -Werror -Os -ffreestanding -nostdinc -nostdlib +CFLAGS += -Wall -Wvla -Werror -Os -ffreestanding -nostdinc -nostdlib ifeq ($(CONFIG_ARCH_X86),y) TARGETARCH = i386 endif diff --git a/payloads/nvramcui/Makefile b/payloads/nvramcui/Makefile index c6a9cd0cf4..bf7053b9a6 100644 --- a/payloads/nvramcui/Makefile +++ b/payloads/nvramcui/Makefile @@ -3,7 +3,7 @@ XCOMPILE=$(LIBPAYLOAD_DIR)/libpayload.xcompile # build libpayload and put .config file in $(CURDIR) instead of ../libpayload # to avoid pollute the libpayload source directory and possible conflicts LPOPTS=obj="$(CURDIR)/build" DESTDIR="$(CURDIR)" DOTCONFIG="$(CURDIR)/.config" -CFLAGS += -Wall -Werror -Os -ffreestanding -nostdinc -nostdlib +CFLAGS += -Wall -Wvla -Werror -Os -ffreestanding -nostdinc -nostdlib all: nvramcui.elf diff --git a/src/Kconfig b/src/Kconfig index 6288d0bc74..a1c016e30f 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -484,12 +484,7 @@ source "src/console/Kconfig" config HAVE_ACPI_RESUME bool default n - -config ACPI_HUGE_LOWMEM_BACKUP - bool - default n - help - On S3 resume path, backup low memory from RAMBASE..RAMTOP in CBMEM. + depends on RELOCATABLE_RAMSTAGE config RESUME_PATH_SAME_AS_BOOT bool @@ -991,7 +986,7 @@ config X86EMU_DEBUG_IO config X86EMU_DEBUG_TIMINGS bool "Output timing information" default n - depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER + depends on X86EMU_DEBUG && HAVE_MONOTONIC_TIMER help Print timing information needed by i915tool. diff --git a/src/arch/arm/Kconfig b/src/arch/arm/Kconfig index 6d9cc7820a..47c333bf6a 100644 --- a/src/arch/arm/Kconfig +++ b/src/arch/arm/Kconfig @@ -1,24 +1,22 @@ config ARCH_ARM bool - default n config ARCH_BOOTBLOCK_ARM bool - default n select ARCH_ARM select C_ENVIRONMENT_BOOTBLOCK config ARCH_VERSTAGE_ARM bool - default n + select ARCH_ARM config ARCH_ROMSTAGE_ARM bool - default n + select ARCH_ARM config ARCH_RAMSTAGE_ARM bool - default n + select ARCH_ARM source src/arch/arm/armv4/Kconfig source src/arch/arm/armv7/Kconfig diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index 06adfe454a..508b0a80f8 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -2,11 +2,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012-2013 The ChromiumOS Authors -## Copyright (C) 2012 Alexandru Gagniuc -## Copyright (C) 2009-2010 coresystems GmbH -## Copyright (C) 2009 Ronald G. Minnich -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/armv4/Kconfig b/src/arch/arm/armv4/Kconfig index aa5fab9bcd..0b501657a4 100644 --- a/src/arch/arm/armv4/Kconfig +++ b/src/arch/arm/armv4/Kconfig @@ -1,15 +1,15 @@ config ARCH_BOOTBLOCK_ARMV4 - def_bool n + bool select ARCH_BOOTBLOCK_ARM config ARCH_VERSTAGE_ARMV4 - def_bool n + bool select ARCH_VERSTAGE_ARM config ARCH_ROMSTAGE_ARMV4 - def_bool n + bool select ARCH_ROMSTAGE_ARM config ARCH_RAMSTAGE_ARMV4 - def_bool n + bool select ARCH_RAMSTAGE_ARM diff --git a/src/arch/arm/armv4/Makefile.inc b/src/arch/arm/armv4/Makefile.inc index e8e49a60a8..2cc5ebba8c 100644 --- a/src/arch/arm/armv4/Makefile.inc +++ b/src/arch/arm/armv4/Makefile.inc @@ -2,8 +2,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 The ChromiumOS Authors -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/armv4/bootblock.S b/src/arch/arm/armv4/bootblock.S index 0391ebf1ac..cf37647e27 100644 --- a/src/arch/arm/armv4/bootblock.S +++ b/src/arch/arm/armv4/bootblock.S @@ -1,17 +1,5 @@ /* - * Early initialization code for ARM architecture. - * - * This file is based off of the OMAP3530/ARM Cortex start.S file from Das - * U-Boot, which itself got the file from armboot. - * - * Copyright (c) 2004 Texas Instruments - * Copyright (c) 2001 Marius Gröger - * Copyright (c) 2002 Alex Züpke - * Copyright (c) 2002 Gary Jennejohn - * Copyright (c) 2003 Richard Woodruff - * Copyright (c) 2003 Kshitij - * Copyright (c) 2006-2008 Syed Mohammed Khasim - * Copyright (c) 2013 The Chromium OS Authors + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -22,6 +10,11 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Early initialization code for ARM architecture. + * + * This file is based off of the OMAP3530/ARM Cortex start.S file from Das + * U-Boot, which itself got the file from armboot. */ #include diff --git a/src/arch/arm/armv7/Kconfig b/src/arch/arm/armv7/Kconfig index 3734426c0f..6d5fb9ee71 100644 --- a/src/arch/arm/armv7/Kconfig +++ b/src/arch/arm/armv7/Kconfig @@ -1,37 +1,39 @@ config ARCH_BOOTBLOCK_ARMV7 - def_bool n + bool select ARCH_BOOTBLOCK_ARM config ARCH_VERSTAGE_ARMV7 - def_bool n + bool select ARCH_VERSTAGE_ARM config ARCH_ROMSTAGE_ARMV7 - def_bool n + bool select ARCH_ROMSTAGE_ARM config ARCH_RAMSTAGE_ARMV7 - def_bool n + bool select ARCH_RAMSTAGE_ARM + config ARCH_BOOTBLOCK_ARMV7_M - def_bool n + bool select ARCH_BOOTBLOCK_ARM + config ARCH_VERSTAGE_ARMV7_M - def_bool n + bool select ARCH_VERSTAGE_ARM config ARCH_BOOTBLOCK_ARMV7_R - def_bool n + bool select ARCH_BOOTBLOCK_ARM config ARCH_VERSTAGE_ARMV7_R - def_bool n + bool select ARCH_VERSTAGE_ARM config ARCH_ROMSTAGE_ARMV7_R - def_bool n + bool select ARCH_ROMSTAGE_ARM config ARCH_RAMSTAGE_ARMV7_R - def_bool n + bool select ARCH_RAMSTAGE_ARM diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index 1d3ae52f54..58592a0818 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -2,8 +2,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 The ChromiumOS Authors -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/armv7/bootblock.S b/src/arch/arm/armv7/bootblock.S index e2d76a1463..da2671c519 100644 --- a/src/arch/arm/armv7/bootblock.S +++ b/src/arch/arm/armv7/bootblock.S @@ -1,17 +1,5 @@ /* - * Early initialization code for ARMv7 architecture. - * - * This file is based off of the OMAP3530/ARM Cortex start.S file from Das - * U-Boot, which itself got the file from armboot. - * - * Copyright (c) 2004 Texas Instruments - * Copyright (c) 2001 Marius Gröger - * Copyright (c) 2002 Alex Züpke - * Copyright (c) 2002 Gary Jennejohn - * Copyright (c) 2003 Richard Woodruff - * Copyright (c) 2003 Kshitij - * Copyright (c) 2006-2008 Syed Mohammed Khasim - * Copyright (c) 2013 The Chromium OS Authors + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -22,6 +10,11 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Early initialization code for ARMv7 architecture. + * + * This file is based off of the OMAP3530/ARM Cortex start.S file from Das + * U-Boot, which itself got the file from armboot. */ #include diff --git a/src/arch/arm/armv7/cpu.S b/src/arch/arm/armv7/cpu.S index 1f6cd5bc25..3f90c0b611 100644 --- a/src/arch/arm/armv7/cpu.S +++ b/src/arch/arm/armv7/cpu.S @@ -1,7 +1,5 @@ /* - * Optimized assembly for low-level CPU operations on ARMv7 processors. - * - * Cache flushing code based off sys/arch/arm/arm/cpufunc_asm_armv7.S in NetBSD + * This file is part of the coreboot project. * * Copyright (c) 2010 Per Odlund * Copyright (c) 2014 Google Inc. @@ -28,6 +26,10 @@ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. + * + * Optimized assembly for low-level CPU operations on ARMv7 processors. + * + * Cache flushing code based off sys/arch/arm/arm/cpufunc_asm_armv7.S in NetBSD */ #include diff --git a/src/arch/arm/armv7/exception.c b/src/arch/arm/armv7/exception.c index 4fac0bcd3c..d6891b0b8d 100644 --- a/src/arch/arm/armv7/exception.c +++ b/src/arch/arm/armv7/exception.c @@ -1,5 +1,5 @@ /* - * This file is part of the libpayload project. + * This file is part of the coreboot project. * * Copyright 2013 Google Inc. * diff --git a/src/arch/arm/armv7/exception_asm.S b/src/arch/arm/armv7/exception_asm.S index f54cd85f9f..6aa4188abc 100644 --- a/src/arch/arm/armv7/exception_asm.S +++ b/src/arch/arm/armv7/exception_asm.S @@ -1,5 +1,5 @@ /* - * This file is part of the libpayload project. + * This file is part of the coreboot project. * * Copyright 2013 Google Inc. * diff --git a/src/arch/arm/armv7/exception_mr.c b/src/arch/arm/armv7/exception_mr.c index d76cc6a739..01e834ea47 100644 --- a/src/arch/arm/armv7/exception_mr.c +++ b/src/arch/arm/armv7/exception_mr.c @@ -1,5 +1,5 @@ /* - * This file is part of the libpayload project. + * This file is part of the coreboot project. * * Copyright 2013 Google Inc. * diff --git a/src/arch/arm/armv7/thread.c b/src/arch/arm/armv7/thread.c index bcf692320c..4e82be708c 100644 --- a/src/arch/arm/armv7/thread.c +++ b/src/arch/arm/armv7/thread.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/asmlib.h b/src/arch/arm/asmlib.h index 0d515517cf..cae4081efd 100644 --- a/src/arch/arm/asmlib.h +++ b/src/arch/arm/asmlib.h @@ -1,9 +1,5 @@ /* - * arch/arm/asmlib.h - * - * Adapted from Linux arch/arm/include/assembler.h - * - * Copyright (C) 1996-2000 Russell King + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -17,6 +13,8 @@ * This file contains arm architecture specific defines * for the different processors. * + * Adapted from Linux arch/arm/include/assembler.h + * * Do not include any C declarations in this file - it is included by * assembler source. */ diff --git a/src/arch/arm/boot.c b/src/arch/arm/boot.c index 1767fe04c2..9d1e4cde5f 100644 --- a/src/arch/arm/boot.c +++ b/src/arch/arm/boot.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/div0.c b/src/arch/arm/div0.c index e474f73d6e..fa3bf7f090 100644 --- a/src/arch/arm/div0.c +++ b/src/arch/arm/div0.c @@ -1,6 +1,5 @@ /* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/arch/arm/eabi_compat.c b/src/arch/arm/eabi_compat.c index 15f7d36667..45f4651a03 100644 --- a/src/arch/arm/eabi_compat.c +++ b/src/arch/arm/eabi_compat.c @@ -1,7 +1,5 @@ /* - * Utility functions needed for (some) EABI conformant tool chains. - * - * (C) Copyright 2009 Wolfgang Denk + * This file is part of the coreboot project. * * This program is Free Software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -12,6 +10,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Utility functions needed for (some) EABI conformant tool chains. */ #include diff --git a/src/arch/arm/include/arch/asm.h b/src/arch/arm/include/arch/asm.h index b148d12b80..b9591b6b86 100644 --- a/src/arch/arm/include/arch/asm.h +++ b/src/arch/arm/include/arch/asm.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/include/arch/cbconfig.h b/src/arch/arm/include/arch/cbconfig.h index 9467f52646..35c1387895 100644 --- a/src/arch/arm/include/arch/cbconfig.h +++ b/src/arch/arm/include/arch/cbconfig.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/include/arch/clock.h b/src/arch/arm/include/arch/clock.h index 77d09d8ef0..248da0607a 100644 --- a/src/arch/arm/include/arch/clock.h +++ b/src/arch/arm/include/arch/clock.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/include/arch/early_variables.h b/src/arch/arm/include/arch/early_variables.h index c469446e86..7002a8805e 100644 --- a/src/arch/arm/include/arch/early_variables.h +++ b/src/arch/arm/include/arch/early_variables.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -20,7 +18,9 @@ static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) -#define car_sync_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) +#define car_get_ptr car_get_var +#define car_set_ptr car_set_var + #endif diff --git a/src/arch/arm/include/arch/header.ld b/src/arch/arm/include/arch/header.ld index 89473109f0..5d93673579 100644 --- a/src/arch/arm/include/arch/header.ld +++ b/src/arch/arm/include/arch/header.ld @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/include/arch/memlayout.h b/src/arch/arm/include/arch/memlayout.h index 4ba2bf8cf2..26b8ef4708 100644 --- a/src/arch/arm/include/arch/memlayout.h +++ b/src/arch/arm/include/arch/memlayout.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/include/arch/pci_ops.h b/src/arch/arm/include/arch/pci_ops.h index 75bb20e05f..4cb05e7c88 100644 --- a/src/arch/arm/include/arch/pci_ops.h +++ b/src/arch/arm/include/arch/pci_ops.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/include/arch/stages.h b/src/arch/arm/include/arch/stages.h index 68a3bd116d..3841265341 100644 --- a/src/arch/arm/include/arch/stages.h +++ b/src/arch/arm/include/arch/stages.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 The ChromiumOS Authors - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/include/armv4/arch/cpu.h b/src/arch/arm/include/armv4/arch/cpu.h index d32bf58c2a..3a27743cbf 100644 --- a/src/arch/arm/include/armv4/arch/cpu.h +++ b/src/arch/arm/include/armv4/arch/cpu.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2012 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/include/armv4/arch/mmio.h b/src/arch/arm/include/armv4/arch/mmio.h index ad89ef5d12..2c43789abf 100644 --- a/src/arch/arm/include/armv4/arch/mmio.h +++ b/src/arch/arm/include/armv4/arch/mmio.h @@ -1,9 +1,5 @@ /* - * Originally imported from linux/include/asm-arm/io.h. This file has changed - * substantially since then. - * - * Copyright 2013 Google Inc. - * Copyright (C) 1996-2000 Russell King + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -14,16 +10,8 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * Modifications: - * 08-Apr-2013 G Replaced several macros with inlines for type safety. - * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both - * constant addresses and variable addresses. - * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture - * specific IO header files. - * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. - * 04-Apr-1999 PJB Added check_signature. - * 12-Dec-1999 RMK More cleanups - * 18-Jun-2000 RMK Removed virt_to_* and friends definitions + * Originally imported from linux/include/asm-arm/io.h. This file has changed + * substantially since then. */ #ifndef __ARCH_MMIO_H__ diff --git a/src/arch/arm/include/armv7.h b/src/arch/arm/include/armv7.h index bec7fd7033..626e6083f3 100644 --- a/src/arch/arm/include/armv7.h +++ b/src/arch/arm/include/armv7.h @@ -1,7 +1,5 @@ /* - * (C) Copyright 2010 - * Texas Instruments, - * Aneesh V + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/arch/arm/include/armv7/arch/cpu.h b/src/arch/arm/include/armv7/arch/cpu.h index 22b3fb443d..0377e2a5c9 100644 --- a/src/arch/arm/include/armv7/arch/cpu.h +++ b/src/arch/arm/include/armv7/arch/cpu.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2012 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -17,12 +15,10 @@ #define __ARCH_CPU_H__ #include +#include #define asmlinkage -#if !defined(__PRE_RAM__) -#include - struct cpu_driver { struct device_operations *ops; const struct cpu_device_id *id_table; @@ -34,8 +30,6 @@ struct cpuinfo_arm { uint8_t arm_model; }; -#endif - /* Primitives for CPU and MP cores. */ /* read Main Id register (MIDR) */ diff --git a/src/arch/arm/include/armv7/arch/exception.h b/src/arch/arm/include/armv7/arch/exception.h index 57076bd57b..df3930977b 100644 --- a/src/arch/arm/include/armv7/arch/exception.h +++ b/src/arch/arm/include/armv7/arch/exception.h @@ -1,5 +1,5 @@ /* - * This file is part of the libpayload project. + * This file is part of the coreboot project. * * Copyright 2013 Google Inc. * diff --git a/src/arch/arm/include/armv7/arch/mmio.h b/src/arch/arm/include/armv7/arch/mmio.h index b245b264fd..87f68715e8 100644 --- a/src/arch/arm/include/armv7/arch/mmio.h +++ b/src/arch/arm/include/armv7/arch/mmio.h @@ -1,9 +1,5 @@ /* - * Originally imported from linux/include/asm-arm/io.h. This file has changed - * substantially since then. - * - * Copyright 2013 Google Inc. - * Copyright (C) 1996-2000 Russell King + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -14,16 +10,8 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * Modifications: - * 08-Apr-2013 G Replaced several macros with inlines for type safety. - * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both - * constant addresses and variable addresses. - * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture - * specific IO header files. - * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. - * 04-Apr-1999 PJB Added check_signature. - * 12-Dec-1999 RMK More cleanups - * 18-Jun-2000 RMK Removed virt_to_* and friends definitions + * Originally imported from linux/include/asm-arm/io.h. This file has changed + * substantially since then. */ #ifndef __ARCH_MMIO_H__ diff --git a/src/arch/arm/include/clocks.h b/src/arch/arm/include/clocks.h index 60afb447f7..4904b6e96a 100644 --- a/src/arch/arm/include/clocks.h +++ b/src/arch/arm/include/clocks.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011 The Chromium OS Authors. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/arch/arm/libgcc/Makefile.inc b/src/arch/arm/libgcc/Makefile.inc index 9a8d4fca53..2d0f6a81da 100644 --- a/src/arch/arm/libgcc/Makefile.inc +++ b/src/arch/arm/libgcc/Makefile.inc @@ -2,8 +2,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 The ChromiumOS Authors -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/libgcc/ashldi3.S b/src/arch/arm/libgcc/ashldi3.S index 1e3aefa209..473e15f3f3 100644 --- a/src/arch/arm/libgcc/ashldi3.S +++ b/src/arch/arm/libgcc/ashldi3.S @@ -1,5 +1,5 @@ -/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005 - Free Software Foundation, Inc. +/* +This file is part of the coreboot project. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the diff --git a/src/arch/arm/libgcc/lib1funcs.S b/src/arch/arm/libgcc/lib1funcs.S index a64218572d..5c2a6ade17 100644 --- a/src/arch/arm/libgcc/lib1funcs.S +++ b/src/arch/arm/libgcc/lib1funcs.S @@ -1,12 +1,5 @@ /* - * linux/arch/arm/lib/lib1funcs.S: Optimized ARM division routines - * - * Author: Nicolas Pitre - * - contributed to gcc-3.4 on Sep 30, 2003 - * - adapted for the Linux kernel on Oct 2, 2003 - */ - -/* Copyright 1995, 1996, 1998, 1999, 2000, 2003 Free Software Foundation, Inc. +This file is part of the coreboot project. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the @@ -28,6 +21,10 @@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. */ +/* + * linux/arch/arm/lib/lib1funcs.S: Optimized ARM division routines + */ + #if defined __GNUC__ diff --git a/src/arch/arm/libgcc/lshrdi3.S b/src/arch/arm/libgcc/lshrdi3.S index 119ec45af9..5e67690010 100644 --- a/src/arch/arm/libgcc/lshrdi3.S +++ b/src/arch/arm/libgcc/lshrdi3.S @@ -1,5 +1,5 @@ -/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005 - Free Software Foundation, Inc. +/* +This file is part of the coreboot project. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the diff --git a/src/arch/arm/libgcc/muldi3.S b/src/arch/arm/libgcc/muldi3.S index 1d783ec87c..c7584745b9 100644 --- a/src/arch/arm/libgcc/muldi3.S +++ b/src/arch/arm/libgcc/muldi3.S @@ -1,18 +1,16 @@ /* - * linux/arch/arm/lib/muldi3.S + * This file is part of the coreboot project. * - * Author: Nicolas Pitre - * Created: Oct 19, 2005 - * Copyright: Monta Vista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Based on linux/arch/arm/lib/muldi3.S */ #if defined __GNUC__ diff --git a/src/arch/arm/libgcc/ucmpdi2.S b/src/arch/arm/libgcc/ucmpdi2.S index 8b21043158..771e93b502 100644 --- a/src/arch/arm/libgcc/ucmpdi2.S +++ b/src/arch/arm/libgcc/ucmpdi2.S @@ -1,18 +1,16 @@ /* - * linux/arch/arm/lib/ucmpdi2.S + * This file is part of the coreboot project. * - * Author: Nicolas Pitre - * Created: Oct 19, 2005 - * Copyright: Monta Vista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Based on linux/arch/arm/lib/ucmpdi2.S */ #if defined __GNUC__ diff --git a/src/arch/arm/libgcc/uldivmod.S b/src/arch/arm/libgcc/uldivmod.S index 521a5d1e33..ecbeccfe4b 100644 --- a/src/arch/arm/libgcc/uldivmod.S +++ b/src/arch/arm/libgcc/uldivmod.S @@ -1,4 +1,6 @@ /* + * This file is part of the coreboot project. + * * Copyright 2010, Google Inc. * All rights reserved. * diff --git a/src/arch/arm/memcpy.S b/src/arch/arm/memcpy.S index fe4f40076f..19592dbfaf 100644 --- a/src/arch/arm/memcpy.S +++ b/src/arch/arm/memcpy.S @@ -1,18 +1,16 @@ /* - * linux/arch/arm/lib/memcpy.S + * This file is part of the coreboot project. * - * Author: Nicolas Pitre - * Created: Sep 28, 2005 - * Copyright: MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Based on linux/arch/arm/lib/memcpy.S */ #include diff --git a/src/arch/arm/memmove.S b/src/arch/arm/memmove.S index f4da9e8f19..3b5681ced2 100644 --- a/src/arch/arm/memmove.S +++ b/src/arch/arm/memmove.S @@ -1,18 +1,16 @@ /* - * linux/arch/arm/lib/memmove.S + * This file is part of the coreboot project. * - * Author: Nicolas Pitre - * Created: Sep 28, 2005 - * Copyright: (C) MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Based on linux/arch/arm/lib/memmove.S */ #include diff --git a/src/arch/arm/memset.S b/src/arch/arm/memset.S index 9a3bc72399..7d71a88bc3 100644 --- a/src/arch/arm/memset.S +++ b/src/arch/arm/memset.S @@ -1,7 +1,5 @@ /* - * linux/arch/arm/lib/memset.S - * - * Copyright (C) 1995-2000 Russell King + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -12,7 +10,9 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * ASM optimised string functions + * Based on linux/arch/arm/lib/memset.S + * + * ASM optimised string functions */ #include diff --git a/src/arch/arm/stages.c b/src/arch/arm/stages.c index 22ade638ae..c9f5744f75 100644 --- a/src/arch/arm/stages.c +++ b/src/arch/arm/stages.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2012 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c index 682715f8c1..ab2b579f0a 100644 --- a/src/arch/arm/tables.c +++ b/src/arch/arm/tables.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2005 Steve Magnani - * Copyright (C) 2008-2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/Kconfig b/src/arch/arm64/Kconfig index 71c9f042f5..3d1d1843e0 100644 --- a/src/arch/arm64/Kconfig +++ b/src/arch/arm64/Kconfig @@ -1,27 +1,27 @@ config ARCH_ARM64 bool - default n config ARCH_BOOTBLOCK_ARM64 bool - default n select ARCH_ARM64 select C_ENVIRONMENT_BOOTBLOCK config ARCH_VERSTAGE_ARM64 bool - default n + select ARCH_ARM64 config ARCH_ROMSTAGE_ARM64 bool - default n + select ARCH_ARM64 config ARCH_RAMSTAGE_ARM64 bool - default n + select ARCH_ARM64 source src/arch/arm64/armv8/Kconfig +if ARCH_ARM64 + config ARM64_USE_ARCH_TIMER bool default n @@ -58,3 +58,5 @@ config ARM64_A53_ERRATUM_843419 incorrect address calculations in rare cases. This option enables a linker workaround to avoid those cases if your toolchain supports it. Should be selected automatically by SoCs that are affected. + +endif # if ARCH_ARM64 diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 6bb7196805..1aee6b83f7 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -2,12 +2,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. -## Copyright (C) 2012-2013 The ChromiumOS Authors -## Copyright (C) 2012 Alexandru Gagniuc -## Copyright (C) 2009-2010 coresystems GmbH -## Copyright (C) 2009 Ronald G. Minnich -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. @@ -107,6 +101,7 @@ romstage-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c romstage-y += memset.S romstage-y += memcpy.S romstage-y += memmove.S +romstage-y += ramdetect.c romstage-y += romstage.c romstage-y += transition.c transition_asm.S @@ -131,11 +126,12 @@ ramstage-y += div0.c ramstage-y += eabi_compat.c ramstage-y += boot.c ramstage-y += tables.c +ramstage-y += ramdetect.c ramstage-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c ramstage-y += memset.S ramstage-y += memcpy.S ramstage-y += memmove.S -ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += arm_tf.c +ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31.c ramstage-y += transition.c transition_asm.S ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c diff --git a/src/arch/arm64/arch_timer.c b/src/arch/arm64/arch_timer.c index e7f3732b0e..2db235a5da 100644 --- a/src/arch/arm64/arch_timer.c +++ b/src/arch/arm64/arch_timer.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. diff --git a/src/arch/arm64/arm_tf.c b/src/arch/arm64/arm_tf.c deleted file mode 100644 index 291e4eef3e..0000000000 --- a/src/arch/arm64/arm_tf.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * TODO: Many of these structures are currently unused. Better not fill them out - * to make future changes fail fast, rather than try to come up with content - * that might turn out to not make sense. Implement later as required. - * -static image_info_t bl31_image_info; -static image_info_t bl32_image_info; -static image_info_t bl33_image_info; - */ -static entry_point_info_t bl32_ep_info; -static entry_point_info_t bl33_ep_info; -static bl31_params_t bl31_params; - -void __weak *soc_get_bl31_plat_params(bl31_params_t *params) -{ - /* Default weak implementation. */ - return NULL; -} - -void arm_tf_run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr) -{ - struct prog bl31 = PROG_INIT(PROG_BL31, CONFIG_CBFS_PREFIX"/bl31"); - void (*bl31_entry)(bl31_params_t *params, void *plat_params) = NULL; - - if (prog_locate(&bl31)) - die("BL31 not found"); - - if (!selfload_check(&bl31, BM_MEM_BL31)) - die("BL31 load failed"); - bl31_entry = prog_entry(&bl31); - - SET_PARAM_HEAD(&bl31_params, PARAM_BL31, VERSION_1, 0); - - if (CONFIG(ARM64_USE_SECURE_OS)) { - struct prog bl32 = PROG_INIT(PROG_BL32, - CONFIG_CBFS_PREFIX"/secure_os"); - - if (prog_locate(&bl32)) - die("BL32 not found"); - - if (cbfs_prog_stage_load(&bl32)) - die("BL32 load failed"); - - SET_PARAM_HEAD(&bl32_ep_info, PARAM_EP, VERSION_1, - PARAM_EP_SECURE); - bl32_ep_info.pc = (uintptr_t)prog_entry(&bl32); - bl32_ep_info.spsr = SPSR_EXCEPTION_MASK | - get_eret_el(EL1, SPSR_USE_L); - bl31_params.bl32_ep_info = &bl32_ep_info; - } - - bl31_params.bl33_ep_info = &bl33_ep_info; - - SET_PARAM_HEAD(&bl33_ep_info, PARAM_EP, VERSION_1, PARAM_EP_NON_SECURE); - bl33_ep_info.pc = payload_entry; - bl33_ep_info.spsr = payload_spsr; - bl33_ep_info.args.arg0 = payload_arg0; - - /* May update bl31_params if necessary. */ - void *bl31_plat_params = soc_get_bl31_plat_params(&bl31_params); - - /* MMU disable will flush cache, so passed params land in memory. */ - raw_write_daif(SPSR_EXCEPTION_MASK); - mmu_disable(); - bl31_entry(&bl31_params, bl31_plat_params); - die("BL31 returned!"); -} diff --git a/src/arch/arm64/armv8/Kconfig b/src/arch/arm64/armv8/Kconfig index 2070bea197..f70b529972 100644 --- a/src/arch/arm64/armv8/Kconfig +++ b/src/arch/arm64/armv8/Kconfig @@ -1,17 +1,17 @@ config ARCH_BOOTBLOCK_ARMV8_64 - def_bool n + bool select ARCH_BOOTBLOCK_ARM64 config ARCH_VERSTAGE_ARMV8_64 - def_bool n + bool select ARCH_VERSTAGE_ARM64 config ARCH_ROMSTAGE_ARMV8_64 - def_bool n + bool select ARCH_ROMSTAGE_ARM64 config ARCH_RAMSTAGE_ARMV8_64 - def_bool n + bool select ARCH_RAMSTAGE_ARM64 config ARCH_ARMV8_EXTENSION diff --git a/src/arch/arm64/armv8/Makefile.inc b/src/arch/arm64/armv8/Makefile.inc index 44ebdef815..127c5f114b 100644 --- a/src/arch/arm64/armv8/Makefile.inc +++ b/src/arch/arm64/armv8/Makefile.inc @@ -2,8 +2,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 The ChromiumOS Authors -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/armv8/bootblock.S b/src/arch/arm64/armv8/bootblock.S index 3950f5530d..64d2405895 100644 --- a/src/arch/arm64/armv8/bootblock.S +++ b/src/arch/arm64/armv8/bootblock.S @@ -1,7 +1,5 @@ /* - * Early initialization code for aarch64 (a.k.a. armv8) - * - * Copyright 2015 Google Inc. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -12,6 +10,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Early initialization code for aarch64 (a.k.a. armv8) */ #include diff --git a/src/arch/arm64/armv8/cpu.S b/src/arch/arm64/armv8/cpu.S index 935f1fe7bd..2bc4defde8 100644 --- a/src/arch/arm64/armv8/cpu.S +++ b/src/arch/arm64/armv8/cpu.S @@ -1,8 +1,5 @@ /* - * Optimized assembly for low-level CPU operations on ARM64 processors. - * - * Copyright (c) 2010 Per Odlund - * Copyright (c) 2014 Google Inc. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -12,6 +9,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Optimized assembly for low-level CPU operations on ARM64 processors. */ #include diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c index 58a35238f6..579e1040b4 100644 --- a/src/arch/arm64/armv8/exception.c +++ b/src/arch/arm64/armv8/exception.c @@ -1,5 +1,5 @@ /* - * This file is part of the libpayload project. + * This file is part of the coreboot project. * * Copyright 2013 Google Inc. * diff --git a/src/arch/arm64/bl31.c b/src/arch/arm64/bl31.c new file mode 100644 index 0000000000..c94b1d101e --- /dev/null +++ b/src/arch/arm64/bl31.c @@ -0,0 +1,125 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static entry_point_info_t bl32_ep_info = { + .h = { + .type = PARAM_EP, + .version = PARAM_VERSION_1, + .size = sizeof(bl32_ep_info), + .attr = EP_SECURE, + }, +}; +static entry_point_info_t bl33_ep_info = { + .h = { + .type = PARAM_EP, + .version = PARAM_VERSION_1, + .size = sizeof(bl33_ep_info), + .attr = EP_NON_SECURE, + }, +}; + +static bl_params_node_t bl32_params_node = { + .image_id = BL32_IMAGE_ID, + .ep_info = &bl32_ep_info, +}; +static bl_params_node_t bl33_params_node = { + .image_id = BL33_IMAGE_ID, + .ep_info = &bl33_ep_info, +}; + +static bl_params_t bl_params = { + .h = { + .type = PARAM_BL_PARAMS, + .version = PARAM_VERSION_2, + .size = sizeof(bl_params), + .attr = 0, + }, + .head = &bl33_params_node, +}; + +static struct bl_aux_param_header *bl_aux_params; + +/* Only works when using the default soc_get_bl31_plat_params() below. */ +void register_bl31_aux_param(struct bl_aux_param_header *param) +{ + param->next = (uintptr_t)bl_aux_params; + bl_aux_params = param; +} + +/* Default implementation. All newly added SoCs should use this if possible! */ +__weak void *soc_get_bl31_plat_params(void) +{ + static struct bl_aux_param_uint64 cbtable_param = { + .h = { .type = BL_AUX_PARAM_COREBOOT_TABLE, }, + }; + if (!cbtable_param.value) { + cbtable_param.value = (uint64_t)cbmem_find(CBMEM_ID_CBTABLE); + if (cbtable_param.value) + register_bl31_aux_param(&cbtable_param.h); + } + return bl_aux_params; +} + +void run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr) +{ + struct prog bl31 = PROG_INIT(PROG_BL31, CONFIG_CBFS_PREFIX"/bl31"); + void (*bl31_entry)(bl_params_t *params, void *plat_params) = NULL; + + if (prog_locate(&bl31)) + die("BL31 not found"); + + if (!selfload_check(&bl31, BM_MEM_BL31)) + die("BL31 load failed"); + bl31_entry = prog_entry(&bl31); + + if (CONFIG(ARM64_USE_SECURE_OS)) { + struct prog bl32 = PROG_INIT(PROG_BL32, + CONFIG_CBFS_PREFIX"/secure_os"); + + if (prog_locate(&bl32)) + die("BL32 not found"); + + if (cbfs_prog_stage_load(&bl32)) + die("BL32 load failed"); + + bl32_ep_info.pc = (uintptr_t)prog_entry(&bl32); + bl32_ep_info.spsr = SPSR_EXCEPTION_MASK | + get_eret_el(EL1, SPSR_USE_L); + bl33_params_node.next_params_info = &bl32_params_node; + } + + bl33_ep_info.pc = payload_entry; + bl33_ep_info.spsr = payload_spsr; + bl33_ep_info.args.arg0 = payload_arg0; + + void *bl31_plat_params = soc_get_bl31_plat_params(); + + /* MMU disable will flush cache, so passed params land in memory. */ + raw_write_daif(SPSR_EXCEPTION_MASK); + mmu_disable(); + bl31_entry(&bl_params, bl31_plat_params); + die("BL31 returned!"); +} diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index 7fbc525a18..c6df0ee02e 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -17,7 +15,7 @@ #include #include #include -#include +#include #include static void run_payload(struct prog *prog) @@ -30,7 +28,7 @@ static void run_payload(struct prog *prog) u64 payload_spsr = get_eret_el(EL2, SPSR_USE_L); if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE)) - arm_tf_run_bl31((u64)doit, (u64)arg, payload_spsr); + run_bl31((u64)doit, (u64)arg, payload_spsr); else transition_to_el2(doit, arg, payload_spsr); } diff --git a/src/arch/arm64/div0.c b/src/arch/arm64/div0.c index afd9dad1f3..daf1d920b0 100644 --- a/src/arch/arm64/div0.c +++ b/src/arch/arm64/div0.c @@ -1,6 +1,5 @@ /* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/arch/arm64/eabi_compat.c b/src/arch/arm64/eabi_compat.c index a6f40a4ea3..79b201758a 100644 --- a/src/arch/arm64/eabi_compat.c +++ b/src/arch/arm64/eabi_compat.c @@ -1,7 +1,5 @@ /* - * Utility functions needed for (some) EABI conformant tool chains. - * - * (C) Copyright 2009 Wolfgang Denk + * This file is part of the coreboot project. * * This program is Free Software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -12,6 +10,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Utility functions needed for (some) EABI conformant tool chains. */ int raise (int signum) __attribute__((used)); diff --git a/src/arch/arm64/fit_payload.c b/src/arch/arm64/fit_payload.c index 46bea23053..4ade1c719d 100644 --- a/src/arch/arm64/fit_payload.c +++ b/src/arch/arm64/fit_payload.c @@ -1,6 +1,5 @@ /* - * Copyright 2013 Google Inc. - * Copyright 2018 Facebook, Inc. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/arch/arm64/include/arch/acpi.h b/src/arch/arm64/include/arch/acpi.h index 6e16482580..4015d18021 100644 --- a/src/arch/arm64/include/arch/acpi.h +++ b/src/arch/arm64/include/arch/acpi.h @@ -1,15 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2004 SUSE LINUX AG - * Copyright (C) 2004 Nick Barker - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2015 Timothy Pearson , - * Raptor Engineering - * Copyright (C) 2016 Siemens AG - * (Written by Stefan Reinauer ) - * Copyright 2018-present Facebook, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/include/arch/asm.h b/src/arch/arm64/include/arch/asm.h index b52724faa8..7d3ad7e6b3 100644 --- a/src/arch/arm64/include/arch/asm.h +++ b/src/arch/arm64/include/arch/asm.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/include/arch/cbconfig.h b/src/arch/arm64/include/arch/cbconfig.h index 9467f52646..35c1387895 100644 --- a/src/arch/arm64/include/arch/cbconfig.h +++ b/src/arch/arm64/include/arch/cbconfig.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/include/arch/early_variables.h b/src/arch/arm64/include/arch/early_variables.h index c469446e86..7002a8805e 100644 --- a/src/arch/arm64/include/arch/early_variables.h +++ b/src/arch/arm64/include/arch/early_variables.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -20,7 +18,9 @@ static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) -#define car_sync_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) +#define car_get_ptr car_get_var +#define car_set_ptr car_set_var + #endif diff --git a/src/arch/arm64/include/arch/header.ld b/src/arch/arm64/include/arch/header.ld index 9d8764ea58..dcba068f9a 100644 --- a/src/arch/arm64/include/arch/header.ld +++ b/src/arch/arm64/include/arch/header.ld @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/include/arch/memlayout.h b/src/arch/arm64/include/arch/memlayout.h index a3fdd66e4f..984a09b86e 100644 --- a/src/arch/arm64/include/arch/memlayout.h +++ b/src/arch/arm64/include/arch/memlayout.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/include/arch/mpidr.h b/src/arch/arm64/include/arch/mpidr.h index 8d7651edc1..cc43309e4b 100644 --- a/src/arch/arm64/include/arch/mpidr.h +++ b/src/arch/arm64/include/arch/mpidr.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/include/arch/pci_ops.h b/src/arch/arm64/include/arch/pci_ops.h index 7a62d4aa10..65dd059529 100644 --- a/src/arch/arm64/include/arch/pci_ops.h +++ b/src/arch/arm64/include/arch/pci_ops.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/include/arch/stages.h b/src/arch/arm64/include/arch/stages.h index 2d6d583fce..d86172b2d0 100644 --- a/src/arch/arm64/include/arch/stages.h +++ b/src/arch/arm64/include/arch/stages.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 The ChromiumOS Authors - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/include/arch/transition.h b/src/arch/arm64/include/arch/transition.h index 290265edb0..8a49eed8de 100644 --- a/src/arch/arm64/include/arch/transition.h +++ b/src/arch/arm64/include/arch/transition.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/include/arm_tf.h b/src/arch/arm64/include/arm_tf.h deleted file mode 100644 index ea5a0f4d6d..0000000000 --- a/src/arch/arm64/include/arm_tf.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ARM_TF_H__ -#define __ARM_TF_H__ - -#include - -/* TODO: Pull in directly from ARM TF once its headers have been reorganized. */ -#include - -/* Load and enter BL31, set it up to exit to payload according to arguments. */ -void arm_tf_run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr); - -/* Return platform-specific bl31_plat_params. May update bl31_params. */ -void *soc_get_bl31_plat_params(bl31_params_t *bl31_params); - -#endif /* __ARM_TF_H__ */ diff --git a/src/arch/arm64/include/arm_tf_temp.h b/src/arch/arm64/include/arm_tf_temp.h deleted file mode 100644 index 8db5dcb49c..0000000000 --- a/src/arch/arm64/include/arm_tf_temp.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __ARM_TF_TEMP_H__ -#define __ARM_TF_TEMP_H__ - -#include - -/* - * Code temporarily copied from arm-trusted-firmware/include/common/bl_common.h, - * since it tries to pull in a few too many standard C headers and needs to be - * cleaned up a bit before we can include it directly. - */ - -#define PARAM_EP_SECURE 0x0 -#define PARAM_EP_NON_SECURE 0x1 -#define PARAM_EP_SECURITY_MASK 0x1 - -#define PARAM_EP_EE_MASK 0x2 -#define PARAM_EP_EE_LITTLE 0x0 -#define PARAM_EP_EE_BIG 0x2 - -#define PARAM_EP_ST_MASK 0x4 -#define PARAM_EP_ST_DISABLE 0x0 -#define PARAM_EP_ST_ENABLE 0x4 - -#define PARAM_EP 0x01 -#define PARAM_IMAGE_BINARY 0x02 -#define PARAM_BL31 0x03 - -#define VERSION_1 0x01 - -#define SET_PARAM_HEAD(_p, _type, _ver, _attr) do { \ - (_p)->h.type = (uint8_t)(_type); \ - (_p)->h.version = (uint8_t)(_ver); \ - (_p)->h.size = (uint16_t)sizeof(*_p); \ - (_p)->h.attr = (uint32_t)(_attr) ; \ - } while (0) - -typedef struct aapcs64_params { - unsigned long arg0; - unsigned long arg1; - unsigned long arg2; - unsigned long arg3; - unsigned long arg4; - unsigned long arg5; - unsigned long arg6; - unsigned long arg7; -} aapcs64_params_t; - -typedef struct param_header { - uint8_t type; /* type of the structure */ - uint8_t version; /* version of this structure */ - uint16_t size; /* size of this structure in bytes */ - uint32_t attr; /* attributes: unused bits SBZ */ -} param_header_t; - -typedef struct entry_point_info { - param_header_t h; - uintptr_t pc; - uint32_t spsr; - aapcs64_params_t args; -} entry_point_info_t; - -typedef struct image_info { - param_header_t h; - uintptr_t image_base; /* physical address of base of image */ - uint32_t image_size; /* bytes read from image file */ -} image_info_t; - -typedef struct bl31_params { - param_header_t h; - image_info_t *bl31_image_info; - entry_point_info_t *bl32_ep_info; - image_info_t *bl32_image_info; - entry_point_info_t *bl33_ep_info; - image_info_t *bl33_image_info; -} bl31_params_t; - -#endif /* __ARM_TF_TEMP_H__ */ diff --git a/src/arch/arm64/include/armv8/arch/barrier.h b/src/arch/arm64/include/armv8/arch/barrier.h index 3c3feb68d7..8da2cc29c8 100644 --- a/src/arch/arm64/include/armv8/arch/barrier.h +++ b/src/arch/arm64/include/armv8/arch/barrier.h @@ -1,7 +1,5 @@ /* - * Based on arch/arm/include/asm/barrier.h - * - * Copyright (C) 2012 ARM Ltd. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -11,6 +9,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Based on arch/arm/include/asm/barrier.h */ #ifndef __ASM_ARM_BARRIER_H #define __ASM_ARM_BARRIER_H diff --git a/src/arch/arm64/include/armv8/arch/cpu.h b/src/arch/arm64/include/armv8/arch/cpu.h index 6e096cc8e6..9b08bb4f7e 100644 --- a/src/arch/arm64/include/armv8/arch/cpu.h +++ b/src/arch/arm64/include/armv8/arch/cpu.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -20,9 +18,6 @@ static inline unsigned int smp_processor_id(void) { return 0; } - -#if !defined(__PRE_RAM__) struct cpu_driver { }; -#endif #endif /* __ARCH_CPU_H__ */ diff --git a/src/arch/arm64/include/armv8/arch/exception.h b/src/arch/arm64/include/armv8/arch/exception.h index f897fefe18..155060f954 100644 --- a/src/arch/arm64/include/armv8/arch/exception.h +++ b/src/arch/arm64/include/armv8/arch/exception.h @@ -1,5 +1,5 @@ /* - * This file is part of the libpayload project. + * This file is part of the coreboot project. * * Copyright 2013 Google Inc. * diff --git a/src/arch/arm64/include/armv8/arch/lib_helpers.h b/src/arch/arm64/include/armv8/arch/lib_helpers.h index b6d067ce65..0afbf82a23 100644 --- a/src/arch/arm64/include/armv8/arch/lib_helpers.h +++ b/src/arch/arm64/include/armv8/arch/lib_helpers.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/arch/arm64/include/armv8/arch/mmio.h b/src/arch/arm64/include/armv8/arch/mmio.h index aabfa87fc9..4342fc60e5 100644 --- a/src/arch/arm64/include/armv8/arch/mmio.h +++ b/src/arch/arm64/include/armv8/arch/mmio.h @@ -1,9 +1,5 @@ /* - * Originally imported from linux/include/asm-arm/io.h. This file has changed - * substantially since then. - * - * Copyright 2014 Google Inc. - * Copyright (C) 1996-2000 Russell King + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -14,16 +10,8 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * Modifications: - * 08-Apr-2013 G Replaced several macros with inlines for type safety. - * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both - * constant addresses and variable addresses. - * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture - * specific IO header files. - * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. - * 04-Apr-1999 PJB Added check_signature. - * 12-Dec-1999 RMK More cleanups - * 18-Jun-2000 RMK Removed virt_to_* and friends definitions + * Originally imported from linux/include/asm-arm/io.h. This file has changed + * substantially since then. */ #ifndef __ARCH_MMIO_H__ diff --git a/src/arch/arm64/include/armv8/arch/mmu.h b/src/arch/arm64/include/armv8/arch/mmu.h index 6c83749e95..4b6d78792a 100644 --- a/src/arch/arm64/include/armv8/arch/mmu.h +++ b/src/arch/arm64/include/armv8/arch/mmu.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/include/bl31.h b/src/arch/arm64/include/bl31.h new file mode 100644 index 0000000000..0f90e774b3 --- /dev/null +++ b/src/arch/arm64/include/bl31.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __BL31_H__ +#define __BL31_H__ + +#include + +#include + +/* Load and enter BL31, set it up to exit to payload according to arguments. */ +void run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr); + +/* Return platform-specific bl31_plat_params. SoCs should avoid overriding this + and stick with the default BL aux parameter framework if possible. */ +void *soc_get_bl31_plat_params(void); + +/* Add a BL aux parameter to the list to be passed to BL31. Only works for SoCs + that use the default soc_get_bl31_plat_params() implementation. */ +void register_bl31_aux_param(struct bl_aux_param_header *param); + +#endif /* __BL31_H__ */ diff --git a/src/arch/arm64/include/clocks.h b/src/arch/arm64/include/clocks.h index 60afb447f7..4904b6e96a 100644 --- a/src/arch/arm64/include/clocks.h +++ b/src/arch/arm64/include/clocks.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011 The Chromium OS Authors. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/arch/arm64/include/cpu/cortex_a57.h b/src/arch/arm64/include/cpu/cortex_a57.h index 1a1becd30a..3259934232 100644 --- a/src/arch/arm64/include/cpu/cortex_a57.h +++ b/src/arch/arm64/include/cpu/cortex_a57.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/memcpy.S b/src/arch/arm64/memcpy.S index 9cfbbb33d2..ef37ea5dc9 100644 --- a/src/arch/arm64/memcpy.S +++ b/src/arch/arm64/memcpy.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 ARM Ltd. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/src/arch/arm64/memmove.S b/src/arch/arm64/memmove.S index fc704f7ed5..ac2865054e 100644 --- a/src/arch/arm64/memmove.S +++ b/src/arch/arm64/memmove.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 ARM Ltd. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/src/arch/arm64/memset.S b/src/arch/arm64/memset.S index a6e98b77ae..5b61b31053 100644 --- a/src/arch/arm64/memset.S +++ b/src/arch/arm64/memset.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 ARM Ltd. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/src/arch/arm64/ramdetect.c b/src/arch/arm64/ramdetect.c new file mode 100644 index 0000000000..bc034c311b --- /dev/null +++ b/src/arch/arm64/ramdetect.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include + +static enum { + ABORT_CHECKER_NOT_TRIGGERED, + ABORT_CHECKER_TRIGGERED, +} abort_state = ABORT_CHECKER_NOT_TRIGGERED; + +static int abort_checker(struct exc_state *state, uint64_t vector_id) +{ + if (raw_read_esr_el3() >> 26 != 0x25) + return EXC_RET_IGNORED; /* Not a data abort. */ + + abort_state = ABORT_CHECKER_TRIGGERED; + state->elx.elr += sizeof(uint32_t); /* Jump over faulting instruction. */ + raw_write_elr_el3(state->elx.elr); + return EXC_RET_HANDLED; +} + +static struct exception_handler sync_el0 = {.handler = &abort_checker}; + +int probe_mb(const uintptr_t dram_start, const uintptr_t size) +{ + uintptr_t addr = dram_start + (size * MiB) - sizeof(uint32_t); + void *ptr = (void *)addr; + + abort_state = ABORT_CHECKER_NOT_TRIGGERED; + exception_handler_register(EXC_VID_CUR_SP_EL0_SYNC, &sync_el0); + read32(ptr); + exception_handler_unregister(EXC_VID_CUR_SP_EL0_SYNC, &sync_el0); + return abort_state == ABORT_CHECKER_NOT_TRIGGERED; +} diff --git a/src/arch/arm64/romstage.c b/src/arch/arm64/romstage.c index 8cdb16baef..58c47e78f3 100644 --- a/src/arch/arm64/romstage.c +++ b/src/arch/arm64/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c index 492eadd764..62334a725f 100644 --- a/src/arch/arm64/tables.c +++ b/src/arch/arm64/tables.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2005 Steve Magnani - * Copyright (C) 2008-2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/transition.c b/src/arch/arm64/transition.c index b1ab2fcf0b..3e8d7f0762 100644 --- a/src/arch/arm64/transition.c +++ b/src/arch/arm64/transition.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/transition_asm.S b/src/arch/arm64/transition_asm.S index 73821c85dd..718832b421 100644 --- a/src/arch/arm64/transition_asm.S +++ b/src/arch/arm64/transition_asm.S @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/Kconfig b/src/arch/mips/Kconfig index b8570c1c5d..9df514b21b 100644 --- a/src/arch/mips/Kconfig +++ b/src/arch/mips/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2014 Imagination Technologies -# # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; version 2 of diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc index cd474eeb48..7130abaaa0 100644 --- a/src/arch/mips/Makefile.inc +++ b/src/arch/mips/Makefile.inc @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2014 Imagination Technologies -# # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; version 2 of diff --git a/src/arch/mips/ashldi3.c b/src/arch/mips/ashldi3.c index f68d78ed60..e3282f55ea 100644 --- a/src/arch/mips/ashldi3.c +++ b/src/arch/mips/ashldi3.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google, Inc. - * - * Based on linux arch/mips/lib/ashldi3.c - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -13,6 +9,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Based on linux arch/mips/lib/ashldi3.c */ #ifndef __ORDER_LITTLE_ENDIAN__ diff --git a/src/arch/mips/boot.c b/src/arch/mips/boot.c index 5ab36ec390..a8518cd094 100644 --- a/src/arch/mips/boot.c +++ b/src/arch/mips/boot.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/bootblock.S b/src/arch/mips/bootblock.S index f8049c96d4..8ae1cfd7fa 100644 --- a/src/arch/mips/bootblock.S +++ b/src/arch/mips/bootblock.S @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/bootblock_simple.c b/src/arch/mips/bootblock_simple.c index e195b6ac85..be0b176b90 100644 --- a/src/arch/mips/bootblock_simple.c +++ b/src/arch/mips/bootblock_simple.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/arch/mips/cache.c b/src/arch/mips/cache.c index 62c20f34a3..2b56174898 100644 --- a/src/arch/mips/cache.c +++ b/src/arch/mips/cache.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/bootblock_common.h b/src/arch/mips/include/arch/bootblock_common.h index f5c11ba9c5..b930b5c4e7 100644 --- a/src/arch/mips/include/arch/bootblock_common.h +++ b/src/arch/mips/include/arch/bootblock_common.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/byteorder.h b/src/arch/mips/include/arch/byteorder.h index 35d444bbef..7c0ce47176 100644 --- a/src/arch/mips/include/arch/byteorder.h +++ b/src/arch/mips/include/arch/byteorder.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/cache.h b/src/arch/mips/include/arch/cache.h index 61a3e7c854..c610c991cf 100644 --- a/src/arch/mips/include/arch/cache.h +++ b/src/arch/mips/include/arch/cache.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/cbconfig.h b/src/arch/mips/include/arch/cbconfig.h index 9467f52646..35c1387895 100644 --- a/src/arch/mips/include/arch/cbconfig.h +++ b/src/arch/mips/include/arch/cbconfig.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/cpu.h b/src/arch/mips/include/arch/cpu.h index 8e35908e4c..61eb0828cf 100644 --- a/src/arch/mips/include/arch/cpu.h +++ b/src/arch/mips/include/arch/cpu.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -16,12 +14,10 @@ #ifndef __MIPS_ARCH_CPU_H #define __MIPS_ARCH_CPU_H -#define asmlinkage - -#ifndef __PRE_RAM__ - #include +#define asmlinkage + struct cpu_driver { struct device_operations *ops; const struct cpu_device_id *id_table; @@ -34,7 +30,6 @@ struct cpu_info { unsigned long index; }; -#endif /* !__PRE_RAM__ */ /*************************************************************************** * The following section was copied from arch/mips/include/asm/mipsregs.h in diff --git a/src/arch/mips/include/arch/early_variables.h b/src/arch/mips/include/arch/early_variables.h index 61f4653640..6ad82606c4 100644 --- a/src/arch/mips/include/arch/early_variables.h +++ b/src/arch/mips/include/arch/early_variables.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -21,7 +19,9 @@ static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) -#define car_sync_var(var) (var) #define car_set_var(var, val) { (var) = (val); } +#define car_get_ptr car_get_var +#define car_set_ptr car_set_var + #endif /* __MIPS_ARCH_EARLY_VARIABLES_H */ diff --git a/src/arch/mips/include/arch/exception.h b/src/arch/mips/include/arch/exception.h index e70d3963ad..a0ab9ecebd 100644 --- a/src/arch/mips/include/arch/exception.h +++ b/src/arch/mips/include/arch/exception.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/header.ld b/src/arch/mips/include/arch/header.ld index 1d84a4e42b..7f832eb51c 100644 --- a/src/arch/mips/include/arch/header.ld +++ b/src/arch/mips/include/arch/header.ld @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -21,7 +19,7 @@ PHDRS to_load PT_LOAD; } -#ifdef __BOOTBLOCK__ +#if ENV_BOOTBLOCK ENTRY(_start) #else ENTRY(stage_entry) diff --git a/src/arch/mips/include/arch/hlt.h b/src/arch/mips/include/arch/hlt.h index 703773ba20..5feafe2b85 100644 --- a/src/arch/mips/include/arch/hlt.h +++ b/src/arch/mips/include/arch/hlt.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/memlayout.h b/src/arch/mips/include/arch/memlayout.h index fe05bd8ae5..bf862a30ea 100644 --- a/src/arch/mips/include/arch/memlayout.h +++ b/src/arch/mips/include/arch/memlayout.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/mmio.h b/src/arch/mips/include/arch/mmio.h index c491b51bcb..2564e3b60d 100644 --- a/src/arch/mips/include/arch/mmio.h +++ b/src/arch/mips/include/arch/mmio.h @@ -1,12 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * - * Based on arch/armv7/include/arch/io.h: - * Copyright 2013 Google Inc. - * Copyright (C) 1996-2000 Russell King - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/mmu.h b/src/arch/mips/include/arch/mmu.h index 8997e27f44..f7377bb88c 100644 --- a/src/arch/mips/include/arch/mmu.h +++ b/src/arch/mips/include/arch/mmu.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/pci_ops.h b/src/arch/mips/include/arch/pci_ops.h index 7bfcbdd8f9..5be52aa3fb 100644 --- a/src/arch/mips/include/arch/pci_ops.h +++ b/src/arch/mips/include/arch/pci_ops.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/stages.h b/src/arch/mips/include/arch/stages.h index 802199f532..63306bd783 100644 --- a/src/arch/mips/include/arch/stages.h +++ b/src/arch/mips/include/arch/stages.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/types.h b/src/arch/mips/include/arch/types.h index 31a2f9fd00..fa14b6a684 100644 --- a/src/arch/mips/include/arch/types.h +++ b/src/arch/mips/include/arch/types.h @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * - * Based on src/arch/armv7/include/arch/types.h - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/mmu.c b/src/arch/mips/mmu.c index b144fd3573..5ef276d273 100644 --- a/src/arch/mips/mmu.c +++ b/src/arch/mips/mmu.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google, Inc. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/arch/mips/stages.c b/src/arch/mips/stages.c index e940faa6cb..0971e98905 100644 --- a/src/arch/mips/stages.c +++ b/src/arch/mips/stages.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/tables.c b/src/arch/mips/tables.c index 50d2a55650..e9de4bfd71 100644 --- a/src/arch/mips/tables.c +++ b/src/arch/mips/tables.c @@ -1,11 +1,6 @@ /* * This file is part of the coreboot project. * - * Based on src/arch/armv7/tables.c: - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2005 Steve Magnani - * Copyright (C) 2008-2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/ppc64/Makefile.inc b/src/arch/ppc64/Makefile.inc index 99d86345ac..fae4c926b7 100644 --- a/src/arch/ppc64/Makefile.inc +++ b/src/arch/ppc64/Makefile.inc @@ -2,9 +2,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2016 Raptor Engineering, LLC -## Copyright (C) 2014 The ChromiumOS Authors -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. @@ -80,7 +77,6 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_PPC64),y) ramstage-y += rom_media.c ramstage-y += stages.c -ramstage-y += misc.c ramstage-y += boot.c ramstage-y += tables.c ramstage-y += \ diff --git a/src/arch/ppc64/boot.c b/src/arch/ppc64/boot.c index 4da60b4e6c..6c13761538 100644 --- a/src/arch/ppc64/boot.c +++ b/src/arch/ppc64/boot.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/ppc64/bootblock.S b/src/arch/ppc64/bootblock.S index 77289a1246..2628e0dabe 100644 --- a/src/arch/ppc64/bootblock.S +++ b/src/arch/ppc64/bootblock.S @@ -1,8 +1,5 @@ /* - * Early initialization code for POWER8. - * - * Copyright 2016 Raptor Engineering, LLC - * Copyright 2013 Google Inc. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -13,6 +10,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the * GNU General Public License for more details. + * + * Early initialization code for POWER8. */ .section ".text._start", "ax", %progbits diff --git a/src/arch/ppc64/include/arch/cbconfig.h b/src/arch/ppc64/include/arch/cbconfig.h index 9467f52646..35c1387895 100644 --- a/src/arch/ppc64/include/arch/cbconfig.h +++ b/src/arch/ppc64/include/arch/cbconfig.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/ppc64/include/arch/cpu.h b/src/arch/ppc64/include/arch/cpu.h index 1e13528037..89816903c8 100644 --- a/src/arch/ppc64/include/arch/cpu.h +++ b/src/arch/ppc64/include/arch/cpu.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2012 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -16,11 +14,10 @@ #ifndef __ARCH_CPU_H__ #define __ARCH_CPU_H__ -#define asmlinkage - -#if !defined(__PRE_RAM__) #include +#define asmlinkage + struct cpu_driver { struct device_operations *ops; const struct cpu_device_id *id_table; @@ -42,7 +39,6 @@ struct cpuinfo_ppc64 { uint8_t ppc64_model; }; -#endif - struct cpu_info *cpu_info(void); + #endif /* __ARCH_CPU_H__ */ diff --git a/src/arch/ppc64/include/arch/early_variables.h b/src/arch/ppc64/include/arch/early_variables.h index 99fc06bb18..05b8bc7e48 100644 --- a/src/arch/ppc64/include/arch/early_variables.h +++ b/src/arch/ppc64/include/arch/early_variables.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -21,8 +19,9 @@ #define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) -#define car_sync_var(var) (var) - #define car_set_var(var, val) do { (var) = (val); } while (0) +#define car_get_ptr car_get_var +#define car_set_ptr car_set_var + #endif diff --git a/src/arch/ppc64/include/arch/header.ld b/src/arch/ppc64/include/arch/header.ld index 7fdc155586..badeefdf49 100644 --- a/src/arch/ppc64/include/arch/header.ld +++ b/src/arch/ppc64/include/arch/header.ld @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -21,7 +19,7 @@ PHDRS to_load PT_LOAD; } -#ifdef __BOOTBLOCK__ +#if ENV_BOOTBLOCK ENTRY(_start) #else ENTRY(stage_entry) diff --git a/src/arch/ppc64/include/arch/memlayout.h b/src/arch/ppc64/include/arch/memlayout.h index 4d2af5953d..09e87c9574 100644 --- a/src/arch/ppc64/include/arch/memlayout.h +++ b/src/arch/ppc64/include/arch/memlayout.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/ppc64/include/arch/stages.h b/src/arch/ppc64/include/arch/stages.h index 90bd60b9a6..a4939b1758 100644 --- a/src/arch/ppc64/include/arch/stages.h +++ b/src/arch/ppc64/include/arch/stages.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 The ChromiumOS Authors - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/ppc64/prologue.inc b/src/arch/ppc64/prologue.inc index a349cf97b3..9e22eb3d49 100644 --- a/src/arch/ppc64/prologue.inc +++ b/src/arch/ppc64/prologue.inc @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2002 Eric Biederman - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/ppc64/rom_media.c b/src/arch/ppc64/rom_media.c index c1713074f9..0fc8be26e0 100644 --- a/src/arch/ppc64/rom_media.c +++ b/src/arch/ppc64/rom_media.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/arch/ppc64/stages.c b/src/arch/ppc64/stages.c index 053fd7634c..3cc9371ffe 100644 --- a/src/arch/ppc64/stages.c +++ b/src/arch/ppc64/stages.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/ppc64/tables.c b/src/arch/ppc64/tables.c index eef6bf2ffd..e9de4bfd71 100644 --- a/src/arch/ppc64/tables.c +++ b/src/arch/ppc64/tables.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2005 Steve Magnani - * Copyright (C) 2008-2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h index 547cb76a04..c62199e3f0 100644 --- a/src/arch/riscv/include/arch/cpu.h +++ b/src/arch/riscv/include/arch/cpu.h @@ -17,12 +17,10 @@ #define __ARCH_CPU_H__ #include +#include #define asmlinkage -#if !defined(__PRE_RAM__) -#include - struct cpu_driver { struct device_operations *ops; const struct cpu_device_id *id_table; @@ -44,8 +42,6 @@ struct cpuinfo_riscv { uint8_t riscv_model; }; -#endif - static inline int supports_extension(char ext) { return read_csr(misa) & (1 << (ext - 'A')); diff --git a/src/arch/riscv/include/arch/early_variables.h b/src/arch/riscv/include/arch/early_variables.h index acc5ac3c6b..a2da5f86ee 100644 --- a/src/arch/riscv/include/arch/early_variables.h +++ b/src/arch/riscv/include/arch/early_variables.h @@ -21,7 +21,9 @@ #define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) -#define car_sync_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) +#define car_get_ptr car_get_var +#define car_set_ptr car_set_var + #endif diff --git a/src/arch/riscv/include/arch/memlayout.h b/src/arch/riscv/include/arch/memlayout.h index 7baab76479..ac707d0978 100644 --- a/src/arch/riscv/include/arch/memlayout.h +++ b/src/arch/riscv/include/arch/memlayout.h @@ -20,7 +20,7 @@ #define STACK(addr, size) REGION(stack, addr, size, 4096) -#if defined(__PRE_RAM__) +#if ENV_ROMSTAGE_OR_BEFORE #define CAR_STACK(addr, size) \ REGION(car_stack, addr, size, 4K) \ ALIAS_REGION(car_stack, stack) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 631d981e45..502e7747f4 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2009-2010 coresystems GmbH -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. @@ -81,6 +79,13 @@ config AP_IN_SIPI_WAIT default n depends on ARCH_X86 && SMP +config RESET_VECTOR_IN_RAM + bool + depends on ARCH_X86 + help + Select this option if the x86 soc implements custom code to handle the + reset vector in RAM instead of the traditional 0xfffffff0 location. + # Aligns 16bit entry code in bootblock so that hyper-threading CPUs # can boot AP CPUs to enable their shared caches. config SIPI_VECTOR_IN_ROM @@ -222,8 +227,9 @@ config VERSTAGE_ADDR # Use the post CAR infrastructure for tearing down cache-as-ram # from a program loaded in RAM and subsequently loading ramstage. config POSTCAR_STAGE - def_bool n - select NO_CAR_GLOBAL_MIGRATION + def_bool y + depends on ARCH_X86 + depends on !CAR_GLOBAL_MIGRATION config VERSTAGE_DEBUG_SPINLOOP bool diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 32e0173804..554107f2fe 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -1,11 +1,6 @@ -################################################################################ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 Alexandru Gagniuc -## Copyright (C) 2009-2010 coresystems GmbH -## Copyright (C) 2009 Ronald G. Minnich -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index fdcbcd3fb5..b48640901c 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -1,22 +1,6 @@ /* * This file is part of the coreboot project. * - * coreboot ACPI Table support - * written by Stefan Reinauer - * - * Copyright (C) 2004 SUSE LINUX AG - * Copyright (C) 2005-2009 coresystems GmbH - * Copyright (C) 2015 Timothy Pearson , - * Raptor Engineering - * Copyright (C) 2016-2019 Siemens AG - * - * ACPI FADT, FACS, and DSDT table support added by - * Nick Barker , and those portions - * Copyright (C) 2004 Nick Barker - * - * Copyright (C) 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. - * 2005.9 yhlu add SRAT table generation - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -25,6 +9,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * coreboot ACPI Table support */ /* diff --git a/src/arch/x86/acpi/debug.asl b/src/arch/x86/acpi/debug.asl index 04a6026d7e..36afac6211 100644 --- a/src/arch/x86/acpi/debug.asl +++ b/src/arch/x86/acpi/debug.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/acpi/globutil.asl b/src/arch/x86/acpi/globutil.asl index 7a00291106..e9b428ad36 100644 --- a/src/arch/x86/acpi/globutil.asl +++ b/src/arch/x86/acpi/globutil.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/acpi/statdef.asl b/src/arch/x86/acpi/statdef.asl index f8c4b32001..99194f428c 100644 --- a/src/arch/x86/acpi/statdef.asl +++ b/src/arch/x86/acpi/statdef.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c index 961faa6118..130f97a678 100644 --- a/src/arch/x86/acpi_bert_storage.c +++ b/src/arch/x86/acpi_bert_storage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index 47bcc52c1e..d367108457 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -81,6 +79,24 @@ const char *acpi_device_name(const struct device *dev) return NULL; } +/* Locate and return the ACPI _HID (Hardware ID) for this device */ +const char *acpi_device_hid(const struct device *dev) +{ + if (!dev) + return NULL; + + /* Check for device specific handler */ + if (dev->ops->acpi_hid) + return dev->ops->acpi_hid(dev); + + /* + * Don't walk up the tree to find any parent that can identify this device, as + * PNP devices are hard to identify. + */ + + return NULL; +} + /* Recursive function to find the root device and print a path from there */ static ssize_t acpi_device_path_fill(const struct device *dev, char *buf, size_t buf_len, size_t cur) diff --git a/src/arch/x86/acpi_pld.c b/src/arch/x86/acpi_pld.c index 904e9f777f..6fbbfe74e3 100644 --- a/src/arch/x86/acpi_pld.c +++ b/src/arch/x86/acpi_pld.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 049fb12e75..52f8a201f7 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2005-2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -24,6 +22,7 @@ #include #include #include +#include #if ENV_RAMSTAGE || ENV_POSTCAR @@ -61,154 +60,22 @@ int acpi_is_wakeup_s4(void) acpi_handoff_wakeup(); return (acpi_slp_type == ACPI_S4); } - -void acpi_fail_wakeup(void) -{ - if (acpi_slp_type == ACPI_S3 || acpi_slp_type == ACPI_S2) - acpi_slp_type = ACPI_S0; -} #endif /* ENV_RAMSTAGE */ -struct resume_backup { - uint64_t cbmem; - uint64_t lowmem; - uint64_t size; - uint8_t valid; -}; - -#define BACKUP_PAGE_SZ 4096 - -static int backup_create_or_update(struct resume_backup *backup_mem, - uintptr_t base, size_t size) -{ - uintptr_t top; - - if (CONFIG(ACPI_HUGE_LOWMEM_BACKUP)) { - base = CONFIG_RAMBASE; - size = HIGH_MEMORY_SAVE; - } - - /* Align backup region to complete pages. */ - top = ALIGN_UP(base + size, BACKUP_PAGE_SZ); - base = ALIGN_DOWN(base, BACKUP_PAGE_SZ); - size = top - base; - - /* Cannot extend existing region, should not happen. */ - if (backup_mem && (backup_mem->size < size)) - return -1; - - /* Allocate backup with room for header. */ - if (!backup_mem) { - size_t header_sz = ALIGN_UP(sizeof(*backup_mem), - BACKUP_PAGE_SZ); - backup_mem = cbmem_add(CBMEM_ID_RESUME, header_sz + size); - if (!backup_mem) - return -1; - - /* Container starts from boundary after header. */ - backup_mem->cbmem = (uintptr_t)backup_mem + header_sz; - } - - backup_mem->valid = 0; - backup_mem->lowmem = base; - backup_mem->size = size; - return 0; -} - -void *acpi_backup_container(uintptr_t base, size_t size) -{ - struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); - if (!backup_mem) - return NULL; - - if (!IS_ALIGNED(base, BACKUP_PAGE_SZ) || !IS_ALIGNED(size, - BACKUP_PAGE_SZ)) - return NULL; - - if (backup_create_or_update(backup_mem, base, size) < 0) - return NULL; - - backup_mem->valid = 1; - return (void *)(uintptr_t)backup_mem->cbmem; -} - -void backup_ramstage_section(uintptr_t base, size_t size) -{ - struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); - - /* For first boot we exit here as CBMEM_ID_RESUME is only - * created late in ramstage with acpi_prepare_resume_backup(). - */ - if (!backup_mem) - return; - - /* Check that the backup is not done twice. */ - if (backup_mem->valid) - return; - - /* When we are called from ramstage loader, update header with - * properties of the ramstage we will load. - */ - if (backup_create_or_update(backup_mem, base, size) < 0) - return; - - /* Back up the OS-controlled memory where ramstage will be loaded. */ - memcpy((void *)(uintptr_t)backup_mem->cbmem, - (void *)(uintptr_t)backup_mem->lowmem, - (size_t)backup_mem->size); - backup_mem->valid = 1; -} - -/* Let's prepare the ACPI S3 Resume area now already, so we can rely on - * it being there during reboot time. If this fails, ACPI resume will - * be disabled. We assume that ramstage does not change while in suspend, - * so base and size of the currently running ramstage are used - * for allocation. - */ -void acpi_prepare_resume_backup(void) -{ - if (!acpi_s3_resume_allowed()) - return; - - if (CONFIG(RELOCATABLE_RAMSTAGE)) - return; - - backup_create_or_update(NULL, (uintptr_t)_program, - REGION_SIZE(program)); -} - #define WAKEUP_BASE 0x600 -asmlinkage void (*acpi_do_wakeup)(uintptr_t vector, u32 backup_source, - u32 backup_target, u32 backup_size) = (void *)WAKEUP_BASE; +asmlinkage void (*acpi_do_wakeup)(uintptr_t vector) = (void *)WAKEUP_BASE; extern unsigned char __wakeup; extern unsigned int __wakeup_size; static void acpi_jump_to_wakeup(void *vector) { - uintptr_t source = 0, target = 0; - size_t size = 0; - if (!acpi_s3_resume_allowed()) { printk(BIOS_WARNING, "ACPI: S3 resume not allowed.\n"); return; } - if (!CONFIG(RELOCATABLE_RAMSTAGE)) { - struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); - if (backup_mem && backup_mem->valid) { - backup_mem->valid = 0; - target = backup_mem->lowmem; - source = backup_mem->cbmem; - size = backup_mem->size; - } else { - printk(BIOS_WARNING, "ACPI: Backup memory missing. " - "No S3 resume.\n"); - return; - } - } - /* Copy wakeup trampoline in place. */ memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size); @@ -216,7 +83,7 @@ static void acpi_jump_to_wakeup(void *vector) timestamp_add_now(TS_ACPI_WAKE_JUMP); - acpi_do_wakeup((uintptr_t)vector, source, target, size); + acpi_do_wakeup((uintptr_t)vector); } void __weak mainboard_suspend_resume(void) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index f9af10229e..1d75889018 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson , - * Raptor Engineering - * Copyright (C) 2009 Rudolf Marek - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/acpigen_dsm.c b/src/arch/x86/acpigen_dsm.c index 1aab90b714..64cdd7228e 100644 --- a/src/arch/x86/acpigen_dsm.c +++ b/src/arch/x86/acpigen_dsm.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 4ead9ea769..c36dc1cb10 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * Copyright (C) 2016 Intel Corp. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -35,12 +32,13 @@ _start: /* reset stack pointer to CAR stack */ mov $_car_stack_end, %esp - /* clear CAR_GLOBAL area as it is not shared */ + /* clear .bss section as it is not shared */ cld xor %eax, %eax - movl $(_car_global_end), %ecx - movl $(_car_global_start), %edi + movl $(_ebss), %ecx + movl $(_bss), %edi sub %edi, %ecx + shrl $2, %ecx rep stosl #if ((ENV_VERSTAGE && CONFIG(VERSTAGE_DEBUG_SPINLOOP)) \ @@ -60,9 +58,7 @@ debug_spinloop: #endif call car_stage_entry -/* This is here for linking purposes. */ -.weak car_stage_entry -car_stage_entry: + /* Expect to never return. */ 1: jmp 1b diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld index 8ccd3e4629..10cd700322 100644 --- a/src/arch/x86/bootblock.ld +++ b/src/arch/x86/bootblock.ld @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index ea55096abd..3cb57e058c 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -1,15 +1,6 @@ /* - * This is the modern bootblock. It is used by platforms which select - * C_ENVIRONMENT_BOOTBLOCK, and it prepares the system for C environment runtime - * setup. The actual setup is done by hardware-specific code. - * - * It provides a bootflow similar to other architectures, and thus is considered - * to be the modern approach. - * * This file is part of the coreboot project. * - * Copyright (C) 2015 Alexandru Gagniuc - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -19,6 +10,14 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * This is the modern bootblock. It is used by platforms which select + * C_ENVIRONMENT_BOOTBLOCK, and it prepares the system for C environment runtime + * setup. The actual setup is done by hardware-specific code. + * + * It provides a bootflow similar to other architectures, and thus is considered + * to be the modern approach. + * */ #include @@ -48,11 +47,10 @@ bootblock_protected_mode_entry: /* MMX registers required here */ /* BIST result in eax */ - movl %eax, %ebx + movd %eax, %mm0 /* Get an early timestamp */ rdtsc - movd %ebx, %mm0 movd %eax, %mm1 movd %edx, %mm2 #endif diff --git a/src/arch/x86/bootblock_romcc.S b/src/arch/x86/bootblock_romcc.S index 02603e91e3..05b34c6c5a 100644 --- a/src/arch/x86/bootblock_romcc.S +++ b/src/arch/x86/bootblock_romcc.S @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 5802b02896..6ccbd8c236 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2006 Advanced Micro Devices, Inc. - * Copyright (C) 2008-2010 coresystems GmbH - * Copyright 2015 Google Inc - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -60,36 +56,35 @@ . += 32; _epdpt = .; #endif - _car_relocatable_data_start = .; - /* The timestamp implementation relies on this storage to be around - * after migration. One of the fields indicates not to use it as the - * backing store once cbmem comes online. Therefore, this data needs - * to reside in the migrated area (between _car_relocatable_data_start - * and _car_relocatable_data_end). */ + TIMESTAMP(., 0x200) + _car_ehci_dbg_info_start = .; /* Reserve sizeof(struct ehci_dbg_info). */ . += 80; _car_ehci_dbg_info_end = .; - /* _car_global_start and _car_global_end provide symbols to per-stage + + /* _bss and _ebss provide symbols to per-stage * variables that are not shared like the timestamp and the pre-ram * cbmem console. This is useful for clearing this area on a per-stage * basis when more than one stage uses cache-as-ram for CAR_GLOBALs. */ - _car_global_start = .; -#if CONFIG(NO_CAR_GLOBAL_MIGRATION) - /* Allow global unitialized variables when CAR_GLOBALs are not used. */ + + . = ALIGN(ARCH_POINTER_ALIGN_SIZE); + _bss = .; +#if ENV_STAGE_HAS_BSS_SECTION + /* Allow global uninitialized variables for stages without CAR teardown. */ *(.bss) *(.bss.*) *(.sbss) *(.sbss.*) #else - /* .car.global_data objects only around when - * !CONFIG_NO_CAR_GLOBAL_MIGRATION is employed. */ + _car_global_start = .; *(.car.global_data); + _car_global_end = .; #endif . = ALIGN(ARCH_POINTER_ALIGN_SIZE); - _car_global_end = .; - _car_relocatable_data_end = .; + _ebss = .; + _car_unallocated_start = .; #if !CONFIG(C_ENVIRONMENT_BOOTBLOCK) _car_stack_start = .; @@ -107,7 +102,7 @@ .illegal_globals . : { *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data) *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*) -#if !CONFIG(NO_CAR_GLOBAL_MIGRATION) +#if CONFIG(CAR_GLOBAL_MIGRATION) *(.bss) *(.bss.*) *(.sbss) diff --git a/src/arch/x86/cbfs_and_run.c b/src/arch/x86/cbfs_and_run.c index f25052b1ed..5ca2c896e5 100644 --- a/src/arch/x86/cbfs_and_run.c +++ b/src/arch/x86/cbfs_and_run.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c index 648633f070..16c35b5dea 100644 --- a/src/arch/x86/cbmem.c +++ b/src/arch/x86/cbmem.c @@ -13,7 +13,6 @@ #include #include -#include #if CONFIG(CBMEM_TOP_BACKUP) @@ -35,13 +34,3 @@ void *cbmem_top(void) } #endif /* CBMEM_TOP_BACKUP */ - -/* Something went wrong, our high memory area got wiped */ -void cbmem_fail_resume(void) -{ -#if !defined(__PRE_RAM__) && CONFIG(HAVE_ACPI_RESUME) - /* ACPI resume needs to be cleared in the fail-to-recover case, but that - * condition is only handled during ramstage. */ - acpi_fail_wakeup(); -#endif -} diff --git a/src/arch/x86/cf9_reset.c b/src/arch/x86/cf9_reset.c index d1e5704ceb..ccfaa7d9f8 100644 --- a/src/arch/x86/cf9_reset.c +++ b/src/arch/x86/cf9_reset.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/ebda.c b/src/arch/x86/ebda.c index 810312c105..d1212f9d32 100644 --- a/src/arch/x86/ebda.c +++ b/src/arch/x86/ebda.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index 769a758b9d..679e335eb3 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld index a9a5942a2f..334145a742 100644 --- a/src/arch/x86/failover.ld +++ b/src/arch/x86/failover.ld @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2006 Advanced Micro Devices, Inc. - * Copyright (C) 2008-2010 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/gdt.c b/src/arch/x86/gdt.c index 81756ff568..27e4af3d47 100644 --- a/src/arch/x86/gdt.c +++ b/src/arch/x86/gdt.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 259efcd2d5..6cd4e9fae8 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -1,14 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2004 SUSE LINUX AG - * Copyright (C) 2004 Nick Barker - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2015 Timothy Pearson , - * Raptor Engineering - * Copyright (C) 2016 Siemens AG - * (Written by Stefan Reinauer ) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -26,8 +18,6 @@ #ifndef __ASM_ACPI_H #define __ASM_ACPI_H -#define HIGH_MEMORY_SAVE (CONFIG_RAMTOP - CONFIG_RAMBASE) - /* * The type and enable fields are common in ACPI, but the * values themselves are hardware implementation defined. @@ -131,6 +121,14 @@ typedef struct acpi_gen_regaddr { #define ACPI_ACCESS_SIZE_DWORD_ACCESS 3 #define ACPI_ACCESS_SIZE_QWORD_ACCESS 4 +/* Common ACPI HIDs */ +#define ACPI_HID_FDC "PNP0700" +#define ACPI_HID_KEYBOARD "PNP0303" +#define ACPI_HID_MOUSE "PNP0F03" +#define ACPI_HID_COM "PNP0501" +#define ACPI_HID_LPT "PNP0400" +#define ACPI_HID_PNP "PNP0C02" + /* Generic ACPI header, provided by (almost) all tables */ typedef struct acpi_table_header { char signature[4]; /* ACPI signature (4 ASCII characters) */ @@ -934,9 +932,7 @@ unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type, void *data, u16 len); /* For ACPI S3 support. */ -void acpi_fail_wakeup(void); void acpi_resume(void *wake_vec); -void acpi_prepare_resume_backup(void); void mainboard_suspend_resume(void); void *acpi_find_wakeup_vector(void); @@ -976,16 +972,9 @@ static inline int acpi_s3_resume_allowed(void) return CONFIG(HAVE_ACPI_RESUME); } -/* Return address in reserved memory where to backup low memory - * while platform resumes from S3 suspend. Caller is responsible of - * making a complete copy of the region base..base+size, with - * parameteres base and size that meet page alignment requirement. - */ -void *acpi_backup_container(uintptr_t base, size_t size); - #if CONFIG(HAVE_ACPI_RESUME) -#ifdef __PRE_RAM__ +#if ENV_ROMSTAGE_OR_BEFORE static inline int acpi_is_wakeup_s3(void) { return (acpi_get_sleep_type() == ACPI_S3); diff --git a/src/arch/x86/include/arch/acpi_device.h b/src/arch/x86/include/arch/acpi_device.h index d74af9da74..382ef1546b 100644 --- a/src/arch/x86/include/arch/acpi_device.h +++ b/src/arch/x86/include/arch/acpi_device.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -63,6 +61,7 @@ struct acpi_dp { struct device; const char *acpi_device_name(const struct device *dev); +const char *acpi_device_hid(const struct device *dev); const char *acpi_device_path(const struct device *dev); const char *acpi_device_scope(const struct device *dev); const char *acpi_device_path_join(const struct device *dev, const char *name); diff --git a/src/arch/x86/include/arch/acpi_ivrs.h b/src/arch/x86/include/arch/acpi_ivrs.h index 5d69141d21..784b5a39a2 100644 --- a/src/arch/x86/include/arch/acpi_ivrs.h +++ b/src/arch/x86/include/arch/acpi_ivrs.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/include/arch/acpi_pld.h b/src/arch/x86/include/arch/acpi_pld.h index 1b4417d2da..f23aacd539 100644 --- a/src/arch/x86/include/arch/acpi_pld.h +++ b/src/arch/x86/include/arch/acpi_pld.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index db003fe113..0f11226eb0 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 Rudolf Marek - * Copyright (C) 2015 Timothy Pearson , - * Raptor Engineering - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/include/arch/acpigen_dsm.h b/src/arch/x86/include/arch/acpigen_dsm.h index 2d8bb4877a..49ed6db632 100644 --- a/src/arch/x86/include/arch/acpigen_dsm.h +++ b/src/arch/x86/include/arch/acpigen_dsm.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/include/arch/bert_storage.h b/src/arch/x86/include/arch/bert_storage.h index 5c87aed8b0..644f24e50c 100644 --- a/src/arch/x86/include/arch/bert_storage.h +++ b/src/arch/x86/include/arch/bert_storage.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/include/arch/cbconfig.h b/src/arch/x86/include/arch/cbconfig.h index 78a5940c6a..b222ef3603 100644 --- a/src/arch/x86/include/arch/cbconfig.h +++ b/src/arch/x86/include/arch/cbconfig.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/include/arch/cbfs.h b/src/arch/x86/include/arch/cbfs.h index 54f0fa97e1..ec367ed1de 100644 --- a/src/arch/x86/include/arch/cbfs.h +++ b/src/arch/x86/include/arch/cbfs.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 293ca02158..263b734529 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -203,12 +203,6 @@ static inline unsigned int cpuid_edx(unsigned int op) unsigned int cpu_cpuid_extended_level(void); int cpu_have_cpuid(void); -/* Only with !PARALLEL_MP. */ -void smm_init(void); -void smm_init_completion(void); - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1); - static inline bool cpu_is_amd(void) { return CONFIG(CPU_AMD_AGESA) || CONFIG(CPU_AMD_PI) @@ -285,11 +279,10 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) c->x86_model += ((tfms >> 16) & 0xF) << 4; } -#endif +/* romcc does not understand regparm. */ #define asmlinkage __attribute__((regparm(0))) -#ifndef __ROMCC__ /* * When using CONFIG_C_ENVIRONMENT_BOOTBLOCK the car_stage_entry() * is the symbol jumped to for each stage after bootblock using @@ -297,60 +290,6 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) */ asmlinkage void car_stage_entry(void); -/* - * Support setting up a stack frame consisting of MTRR information - * for use in bootstrapping the caching attributes after cache-as-ram - * is torn down. - */ - -struct postcar_frame { - uintptr_t stack; - uint32_t upper_mask; - int max_var_mtrrs; - int num_var_mtrrs; -}; - -/* - * Initialize postcar_frame object allocating stack from cbmem, - * with stack_size == 0, default 4 KiB is allocated. - * Returns 0 on success, < 0 on error. - */ -int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size); - -/* - * Add variable MTRR covering the provided range with MTRR type. - */ -void postcar_frame_add_mtrr(struct postcar_frame *pcf, - uintptr_t addr, size_t size, int type); - -/* - * Add variable MTRR covering the memory-mapped ROM with given MTRR type. - */ -void postcar_frame_add_romcache(struct postcar_frame *pcf, int type); - -/* - * Push used MTRR and Max MTRRs on to the stack - * and return pointer to stack top. - */ -void *postcar_commit_mtrrs(struct postcar_frame *pcf); - -/* - * Load and run a program that takes control of execution that - * tears down CAR and loads ramstage. The postcar_frame object - * indicates how to set up the frame. If caching is enabled at - * the time of the call it is up to the platform code to handle - * coherency with dirty lines in the cache using some mechansim - * such as platform_prog_run() because run_postcar_phase() - * utilizes prog_run() internally. - */ -void run_postcar_phase(struct postcar_frame *pcf); - -/* - * Systems without a native coreboot cache-as-ram teardown may implement - * this to use an alternate method. - */ -void late_car_teardown(void); - #endif /* diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index a69c230596..b88495c85b 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -20,7 +18,17 @@ #include #include -#if ENV_CACHE_AS_RAM && !CONFIG(NO_CAR_GLOBAL_MIGRATION) +#if ENV_ROMSTAGE && CONFIG(CAR_GLOBAL_MIGRATION) + +/* + * The _car_global_[start|end]symbols cover CAR data which is relocatable + * once memory comes online. Variables with CAR_GLOBAL decoration + * reside within this region. + */ +extern char _car_global_start[]; +extern char _car_global_end[]; +#define _car_global_size (_car_global_end - _car_global_start) + asm(".section .car.global_data,\"w\",@nobits"); asm(".previous"); #ifdef __clang__ @@ -29,78 +37,62 @@ asm(".previous"); #define CAR_GLOBAL __attribute__((used, section(".car.global_data#"))) #endif /* __clang__ */ -/* - * In stages that use CAR (verstage, C bootblock) all CAR_GLOBAL variables are - * accessed unconditionally because cbmem is never initialized until romstage - * when dram comes up. - */ -#if !ENV_ROMSTAGE -static inline void *car_get_var_ptr(void *var) +/* Get the correct pointer for the CAR global variable. */ +void *car_get_var_ptr(void *var); + +/* Return 1 when currently running with globals in Cache-as-RAM, 0 otherwise. */ +int car_active(void); + +/* Get and set a primitive type global variable. */ +#define car_get_var(var) \ + (*(typeof(var) *)car_get_var_ptr(&(var))) +#define car_set_var(var, val) car_get_var(var) = (val) + +/* Get and set a CAR_GLOBAL pointing elsewhere inside CAR. */ +#if !CONFIG(PLATFORM_USES_FSP1_0) +#define car_get_ptr car_get_var +#define car_set_ptr car_set_var +#else +void *car_get_reloc_ptr(void *var); +void car_set_reloc_ptr(void *var, void *val); +#define car_get_ptr(var) car_get_reloc_ptr(&(var)) +#define car_set_ptr(var, val) car_set_reloc_ptr(&(var), (val)) +#endif + +static inline size_t car_data_size(void) { - return var; + size_t car_size = _car_global_size; + return ALIGN(car_size, 64); } -static inline void *car_sync_var_ptr(void *var) +static inline size_t car_object_offset(void *ptr) +{ + return (char *)ptr - &_car_global_start[0]; +} + +#else + +/* + * For all stages other than romstage, all CAR_GLOBAL variables are accessed + * unconditionally as there is no migration of symbols. + */ + +#define CAR_GLOBAL +#define car_get_var(var) (var) +#define car_set_var(var, val) (var) = (val) +#define car_get_ptr car_get_var +#define car_set_ptr car_set_var + +static inline void *car_get_var_ptr(void *var) { return var; } static inline int car_active(void) { - return 1; -} -#else -/* Get the correct pointer for the CAR global variable. */ -void *car_get_var_ptr(void *var); - -/* Get and update a CAR_GLOBAL pointing elsewhere in car.global_data*/ -void *car_sync_var_ptr(void *var); - -/* Return 1 when currently running with globals in Cache-as-RAM, 0 otherwise. */ -int car_active(void); -#endif /* !ENV_ROMSTAGE */ - -/* Get and set a primitive type global variable. */ -#define car_get_var(var) \ - (*(typeof(var) *)car_get_var_ptr(&(var))) -#define car_sync_var(var) \ - (*(typeof(var) *)car_sync_var_ptr(&(var))) -#define car_set_var(var, val) car_get_var(var) = (val) - -static inline size_t car_data_size(void) -{ - size_t car_size = _car_relocatable_data_size; - return ALIGN_UP(car_size, 64); + return ENV_CACHE_AS_RAM; } -static inline size_t car_object_offset(void *ptr) -{ - return (char *)ptr - &_car_relocatable_data_start[0]; -} - -#else - -/* - * We might end up here if: - * 1. ENV_CACHE_AS_RAM is not set for the stage or - * 2. ENV_CACHE_AS_RAM is set for the stage but CONFIG_NO_CAR_GLOBAL_MIGRATION - * is also set. In this case, there is no need to migrate CAR global - * variables. But, since we might still be running out of CAR, car_active needs - * to return 1 if ENV_CACHE_AS_RAM is set. - */ - -#define CAR_GLOBAL -static inline void *car_get_var_ptr(void *var) { return var; } - -#if ENV_CACHE_AS_RAM -static inline int car_active(void) { return 1; } -#else -static inline int car_active(void) { return 0; } -#endif /* ENV_CACHE_AS_RAM */ - -#define car_get_var(var) (var) -#define car_sync_var(var) (var) -#define car_set_var(var, val) (var) = (val) -#endif /* ENV_CACHE_AS_RAM && !CONFIG(NO_CAR_GLOBAL_MIGRATION) */ +#endif #endif /* ARCH_EARLY_VARIABLES_H */ diff --git a/src/arch/x86/include/arch/ebda.h b/src/arch/x86/include/arch/ebda.h index 2347ea5318..534fb3d590 100644 --- a/src/arch/x86/include/arch/ebda.h +++ b/src/arch/x86/include/arch/ebda.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/arch/x86/include/arch/exception.h b/src/arch/x86/include/arch/exception.h index d71d5a51f4..df6f9e5ee7 100644 --- a/src/arch/x86/include/arch/exception.h +++ b/src/arch/x86/include/arch/exception.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld index 77eb187222..69f6d7d671 100644 --- a/src/arch/x86/include/arch/header.ld +++ b/src/arch/x86/include/arch/header.ld @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/include/arch/intel-family.h b/src/arch/x86/include/arch/intel-family.h deleted file mode 100644 index 43eb0e6b34..0000000000 --- a/src/arch/x86/include/arch/intel-family.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ARCH_INTEL_FAMILY_H -#define ARCH_INTEL_FAMILY_H - -#define CPU_MODEL_INTEL_CORE_YONAH 0x0E - -#define CPU_MODEL_INTEL_CORE2_MEROM 0x0F -#define CPU_MODEL_INTEL_CORE2_MEROM_L 0x16 -#define CPU_MODEL_INTEL_CORE2_PENRYN 0x17 -#define CPU_MODEL_INTEL_CORE2_DUNNINGTON 0x1D - -#define CPU_MODEL_INTEL_NEHALEM 0x1E -/* Auburndale / Havendale */ -#define CPU_MODEL_INTEL_NEHALEM_G 0x1F -#define CPU_MODEL_INTEL_NEHALEM_EP 0x1A -#define CPU_MODEL_INTEL_NEHALEM_EX 0x2E - -#define CPU_MODEL_INTEL_WESTMERE 0x25 -#define CPU_MODEL_INTEL_WESTMERE_EP 0x2C -#define CPU_MODEL_INTEL_WESTMERE_EX 0x2F - -#define CPU_MODEL_INTEL_SANDYBRIDGE 0x2A -#define CPU_MODEL_INTEL_SANDYBRIDGE_X 0x2D -#define CPU_MODEL_INTEL_IVYBRIDGE 0x3A -#define CPU_MODEL_INTEL_IVYBRIDGE_X 0x3E - -#define CPU_MODEL_INTEL_HASWELL_CORE 0x3C -#define CPU_MODEL_INTEL_HASWELL_X 0x3F -#define CPU_MODEL_INTEL_HASWELL_ULT 0x45 -#define CPU_MODEL_INTEL_HASWELL_GT3E 0x46 - -#define CPU_MODEL_INTEL_BROADWELL_CORE 0x3D -#define CPU_MODEL_INTEL_BROADWELL_GT3E 0x47 -#define CPU_MODEL_INTEL_BROADWELL_X 0x4F -#define CPU_MODEL_INTEL_BROADWELL_XEON_D 0x56 - -#define CPU_MODEL_INTEL_SKYLAKE_MOBILE 0x4E -#define CPU_MODEL_INTEL_SKYLAKE_DESKTOP 0x5E -#define CPU_MODEL_INTEL_SKYLAKE_X 0x55 -#define CPU_MODEL_INTEL_KABYLAKE_MOBILE 0x8E -#define CPU_MODEL_INTEL_KABYLAKE_DESKTOP 0x9E -#define CPU_MODEL_INTEL_CANNONLAKE_MOBILE 0x66 -#define CPU_MODEL_INTEL_ICELAKE_MOBILE 0x7E - -/* "Small Core" Processors (Atom) */ - -#define CPU_MODEL_INTEL_ATOM_PINEVIEW 0x1C -#define CPU_MODEL_INTEL_ATOM_LINCROFT 0x26 -#define CPU_MODEL_INTEL_ATOM_PENWELL 0x27 -#define CPU_MODEL_INTEL_ATOM_CLOVERVIEW 0x35 -#define CPU_MODEL_INTEL_ATOM_CEDARVIEW 0x36 -/* BayTrail/BYT / Valleyview */ -#define CPU_MODEL_INTEL_ATOM_SILVERMONT1 0x37 -/* Avaton/Rangely */ -#define CPU_MODEL_INTEL_ATOM_SILVERMONT2 0x4D -/* CherryTrail / Braswell */ -#define CPU_MODEL_INTEL_ATOM_AIRMONT 0x4C -/* Tangier */ -#define CPU_MODEL_INTEL_ATOM_MERRIFIELD 0x4A -/* Anniedale */ -#define CPU_MODEL_INTEL_ATOM_MOOREFIELD 0x5A -#define CPU_MODEL_INTEL_ATOM_GOLDMONT 0x5C -/* Goldmont Microserver */ -#define CPU_MODEL_INTEL_ATOM_DENVERTON 0x5F -#define CPU_MODEL_INTEL_ATOM_GEMINI_LAKE 0x7A - -/* Xeon Phi */ - -/* Knights Landing */ -#define CPU_MODEL_INTEL_XEON_PHI_KNL 0x57 -/* Knights Mill */ -#define CPU_MODEL_INTEL_XEON_PHI_KNM 0x85 - -#endif /* ARCH_INTEL_FAMILY_H */ diff --git a/src/arch/x86/include/arch/interrupt.h b/src/arch/x86/include/arch/interrupt.h index 086e5bc8f2..baf6b7829a 100644 --- a/src/arch/x86/include/arch/interrupt.h +++ b/src/arch/x86/include/arch/interrupt.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2009 Libra Li - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index bc229d9952..5938cdc51d 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h index de80f42a0d..11da892af0 100644 --- a/src/arch/x86/include/arch/memlayout.h +++ b/src/arch/x86/include/arch/memlayout.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -16,13 +14,6 @@ #ifndef __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H - -#if ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_VERSTAGE -/* No .data or .bss sections. Cache as RAM is handled separately. */ -#define ARCH_STAGE_HAS_DATA_SECTION 0 -#define ARCH_STAGE_HAS_BSS_SECTION 0 -#endif - #if (CONFIG_RAMTOP == 0) # error "CONFIG_RAMTOP not configured" #endif diff --git a/src/arch/x86/include/arch/memory_clear.h b/src/arch/x86/include/arch/memory_clear.h index 87ad7ada85..2b887b848f 100644 --- a/src/arch/x86/include/arch/memory_clear.h +++ b/src/arch/x86/include/arch/memory_clear.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 9elements Agency GmbH - * Copyright (C) 2019 Facebook Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h b/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h index 00e8e41088..36a88f1e4d 100644 --- a/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h +++ b/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/include/arch/pirq_routing.h b/src/arch/x86/include/arch/pirq_routing.h index b416ec1422..60495a1d46 100644 --- a/src/arch/x86/include/arch/pirq_routing.h +++ b/src/arch/x86/include/arch/pirq_routing.h @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Alexandru Gagniuc - * Copyright (C) 2012 Patrick Georgi - * Copyright (C) 2010 Stefan Reinauer - * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 2 of the License, or diff --git a/src/arch/x86/include/arch/registers.h b/src/arch/x86/include/arch/registers.h index 41275a8dc2..8cf0d48486 100644 --- a/src/arch/x86/include/arch/registers.h +++ b/src/arch/x86/include/arch/registers.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h new file mode 100644 index 0000000000..15c93f24bd --- /dev/null +++ b/src/arch/x86/include/arch/romstage.h @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ARCH_ROMSTAGE_H__ +#define __ARCH_ROMSTAGE_H__ + +#include +#include +#include + +void mainboard_romstage_entry(void); + +/* + * Support setting up a stack frame consisting of MTRR information + * for use in bootstrapping the caching attributes after cache-as-ram + * is torn down. + */ + +struct postcar_frame { + uintptr_t stack; + uint32_t upper_mask; + int max_var_mtrrs; + int num_var_mtrrs; + int skip_common_mtrr; +}; + +/* + * Initialize postcar_frame object allocating stack from cbmem, + * with stack_size == 0, default 4 KiB is allocated. + * Returns 0 on success, < 0 on error. + */ +int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size); + +/* + * Add variable MTRR covering the provided range with MTRR type. + */ +void postcar_frame_add_mtrr(struct postcar_frame *pcf, + uintptr_t addr, size_t size, int type); + +/* + * Add variable MTRR covering the memory-mapped ROM with given MTRR type. + */ +void postcar_frame_add_romcache(struct postcar_frame *pcf, int type); + +/* + * Add a common MTRR setup most platforms will have as a subset. + */ +void postcar_frame_common_mtrrs(struct postcar_frame *pcf); + +/* + * fill_postcar_frame() is called after raminit completes and right before + * calling run_postcar_phase(). Implementation should call postcar_frame_add_mtrr() + * to tag memory ranges as cacheable to speed up execution of postcar and + * early ramstage. + */ +void fill_postcar_frame(struct postcar_frame *pcf); + +/* + * prepare_and_run_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. + */ +void prepare_and_run_postcar(struct postcar_frame *pcf); + +/* + * Load and run a program that takes control of execution that + * tears down CAR and loads ramstage. The postcar_frame object + * indicates how to set up the frame. If caching is enabled at + * the time of the call it is up to the platform code to handle + * coherency with dirty lines in the cache using some mechansim + * such as platform_prog_run() because run_postcar_phase() + * utilizes prog_run() internally. + */ +void run_postcar_phase(struct postcar_frame *pcf); + +/* + * Systems without a native coreboot cache-as-ram teardown may implement + * this to use an alternate method. + */ +void late_car_teardown(void); + +/* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ +void postcar_enable_tseg_cache(struct postcar_frame *pcf); + +#endif /* __ARCH_ROMSTAGE_H__ */ diff --git a/src/arch/x86/include/arch/smp/mpspec.h b/src/arch/x86/include/arch/smp/mpspec.h index 1e7300fea6..7500945c42 100644 --- a/src/arch/x86/include/arch/smp/mpspec.h +++ b/src/arch/x86/include/arch/smp/mpspec.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/include/arch/stages.h b/src/arch/x86/include/arch/stages.h index 5716030274..3ef3cae148 100644 --- a/src/arch/x86/include/arch/stages.h +++ b/src/arch/x86/include/arch/stages.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/include/arch/symbols.h b/src/arch/x86/include/arch/symbols.h index 97a07c0746..f715e0a6d1 100644 --- a/src/arch/x86/include/arch/symbols.h +++ b/src/arch/x86/include/arch/symbols.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -27,31 +24,18 @@ extern char _car_region_end[]; #define _car_region_size (_car_region_end - _car_region_start) /* - * This is the stack used under CONFIG_C_ENVIRONMENT_BOOTBLOCK for - * all stages that execute when cache-as-ram is up. + * This is the stack area used for all stages that execute when cache-as-ram + * is up. Area is not cleared in between stages. */ extern char _car_stack_start[]; extern char _car_stack_end[]; #define _car_stack_size (_car_stack_end - _car_stack_start) +extern char _car_unallocated_start[]; + extern char _car_ehci_dbg_info_start[]; extern char _car_ehci_dbg_info_end[]; #define _car_ehci_dbg_info_size \ (_car_ehci_dbg_info_end - _car_ehci_dbg_info_start) -/* - * The _car_relocatable_data_[start|end] symbols cover CAR data which is - * relocatable once memory comes online. Variables with CAR_GLOBAL decoration - * reside within this region. The _car_global_[start|end] is a subset of the - * relocatable region which excludes the timestamp region because of - * intricacies in the timestamp code. - */ -extern char _car_relocatable_data_start[]; -extern char _car_relocatable_data_end[]; -#define _car_relocatable_data_size \ - (_car_relocatable_data_end - _car_relocatable_data_start) -extern char _car_global_start[]; -extern char _car_global_end[]; -#define _car_global_size (_car_global_end - _car_global_start) - #endif diff --git a/src/arch/x86/include/cf9_reset.h b/src/arch/x86/include/cf9_reset.h index 7b44e0f2a6..e05c2e1c34 100644 --- a/src/arch/x86/include/cf9_reset.h +++ b/src/arch/x86/include/cf9_reset.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corp. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/include/smm.h b/src/arch/x86/include/smm.h index d66e8906d6..320bac61aa 100644 --- a/src/arch/x86/include/smm.h +++ b/src/arch/x86/include/smm.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index 34ab202f71..bf2ba6b255 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index cc72552254..9fd9889911 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -16,6 +14,15 @@ #include #include +/* Pull in the either CAR or early DRAM rules. */ +#if ENV_ROMSTAGE_OR_BEFORE +#if ENV_CACHE_AS_RAM +#define EARLY_MEMLAYOUT "car.ld" +#else +#error "Early DRAM environment for x86 is work-in-progress. */ +#endif +#endif + SECTIONS { /* @@ -34,23 +41,20 @@ SECTIONS * Link at 32MiB address and rely on cbfstool to relocate to XIP. */ ROMSTAGE(CONFIG_ROMSTAGE_ADDR, 1M) - /* Pull in the cache-as-ram rules. */ - #include "car.ld" + #include EARLY_MEMLAYOUT #elif ENV_VERSTAGE /* The 1M size is not allocated. It's just for basic size checking. * Link at 32MiB address and rely on cbfstool to relocate to XIP. */ VERSTAGE(CONFIG_VERSTAGE_ADDR, 1M) - /* Pull in the cache-as-ram rules. */ - #include "car.ld" + #include EARLY_MEMLAYOUT #elif ENV_BOOTBLOCK /* This is for C_ENVIRONMENT_BOOTBLOCK. arch/x86/bootblock.ld contains * the logic for the romcc linking. */ BOOTBLOCK(0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1, CONFIG_C_ENV_BOOTBLOCK_SIZE) - /* Pull in the cache-as-ram rules. */ - #include "car.ld" + #include EARLY_MEMLAYOUT #elif ENV_POSTCAR POSTCAR(32M, 1M) diff --git a/src/arch/x86/memset.c b/src/arch/x86/memset.c index b536e68227..0767683d12 100644 --- a/src/arch/x86/memset.c +++ b/src/arch/x86/memset.c @@ -1,6 +1,4 @@ /* - * Copyright (C) 1991,1992,1993,1997,1998,2003, 2005 Free Software Foundation, - * Inc. * This file is part of the GNU C Library. * * This program is free software; you can redistribute it and/or diff --git a/src/arch/x86/mmap_boot.c b/src/arch/x86/mmap_boot.c index abfa024a54..762193090b 100644 --- a/src/arch/x86/mmap_boot.c +++ b/src/arch/x86/mmap_boot.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/mpspec.c b/src/arch/x86/mpspec.c index 28a9080e2e..eeca81606e 100644 --- a/src/arch/x86/mpspec.c +++ b/src/arch/x86/mpspec.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/pirq_routing.c b/src/arch/x86/pirq_routing.c index 9d1f5910e9..ab3793c3a7 100644 --- a/src/arch/x86/pirq_routing.c +++ b/src/arch/x86/pirq_routing.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Alexandru Gagniuc - * Copyright (C) 2010 Stefan Reinauer - * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 2 of the License, or diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index b4efc949b4..add72c2cda 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -13,7 +11,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include @@ -33,7 +31,10 @@ void main(void) console_init(); - /* Recover cbmem so infrastruture using it is functional. */ + /* + * CBMEM needs to be recovered because timestamps rely on + * the cbmem infrastructure being around. Explicitly recover it. + */ cbmem_initialize(); timestamp_add_now(TS_START_POSTCAR); diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 35e139fe1c..c6149ab26a 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -13,12 +11,13 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include #include #include +#include #include #include #include @@ -120,7 +119,31 @@ void postcar_frame_add_romcache(struct postcar_frame *pcf, int type) postcar_frame_add_mtrr(pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, type); } -void *postcar_commit_mtrrs(struct postcar_frame *pcf) +void postcar_frame_common_mtrrs(struct postcar_frame *pcf) +{ + if (pcf->skip_common_mtrr) + return; + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT); +} + +/* prepare_and_run_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. */ +void prepare_and_run_postcar(struct postcar_frame *pcf) +{ + if (postcar_frame_init(pcf, 0)) + die("Unable to initialize postcar frame.\n"); + + fill_postcar_frame(pcf); + + postcar_frame_common_mtrrs(pcf); + + run_postcar_phase(pcf); + /* We do not return here. */ +} + +static void postcar_commit_mtrrs(struct postcar_frame *pcf) { /* * Place the number of used variable MTRRs on stack then max number @@ -128,7 +151,6 @@ void *postcar_commit_mtrrs(struct postcar_frame *pcf) */ stack_push(pcf, pcf->num_var_mtrrs); stack_push(pcf, pcf->max_var_mtrrs); - return (void *) pcf->stack; } static void finalize_load(uintptr_t *stack_top_ptr, uintptr_t stack_top) @@ -166,6 +188,23 @@ static void load_postcar_cbfs(struct prog *prog, struct postcar_frame *pcf) stage_cache_add(STAGE_POSTCAR, prog); } +/* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ +void postcar_enable_tseg_cache(struct postcar_frame *pcf) +{ + uintptr_t smm_base; + size_t smm_size; + + smm_region(&smm_base, &smm_size); + postcar_frame_add_mtrr(pcf, smm_base, smm_size, + MTRR_TYPE_WRBACK); +} + void run_postcar_phase(struct postcar_frame *pcf) { struct prog prog = diff --git a/src/arch/x86/prologue.inc b/src/arch/x86/prologue.inc index 209a0042ac..4036ff9862 100644 --- a/src/arch/x86/prologue.inc +++ b/src/arch/x86/prologue.inc @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2002 Eric Biederman - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/rdrand.c b/src/arch/x86/rdrand.c index c9090df1fd..bf9e687ae1 100644 --- a/src/arch/x86/rdrand.c +++ b/src/arch/x86/rdrand.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 346e874217..4eb8726137 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -1,11 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson , - * Raptor Engineering - * Copyright (C) 2011 Sven Schnelle - * Copyright (C) 2018 Patrick Rudolph - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of @@ -275,20 +270,18 @@ static void trim_trailing_whitespace(char *buffer, size_t buffer_size) static void smbios_fill_dimm_part_number(const char *part_number, struct smbios_type17 *t) { - const size_t trimmed_buffer_size = DIMM_INFO_PART_NUMBER_SIZE; - int invalid; size_t i, len; - char trimmed_part_number[trimmed_buffer_size]; + char trimmed_part_number[DIMM_INFO_PART_NUMBER_SIZE]; - strncpy(trimmed_part_number, part_number, trimmed_buffer_size); - trimmed_part_number[trimmed_buffer_size - 1] = '\0'; + strncpy(trimmed_part_number, part_number, sizeof(trimmed_part_number)); + trimmed_part_number[sizeof(trimmed_part_number) - 1] = '\0'; /* * SPD mandates that unused characters be represented with a ' '. * We don't want to publish the whitespace in the SMBIOS tables. */ - trim_trailing_whitespace(trimmed_part_number, trimmed_buffer_size); + trim_trailing_whitespace(trimmed_part_number, sizeof(trimmed_part_number)); len = strlen(trimmed_part_number); @@ -304,8 +297,7 @@ static void smbios_fill_dimm_part_number(const char *part_number, /* Null String in Part Number will have "None" instead. */ t->part_number = smbios_add_string(t->eos, "None"); } else if (invalid) { - char string_buffer[trimmed_buffer_size + - 10 /* strlen("Invalid ()") */]; + char string_buffer[sizeof(trimmed_part_number) + 10]; snprintf(string_buffer, sizeof(string_buffer), "Invalid (%s)", trimmed_part_number); diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 0baa58eb2b..ddb0710c8a 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2005 Steve Magnani - * Copyright (C) 2008-2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/thread.c b/src/arch/x86/thread.c index b1cd99fe99..d92d8fdeca 100644 --- a/src/arch/x86/thread.c +++ b/src/arch/x86/thread.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/thread_switch.S b/src/arch/x86/thread_switch.S index 169b7ebde7..1c1dedef1b 100644 --- a/src/arch/x86/thread_switch.S +++ b/src/arch/x86/thread_switch.S @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/timestamp.c b/src/arch/x86/timestamp.c index 5b48c23be2..92d9590af4 100644 --- a/src/arch/x86/timestamp.c +++ b/src/arch/x86/timestamp.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/verstage.c b/src/arch/x86/verstage.c index d24866bcab..ad13e60f0c 100644 --- a/src/arch/x86/verstage.c +++ b/src/arch/x86/verstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/x86/wakeup.S b/src/arch/x86/wakeup.S index ba502fefa5..187b96cab9 100644 --- a/src/arch/x86/wakeup.S +++ b/src/arch/x86/wakeup.S @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 Rudolf Marek - * Copyright (C) 2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -64,14 +61,6 @@ __wakeup: shr $4, %eax movw %ax, (__wakeup_segment) - /* Then overwrite coreboot with our backed up memory */ - cld - movl 8(%esp), %esi - movl 12(%esp), %edi - movl 16(%esp), %ecx - shrl $2, %ecx - rep movsl - /* Activate the right segment descriptor real mode. */ ljmp $0x28, $RELOCATED(1f) 1: diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c index a509bc9f61..5c9aacba20 100644 --- a/src/commonlib/cbfs.c +++ b/src/commonlib/cbfs.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/commonlib/fsp_relocate.c b/src/commonlib/fsp_relocate.c index 32e6b6da64..85deda2470 100644 --- a/src/commonlib/fsp_relocate.c +++ b/src/commonlib/fsp_relocate.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/commonlib/include/commonlib/cbfs.h b/src/commonlib/include/commonlib/cbfs.h index c31df51263..cadc8c92cc 100644 --- a/src/commonlib/include/commonlib/cbfs.h +++ b/src/commonlib/include/commonlib/cbfs.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index ec702ecfdf..30bf88ada8 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2013 Google, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -79,6 +76,7 @@ #define CBMEM_ID_ROM1 0x524f4d31 #define CBMEM_ID_ROM2 0x524f4d32 #define CBMEM_ID_ROM3 0x524f4d33 +#define CBMEM_ID_FMAP 0x464d4150 #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ @@ -137,5 +135,6 @@ { CBMEM_ID_ROM0, "VGA ROM #0 "}, \ { CBMEM_ID_ROM1, "VGA ROM #1 "}, \ { CBMEM_ID_ROM2, "VGA ROM #2 "}, \ - { CBMEM_ID_ROM3, "VGA ROM #3 "}, + { CBMEM_ID_ROM3, "VGA ROM #3 "}, \ + { CBMEM_ID_FMAP, "FMAP "}, #endif /* _CBMEM_ID_H_ */ diff --git a/src/commonlib/include/commonlib/compiler.h b/src/commonlib/include/commonlib/compiler.h index 5078759360..972a2293a2 100644 --- a/src/commonlib/include/commonlib/compiler.h +++ b/src/commonlib/include/commonlib/compiler.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/commonlib/include/commonlib/compression.h b/src/commonlib/include/commonlib/compression.h index 428ee42e65..3988ef8ade 100644 --- a/src/commonlib/include/commonlib/compression.h +++ b/src/commonlib/include/commonlib/compression.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 7bded2a3a3..68166701b0 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -89,6 +89,7 @@ enum { LB_TAG_VBOOT_WORKBUF = 0x0034, LB_TAG_MMC_INFO = 0x0035, LB_TAG_TCPA_LOG = 0x0036, + LB_TAG_FMAP = 0x0037, LB_TAG_CMOS_OPTION_TABLE = 0x00c8, LB_TAG_OPTION = 0x00c9, LB_TAG_OPTION_ENUM = 0x00ca, diff --git a/src/commonlib/include/commonlib/endian.h b/src/commonlib/include/commonlib/endian.h index 7b08eee7af..3d7ccb112b 100644 --- a/src/commonlib/include/commonlib/endian.h +++ b/src/commonlib/include/commonlib/endian.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/commonlib/include/commonlib/fsp.h b/src/commonlib/include/commonlib/fsp.h index a2a2faebe8..2ae7949c8e 100644 --- a/src/commonlib/include/commonlib/fsp.h +++ b/src/commonlib/include/commonlib/fsp.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/commonlib/include/commonlib/iobuf.h b/src/commonlib/include/commonlib/iobuf.h index c5a0f4c6fb..f114ef8fe5 100644 --- a/src/commonlib/include/commonlib/iobuf.h +++ b/src/commonlib/include/commonlib/iobuf.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/commonlib/include/commonlib/loglevel.h b/src/commonlib/include/commonlib/loglevel.h index 4247532c89..7a1654179d 100644 --- a/src/commonlib/include/commonlib/loglevel.h +++ b/src/commonlib/include/commonlib/loglevel.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Nicholas Sielicki - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/commonlib/include/commonlib/mem_pool.h b/src/commonlib/include/commonlib/mem_pool.h index c21fa0e8aa..ed473ebdf2 100644 --- a/src/commonlib/include/commonlib/mem_pool.h +++ b/src/commonlib/include/commonlib/mem_pool.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h index 45484dddd6..dca12dc741 100644 --- a/src/commonlib/include/commonlib/region.h +++ b/src/commonlib/include/commonlib/region.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/commonlib/include/commonlib/rmodule-defs.h b/src/commonlib/include/commonlib/rmodule-defs.h index 564fcd26af..de06941fa2 100644 --- a/src/commonlib/include/commonlib/rmodule-defs.h +++ b/src/commonlib/include/commonlib/rmodule-defs.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/commonlib/include/commonlib/sd_mmc_ctrlr.h b/src/commonlib/include/commonlib/sd_mmc_ctrlr.h index 247c0a513a..d4a7d54ff5 100644 --- a/src/commonlib/include/commonlib/sd_mmc_ctrlr.h +++ b/src/commonlib/include/commonlib/sd_mmc_ctrlr.h @@ -1,10 +1,5 @@ /* - * Copyright 2011, Marvell Semiconductor Inc. - * Lei Wen - * - * Copyright 2017 Intel Corporation - * - * Controller independent definitions + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -15,6 +10,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Controller independent definitions */ #ifndef __COMMONLIB_SD_MMC_CTRLR_H__ #define __COMMONLIB_SD_MMC_CTRLR_H__ diff --git a/src/commonlib/include/commonlib/sdhci.h b/src/commonlib/include/commonlib/sdhci.h index ffeb6625d9..015fd0c6f9 100644 --- a/src/commonlib/include/commonlib/sdhci.h +++ b/src/commonlib/include/commonlib/sdhci.h @@ -1,10 +1,5 @@ /* - * Copyright 2011, Marvell Semiconductor Inc. - * Lei Wen - * - * Copyright 2017 Intel Corporation - * - * SD host controller specific definitions + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -15,6 +10,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * SD host controller specific definitions */ #ifndef __COMMONLIB_SDHCI_H__ #define __COMMONLIB_SDHCI_H__ diff --git a/src/commonlib/include/commonlib/sort.h b/src/commonlib/include/commonlib/sort.h index 3d94d25d40..3d91cd8ec8 100644 --- a/src/commonlib/include/commonlib/sort.h +++ b/src/commonlib/include/commonlib/sort.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Siemens AG - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/commonlib/include/commonlib/storage.h b/src/commonlib/include/commonlib/storage.h index 6ad53dcf8e..47a2bb6543 100644 --- a/src/commonlib/include/commonlib/storage.h +++ b/src/commonlib/include/commonlib/storage.h @@ -1,9 +1,5 @@ /* - * Copyright 2008,2010 Freescale Semiconductor, Inc - * Andy Fleming - * - * Copyright 2013 Google Inc. All rights reserved. - * Copyright 2017 Intel Corporation + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/commonlib/include/commonlib/tcpa_log_serialized.h b/src/commonlib/include/commonlib/tcpa_log_serialized.h index 434ff34c46..020eb04eee 100644 --- a/src/commonlib/include/commonlib/tcpa_log_serialized.h +++ b/src/commonlib/include/commonlib/tcpa_log_serialized.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Facebook Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index bb0dcfc7f4..7b1a7301c7 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/commonlib/iobuf.c b/src/commonlib/iobuf.c index b73ee1929e..fc0b2ed809 100644 --- a/src/commonlib/iobuf.c +++ b/src/commonlib/iobuf.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c index cb3e726f25..0aa821b24f 100644 --- a/src/commonlib/mem_pool.c +++ b/src/commonlib/mem_pool.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/commonlib/region.c b/src/commonlib/region.c index 541a125ad4..ca7b6efe4b 100644 --- a/src/commonlib/region.c +++ b/src/commonlib/region.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -27,10 +25,10 @@ int region_is_subregion(const struct region *p, const struct region *c) if (region_offset(c) < region_offset(p)) return 0; - if (region_sz(c) > region_sz(p)) + if (region_end(c) > region_end(p)) return 0; - if (region_end(c) > region_end(p)) + if (region_end(c) < region_offset(c)) return 0; return 1; diff --git a/src/commonlib/sort.c b/src/commonlib/sort.c index 350138ec02..98d2db264f 100644 --- a/src/commonlib/sort.c +++ b/src/commonlib/sort.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Siemens AG - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/commonlib/storage/Kconfig b/src/commonlib/storage/Kconfig index c7bb70d399..88b8204472 100644 --- a/src/commonlib/storage/Kconfig +++ b/src/commonlib/storage/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2017 Intel Corp. -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/commonlib/storage/Makefile.inc b/src/commonlib/storage/Makefile.inc index af5137e287..75b4548a57 100644 --- a/src/commonlib/storage/Makefile.inc +++ b/src/commonlib/storage/Makefile.inc @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Intel Corporation. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. diff --git a/src/commonlib/storage/bouncebuf.c b/src/commonlib/storage/bouncebuf.c index 5d98c74489..99287b6270 100644 --- a/src/commonlib/storage/bouncebuf.c +++ b/src/commonlib/storage/bouncebuf.c @@ -1,8 +1,5 @@ /* - * Generic bounce buffer implementation - * - * Copyright (C) 2012 Marek Vasut - * Copyright 2013 Google Inc. All rights reserved. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -13,6 +10,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Generic bounce buffer implementation */ #include diff --git a/src/commonlib/storage/bouncebuf.h b/src/commonlib/storage/bouncebuf.h index 0d81be1faa..3e702fad29 100644 --- a/src/commonlib/storage/bouncebuf.h +++ b/src/commonlib/storage/bouncebuf.h @@ -1,8 +1,5 @@ /* - * Generic bounce buffer implementation - * - * Copyright (C) 2012 Marek Vasut - * Copyright 2013 Google Inc. All rights reserved. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -13,6 +10,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Generic bounce buffer implementation */ #ifndef __COMMONLIB_STORAGE_BOUNCEBUF_H__ diff --git a/src/commonlib/storage/mmc.c b/src/commonlib/storage/mmc.c index 3c82f51a4f..0b682adc89 100644 --- a/src/commonlib/storage/mmc.c +++ b/src/commonlib/storage/mmc.c @@ -1,12 +1,5 @@ /* - * Copyright 2008, Freescale Semiconductor, Inc - * Andy Fleming - * - * Copyright 2013 Google Inc. All rights reserved. - * Copyright 2017 Intel Corporation - * - * MultiMediaCard (MMC) and eMMC specific support code - * This code is controller independent + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -17,6 +10,9 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * MultiMediaCard (MMC) and eMMC specific support code + * This code is controller independent */ #include diff --git a/src/commonlib/storage/mmc.h b/src/commonlib/storage/mmc.h index 87d16353c8..2441d5d7e8 100644 --- a/src/commonlib/storage/mmc.h +++ b/src/commonlib/storage/mmc.h @@ -1,9 +1,5 @@ /* - * Copyright 2008,2010 Freescale Semiconductor, Inc - * Andy Fleming - * - * Copyright 2013 Google Inc. All rights reserved. - * Copyright 2017 Intel Corporation + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/commonlib/storage/pci_sdhci.c b/src/commonlib/storage/pci_sdhci.c index 1798c2cac7..de248b7720 100644 --- a/src/commonlib/storage/pci_sdhci.c +++ b/src/commonlib/storage/pci_sdhci.c @@ -1,6 +1,5 @@ /* - * Copyright 2013 Google Inc. - * Copyright 2017 Intel Corporation + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/commonlib/storage/sd.c b/src/commonlib/storage/sd.c index 06f0156c82..bdb0baa2e4 100644 --- a/src/commonlib/storage/sd.c +++ b/src/commonlib/storage/sd.c @@ -1,12 +1,5 @@ /* - * Copyright 2008, Freescale Semiconductor, Inc - * Andy Fleming - * - * Copyright 2013 Google Inc. All rights reserved. - * Copyright 2017 Intel Corporation - * - * Secure Digital (SD) card specific support code - * This code is controller independent + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -17,6 +10,9 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Secure Digital (SD) card specific support code + * This code is controller independent */ #include diff --git a/src/commonlib/storage/sd_mmc.c b/src/commonlib/storage/sd_mmc.c index 348d3fe17d..ae15656189 100644 --- a/src/commonlib/storage/sd_mmc.c +++ b/src/commonlib/storage/sd_mmc.c @@ -1,13 +1,5 @@ /* - * Copyright 2008, Freescale Semiconductor, Inc - * Andy Fleming - * - * Copyright 2013 Google Inc. All rights reserved. - * Copyright 2017 Intel Corporation - * - * MultiMediaCard (MMC), eMMC and Secure Digital (SD) common initialization - * code which brings the card into the standby state. This code is controller - * independent. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -18,6 +10,10 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * MultiMediaCard (MMC), eMMC and Secure Digital (SD) common initialization + * code which brings the card into the standby state. This code is controller + * independent. */ #include diff --git a/src/commonlib/storage/sd_mmc.h b/src/commonlib/storage/sd_mmc.h index f3a6e8adbd..b1ae0f3f06 100644 --- a/src/commonlib/storage/sd_mmc.h +++ b/src/commonlib/storage/sd_mmc.h @@ -1,5 +1,5 @@ /* - * Copyright 2017 Intel Corporation + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/commonlib/storage/sdhci.c b/src/commonlib/storage/sdhci.c index 19daa2ee7e..25c0d6f1eb 100644 --- a/src/commonlib/storage/sdhci.c +++ b/src/commonlib/storage/sdhci.c @@ -1,10 +1,5 @@ /* - * Copyright 2011, Marvell Semiconductor Inc. - * Lei Wen - * - * Copyright 2017 Intel Corporation - * - * Secure Digital (SD) Host Controller interface specific code + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -15,6 +10,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Secure Digital (SD) Host Controller interface specific code */ #include "bouncebuf.h" diff --git a/src/commonlib/storage/sdhci.h b/src/commonlib/storage/sdhci.h index ed8984ae6f..c745b8cc09 100644 --- a/src/commonlib/storage/sdhci.h +++ b/src/commonlib/storage/sdhci.h @@ -1,8 +1,5 @@ /* - * Copyright 2011, Marvell Semiconductor Inc. - * Lei Wen - * - * Copyright 2017 Intel Corporation + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/commonlib/storage/sdhci_adma.c b/src/commonlib/storage/sdhci_adma.c index e3209734ba..2806bdeaee 100644 --- a/src/commonlib/storage/sdhci_adma.c +++ b/src/commonlib/storage/sdhci_adma.c @@ -1,10 +1,5 @@ /* - * Copyright 2011, Marvell Semiconductor Inc. - * Lei Wen - * - * Copyright 2017 Intel Corporation - * - * Secure Digital (SD) Host Controller interface DMA support code + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -15,6 +10,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Secure Digital (SD) Host Controller interface DMA support code */ #include diff --git a/src/commonlib/storage/sdhci_display.c b/src/commonlib/storage/sdhci_display.c index 6545424e07..1bb0bcf8d8 100644 --- a/src/commonlib/storage/sdhci_display.c +++ b/src/commonlib/storage/sdhci_display.c @@ -1,10 +1,5 @@ /* - * Copyright 2011, Marvell Semiconductor Inc. - * Lei Wen - * - * Copyright 2017 Intel Corporation - * - * Secure Digital (SD) Host Controller interface specific code + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -15,6 +10,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Secure Digital (SD) Host Controller interface specific code */ #include diff --git a/src/commonlib/storage/storage.c b/src/commonlib/storage/storage.c index f434a6c0b6..df040cae21 100644 --- a/src/commonlib/storage/storage.c +++ b/src/commonlib/storage/storage.c @@ -1,14 +1,5 @@ /* - * Copyright 2008, Freescale Semiconductor, Inc - * Andy Fleming - * - * Copyright 2013 Google Inc. All rights reserved. - * Copyright 2017 Intel Corporation - * - * MultiMediaCard (MMC), eMMC and Secure Digital (SD) common code which - * transitions the card from the standby state to the transfer state. The - * common code supports read operations, erase and write operations are in - * a separate modules. This code is controller independent. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -19,6 +10,11 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * MultiMediaCard (MMC), eMMC and Secure Digital (SD) common code which + * transitions the card from the standby state to the transfer state. The + * common code supports read operations, erase and write operations are in + * a separate modules. This code is controller independent. */ #include diff --git a/src/commonlib/storage/storage.h b/src/commonlib/storage/storage.h index c71510dd19..f03ed554fc 100644 --- a/src/commonlib/storage/storage.h +++ b/src/commonlib/storage/storage.h @@ -1,5 +1,5 @@ /* - * Copyright 2017 Intel Corporation + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/commonlib/storage/storage_erase.c b/src/commonlib/storage/storage_erase.c index 8e97755238..a8da366438 100644 --- a/src/commonlib/storage/storage_erase.c +++ b/src/commonlib/storage/storage_erase.c @@ -1,12 +1,5 @@ /* - * Copyright 2008, Freescale Semiconductor, Inc - * Andy Fleming - * - * Copyright 2013 Google Inc. All rights reserved. - * Copyright 2017 Intel Corporation - * - * MultiMediaCard (MMC), eMMC and Secure Digital (SD) erase support code. - * This code is controller independent. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -17,6 +10,9 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * MultiMediaCard (MMC), eMMC and Secure Digital (SD) erase support code. + * This code is controller independent. */ #include "sd_mmc.h" diff --git a/src/commonlib/storage/storage_write.c b/src/commonlib/storage/storage_write.c index d21cc293db..ec19dd2182 100644 --- a/src/commonlib/storage/storage_write.c +++ b/src/commonlib/storage/storage_write.c @@ -1,12 +1,5 @@ /* - * Copyright 2008, Freescale Semiconductor, Inc - * Andy Fleming - * - * Copyright 2013 Google Inc. All rights reserved. - * Copyright 2017 Intel Corporation - * - * MultiMediaCard (MMC), eMMC and Secure Digital (SD) write support code. - * This code is controller independent. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -17,6 +10,9 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * MultiMediaCard (MMC), eMMC and Secure Digital (SD) write support code. + * This code is controller independent. */ #include diff --git a/src/console/Kconfig b/src/console/Kconfig index 4cb407e785..5d505d2d21 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -13,7 +13,7 @@ config BOOTBLOCK_CONSOLE config POSTCAR_CONSOLE bool "Enable console output during postcar." depends on POSTCAR_STAGE - default n + default y help Use console during the postcar if supported diff --git a/src/console/console.c b/src/console/console.c index 50ee5c30e5..a36cb96ed1 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003 Eric Biederman - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/console/die.c b/src/console/die.c index 3a17126264..76c456d1fb 100644 --- a/src/console/die.c +++ b/src/console/die.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003 Eric Biederman - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/console/hw-debug_sink.adb b/src/console/hw-debug_sink.adb index 4331b87549..78359cd50b 100644 --- a/src/console/hw-debug_sink.adb +++ b/src/console/hw-debug_sink.adb @@ -1,8 +1,6 @@ -- -- This file is part of the coreboot project. -- --- Copyright (C) 2015 secunet Security Networks AG --- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; version 2 of the License. diff --git a/src/console/hw-debug_sink.ads b/src/console/hw-debug_sink.ads index 322249e1cb..8598966f0c 100644 --- a/src/console/hw-debug_sink.ads +++ b/src/console/hw-debug_sink.ads @@ -1,8 +1,6 @@ -- -- This file is part of the coreboot project. -- --- Copyright (C) 2015 secunet Security Networks AG --- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; version 2 of the License. diff --git a/src/console/init.c b/src/console/init.c index 43b499d816..d4818580e4 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003 Eric Biederman - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of @@ -24,11 +22,7 @@ #include /* Mutable console log level only allowed when RAM comes online. */ -#if defined(__PRE_RAM__) -#define CONSOLE_LEVEL_CONST 1 -#else -#define CONSOLE_LEVEL_CONST 0 -#endif +#define CONSOLE_LEVEL_CONST !ENV_STAGE_HAS_DATA_SECTION static int console_inited CAR_GLOBAL; static int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; diff --git a/src/console/post.c b/src/console/post.c index 0719e5e7df..64aa2a5513 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003 Eric Biederman - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/console/printk.c b/src/console/printk.c index 8606bbb5c9..15c599dce0 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 1991, 1992 Linus Torvalds - * Copyright (C) 2015 Timothy Pearson , - * Raptor Engineering - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -49,8 +45,7 @@ int do_vprintk(int msg_level, const char *fmt, va_list args) { int i, log_this; - if (CONFIG(SQUELCH_EARLY_SMP) && ENV_CACHE_AS_RAM && - !boot_cpu()) + if (CONFIG(SQUELCH_EARLY_SMP) && ENV_ROMSTAGE_OR_BEFORE && !boot_cpu()) return 0; log_this = console_log_level(msg_level); diff --git a/src/console/vsprintf.c b/src/console/vsprintf.c index 4892fdd1ff..78bc09f5a7 100644 --- a/src/console/vsprintf.c +++ b/src/console/vsprintf.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index f34c91bb5f..1efe55a332 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 1991, 1992 Linus Torvalds - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 6078022397..3c0bf89afd 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -6,16 +6,11 @@ source "src/cpu/*/Kconfig" if ARCH_X86 -config CACHE_AS_RAM - bool - default y - -config NO_CAR_GLOBAL_MIGRATION +config CAR_GLOBAL_MIGRATION bool default n - depends on CACHE_AS_RAM help - This option is selected if there is no need to migrate CAR globals. + This option is selected if there is need to migrate CAR globals. All stages which use CAR globals can directly access the variables from their linked addresses. @@ -28,12 +23,6 @@ config DCACHE_RAM_SIZE config DCACHE_BSP_STACK_SIZE hex -config DCACHE_BSP_STACK_SLUSH - hex - -config DCACHE_AP_STACK_SIZE - hex - config SMP bool default y if MAX_CPUS != 1 diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 4c5463cc8a..f21bf5467f 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. @@ -29,7 +27,6 @@ config CPU_AMD_AGESA select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME - select POSTCAR_STAGE select SMM_ASEG if CPU_AMD_AGESA diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index daa3d50601..d99f2b051f 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/agesa/family12/Kconfig b/src/cpu/amd/agesa/family12/Kconfig index 921ec90df8..4fc2ba076c 100644 --- a/src/cpu/amd/agesa/family12/Kconfig +++ b/src/cpu/amd/agesa/family12/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/agesa/family12/chip_name.c b/src/cpu/amd/agesa/family12/chip_name.c index 95975c5ddc..ca3c39e0ab 100644 --- a/src/cpu/amd/agesa/family12/chip_name.c +++ b/src/cpu/amd/agesa/family12/chip_name.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/agesa/family12/fixme.c b/src/cpu/amd/agesa/family12/fixme.c index f3ea89989c..c1d4c7d1a6 100644 --- a/src/cpu/amd/agesa/family12/fixme.c +++ b/src/cpu/amd/agesa/family12/fixme.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c index 406d300b21..c0669a857d 100644 --- a/src/cpu/amd/agesa/family12/model_12_init.c +++ b/src/cpu/amd/agesa/family12/model_12_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/agesa/family12/romstage.c b/src/cpu/amd/agesa/family12/romstage.c index 9d617efe4b..bca2baf483 100644 --- a/src/cpu/amd/agesa/family12/romstage.c +++ b/src/cpu/amd/agesa/family12/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2017 Kyösti Mälkki - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 0ee7eb0c4f..adbe7fdb76 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 3da8dd599b..7db1fe4ac9 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/agesa/family14/acpi/cpu.asl b/src/cpu/amd/agesa/family14/acpi/cpu.asl index f521b0a432..81b5a3550a 100644 --- a/src/cpu/amd/agesa/family14/acpi/cpu.asl +++ b/src/cpu/amd/agesa/family14/acpi/cpu.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/agesa/family14/chip_name.c b/src/cpu/amd/agesa/family14/chip_name.c index e5952876f2..4b40ec2a16 100644 --- a/src/cpu/amd/agesa/family14/chip_name.c +++ b/src/cpu/amd/agesa/family14/chip_name.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index 2368bea2b8..c2e859e229 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 7f05cd15b6..04e6f44df4 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/agesa/family14/romstage.c b/src/cpu/amd/agesa/family14/romstage.c index 7fd522fb1e..54069cc30d 100644 --- a/src/cpu/amd/agesa/family14/romstage.c +++ b/src/cpu/amd/agesa/family14/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2017 Kyösti Mälkki - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig index 7514590bb8..fde1adf118 100644 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index 46ae346282..8522eb2618 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/agesa/family15tn/acpi/cpu.asl b/src/cpu/amd/agesa/family15tn/acpi/cpu.asl index 88d611e9ac..82168508c4 100644 --- a/src/cpu/amd/agesa/family15tn/acpi/cpu.asl +++ b/src/cpu/amd/agesa/family15tn/acpi/cpu.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/agesa/family15tn/chip_name.c b/src/cpu/amd/agesa/family15tn/chip_name.c index a4285d96cd..876ef3a274 100644 --- a/src/cpu/amd/agesa/family15tn/chip_name.c +++ b/src/cpu/amd/agesa/family15tn/chip_name.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c index a3767674d8..e92aa9a9bf 100644 --- a/src/cpu/amd/agesa/family15tn/fixme.c +++ b/src/cpu/amd/agesa/family15tn/fixme.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index b614eedf56..be3d58bb1b 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/agesa/family15tn/udelay.c b/src/cpu/amd/agesa/family15tn/udelay.c index 7ff4c5c7a8..898f6c1fef 100644 --- a/src/cpu/amd/agesa/family15tn/udelay.c +++ b/src/cpu/amd/agesa/family15tn/udelay.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Alexandru Gagniuc - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig index 5138745537..9fef94d327 100644 --- a/src/cpu/amd/agesa/family16kb/Kconfig +++ b/src/cpu/amd/agesa/family16kb/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc index 9367b458a3..2ce827d951 100644 --- a/src/cpu/amd/agesa/family16kb/Makefile.inc +++ b/src/cpu/amd/agesa/family16kb/Makefile.inc @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/agesa/family16kb/acpi/cpu.asl b/src/cpu/amd/agesa/family16kb/acpi/cpu.asl index aae3287ba6..bc52b681e5 100644 --- a/src/cpu/amd/agesa/family16kb/acpi/cpu.asl +++ b/src/cpu/amd/agesa/family16kb/acpi/cpu.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/agesa/family16kb/chip_name.c b/src/cpu/amd/agesa/family16kb/chip_name.c index 0ed0e61e5e..caf2c1b2c1 100644 --- a/src/cpu/amd/agesa/family16kb/chip_name.c +++ b/src/cpu/amd/agesa/family16kb/chip_name.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c index 70e9b585f6..73d09956cd 100644 --- a/src/cpu/amd/agesa/family16kb/fixme.c +++ b/src/cpu/amd/agesa/family16kb/fixme.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index 6c1309eea4..3d53b5192b 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index f923a47db4..2054ea3438 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2005-2007 Advanced Micro Devices, Inc. - * Copyright (C) 2008 Carl-Daniel Hailfinger - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -22,8 +18,8 @@ #define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase CONFIG_DCACHE_RAM_BASE -#define CacheSizeBSPStack CONFIG_DCACHE_BSP_STACK_SIZE -#define CacheSizeBSPSlush CONFIG_DCACHE_BSP_STACK_SLUSH +#define CacheSizeBSPStack CONFIG_DCACHE_BSP_TOP_STACK_SIZE +#define CacheSizeBSPSlush CONFIG_DCACHE_BSP_TOP_STACK_SLUSH /* For CAR with Fam10h. */ #define CacheSizeAPStack CONFIG_DCACHE_AP_STACK_SIZE diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index 199a453501..fb632bb644 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -1,12 +1,6 @@ /* * This file is part of the coreboot project. * - * original idea yhlu 6.2005 (assembler code) - * - * Copyright (C) 2010 Rudolf Marek - * Copyright (C) 2015 Timothy Pearson , - * Raptor Engineering - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 50ed657f42..78e417fc13 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -1,12 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson , - * Raptor Engineering - * Copyright (C) 2012 Google LLC - * 2005.6 by yhlu - * 2006.3 yhlu add copy data from CAR to ram - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -27,6 +21,7 @@ #include #include #include +#include #include #include "cpu/amd/car/disable_cache_as_ram.c" @@ -44,12 +39,6 @@ #define print_car_debug(format, arg...) #endif -static size_t backup_size(void) -{ - size_t car_size = car_data_size(); - return ALIGN_UP(car_size + 1024, 1024); -} - static void memcpy_(void *d, const void *s, size_t len) { print_car_debug(" Copy [%08x-%08x] to [%08x - %08x] ...", @@ -58,13 +47,6 @@ static void memcpy_(void *d, const void *s, size_t len) memcpy(d, s, len); } -static void memset_(void *d, int val, size_t len) -{ - print_car_debug(" Fill [%08x-%08x] ...", - (uint32_t) d, (uint32_t) (d + len - 1)); - memset(d, val, len); -} - static int memcmp_(void *d, const void *s, size_t len) { print_car_debug(" Compare [%08x-%08x] with [%08x - %08x] ...", @@ -73,41 +55,6 @@ static int memcmp_(void *d, const void *s, size_t len) return memcmp(d, s, len); } -static void prepare_romstage_ramstack(int s3resume) -{ - size_t backup_top = backup_size(); - print_car_debug("Prepare CAR migration and stack regions..."); - - if (s3resume) { - void *resume_backup_memory = - acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - if (resume_backup_memory) - memcpy_(resume_backup_memory - + HIGH_MEMORY_SAVE - backup_top, - (void *)(CONFIG_RAMTOP - backup_top), - backup_top); - } - memset_((void *)(CONFIG_RAMTOP - backup_top), 0, backup_top); - - print_car_debug(" Done\n"); -} - -static void prepare_ramstage_region(int s3resume) -{ - size_t backup_top = backup_size(); - print_car_debug("Prepare ramstage memory region..."); - - if (s3resume) { - void *resume_backup_memory = - acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - if (resume_backup_memory) - memcpy_(resume_backup_memory, (void *) CONFIG_RAMBASE, - HIGH_MEMORY_SAVE - backup_top); - } - - print_car_debug(" Done\n"); -} - /* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 * and RevGuide for Fam12h, Pub#44739 Rev 3.10 */ @@ -131,15 +78,16 @@ asmlinkage void *post_cache_as_ram(void) * boundary during romstage execution */ volatile uint32_t *lower_stack_boundary; - lower_stack_boundary = - (void *)((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - - CONFIG_DCACHE_BSP_STACK_SIZE); + lower_stack_boundary = (void *)((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - + CONFIG_DCACHE_BSP_TOP_STACK_SIZE); + if ((*lower_stack_boundary) != 0xdeadbeef) printk(BIOS_WARNING, "BSP overran lower stack boundary. Undefined behaviour may result!\n"); - s3resume = acpi_is_wakeup_s3(); - prepare_romstage_ramstack(s3resume); + /* ACPI S3 is not supported without RELOCATABLE_RAMSTAGE and + * this will always return 0. */ + s3resume = acpi_is_wakeup_s3(); romstage_handoff_init(s3resume); @@ -153,11 +101,11 @@ asmlinkage void *post_cache_as_ram(void) void *migrated_car = (void *)(CONFIG_RAMTOP - car_size); print_car_debug("Copying data from cache to RAM..."); - memcpy_(migrated_car, _car_relocatable_data_start, car_size); + memcpy_(migrated_car, _car_global_start, car_size); print_car_debug(" Done\n"); print_car_debug("Verifying data integrity in RAM..."); - if (memcmp_(migrated_car, _car_relocatable_data_start, car_size) == 0) + if (memcmp_(migrated_car, _car_global_start, car_size) == 0) print_car_debug(" Done\n"); else print_car_debug(" FAILED\n"); @@ -177,8 +125,6 @@ asmlinkage void cache_as_ram_new_stack(void) set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); enable_cache(); - prepare_ramstage_region(acpi_is_wakeup_s3()); - set_sysinfo_in_ram(1); // So other core0 could start to train mem /*copy and execute ramstage */ diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index df6549987e..ad4f5f4ba6 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -9,7 +9,7 @@ config CPU_AMD_MODEL_10XXX select UDELAY_LAPIC select SUPPORT_CPU_UCODE_IN_CBFS select CPU_MICROCODE_MULTIPLE_FILES - select ACPI_HUGE_LOWMEM_BACKUP + select CAR_GLOBAL_MIGRATION if CPU_AMD_MODEL_10XXX @@ -36,11 +36,11 @@ config DCACHE_RAM_SIZE hex default 0x0c000 -config DCACHE_BSP_STACK_SIZE +config DCACHE_BSP_TOP_STACK_SIZE hex default 0x4000 -config DCACHE_BSP_STACK_SLUSH +config DCACHE_BSP_TOP_STACK_SLUSH hex default 0x4000 if USE_LARGE_DCACHE default 0x1000 diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h index edf69f773d..6b9cd19b0f 100644 --- a/src/cpu/amd/family_10h-family_15h/defaults.h +++ b/src/cpu/amd/family_10h-family_15h/defaults.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index c5d523a74c..1c2b214dce 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -92,7 +89,7 @@ b.- prep_fid_change(...) #include #include #include -#include +#include #include static inline void print_debug_fv(const char *str, u32 val) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index f416d9ccdb..452f7ce3fd 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -379,12 +376,19 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) uint8_t fam15_bsp_core1_apicid; struct node_core_id id; - /* Please refer to the calculations and explaination in cache_as_ram.inc before modifying these values */ + /* Please refer to the calculations and explaination in cache_as_ram.inc + * before modifying these values */ uint32_t max_ap_stack_region_size = CONFIG_MAX_CPUS * CONFIG_DCACHE_AP_STACK_SIZE; - uint32_t max_bsp_stack_region_size = CONFIG_DCACHE_BSP_STACK_SIZE + CONFIG_DCACHE_BSP_STACK_SLUSH; - uint32_t bsp_stack_region_upper_boundary = CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE; - uint32_t bsp_stack_region_lower_boundary = bsp_stack_region_upper_boundary - max_bsp_stack_region_size; - void *lower_stack_region_boundary = (void *)(bsp_stack_region_lower_boundary - max_ap_stack_region_size); + uint32_t max_bsp_stack_region_size = CONFIG_DCACHE_BSP_TOP_STACK_SIZE + + CONFIG_DCACHE_BSP_TOP_STACK_SLUSH; + uint32_t bsp_stack_region_upper_boundary = CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE; + uint32_t bsp_stack_region_lower_boundary = bsp_stack_region_upper_boundary - + max_bsp_stack_region_size; + + void *lower_stack_region_boundary = (void *)(bsp_stack_region_lower_boundary - + max_ap_stack_region_size); + if (((void*)(sysinfo + 1)) > lower_stack_region_boundary) printk(BIOS_WARNING, "sysinfo extends into stack region (sysinfo range: [%p,%p] lower stack region boundary: %p)\n", diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.h b/src/cpu/amd/family_10h-family_15h/init_cpus.h index cca00496ea..07d7dbf8a9 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.h +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Damien Zammit - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c index ff9c7de1d3..9c040eb983 100644 --- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/family_10h-family_15h/monotonic_timer.c b/src/cpu/amd/family_10h-family_15h/monotonic_timer.c index fe01345e24..51244b83ae 100644 --- a/src/cpu/amd/family_10h-family_15h/monotonic_timer.c +++ b/src/cpu/amd/family_10h-family_15h/monotonic_timer.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2013 Google, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c index be936f66e3..4029f723df 100644 --- a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c +++ b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. - * Copyright (C) 2009 Rudolf Marek - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/family_10h-family_15h/processor_name.c b/src/cpu/amd/family_10h-family_15h/processor_name.c index 5672efdc13..fbd2bb5a33 100644 --- a/src/cpu/amd/family_10h-family_15h/processor_name.c +++ b/src/cpu/amd/family_10h-family_15h/processor_name.c @@ -1,11 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2008 Peter Stuge - * Copyright (C) 2010 Marc Jones - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.c b/src/cpu/amd/family_10h-family_15h/ram_calc.c index 1433e0753f..5b97232cb4 100644 --- a/src/cpu/amd/family_10h-family_15h/ram_calc.c +++ b/src/cpu/amd/family_10h-family_15h/ram_calc.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -68,7 +65,7 @@ uint64_t get_cc6_memory_size() if (is_fam15h()) { enable_cc6 = 0; -#ifdef __PRE_RAM__ +#ifdef __SIMPLE_DEVICE__ if (pci_read_config32(PCI_DEV(0, 0x18, 2), 0x118) & (0x1 << 18)) enable_cc6 = 1; #else diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.h b/src/cpu/amd/family_10h-family_15h/ram_calc.h index 0bb4cacc3e..2b541d053e 100644 --- a/src/cpu/amd/family_10h-family_15h/ram_calc.h +++ b/src/cpu/amd/family_10h-family_15h/ram_calc.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/family_10h-family_15h/tsc_freq.c b/src/cpu/amd/family_10h-family_15h/tsc_freq.c index 63b4ac0e8a..793cc1bfad 100644 --- a/src/cpu/amd/family_10h-family_15h/tsc_freq.c +++ b/src/cpu/amd/family_10h-family_15h/tsc_freq.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Raptor Engineering - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/family_10h-family_15h/update_microcode.c b/src/cpu/amd/family_10h-family_15h/update_microcode.c index a12091a0c5..4a2db4e4d4 100644 --- a/src/cpu/amd/family_10h-family_15h/update_microcode.c +++ b/src/cpu/amd/family_10h-family_15h/update_microcode.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c index 584041e923..06939b0524 100644 --- a/src/cpu/amd/microcode/microcode.c +++ b/src/cpu/amd/microcode/microcode.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Raptor Engineering - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig index 75a8441e45..e5e27b55b4 100644 --- a/src/cpu/amd/pi/00630F01/Kconfig +++ b/src/cpu/amd/pi/00630F01/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/pi/00630F01/Makefile.inc b/src/cpu/amd/pi/00630F01/Makefile.inc index 46ae346282..8522eb2618 100644 --- a/src/cpu/amd/pi/00630F01/Makefile.inc +++ b/src/cpu/amd/pi/00630F01/Makefile.inc @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/pi/00630F01/acpi/cpu.asl b/src/cpu/amd/pi/00630F01/acpi/cpu.asl index ffef539710..ef71a0fd5b 100644 --- a/src/cpu/amd/pi/00630F01/acpi/cpu.asl +++ b/src/cpu/amd/pi/00630F01/acpi/cpu.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/pi/00630F01/chip_name.c b/src/cpu/amd/pi/00630F01/chip_name.c index 65fe55e832..68a7cfe62d 100644 --- a/src/cpu/amd/pi/00630F01/chip_name.c +++ b/src/cpu/amd/pi/00630F01/chip_name.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c index 10fd9f568c..12f8062dfa 100644 --- a/src/cpu/amd/pi/00630F01/fixme.c +++ b/src/cpu/amd/pi/00630F01/fixme.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c index 550f116567..f1dd58ee5d 100644 --- a/src/cpu/amd/pi/00630F01/model_15_init.c +++ b/src/cpu/amd/pi/00630F01/model_15_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/pi/00630F01/udelay.c b/src/cpu/amd/pi/00630F01/udelay.c index 2cb53e9c20..d4bf45f7d2 100644 --- a/src/cpu/amd/pi/00630F01/udelay.c +++ b/src/cpu/amd/pi/00630F01/udelay.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Alexandru Gagniuc - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License or (at your option) diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig index a6eca07f44..647044843a 100644 --- a/src/cpu/amd/pi/00660F01/Kconfig +++ b/src/cpu/amd/pi/00660F01/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Advanced Micro Devices, Inc. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/pi/00660F01/Makefile.inc b/src/cpu/amd/pi/00660F01/Makefile.inc index 6c6a2b8ac8..fbd683c320 100644 --- a/src/cpu/amd/pi/00660F01/Makefile.inc +++ b/src/cpu/amd/pi/00660F01/Makefile.inc @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Advanced Micro Devices, Inc. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/pi/00660F01/acpi/cpu.asl b/src/cpu/amd/pi/00660F01/acpi/cpu.asl index aae3287ba6..bc52b681e5 100644 --- a/src/cpu/amd/pi/00660F01/acpi/cpu.asl +++ b/src/cpu/amd/pi/00660F01/acpi/cpu.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/pi/00660F01/chip_name.c b/src/cpu/amd/pi/00660F01/chip_name.c index 397bad7132..f3f2bb52a6 100644 --- a/src/cpu/amd/pi/00660F01/chip_name.c +++ b/src/cpu/amd/pi/00660F01/chip_name.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c index 2cbeab8316..237d52b2c1 100644 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c index 54446f7d96..78f3ce00ff 100644 --- a/src/cpu/amd/pi/00660F01/model_15_init.c +++ b/src/cpu/amd/pi/00660F01/model_15_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig index f3f488d2dd..43abc80aba 100644 --- a/src/cpu/amd/pi/00730F01/Kconfig +++ b/src/cpu/amd/pi/00730F01/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/pi/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc index 99b6ef33a9..c4a92cf65d 100644 --- a/src/cpu/amd/pi/00730F01/Makefile.inc +++ b/src/cpu/amd/pi/00730F01/Makefile.inc @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. @@ -14,8 +12,6 @@ # romstage-y += fixme.c -romstage-y += update_microcode.c -romstage-y += microcode_fam16h.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/pi/00730F01/acpi/cpu.asl b/src/cpu/amd/pi/00730F01/acpi/cpu.asl index 88d611e9ac..82168508c4 100644 --- a/src/cpu/amd/pi/00730F01/acpi/cpu.asl +++ b/src/cpu/amd/pi/00730F01/acpi/cpu.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/pi/00730F01/chip_name.c b/src/cpu/amd/pi/00730F01/chip_name.c index 4da24b73a4..3ce3d0cf48 100644 --- a/src/cpu/amd/pi/00730F01/chip_name.c +++ b/src/cpu/amd/pi/00730F01/chip_name.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index 3769319866..a0621cbb7f 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/pi/00730F01/microcode_fam16h.c b/src/cpu/amd/pi/00730F01/microcode_fam16h.c index ad951242a7..1f1dbd90d1 100644 --- a/src/cpu/amd/pi/00730F01/microcode_fam16h.c +++ b/src/cpu/amd/pi/00730F01/microcode_fam16h.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Raptor Engineering - * Copyright (C) 2019 PC Engines GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -20,8 +16,6 @@ #include #include #include -#include -#include /* * Values and header structure from: @@ -126,22 +120,12 @@ void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id) "Skipping microcode patch!\n"); return; } -#ifdef __PRE_RAM__ -#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) - spin_lock(romstage_microcode_cbfs_lock()); -#endif -#endif ucode = cbfs_boot_map_with_leak("cpu_microcode_blob.bin", CBFS_TYPE_MICROCODE, &ucode_len); if (!ucode) { printk(BIOS_DEBUG, "cpu_microcode_blob.bin not found. " "Skipping updates.\n"); -#ifdef __PRE_RAM__ -#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) - spin_unlock(romstage_microcode_cbfs_lock()); -#endif -#endif return; } @@ -149,21 +133,8 @@ void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id) ucode_len < F16H_MPB_DATA_OFFSET) { printk(BIOS_DEBUG, "microcode file invalid. Skipping " "updates.\n"); -#ifdef __PRE_RAM__ -#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) - spin_unlock(romstage_microcode_cbfs_lock()); -#endif -#endif return; } - amd_update_microcode(ucode, ucode_len, - equivalent_processor_rev_id); - -#ifdef __PRE_RAM__ -#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) - spin_unlock(romstage_microcode_cbfs_lock()); -#endif -#endif - + amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id); } diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index b0449a73b2..8edf0d9348 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/pi/00730F01/update_microcode.c b/src/cpu/amd/pi/00730F01/update_microcode.c index 6acf13a6ef..92af1af2a5 100644 --- a/src/cpu/amd/pi/00730F01/update_microcode.c +++ b/src/cpu/amd/pi/00730F01/update_microcode.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2019 PC Engines GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index a902089099..973a086e9f 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 - 2016 Advanced Micro Devices, Inc. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. @@ -28,7 +26,7 @@ config CPU_AMD_PI select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME - select POSTCAR_STAGE if !BINARYPI_LEGACY_WRAPPER + select CAR_GLOBAL_MIGRATION if BINARYPI_LEGACY_WRAPPER select SMM_ASEG if CPU_AMD_PI diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc index d25215beef..0a9b0649a9 100644 --- a/src/cpu/amd/pi/Makefile.inc +++ b/src/cpu/amd/pi/Makefile.inc @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 - 2016 Advanced Micro Devices, Inc. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/pi/amd_late_init.c b/src/cpu/amd/pi/amd_late_init.c index 8c0da9d48f..46144c6fbb 100644 --- a/src/cpu/amd/pi/amd_late_init.c +++ b/src/cpu/amd/pi/amd_late_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -17,7 +15,6 @@ #include #include #include -#include #include #include diff --git a/src/cpu/amd/pi/romstage.c b/src/cpu/amd/pi/romstage.c index cfd41648ba..cac5664697 100644 --- a/src/cpu/amd/pi/romstage.c +++ b/src/cpu/amd/pi/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Kyösti Mälkki - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c index f9aba5181c..ac637ff817 100644 --- a/src/cpu/amd/quadcore/amd_sibling.c +++ b/src/cpu/amd/quadcore/amd_sibling.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c index 125876badf..8125fb474f 100644 --- a/src/cpu/amd/quadcore/quadcore.c +++ b/src/cpu/amd/quadcore/quadcore.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , - * Raptor Engineering - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c index 5afb051ace..2c4d60dd05 100644 --- a/src/cpu/amd/quadcore/quadcore_id.c +++ b/src/cpu/amd/quadcore/quadcore_id.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson , - * Raptor Engineering - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -17,11 +13,9 @@ #include +#include #include #include -#ifdef __PRE_RAM__ -#include -#endif //called by bus_cpu_scan too u32 read_nb_cfg_54(void) @@ -48,7 +42,7 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54) uint32_t family; uint32_t model; -#ifdef __PRE_RAM__ +#ifdef __SIMPLE_DEVICE__ f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8); #else f3xe8 = pci_read_config32(get_node_pci(0, 3), 0xe8); @@ -115,7 +109,7 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54) uint32_t f5x84; uint8_t core_count; -#ifdef __PRE_RAM__ +#ifdef __SIMPLE_DEVICE__ f5x84 = pci_read_config32(NODE_PCI(0, 5), 0x84); #else f5x84 = pci_read_config32(get_node_pci(0, 5), 0x84); diff --git a/src/cpu/amd/smm/smm_init.c b/src/cpu/amd/smm/smm_init.c index 60e506c4e5..8f859f31e3 100644 --- a/src/cpu/amd/smm/smm_init.c +++ b/src/cpu/amd/smm/smm_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 coresystems GmbH - * Copyright (C) 2010 Rudolf Marek - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -21,6 +18,7 @@ #include #include #include +#include #include void smm_init(void) diff --git a/src/cpu/amd/socket_G34/socket_G34.c b/src/cpu/amd/socket_G34/socket_G34.c index 6042a3deb8..1cac37c671 100644 --- a/src/cpu/amd/socket_G34/socket_G34.c +++ b/src/cpu/amd/socket_G34/socket_G34.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/intel/car/bootblock.c b/src/cpu/intel/car/bootblock.c index d751d86272..664c2b5074 100644 --- a/src/cpu/intel/car/bootblock.c +++ b/src/cpu/intel/car/bootblock.c @@ -21,7 +21,7 @@ asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) { saved_bist = bist; /* Call lib/bootblock.c main */ - bootblock_main_with_timestamp(base_timestamp, NULL, 0); + bootblock_main_with_basetime(base_timestamp); } void __weak bootblock_early_northbridge_init(void) { } diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 5dc2bbd295..f8fa806125 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2000,2007 Ronald G. Minnich - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2012 Kyösti Mälkki - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 251714cb8f..08ad195964 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2000,2007 Ronald G. Minnich - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2012 Kyösti Mälkki - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/intel/car/non-evict/exit_car.S b/src/cpu/intel/car/non-evict/exit_car.S index 8adc5f6a00..5400ae51ce 100644 --- a/src/cpu/intel/car/non-evict/exit_car.S +++ b/src/cpu/intel/car/non-evict/exit_car.S @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2000,2007 Ronald G. Minnich - * Copyright (C) 2007-2008 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 2a9259c30c..9a7dc5f256 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -1,11 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2000,2007 Ronald G. Minnich - * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan) - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2012 Kyösti Mälkki - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 4beac0b94c..b7eb37b6a6 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -1,11 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2000,2007 Ronald G. Minnich - * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan) - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2012 Kyösti Mälkki - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/intel/car/p4-netburst/exit_car.S b/src/cpu/intel/car/p4-netburst/exit_car.S index 3b991288ff..2d7fdaf8af 100644 --- a/src/cpu/intel/car/p4-netburst/exit_car.S +++ b/src/cpu/intel/car/p4-netburst/exit_car.S @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2000,2007 Ronald G. Minnich - * Copyright (C) 2007-2008 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 89052d6be6..547b1211df 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -11,30 +11,38 @@ * GNU General Public License for more details. */ +#include +#include #include #include -#include #include +#include #include #include #include #include +/* If we do not have a constrained _car_stack region size, use the + following as a guideline for acceptable stack usage. */ #define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000 +static struct postcar_frame early_mtrrs; + static void romstage_main(unsigned long bist) { int i; - const int num_guards = 4; + const int num_guards = 64; const u32 stack_guard = 0xdeadbeef; u32 *stack_base; u32 size; + const size_t stack_size = MAX(CONFIG_DCACHE_BSP_STACK_SIZE, + DCACHE_RAM_ROMSTAGE_STACK_SIZE); /* Size of unallocated CAR. */ size = ALIGN_DOWN(_car_stack_size, 16); - size = MIN(size, DCACHE_RAM_ROMSTAGE_STACK_SIZE); - if (size < DCACHE_RAM_ROMSTAGE_STACK_SIZE) + size = MIN(size, stack_size); + if (size < stack_size) printk(BIOS_DEBUG, "Romstage stack size limited to 0x%x!\n", size); @@ -43,7 +51,7 @@ static void romstage_main(unsigned long bist) for (i = 0; i < num_guards; i++) stack_base[i] = stack_guard; - mainboard_romstage_entry(bist); + mainboard_romstage_entry(); /* Check the stack. */ for (i = 0; i < num_guards; i++) { @@ -52,7 +60,11 @@ static void romstage_main(unsigned long bist) printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n"); } - platform_enter_postcar(); + if (CONFIG(SMM_TSEG)) + smm_list_regions(); + + prepare_and_run_postcar(&early_mtrrs); + /* We do not return here. */ } #if !CONFIG(C_ENVIRONMENT_BOOTBLOCK) @@ -75,6 +87,8 @@ asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) asmlinkage void car_stage_entry(void) { + timestamp_add_now(TS_START_ROMSTAGE); + /* Assumes the hardware was set up during the bootblock */ console_init(); diff --git a/src/cpu/intel/common/Kconfig b/src/cpu/intel/common/Kconfig index 56bed22a1a..4074d8cc66 100644 --- a/src/cpu/intel/common/Kconfig +++ b/src/cpu/intel/common/Kconfig @@ -19,4 +19,7 @@ config SET_IA32_FC_LOCK_BIT However, leaving the lock bit unset will break Windows' detection of VMX support and built-in virtualization features like Hyper-V. +config CPU_INTEL_COMMON_TIMEBASE + bool + endif diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc index 2fc6da908b..c38e81c380 100644 --- a/src/cpu/intel/common/Makefile.inc +++ b/src/cpu/intel/common/Makefile.inc @@ -1,5 +1,10 @@ ramstage-y += common_init.c -romstage-$(CONFIG_UDELAY_LAPIC) += fsb.c -ramstage-$(CONFIG_UDELAY_LAPIC) += fsb.c -postcar-$(CONFIG_UDELAY_LAPIC) += fsb.c + +ifeq ($(CONFIG_CPU_INTEL_COMMON_TIMEBASE),y) +bootblock-y += fsb.c +verstage-y += fsb.c +romstage-y += fsb.c +postcar-y += fsb.c +ramstage-y += fsb.c smm-y += fsb.c +endif diff --git a/src/cpu/intel/common/acpi/cpu.asl b/src/cpu/intel/common/acpi/cpu.asl index 6fad17f74e..14ade7d6ec 100644 --- a/src/cpu/intel/common/acpi/cpu.asl +++ b/src/cpu/intel/common/acpi/cpu.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index a2ff65cecc..2fff90c690 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index d66e87a396..c32bc235c2 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -11,21 +11,29 @@ * GNU General Public License for more details. */ +#include #include #include +#include #include #include #include #include +#include -static int get_fsb(void) +static u32 g_timer_fsb CAR_GLOBAL; +static u32 g_timer_tsc CAR_GLOBAL; + +/* This is not an architectural MSR. */ +#define MSR_PLATFORM_INFO 0xce + +static int get_fsb_tsc(int *fsb, int *ratio) { struct cpuinfo_x86 c; static const short core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 }; static const short core2_fsb[8] = { 266, 133, 200, 166, 333, 100, 400, -1 }; static const short f2x_fsb[8] = { 100, 133, 200, 166, 333, -1, -1, -1 }; msr_t msr; - int ret = -2; get_fms(&c, cpuid_eax(1)); switch (c.x86) { @@ -33,50 +41,99 @@ static int get_fsb(void) switch (c.x86_model) { case 0xe: /* Core Solo/Duo */ case 0x1c: /* Atom */ - ret = core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; + *fsb = core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; + *ratio = (rdmsr(IA32_PERF_STATUS).hi >> 8) & 0x1f; break; case 0xf: /* Core 2 or Xeon */ case 0x17: /* Enhanced Core */ - ret = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; + *fsb = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; + *ratio = (rdmsr(IA32_PERF_STATUS).hi >> 8) & 0x1f; break; case 0x25: /* Nehalem BCLK fixed at 133MHz */ - ret = 133; + *fsb = 133; + *ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff; break; case 0x2a: /* SandyBridge BCLK fixed at 100MHz */ case 0x3a: /* IvyBridge BCLK fixed at 100MHz */ case 0x3c: /* Haswell BCLK fixed at 100MHz */ case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */ case 0x4d: /* Rangeley BCLK fixed at 100MHz */ - ret = 100; + *fsb = 100; + *ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff; break; + default: + return -2; } break; case 0xf: /* Netburst */ msr = rdmsr(MSR_EBC_FREQUENCY_ID); + *ratio = msr.lo >> 24; switch (c.x86_model) { case 0x2: - ret = f2x_fsb[(msr.lo >> 16) & 7]; + *fsb = f2x_fsb[(msr.lo >> 16) & 7]; break; case 0x3: case 0x4: case 0x6: - ret = core2_fsb[(msr.lo >> 16) & 7]; + *fsb = core2_fsb[(msr.lo >> 16) & 7]; break; + default: + return -2; } + break; + default: + return -2; } - return ret; + if (*fsb > 0) + return 0; + return -1; } -int get_ia32_fsb(void) +static void resolve_timebase(void) { - int ret; + int ret, fsb, ratio; + + ret = get_fsb_tsc(&fsb, &ratio); + if (ret == 0) { + u32 tsc = 100 * DIV_ROUND_CLOSEST(ratio * fsb, 100); + car_set_var(g_timer_fsb, fsb); + car_set_var(g_timer_tsc, tsc); + return; + } - ret = get_fsb(); if (ret == -1) printk(BIOS_ERR, "FSB not found\n"); if (ret == -2) printk(BIOS_ERR, "CPU not supported\n"); - return ret; + + /* Set some semi-ridiculous defaults. */ + car_set_var(g_timer_fsb, 500); + car_set_var(g_timer_tsc, 5000); + return; +} + +u32 get_timer_fsb(void) +{ + u32 fsb; + + fsb = car_get_var(g_timer_fsb); + if (fsb > 0) + return fsb; + + resolve_timebase(); + return car_get_var(g_timer_fsb); +} + +unsigned long tsc_freq_mhz(void) +{ + u32 tsc; + + tsc = car_get_var(g_timer_tsc); + if (tsc > 0) + return tsc; + + resolve_timebase(); + return car_get_var(g_timer_tsc); } /** @@ -87,7 +144,7 @@ int get_ia32_fsb(void) */ int get_ia32_fsb_x3(void) { - const int fsb = get_ia32_fsb(); + const int fsb = get_timer_fsb(); if (fsb > 0) return 100 * DIV_ROUND_CLOSEST(3 * fsb, 100); diff --git a/src/cpu/intel/fit/Kconfig b/src/cpu/intel/fit/Kconfig index e48dca9f70..fa10802926 100644 --- a/src/cpu/intel/fit/Kconfig +++ b/src/cpu/intel/fit/Kconfig @@ -5,6 +5,7 @@ config CPU_INTEL_FIRMWARE_INTERFACE_TABLE config CPU_INTEL_NUM_FIT_ENTRIES int + default 16 if INTEL_TXT default 4 depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE help diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 6bf8dc7eec..77ba0bdb98 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. @@ -28,13 +26,15 @@ config CPU_SPECIFIC_OPTIONS select SMP select MMX select SSE2 - select UDELAY_LAPIC + select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_NOT_IN_BLOB_REPO select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE - select LAPIC_MONOTONIC_TIMER + select TSC_MONOTONIC_TIMER + select TSC_CONSTANT_RATE select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_TIMEBASE select NO_SMM # Microcode header files are delivered in FSP package diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc index 97bb981a66..d7fb4a886c 100644 --- a/src/cpu/intel/fsp_model_406dx/Makefile.inc +++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyrignt (C) 2014 Sage Electronic Engineering, LLC. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/intel/fsp_model_406dx/acpi.c b/src/cpu/intel/fsp_model_406dx/acpi.c index f30567e037..6672eab3d1 100644 --- a/src/cpu/intel/fsp_model_406dx/acpi.c +++ b/src/cpu/intel/fsp_model_406dx/acpi.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/cpu/intel/fsp_model_406dx/bootblock.c b/src/cpu/intel/fsp_model_406dx/bootblock.c index 14cfad9de1..045b0f628c 100644 --- a/src/cpu/intel/fsp_model_406dx/bootblock.c +++ b/src/cpu/intel/fsp_model_406dx/bootblock.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering LLC. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/intel/fsp_model_406dx/chip.h b/src/cpu/intel/fsp_model_406dx/chip.h index bf547769c2..aaaed160ad 100644 --- a/src/cpu/intel/fsp_model_406dx/chip.h +++ b/src/cpu/intel/fsp_model_406dx/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h index 6c5cc313b4..53a77a98a3 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx.h +++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c index efa86935f5..94925106f8 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c +++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 8f91b60953..db119a05cc 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -22,6 +22,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select PARALLEL_MP select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_TIMEBASE select NO_FIXED_XIP_ROM_SIZE config SMM_TSEG_SIZE diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index d46a422e4a..7661a4e2d8 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -1,27 +1,19 @@ ramstage-y += haswell_init.c -ramstage-y += tsc_freq.c romstage-y += romstage.c -romstage-y += tsc_freq.c romstage-y += ../car/romstage.c -postcar-y += tsc_freq.c - ramstage-y += acpi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c smm-y += finalize.c -smm-y += tsc_freq.c bootblock-y += ../car/non-evict/cache_as_ram.S bootblock-y += ../car/bootblock.c bootblock-y += ../../x86/early_reset.S bootblock-y += bootblock.c -bootblock-y += tsc_freq.c postcar-y += ../car/non-evict/exit_car.S -verstage-y += tsc_freq.c - subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index 9dcd8ece1e..282dd962cc 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index 7baa2a81ec..94e5d36e18 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -20,7 +18,6 @@ #include #include -#include #include "haswell.h" #include diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h index cd9ec5d51b..f3b97572da 100644 --- a/src/cpu/intel/haswell/chip.h +++ b/src/cpu/intel/haswell/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -13,8 +11,6 @@ * GNU General Public License for more details. */ -extern struct chip_operations cpu_intel_haswell_ops; - /* Magic value used to locate this chip in the device tree */ #define SPEEDSTEP_APIC_MAGIC 0xACAC diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c index 16e54d746a..b75d145ffd 100644 --- a/src/cpu/intel/haswell/finalize.c +++ b/src/cpu/intel/haswell/finalize.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index cfd9d45690..4c67ba82ab 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of @@ -132,40 +130,22 @@ # error "CONFIG_IED_REGION_SIZE is not a power of 2" #endif -#if !defined(__ROMCC__) // FIXME romcc should handle below constructs - -#if defined(__PRE_RAM__) struct pei_data; struct rcba_config_instruction; struct romstage_params { struct pei_data *pei_data; const void *gpio_map; const struct rcba_config_instruction *rcba_config; - unsigned long bist; void (*copy_spd)(struct pei_data *); }; void romstage_common(const struct romstage_params *params); -#endif -#ifdef __SMM__ /* Lock MSRs */ void intel_cpu_haswell_finalize_smm(void); -#else + /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); -void smm_relocate(void); -void smm_lock(void); -struct bus; -void bsp_init_and_start_aps(struct bus *cpu_bus); -/* Determine if HyperThreading is disabled. The variable is not valid until - * setup_ap_init() has been called. */ -#endif /* CPU identification */ int haswell_family_model(void); @@ -173,5 +153,3 @@ int haswell_stepping(void); int haswell_is_ult(void); #endif - -#endif diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 95d719c2f1..66dca28dc5 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of @@ -24,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -761,7 +759,7 @@ static void post_mp_init(void) { /* Now that all APs have been relocated as well as the BSP let SMIs * start flowing. */ - southbridge_smm_enable_smi(); + smm_southbridge_enable_smi(); /* Lock down the SMRAM space. */ smm_lock(); @@ -778,7 +776,7 @@ static const struct mp_ops mp_ops = { .post_mp_init = post_mp_init, }; -void bsp_init_and_start_aps(struct bus *cpu_bus) +void mp_init_cpus(struct bus *cpu_bus) { if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 47b9976786..34fd7b0458 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -15,69 +13,28 @@ #include #include -#include #include #include -#include -#include #include -#include #include #include #include -#include #include -#include -#if CONFIG(EC_GOOGLE_CHROMEEC) -#include -#endif #include #include #include #include -#include #include "haswell.h" -/* platform_enter_postcar() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use, - * and continues execution in postcar stage. */ -void platform_enter_postcar(void) -{ - struct postcar_frame pcf; - uintptr_t top_of_ram; - - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB - * above top of the ram. This satisfies MTRR alignment requirement - * with different TSEG size configurations. - */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, - MTRR_TYPE_WRBACK); - - run_postcar_phase(&pcf); -} - void romstage_common(const struct romstage_params *params) { int boot_mode; int wake_from_s3; - if (params->bist == 0) - enable_lapic(); + enable_lapic(); wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config); - /* Halt if there was a built in self test failure */ - report_bist_failure(params->bist); - /* Perform some early chipset initialization required * before RAM initialization can work */ diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 3a4a0a7830..c33a00a95c 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -24,15 +22,17 @@ #include #include #include +#include +#include #include #include #include #include "haswell.h" -#define EMRRphysBase_MSR 0x1f4 -#define EMRRphysMask_MSR 0x1f5 -#define UNCORE_EMRRphysBase_MSR 0x2f4 -#define UNCORE_EMRRphysMask_MSR 0x2f5 +#define MSR_PRMRR_PHYS_BASE 0x1f4 +#define MSR_PRMRR_PHYS_MASK 0x1f5 +#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 +#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 #define SMM_MCA_CAP_MSR 0x17d #define SMM_CPU_SVRSTR_BIT 57 #define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) @@ -43,19 +43,17 @@ #define IEDBASE_MSR 0xc22 #define SMRR_SUPPORTED (1 << 11) -#define EMRR_SUPPORTED (1 << 12) +#define PRMRR_SUPPORTED (1 << 12) struct smm_relocation_params { - u32 smram_base; - u32 smram_size; - u32 ied_base; - u32 ied_size; + uintptr_t ied_base; + size_t ied_size; msr_t smrr_base; msr_t smrr_mask; - msr_t emrr_base; - msr_t emrr_mask; - msr_t uncore_emrr_base; - msr_t uncore_emrr_mask; + msr_t prmrr_base; + msr_t prmrr_mask; + msr_t uncore_prmrr_base; + msr_t uncore_prmrr_mask; /* The smm_save_state_in_msrs field indicates if SMM save state * locations live in MSRs. This indicates to the CPUs how to adjust * the SMMBASE and IEDBASE */ @@ -73,22 +71,22 @@ static inline void write_smrr(struct smm_relocation_params *relo_params) wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); } -static inline void write_emrr(struct smm_relocation_params *relo_params) +static inline void write_prmrr(struct smm_relocation_params *relo_params) { - printk(BIOS_DEBUG, "Writing EMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->emrr_base.lo, relo_params->emrr_mask.lo); - wrmsr(EMRRphysBase_MSR, relo_params->emrr_base); - wrmsr(EMRRphysMask_MSR, relo_params->emrr_mask); + printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo); + wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base); + wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask); } -static inline void write_uncore_emrr(struct smm_relocation_params *relo_params) +static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params) { printk(BIOS_DEBUG, - "Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->uncore_emrr_base.lo, - relo_params->uncore_emrr_mask.lo); - wrmsr(UNCORE_EMRRphysBase_MSR, relo_params->uncore_emrr_base); - wrmsr(UNCORE_EMRRphysMask_MSR, relo_params->uncore_emrr_mask); + "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->uncore_prmrr_base.lo, + relo_params->uncore_prmrr_mask.lo); + wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base); + wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask); } static void update_save_state(int cpu, uintptr_t curr_smbase, @@ -196,38 +194,27 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, /* Make appropriate changes to the save state map. */ update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); - /* Write EMRR and SMRR MSRs based on indicated support. */ + /* Write PRMRR and SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); if (mtrr_cap.lo & SMRR_SUPPORTED) write_smrr(relo_params); - if (mtrr_cap.lo & EMRR_SUPPORTED) { - write_emrr(relo_params); - /* UNCORE_EMRR msrs are package level. Therefore, only + if (mtrr_cap.lo & PRMRR_SUPPORTED) { + write_prmrr(relo_params); + /* UNCORE_PRMRR msrs are package level. Therefore, only * configure these MSRs on the BSP. */ if (cpu == 0) - write_uncore_emrr(relo_params); + write_uncore_prmrr(relo_params); } } -static u32 northbridge_get_base_reg(struct device *dev, int reg) +static void fill_in_relocation_params(struct smm_relocation_params *params) { - u32 value; + uintptr_t tseg_base; + size_t tseg_size; - value = pci_read_config32(dev, reg); - /* Base registers are at 1MiB granularity. */ - value &= ~((1 << 20) - 1); - return value; -} - -static void fill_in_relocation_params(struct device *dev, - struct smm_relocation_params *params) -{ - u32 tseg_size; - u32 tsegmb; - u32 bgsm; - u32 emrr_base; - u32 emrr_size; + u32 prmrr_base; + u32 prmrr_size; int phys_bits; /* All range registers are aligned to 4KiB */ const u32 rmask = ~((1 << 12) - 1); @@ -240,43 +227,34 @@ static void fill_in_relocation_params(struct device *dev, * SMRAM range as well as the IED range. However, the SMRAM available * to the handler is 4MiB since the IEDRAM lives TSEGMB + 4MiB. */ - tsegmb = northbridge_get_base_reg(dev, TSEG); - bgsm = northbridge_get_base_reg(dev, BGSM); - tseg_size = bgsm - tsegmb; - - params->smram_base = tsegmb; - params->smram_size = 4 << 20; - params->ied_base = tsegmb + params->smram_size; - params->ied_size = tseg_size - params->smram_size; - - /* Adjust available SMM handler memory size. */ - params->smram_size -= CONFIG_SMM_RESERVED_SIZE; + smm_region(&tseg_base, &tseg_size); /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) - | MTRR_PHYS_MASK_VALID; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; params->smrr_mask.hi = 0; - /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */ - emrr_base = (params->ied_base + (2 << 20)) & rmask; - emrr_size = params->ied_size - (2 << 20); + smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); - /* EMRR has 46 bits of valid address aligned to 4KiB. It's dependent + /* The PRMRR and UNCORE_PRMRR are at IEDBASE + 2MiB */ + prmrr_base = (params->ied_base + (2 << 20)) & rmask; + prmrr_size = params->ied_size - (2 << 20); + + /* PRMRR has 46 bits of valid address aligned to 4KiB. It's dependent * on the number of physical address bits supported. */ - params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK; - params->emrr_base.hi = 0; - params->emrr_mask.lo = (~(emrr_size - 1) & rmask) + params->prmrr_base.lo = prmrr_base | MTRR_TYPE_WRBACK; + params->prmrr_base.hi = 0; + params->prmrr_mask.lo = (~(prmrr_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1; + params->prmrr_mask.hi = (1 << (phys_bits - 32)) - 1; - /* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */ - params->uncore_emrr_base.lo = emrr_base; - params->uncore_emrr_base.hi = 0; - params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) | + /* UNCORE_PRMRR has 39 bits of valid address aligned to 4KiB. */ + params->uncore_prmrr_base.lo = prmrr_base; + params->uncore_prmrr_base.hi = 0; + params->uncore_prmrr_mask.lo = (~(prmrr_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1; + params->uncore_prmrr_mask.hi = (1 << (39 - 32)) - 1; } static void setup_ied_area(struct smm_relocation_params *params) @@ -299,7 +277,7 @@ static void setup_ied_area(struct smm_relocation_params *params) /* According to the BWG MP init section 2MiB of memory at IEDBASE + * 2MiB should be zeroed as well. However, I suspect what is intended - * is to clear the memory covered by EMRR. TODO(adurbin): figure out if + * is to clear the memory covered by PRMRR. TODO(adurbin): figure out if * this is really required. */ //memset(ied_base + (2 << 20), 0, (2 << 20)); @@ -308,23 +286,21 @@ static void setup_ied_area(struct smm_relocation_params *params) void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - struct device *dev = pcidev_on_root(0, 0); - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - fill_in_relocation_params(dev, &smm_reloc_params); + fill_in_relocation_params(&smm_reloc_params); + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); setup_ied_area(&smm_reloc_params); - *perm_smbase = smm_reloc_params.smram_base; - *perm_smsize = smm_reloc_params.smram_size; *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); } void smm_initialize(void) { /* Clear the SMM state in the southbridge. */ - southbridge_smm_clear_state(); + smm_southbridge_clear_state(); /* * Run the relocation handler for on the BSP to check and set up diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index 2df1d5eb6f..b13172ee16 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -1,5 +1,6 @@ bootblock-$(CONFIG_MICROCODE_UPDATE_PRE_RAM) += microcode_asm.S romstage-$(CONFIG_MICROCODE_UPDATE_PRE_RAM) += microcode_asm.S +bootblock-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c romstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 44f7f1fbbb..feb73c8b42 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2000 Ronald G. Minnich - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -27,11 +24,9 @@ #include #include #include - -#if !defined(__PRE_RAM__) #include + DECLARE_SPIN_LOCK(microcode_lock) -#endif struct microcode { u32 hdrver; /* Header Version */ @@ -228,15 +223,11 @@ void intel_update_microcode_from_cbfs(void) { const void *patch = intel_microcode_find(); -#if !defined(__ROMCC__) && !defined(__PRE_RAM__) spin_lock(µcode_lock); -#endif intel_microcode_load_unlocked(patch); -#if !defined(__ROMCC__) && !defined(__PRE_RAM__) spin_unlock(µcode_lock); -#endif } #if ENV_RAMSTAGE diff --git a/src/cpu/intel/microcode/microcode_asm.S b/src/cpu/intel/microcode/microcode_asm.S index 319785d2de..647f67c774 100644 --- a/src/cpu/intel/microcode/microcode_asm.S +++ b/src/cpu/intel/microcode/microcode_asm.S @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Arthur Heymans - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 3ea812573c..037234ab37 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -6,7 +6,10 @@ config CPU_INTEL_MODEL_1067X select ARCH_RAMSTAGE_X86_32 select SMP select SSE2 - select UDELAY_LAPIC + select UDELAY_TSC + select TSC_CONSTANT_RATE + select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_TIMEBASE diff --git a/src/cpu/intel/model_1067x/chip.h b/src/cpu/intel/model_1067x/chip.h index 8b3cc2a9c6..6cc004d918 100644 --- a/src/cpu/intel/model_1067x/chip.h +++ b/src/cpu/intel/model_1067x/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index e47712c020..94adc8c327 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * 2012 secunet Security Networks AG - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of @@ -24,7 +21,7 @@ #include #include #include -#include +#include #include #include "chip.h" diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index ea2d83841f..dd44582e1c 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * 2012 secunet Security Networks AG - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of @@ -19,8 +16,9 @@ #include #include #include -#include +#include #include +#include /* Parallel MP initialization support. */ static const void *microcode_patch; @@ -93,7 +91,7 @@ static void post_mp_init(void) { /* Now that all APs have been relocated as well as the BSP let SMIs * start flowing. */ - southbridge_smm_init(); + smm_southbridge_enable_smi(); /* Lock down the SMRAM space. */ smm_lock(); @@ -110,7 +108,7 @@ static const struct mp_ops mp_ops = { .post_mp_init = post_mp_init, }; -void bsp_init_and_start_aps(struct bus *cpu_bus) +void mp_init_cpus(struct bus *cpu_bus) { microcode_patch = intel_microcode_find(); diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index f365cf179e..43c4048786 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -6,13 +6,16 @@ config CPU_INTEL_MODEL_106CX select ARCH_RAMSTAGE_X86_32 select SMP select SSE2 - select UDELAY_LAPIC + select UDELAY_TSC + select TSC_CONSTANT_RATE + select TSC_MONOTONIC_TIMER select SIPI_VECTOR_IN_ROM select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS select SERIALIZED_SMM_INITIALIZATION select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_TIMEBASE if CPU_INTEL_MODEL_106CX diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index f43db16185..e529ffd595 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index a3a58b65e6..897a3b4804 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_TIMEBASE select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index 1f6d1a22b9..4f6d3c2fd8 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -10,11 +10,6 @@ subdirs-y += ../../x86/smm subdirs-y += ../smm/gen1 subdirs-y += ../common -ramstage-y += tsc_freq.c -romstage-y += tsc_freq.c -postcar-y += tsc_freq.c -smm-y += tsc_freq.c - ramstage-y += acpi.c smm-y += finalize.c diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index 514ea44ecb..51acc278cc 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c index 19dbda850a..273c193f3a 100644 --- a/src/cpu/intel/model_2065x/bootblock.c +++ b/src/cpu/intel/model_2065x/bootblock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/intel/model_2065x/chip.h b/src/cpu/intel/model_2065x/chip.h index 21fe499b3d..50afca0ce1 100644 --- a/src/cpu/intel/model_2065x/chip.h +++ b/src/cpu/intel/model_2065x/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c index 724e09ca20..3c1c2db1c4 100644 --- a/src/cpu/intel/model_2065x/finalize.c +++ b/src/cpu/intel/model_2065x/finalize.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 2f3584a67e..8087edb828 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 289d4471e6..d7e84ec006 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of @@ -31,7 +28,7 @@ #include #include "model_2065x.h" #include "chip.h" -#include +#include #include /* @@ -316,7 +313,7 @@ static void post_mp_init(void) { /* Now that all APs have been relocated as well as the BSP let SMIs * start flowing. */ - southbridge_smm_init(); + smm_southbridge_enable_smi(); /* Lock down the SMRAM space. */ smm_lock(); @@ -334,7 +331,7 @@ static const struct mp_ops mp_ops = { .post_mp_init = post_mp_init, }; -void bsp_init_and_start_aps(struct bus *cpu_bus) +void mp_init_cpus(struct bus *cpu_bus) { if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index ced3340903..97d8d3d0d6 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_TIMEBASE select PARALLEL_MP select NO_FIXED_XIP_ROM_SIZE diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index e723d74d78..d19d860304 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -17,11 +17,6 @@ ramstage-y += common.c romstage-y += common.c smm-y += common.c -ramstage-y += tsc_freq.c -romstage-y += tsc_freq.c -postcar-y += tsc_freq.c -smm-y += tsc_freq.c - smm-y += finalize.c cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*) diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index aca2277fa6..60664213ba 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index 9dcbe372ff..72b4a672c2 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/intel/model_206ax/chip.h b/src/cpu/intel/model_206ax/chip.h index aad399dbe5..68cc6e5577 100644 --- a/src/cpu/intel/model_206ax/chip.h +++ b/src/cpu/intel/model_206ax/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/intel/model_206ax/common.c b/src/cpu/intel/model_206ax/common.c index 1e832c8e60..b4017fb17d 100644 --- a/src/cpu/intel/model_206ax/common.c +++ b/src/cpu/intel/model_206ax/common.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 98ce5552da..c9d53769b3 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index 2dc929345d..f2a0b71a5b 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 80d85f3347..cc20676fff 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of @@ -32,7 +29,7 @@ #include #include "model_206ax.h" #include "chip.h" -#include +#include #include /* @@ -542,7 +539,7 @@ static void post_mp_init(void) { /* Now that all APs have been relocated as well as the BSP let SMIs * start flowing. */ - southbridge_smm_init(); + smm_southbridge_enable_smi(); /* Lock down the SMRAM space. */ smm_lock(); @@ -560,7 +557,7 @@ static const struct mp_ops mp_ops = { .post_mp_init = post_mp_init, }; -void bsp_init_and_start_aps(struct bus *cpu_bus) +void mp_init_cpus(struct bus *cpu_bus) { if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); diff --git a/src/cpu/intel/model_65x/Makefile.inc b/src/cpu/intel/model_65x/Makefile.inc index c1f471c33a..043a44e1b3 100644 --- a/src/cpu/intel/model_65x/Makefile.inc +++ b/src/cpu/intel/model_65x/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2010 Keith Hui -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c index dde34276fb..87a2821d85 100644 --- a/src/cpu/intel/model_65x/model_65x_init.c +++ b/src/cpu/intel/model_65x/model_65x_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2010 Keith Hui - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/intel/model_67x/Makefile.inc b/src/cpu/intel/model_67x/Makefile.inc index ef68df4346..131c7faf47 100644 --- a/src/cpu/intel/model_67x/Makefile.inc +++ b/src/cpu/intel/model_67x/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2010 Keith Hui -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c index 130105eece..0d7afb25e0 100644 --- a/src/cpu/intel/model_67x/model_67x_init.c +++ b/src/cpu/intel/model_67x/model_67x_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2010 Keith Hui - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/intel/model_68x/Kconfig b/src/cpu/intel/model_68x/Kconfig index b1595ad369..9cca8f80a6 100644 --- a/src/cpu/intel/model_68x/Kconfig +++ b/src/cpu/intel/model_68x/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2010 Joseph Smith -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or diff --git a/src/cpu/intel/model_68x/Makefile.inc b/src/cpu/intel/model_68x/Makefile.inc index 95aacb3fa6..74ddfa51e9 100644 --- a/src/cpu/intel/model_68x/Makefile.inc +++ b/src/cpu/intel/model_68x/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2010 Joseph Smith -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c index 4c549bc3b9..fc2cac0db6 100644 --- a/src/cpu/intel/model_68x/model_68x_init.c +++ b/src/cpu/intel/model_68x/model_68x_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2010 Joseph Smith - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c index 617c8aaa26..777432eddc 100644 --- a/src/cpu/intel/model_6bx/model_6bx_init.c +++ b/src/cpu/intel/model_6bx/model_6bx_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2010 Joseph Smith - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index 10ebcc7044..ff16724651 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -6,8 +6,11 @@ config CPU_INTEL_MODEL_6EX select ARCH_RAMSTAGE_X86_32 select SMP select SSE2 - select UDELAY_LAPIC + select UDELAY_TSC + select TSC_CONSTANT_RATE + select TSC_MONOTONIC_TIMER select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_TIMEBASE diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 740af4237a..5f61fb05b5 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index 8f053142d4..32f6e8c42a 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -6,8 +6,11 @@ config CPU_INTEL_MODEL_6FX select ARCH_RAMSTAGE_X86_32 select SMP select SSE2 - select UDELAY_LAPIC + select UDELAY_TSC + select TSC_CONSTANT_RATE + select TSC_MONOTONIC_TIMER select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_TIMEBASE diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 26d0c9d206..2aefcc7add 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc index 9bb5dca626..5d60d21eda 100644 --- a/src/cpu/intel/model_f2x/Makefile.inc +++ b/src/cpu/intel/model_f2x/Makefile.inc @@ -1,3 +1,5 @@ +subdirs-y += ../common + ramstage-y += model_f2x_init.c cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-02-*) diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index adfc2da75a..d9324944da 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2010 Keith Hui -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc index c18a7bf87c..599a5d0f24 100644 --- a/src/cpu/intel/slot_1/Makefile.inc +++ b/src/cpu/intel/slot_1/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2009 Uwe Hermann -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c index 7821ad1ff5..2602527d5f 100644 --- a/src/cpu/intel/slot_1/l2_cache.c +++ b/src/cpu/intel/slot_1/l2_cache.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2000 Denis Dowling - * Copyright (C) 2010 Keith Hui - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/cpu/intel/slot_1/slot_1.c b/src/cpu/intel/slot_1/slot_1.c index 251d9892c6..9a03f6bf68 100644 --- a/src/cpu/intel/slot_1/slot_1.c +++ b/src/cpu/intel/slot_1/slot_1.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Keith Hui - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/cpu/intel/smm/gen1/smi.h deleted file mode 100644 index 3d5149a430..0000000000 --- a/src/cpu/intel/smm/gen1/smi.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -void bsp_init_and_start_aps(struct bus *cpu_bus); - -/* These helpers are for performing SMM relocation. */ -void southbridge_smm_init(void); -u32 northbridge_get_tseg_base(void); -u32 northbridge_get_tseg_size(void); -void northbridge_write_smram(u8 smram); - -bool cpu_has_alternative_smrr(void); - -/* parallel MP helper functions */ -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); -void southbridge_smm_clear_state(void); -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_relocate(void); -void smm_lock(void); diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index d8021e6ac2..4ecd7db78e 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -27,9 +25,10 @@ #include #include #include +#include +#include #include #include -#include "smi.h" #define SMRR_SUPPORTED (1 << 11) @@ -39,18 +38,11 @@ #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) -struct ied_header { - char signature[10]; - u32 size; - u8 reserved[34]; -} __packed; struct smm_relocation_params { - u32 smram_base; - u32 smram_size; - u32 ied_base; - u32 ied_size; + uintptr_t ied_base; + size_t ied_size; msr_t smrr_base; msr_t smrr_mask; }; @@ -77,75 +69,61 @@ bool cpu_has_alternative_smrr(void) } } +static void write_smrr_alt(struct smm_relocation_params *relo_params) +{ + msr_t msr; + msr = rdmsr(IA32_FEATURE_CONTROL); + /* SMRR enabled and feature locked */ + if (!((msr.lo & SMRR_ENABLE) + && (msr.lo & FEATURE_CONTROL_LOCK_BIT))) { + printk(BIOS_WARNING, + "SMRR not enabled, skip writing SMRR...\n"); + return; + } + + printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->smrr_base.lo, relo_params->smrr_mask.lo); + + wrmsr(MSR_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask); +} + static void write_smrr(struct smm_relocation_params *relo_params) { printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - if (cpu_has_alternative_smrr()) { - msr_t msr; - msr = rdmsr(IA32_FEATURE_CONTROL); - /* SMRR enabled and feature locked */ - if (!((msr.lo & SMRR_ENABLE) - && (msr.lo & FEATURE_CONTROL_LOCK_BIT))) { - printk(BIOS_WARNING, - "SMRR not enabled, skip writing SMRR...\n"); - return; - } - wrmsr(MSR_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask); - } else { - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); - } + wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); } static void fill_in_relocation_params(struct smm_relocation_params *params) { + uintptr_t tseg_base; + size_t tseg_size; + /* All range registers are aligned to 4KiB */ const u32 rmask = ~((1 << 12) - 1); - const u32 tsegmb = northbridge_get_tseg_base(); - /* TSEG base is usually aligned down (to 8MiB). So we can't - derive the TSEG size from the distance to GTT but use the - configuration value instead. */ - const u32 tseg_size = northbridge_get_tseg_size(); + smm_region(&tseg_base, &tseg_size); - params->smram_base = tsegmb; - params->smram_size = tseg_size; - if (CONFIG_IED_REGION_SIZE != 0) { - ASSERT(params->smram_size > CONFIG_IED_REGION_SIZE); - params->smram_size -= CONFIG_IED_REGION_SIZE; - params->ied_base = tsegmb + tseg_size - CONFIG_IED_REGION_SIZE; - params->ied_size = CONFIG_IED_REGION_SIZE; - } - - /* Adjust available SMM handler memory size. */ - if (CONFIG(TSEG_STAGE_CACHE)) { - ASSERT(params->smram_size > CONFIG_SMM_RESERVED_SIZE); - params->smram_size -= CONFIG_SMM_RESERVED_SIZE; - } - - if (IS_ALIGNED(tsegmb, tseg_size)) { - /* SMRR has 32-bits of valid address aligned to 4KiB. */ - struct cpuinfo_x86 c; - - /* On model_6fx and model_1067x bits [0:11] on smrr_base - are reserved */ - get_fms(&c, cpuid_eax(1)); - if (cpu_has_alternative_smrr()) - params->smrr_base.lo = (params->smram_base & rmask); - else - params->smrr_base.lo = (params->smram_base & rmask) - | MTRR_TYPE_WRBACK; - params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) - | MTRR_PHYS_MASK_VALID; - params->smrr_mask.hi = 0; - } else { + if (!IS_ALIGNED(tseg_base, tseg_size)) { printk(BIOS_WARNING, "TSEG base not aligned with TSEG SIZE! Not setting SMRR\n"); + return; } + + /* SMRR has 32-bits of valid address aligned to 4KiB. */ + params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.hi = 0; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; + params->smrr_mask.hi = 0; + + /* On model_6fx and model_1067x bits [0:11] on smrr_base are reserved */ + if (cpu_has_alternative_smrr()) + params->smrr_base.lo &= ~rmask; + + smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); } static void setup_ied_area(struct smm_relocation_params *params) @@ -185,18 +163,18 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, fill_in_relocation_params(&smm_reloc_params); - if (CONFIG_IED_REGION_SIZE != 0) + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + + if (smm_reloc_params.ied_size) setup_ied_area(&smm_reloc_params); - *perm_smbase = smm_reloc_params.smram_base; - *perm_smsize = smm_reloc_params.smram_size; *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); } void smm_initialize(void) { /* Clear the SMM state in the southbridge. */ - southbridge_smm_clear_state(); + smm_southbridge_clear_state(); /* * Run the relocation handler for on the BSP to check and set up @@ -220,7 +198,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); /* Make appropriate changes to the save state map. */ - if (CONFIG_IED_REGION_SIZE != 0) + if (relo_params->ied_size) printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", smbase, iedbase); else @@ -234,7 +212,12 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, /* Write EMRR and SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); - if (mtrr_cap.lo & SMRR_SUPPORTED && relo_params->smrr_mask.lo != 0) + if (!(mtrr_cap.lo & SMRR_SUPPORTED)) + return; + + if (cpu_has_alternative_smrr()) + write_smrr_alt(relo_params); + else write_smrr(relo_params); } diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 1453f9962b..4ec46e0ac8 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -9,9 +9,12 @@ config SOCKET_SPECIFIC_OPTIONS # dummy select MMX select SSE select UDELAY_TSC + select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select SIPI_VECTOR_IN_ROM select C_ENVIRONMENT_BOOTBLOCK + select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_TIMEBASE # mPGA604 are usually Intel Netburst CPUs which should have SSE2 # but the ramtest.c code on the Dell S1850 seems to choke on diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 7111f5efd5..47565f44dc 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH - * 2012 secunet Security Networks AG - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/cpu/intel/speedstep/speedstep.c b/src/cpu/intel/speedstep/speedstep.c index 43d5b5a56b..ea418676e0 100644 --- a/src/cpu/intel/speedstep/speedstep.c +++ b/src/cpu/intel/speedstep/speedstep.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c index ae97f9a8cf..d0b49416d4 100644 --- a/src/cpu/intel/turbo/turbo.c +++ b/src/cpu/intel/turbo/turbo.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/cpu/qemu-power8/Kconfig b/src/cpu/qemu-power8/Kconfig index ef995b6398..d7f3ae7d6b 100644 --- a/src/cpu/qemu-power8/Kconfig +++ b/src/cpu/qemu-power8/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Gerd Hoffmann -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 141749eca4..a6c9b74360 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Gerd Hoffmann -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. @@ -21,6 +19,6 @@ config CPU_QEMU_X86 select ARCH_RAMSTAGE_X86_32 select SMP select UDELAY_TSC - select NO_MONOTONIC_TIMER + select TSC_MONOTONIC_TIMER select C_ENVIRONMENT_BOOTBLOCK select SMM_ASEG diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc index 8ddaa81227..6278f1b231 100644 --- a/src/cpu/qemu-x86/Makefile.inc +++ b/src/cpu/qemu-x86/Makefile.inc @@ -14,7 +14,11 @@ bootblock-y += cache_as_ram_bootblock.S bootblock-y += bootblock.c + +romstage-y += ../intel/car/romstage.c + ramstage-y += qemu.c + subdirs-y += ../x86/mtrr subdirs-y += ../x86/lapic subdirs-y += ../x86/smm diff --git a/src/cpu/qemu-x86/bootblock.c b/src/cpu/qemu-x86/bootblock.c index 8dcf576990..35a241c32f 100644 --- a/src/cpu/qemu-x86/bootblock.c +++ b/src/cpu/qemu-x86/bootblock.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2004 Stefan Reinauer - * Copyright (C) 2018 Patrick Rudolph - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -29,5 +26,5 @@ asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) } /* Call lib/bootblock.c main */ - bootblock_main_with_timestamp(base_timestamp, NULL, 0); + bootblock_main_with_basetime(base_timestamp); } diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index 8e78aaaf96..6ec2e4dc2c 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2000,2007 Ronald G. Minnich - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2018 Patrick Rudolph - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -28,22 +24,22 @@ cache_as_ram: * initialization. */ - post_code(0x21) - - movl $_car_stack_end, %esp - /* Align the stack and keep aligned for call to bootblock_c_entry() */ - and $0xfffffff0, %esp - sub $12, %esp - /* Clear the cache memory region. This will also clear CAR GLOBAL */ - movl $_car_region_start, %esi - movl %esi, %edi + movl $_car_region_start, %edi movl $_car_region_end, %ecx - sub $_car_region_start, %ecx + sub %edi, %ecx shr $2, %ecx xorl %eax, %eax rep stosl + post_code(0x21) + + movl $_car_stack_end, %esp + + /* Align the stack and keep aligned for call to bootblock_c_entry() */ + and $0xfffffff0, %esp + sub $4, %esp + /* Restore the BIST result and timestamps. */ movd %mm0, %ebx movd %mm1, %eax diff --git a/src/cpu/ti/am335x/bootblock.c b/src/cpu/ti/am335x/bootblock.c index cf80ee810a..93c29c034b 100644 --- a/src/cpu/ti/am335x/bootblock.c +++ b/src/cpu/ti/am335x/bootblock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/ti/am335x/bootblock_media.c b/src/cpu/ti/am335x/bootblock_media.c index 2c208b98a1..644665f6b6 100644 --- a/src/cpu/ti/am335x/bootblock_media.c +++ b/src/cpu/ti/am335x/bootblock_media.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/ti/am335x/clock.h b/src/cpu/ti/am335x/clock.h index c0b62fcb63..4a2b4018e8 100644 --- a/src/cpu/ti/am335x/clock.h +++ b/src/cpu/ti/am335x/clock.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Google Inc. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/cpu/ti/am335x/dmtimer.c b/src/cpu/ti/am335x/dmtimer.c index 42a2327497..480e8829de 100644 --- a/src/cpu/ti/am335x/dmtimer.c +++ b/src/cpu/ti/am335x/dmtimer.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/ti/am335x/dmtimer.h b/src/cpu/ti/am335x/dmtimer.h index bd850c0c0b..42afa95d47 100644 --- a/src/cpu/ti/am335x/dmtimer.h +++ b/src/cpu/ti/am335x/dmtimer.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/ti/am335x/gpio.c b/src/cpu/ti/am335x/gpio.c index 8660f2ca91..0b3eae815c 100644 --- a/src/cpu/ti/am335x/gpio.c +++ b/src/cpu/ti/am335x/gpio.c @@ -1,5 +1,5 @@ /* - * Copyright 2013 Google Inc. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/cpu/ti/am335x/gpio.h b/src/cpu/ti/am335x/gpio.h index 616c0afd9e..b6e2a997dc 100644 --- a/src/cpu/ti/am335x/gpio.h +++ b/src/cpu/ti/am335x/gpio.h @@ -1,5 +1,5 @@ /* - * Copyright 2013 Google Inc. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/cpu/ti/am335x/header.c b/src/cpu/ti/am335x/header.c index 847c8b073c..bef1e5607f 100644 --- a/src/cpu/ti/am335x/header.c +++ b/src/cpu/ti/am335x/header.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Google Inc. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/cpu/ti/am335x/header.h b/src/cpu/ti/am335x/header.h index fa5bf74071..9b40f4b7ce 100644 --- a/src/cpu/ti/am335x/header.h +++ b/src/cpu/ti/am335x/header.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Google Inc. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/cpu/ti/am335x/header.ld b/src/cpu/ti/am335x/header.ld index 1369154960..fed7b47c95 100644 --- a/src/cpu/ti/am335x/header.ld +++ b/src/cpu/ti/am335x/header.ld @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/ti/am335x/memlayout.ld b/src/cpu/ti/am335x/memlayout.ld index 9efb710f34..0de86f1f44 100644 --- a/src/cpu/ti/am335x/memlayout.ld +++ b/src/cpu/ti/am335x/memlayout.ld @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/ti/am335x/monotonic_timer.c b/src/cpu/ti/am335x/monotonic_timer.c index 94db4188e7..fc8499d924 100644 --- a/src/cpu/ti/am335x/monotonic_timer.c +++ b/src/cpu/ti/am335x/monotonic_timer.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/ti/am335x/nand.c b/src/cpu/ti/am335x/nand.c index 6b20368ee4..20f23fec49 100644 --- a/src/cpu/ti/am335x/nand.c +++ b/src/cpu/ti/am335x/nand.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/ti/am335x/pinmux.c b/src/cpu/ti/am335x/pinmux.c index 71e9cadb58..58e0fffb51 100644 --- a/src/cpu/ti/am335x/pinmux.c +++ b/src/cpu/ti/am335x/pinmux.c @@ -1,6 +1,5 @@ /* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * Copyright (C) 2013 Google Inc. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/cpu/ti/am335x/pinmux.h b/src/cpu/ti/am335x/pinmux.h index d36e0d9b49..714ba22c19 100644 --- a/src/cpu/ti/am335x/pinmux.h +++ b/src/cpu/ti/am335x/pinmux.h @@ -1,6 +1,5 @@ /* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * Copyright (C) 2013 Google Inc. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index 4e9d012037..24aa7df53b 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -1,5 +1,5 @@ /* - * Copyright 2013 Google Inc. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -182,7 +182,6 @@ void uart_tx_flush(int idx) { } -#ifndef __PRE_RAM__ void uart_fill_lb(void *data) { struct lb_serial serial; @@ -190,8 +189,9 @@ void uart_fill_lb(void *data) serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = get_uart_baudrate(); serial.regwidth = 2; + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } -#endif diff --git a/src/cpu/ti/am335x/uart.h b/src/cpu/ti/am335x/uart.h index fe9197f1e1..3ad84dc6a2 100644 --- a/src/cpu/ti/am335x/uart.h +++ b/src/cpu/ti/am335x/uart.h @@ -1,5 +1,5 @@ /* - * Copyright 2013 Google Inc. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index b7803d8fde..e4ca008f8b 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -1,16 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2000,2007 Ronald G. Minnich - * Copyright (C) 2005 Eswar Nallusamy, LANL - * Copyright (C) 2005 Tyan - * (Written by Yinghai Lu for Tyan) - * Copyright (C) 2007 coresystems GmbH - * (Written by Stefan Reinauer for coresystems GmbH) - * Copyright (C) 2007,2008 Carl-Daniel Hailfinger - * Copyright (C) 2008 VIA Technologies, Inc. - * (Written by Jason Zhao for VIA) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig index de1c2155e5..4b96c7ce82 100644 --- a/src/cpu/via/nano/Kconfig +++ b/src/cpu/via/nano/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 Alexandru Gagniuc -## ## This program is free software: you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation, either version 2 of the License, or @@ -26,10 +24,11 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select UDELAY_TSC - select NO_MONOTONIC_TIMER + select TSC_MONOTONIC_TIMER select MMX select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS + select CAR_GLOBAL_MIGRATION config DCACHE_RAM_BASE hex diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc index 43d03528cc..6fb699bee0 100644 --- a/src/cpu/via/nano/Makefile.inc +++ b/src/cpu/via/nano/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 Alexandru Gagniuc -## ## This program is free software: you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation, either version 2 of the License, or diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c index cbd80cee72..61d82f12f2 100644 --- a/src/cpu/via/nano/nano_init.c +++ b/src/cpu/via/nano/nano_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Alexandru Gagniuc - * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 2 of the License, or diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c index 0ccddc7be0..373a7d8db8 100644 --- a/src/cpu/via/nano/update_ucode.c +++ b/src/cpu/via/nano/update_ucode.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Alexandru Gagniuc - * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 2 of the License, or diff --git a/src/cpu/via/nano/update_ucode.h b/src/cpu/via/nano/update_ucode.h index acf8fdc700..31f5925cf0 100644 --- a/src/cpu/via/nano/update_ucode.h +++ b/src/cpu/via/nano/update_ucode.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Alexandru Gagniuc - * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 2 of the License, or diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 65c092133f..9c18d44945 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -1,8 +1,4 @@ -ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) -ifneq ($(CONFIG_NO_CAR_GLOBAL_MIGRATION),y) -romstage-$(CONFIG_CACHE_AS_RAM) += car.c -endif -endif +romstage-$(CONFIG_CAR_GLOBAL_MIGRATION) += car.c subdirs-y += pae subdirs-$(CONFIG_PARALLEL_MP) += name diff --git a/src/cpu/x86/backup_default_smm.c b/src/cpu/x86/backup_default_smm.c index 7b982a629e..574d87b066 100644 --- a/src/cpu/x86/backup_default_smm.c +++ b/src/cpu/x86/backup_default_smm.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index 6fc61686df..d8767ae52e 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -46,8 +44,8 @@ void *car_get_var_ptr(void *var) { char *migrated_base = NULL; int offset; - void *_car_start = _car_relocatable_data_start; - void *_car_end = _car_relocatable_data_end; + void *_car_start = _car_global_start; + void *_car_end = _car_global_end; /* If the cache-as-ram has not been migrated return the pointer * passed in. */ @@ -77,42 +75,37 @@ void *car_get_var_ptr(void *var) return &migrated_base[offset]; } +#if CONFIG(PLATFORM_USES_FSP1_0) /* - * Update a CAR_GLOBAL variable var, originally pointing to CAR region, - * with the address in migrated CAR region in DRAM. + * When a CAR_GLOBAL points to target object inside CAR, use relative + * addressing. Such CAR_GLOBAL has to be expicitly accessed using + * car_set_reloc_ptr() and car_get_reloc_ptr() as the stored value is now + * an offset instead of the absolute address (pointer) of the target. + * + * This way discovery of objects that are not CAR_GLOBALs themselves, + * remain discoverable after CAR migration has implicitly happened. */ -void *car_sync_var_ptr(void *var) +void car_set_reloc_ptr(void *var, void *val) { - void **mig_var = car_get_var_ptr(var); - void *_car_start = _car_relocatable_data_start; - void *_car_end = _car_relocatable_data_end; + uintptr_t *offset = car_get_var_ptr(var); + *offset = 0; - /* Not moved or migrated yet. */ - if (mig_var == var) - return mig_var; - - /* - * Migrate the cbmem console pointer for FSP 1.0 platforms. Otherwise, - * keep console buffer in CAR until cbmemc_reinit() moves it. - */ - if (*mig_var == _preram_cbmem_console) { - if (CONFIG(PLATFORM_USES_FSP1_0)) - *mig_var += (char *)mig_var - (char *)var; - return mig_var; - } - - /* It's already pointing outside car.global_data. */ - if (*mig_var < _car_start || *mig_var > _car_end) - return mig_var; - - /* Move the pointer by the same amount the variable storing it was - * moved by. - */ - *mig_var += (char *)mig_var - (char *)var; - - return mig_var; + if (val) + *offset = (uintptr_t)offset - (uintptr_t)val; } +void *car_get_reloc_ptr(void *var) +{ + uintptr_t *offset = car_get_var_ptr(var); + void *val = NULL; + + if (*offset) + val = (void *)((uintptr_t)offset - *offset); + + return val; +} +#endif + int car_active(void) { return !car_migrated; @@ -134,7 +127,7 @@ static void do_car_migrate_variables(void) return; } - memcpy(migrated_base, _car_relocatable_data_start, car_size); + memcpy(migrated_base, _car_global_start, car_size); /* Mark that the data has been moved. */ car_migrated = ~0; diff --git a/src/cpu/x86/fpu_enable.inc b/src/cpu/x86/fpu_enable.inc index 2c87cc5b5f..e3dd4c7372 100644 --- a/src/cpu/x86/fpu_enable.inc +++ b/src/cpu/x86/fpu_enable.inc @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2002 Eric Biederman - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 6521a8a308..58836b5e3f 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -20,44 +17,8 @@ #include #include #include -#include #include #include -#include - -/* NOTE: This code uses global variables, so it can not be used during - * memory init. - */ - -#if CONFIG_UDELAY_LAPIC_FIXED_FSB != 0 -static inline u32 get_timer_fsb(void) -{ - return CONFIG_UDELAY_LAPIC_FIXED_FSB; -} - -static int set_timer_fsb(void) -{ - return 0; -} -#else -static u32 g_timer_fsb CAR_GLOBAL; - -static int set_timer_fsb(void) -{ - int ia32_fsb = get_ia32_fsb(); - - if (ia32_fsb > 0) { - car_set_var(g_timer_fsb, ia32_fsb); - return 0; - } - return -1; -} - -static inline u32 get_timer_fsb(void) -{ - return car_get_var(g_timer_fsb); -} -#endif void init_timer(void) { @@ -69,9 +30,6 @@ void init_timer(void) /* Set the initial counter to 0xffffffff */ lapic_write(LAPIC_TMICT, 0xffffffff); - - /* Set FSB frequency to a reasonable value */ - set_timer_fsb(); } void udelay(u32 usecs) diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index cbbc10df31..668988a70e 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -1,13 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2001 Eric Biederman - * Copyright (C) 2001 Ronald G. Minnich - * Copyright (C) 2005 Yinghai Lu - * Copyright (C) 2008 coresystems GmbH - * Copyright (C) 2015 Timothy Pearson , - * Raptor Engineering - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -21,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -590,14 +584,3 @@ void initialize_cpus(struct bus *cpu_bus) if (is_smp_boot()) recover_lowest_1M(); } - -#if !CONFIG(HAVE_SMI_HANDLER) -/* Empty stubs for platforms without SMI handlers. */ -void smm_init(void) -{ -} - -void smm_init_completion(void) -{ -} -#endif diff --git a/src/cpu/x86/mirror_payload.c b/src/cpu/x86/mirror_payload.c index 88c5e8183f..9dec8dbc68 100644 --- a/src/cpu/x86/mirror_payload.c +++ b/src/cpu/x86/mirror_payload.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 3658a5b698..29ae3de87a 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of @@ -964,12 +962,13 @@ int mp_run_on_aps(void (*func)(void *), void *arg, int logical_cpu_num, return run_ap_work(&lcb, expire_us); } -int mp_run_on_all_cpus(void (*func)(void *), void *arg, long expire_us) +int mp_run_on_all_cpus(void (*func)(void *), void *arg) { /* Run on BSP first. */ func(arg); - return mp_run_on_aps(func, arg, MP_RUN_ON_ALL_CPUS, expire_us); + /* For up to 1 second for AP to finish previous work. */ + return mp_run_on_aps(func, arg, MP_RUN_ON_ALL_CPUS, 1000 * USECS_PER_MSEC); } int mp_park_aps(void) @@ -981,7 +980,7 @@ int mp_park_aps(void) stopwatch_init(&sw); ret = mp_run_on_aps(park_this_cpu, NULL, MP_RUN_ON_ALL_CPUS, - 250 * USECS_PER_MSEC); + 1000 * USECS_PER_MSEC); duration_msecs = stopwatch_duration_msecs(&sw); diff --git a/src/cpu/x86/mtrr/debug.c b/src/cpu/x86/mtrr/debug.c index c430bc1e8f..09ffa9f977 100644 --- a/src/cpu/x86/mtrr/debug.c +++ b/src/cpu/x86/mtrr/debug.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Intel Corporation. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 98449d5542..b26e31a1d4 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -1,10 +1,5 @@ /* - * mtrr.c: setting MTRR to decent values for cache initialization on P6 - * - * Derived from intel_set_mtrr in intel_subr.c and mtrr.c in linux kernel - * - * Copyright 2000 Silicon Integrated System Corporation - * Copyright 2013 Google Inc. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,6 +11,8 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * + * mtrr.c: setting MTRR to decent values for cache initialization on P6 + * Derived from intel_set_mtrr in intel_subr.c and mtrr.c in linux kernel * * Reference: Intel Architecture Software Developer's Manual, Volume 3: System * Programming diff --git a/src/cpu/x86/name/Makefile.inc b/src/cpu/x86/name/Makefile.inc index 5dba1a2f2e..a2e37e56fc 100644 --- a/src/cpu/x86/name/Makefile.inc +++ b/src/cpu/x86/name/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2010 Uwe Hermann -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/x86/name/name.c b/src/cpu/x86/name/name.c index fc360cd877..b3452763c0 100644 --- a/src/cpu/x86/name/name.c +++ b/src/cpu/x86/name/name.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index f54a1c35db..47d7e1f954 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2005 Yinghai Lu - * Copyright (C) 2019 9elements Agency GmbH - * Copyright (C) 2019 Facebook Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -363,7 +359,7 @@ static int read_from_cbfs(const char *name, void *buf, size_t size) int paging_enable_for_car(const char *pdpt_name, const char *pt_name) { - if (!ENV_CACHE_AS_RAM) + if (!preram_symbols_available()) return -1; if (read_from_cbfs(pdpt_name, _pdpt, REGION_SIZE(pdpt))) { @@ -383,7 +379,7 @@ int paging_enable_for_car(const char *pdpt_name, const char *pt_name) static void *get_pdpt_addr(void) { - if (ENV_CACHE_AS_RAM) + if (preram_symbols_available()) return _pdpt; return (void *)(uintptr_t)read_cr3(); } diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index 11f0c2476a..edc1e779be 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index fe149f140f..11a4e67199 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2008-2010 coresystems GmbH -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. @@ -42,9 +40,9 @@ endif ifeq ($(CONFIG_SMM_TSEG),y) -ramstage-y += stage_cache.c -romstage-y += stage_cache.c -postcar-y += stage_cache.c +ramstage-y += tseg_region.c +romstage-y += tseg_region.c +postcar-y += tseg_region.c smmstub-y += smm_stub.S diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index bc01522291..68b7859a04 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of @@ -18,11 +16,34 @@ #include #include #include +#include +#include +#include +#include +#include +#include #if CONFIG(SPI_FLASH_SMM) #include #endif +typedef enum { + AMD64, + EM64T, + EM64T101, + LEGACY +} save_state_type_t; + +typedef struct { + save_state_type_t type; + union { + amd64_smm_state_save_area_t *amd64_state_save; + em64t_smm_state_save_area_t *em64t_state_save; + em64t101_smm_state_save_area_t *em64t101_state_save; + legacy_smm_state_save_area_t *legacy_state_save; + }; +} smm_state_save_area_t; + static int do_driver_init = 1; typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore; @@ -193,9 +214,7 @@ void smi_handler(u32 smm_revision) } /* Call chipset specific SMI handlers. */ - cpu_smi_handler(node, &state_save); - northbridge_smi_handler(node, &state_save); - southbridge_smi_handler(node, &state_save); + southbridge_smi_handler(); smi_restore_pci_address(); @@ -210,12 +229,7 @@ void smi_handler(u32 smm_revision) * weak relocations w/o a symbol have a 0 address which is where the modules * are linked at. */ int __weak mainboard_io_trap_handler(int smif) { return 0; } -void __weak cpu_smi_handler(unsigned int node, - smm_state_save_area_t *state_save) {} -void __weak northbridge_smi_handler(unsigned int node, - smm_state_save_area_t *state_save) {} -void __weak southbridge_smi_handler(unsigned int node, - smm_state_save_area_t *state_save) {} +void __weak southbridge_smi_handler(void) {} void __weak mainboard_smi_gpi(u32 gpi_sts) {} int __weak mainboard_smi_apmc(u8 data) { return 0; } void __weak mainboard_smi_sleep(u8 slp_typ) {} diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index 0d9abc5763..bd4d48c555 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index fb5c5f33e9..c6c6b38737 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 59eb27c8b5..f0e55f9a18 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google LLC - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index f586b35154..a2be7f2310 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 coresystems GmbH - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index e23b082aa7..f64b36507f 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2010 coresystems GmbH - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of @@ -14,9 +12,6 @@ * GNU General Public License for more details. */ -// Make sure no stage 2 code is included: -#define __PRE_RAM__ - // FIXME: Is this piece of code southbridge specific, or // can it be cleaned up so this include is not required? // It's needed right now because we get our DEFAULT_PMBASE from diff --git a/src/cpu/x86/smm/tseg_region.c b/src/cpu/x86/smm/tseg_region.c new file mode 100644 index 0000000000..a8b8bb7b9a --- /dev/null +++ b/src/cpu/x86/smm/tseg_region.c @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +/* + * Subregions within SMM + * +-------------------------+ + * | IED | IED_REGION_SIZE + * +-------------------------+ + * | External Stage Cache | SMM_RESERVED_SIZE + * +-------------------------+ + * | code and data | + * | (TSEG) | + * +-------------------------+ TSEG + */ +int smm_subregion(int sub, uintptr_t *start, size_t *size) +{ + uintptr_t sub_base; + size_t sub_size; + const size_t ied_size = CONFIG_IED_REGION_SIZE; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + smm_region(&sub_base, &sub_size); + + ASSERT(IS_ALIGNED(sub_base, sub_size)); + ASSERT(sub_size > (cache_size + ied_size)); + + switch (sub) { + case SMM_SUBREGION_HANDLER: + /* Handler starts at the base of TSEG. */ + sub_size -= ied_size; + sub_size -= cache_size; + break; + case SMM_SUBREGION_CACHE: + /* External cache is in the middle of TSEG. */ + sub_base += sub_size - (ied_size + cache_size); + sub_size = cache_size; + break; + case SMM_SUBREGION_CHIPSET: + /* IED is at the top. */ + sub_base += sub_size - ied_size; + sub_size = ied_size; + break; + default: + *start = 0; + *size = 0; + return -1; + } + + *start = sub_base; + *size = sub_size; + return 0; +} + +void stage_cache_external_region(void **base, size_t *size) +{ + if (smm_subregion(SMM_SUBREGION_CACHE, (uintptr_t *)base, size)) { + printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); + *base = NULL; + *size = 0; + } +} + +void smm_list_regions(void) +{ + uintptr_t base; + size_t size; + int i; + + smm_region(&base, &size); + if (!size) + return; + + printk(BIOS_DEBUG, "SMM Memory Map\n"); + printk(BIOS_DEBUG, "SMRAM : 0x%zx 0x%zx\n", base, size); + + for (i = 0; i < SMM_SUBREGION_NUM; i++) { + if (smm_subregion(i, &base, &size)) + continue; + printk(BIOS_DEBUG, " Subregion %d: 0x%zx 0x%zx\n", i, base, size); + } +} diff --git a/src/cpu/x86/sse_enable.inc b/src/cpu/x86/sse_enable.inc index cef3c85cac..7608230e5e 100644 --- a/src/cpu/x86/sse_enable.inc +++ b/src/cpu/x86/sse_enable.inc @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2002 Eric Biederman - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/device/Kconfig b/src/device/Kconfig index e605bc2097..97ed997aee 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -1,9 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2010 coresystems GmbH -## (Written by Stefan Reinauer for coresystems GmbH) -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. @@ -392,18 +389,6 @@ config FRAMEBUFFER_VESA_MODE default 0x11A if FRAMEBUFFER_VESA_MODE_11A default 0x11B if FRAMEBUFFER_VESA_MODE_11B default 0x118 if FRAMEBUFFER_VESA_MODE_USER - -config BOOTSPLASH - prompt "Show graphical bootsplash" - bool - help - This option shows a graphical bootsplash screen. The graphics are - loaded from the CBFS file bootsplash.jpg. - - You can either specify the location and file name of the - image in the 'General' section or add it manually to CBFS, using, - for example, cbfstool. - endif # FRAMEBUFFER_SET_VESA_MODE choice @@ -447,6 +432,18 @@ config LINEAR_FRAMEBUFFER def_bool y depends on VBE_LINEAR_FRAMEBUFFER || GENERIC_LINEAR_FRAMEBUFFER +config BOOTSPLASH + prompt "Show graphical bootsplash" + bool + depends on LINEAR_FRAMEBUFFER + help + This option shows a graphical bootsplash screen. The graphics are + loaded from the CBFS file bootsplash.jpg. + + You can either specify the location and file name of the + image in the 'General' section or add it manually to CBFS, using, + for example, cbfstool. + config LINEAR_FRAMEBUFFER_MAX_WIDTH int "Maximum width in pixels" depends on LINEAR_FRAMEBUFFER && MAINBOARD_USE_LIBGFXINIT diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index baa45bec3e..966ca0d198 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -53,3 +53,8 @@ verstage-y += i2c.c romstage-y += i2c.c ramstage-y += i2c.c ramstage-y += i2c_bus.c + +bootblock-y += mmio.c +verstage-y += mmio.c +romstage-y += mmio.c +ramstage-y += mmio.c diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index a2849b773a..519d4612aa 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 DMP Electronics Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -16,7 +14,6 @@ #include #include #include -#include #include #include #include diff --git a/src/device/cardbus_device.c b/src/device/cardbus_device.c index adfc503581..48c54bc16a 100644 --- a/src/device/cardbus_device.c +++ b/src/device/cardbus_device.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2005 Linux Networx - * (Written by Eric Biederman for Linux Networx) - * Copyright (C) 2005 Ronald G. Minnich - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -156,16 +152,14 @@ void cardbus_enable_resources(struct device *dev) ctrl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL); ctrl |= (dev->link_list->bridge_ctrl & ( - PCI_BRIDGE_CTL_PARITY | - PCI_BRIDGE_CTL_SERR | PCI_BRIDGE_CTL_NO_ISA | PCI_BRIDGE_CTL_VGA | PCI_BRIDGE_CTL_MASTER_ABORT | PCI_BRIDGE_CTL_BUS_RESET)); /* Error check */ - ctrl |= (PCI_CB_BRIDGE_CTL_PARITY + PCI_CB_BRIDGE_CTL_SERR); + ctrl |= (PCI_CB_BRIDGE_CTL_PARITY | PCI_CB_BRIDGE_CTL_SERR); printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); - pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); + pci_write_config16(dev, PCI_CB_BRIDGE_CONTROL, ctrl); pci_dev_enable_resources(dev); } diff --git a/src/device/cpu_device.c b/src/device/cpu_device.c index f59cce3573..a786dc0614 100644 --- a/src/device/cpu_device.c +++ b/src/device/cpu_device.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2012 Kyösti Mälkki - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/device/device.c b/src/device/device.c index 17cd8f4ab8..44d1f95f75 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -1,20 +1,6 @@ /* * This file is part of the coreboot project. * - * It was originally based on the Linux kernel (arch/i386/kernel/pci-pc.c). - * - * Modifications are: - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2003-2004 Linux Networx - * (Written by Eric Biederman for Linux Networx) - * Copyright (C) 2003 Ronald G. Minnich - * Copyright (C) 2004-2005 Li-Ta Lo - * Copyright (C) 2005-2006 Tyan - * (Written by Yinghai Lu for Tyan) - * Copyright (C) 2005-2006 Stefan Reinauer - * Copyright (C) 2009 Myles Watson - * Copyright (c) 1999--2000 Martin Mares - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -26,16 +12,7 @@ */ /* - * Lots of mods by Ron Minnich , with - * the final architecture guidance from Tom Merritt . - * - * In particular, we changed from the one-pass original version to - * Tom's recommended multiple-pass version. I wasn't sure about doing - * it with multiple passes, until I actually started doing it and saw - * the wisdom of Tom's recommendations... - * - * Lots of cleanups by Eric Biederman to handle bridges, and to - * handle resource allocation for non-PCI devices. + * Originally based on the Linux kernel (arch/i386/kernel/pci-pc.c). */ #include diff --git a/src/device/device_const.c b/src/device/device_const.c index c472aeaa79..5143563a87 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -1,13 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003-2004 Linux Networx - * (Written by Eric Biederman for Linux Networx) - * Copyright (C) 2003 Greg Watson - * Copyright (C) 2004 Li-Ta Lo - * Copyright (C) 2005-2006 Tyan - * (Written by Yinghai Lu for Tyan) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -204,7 +197,7 @@ DEVTREE_CONST struct device *pcidev_path_on_bus(unsigned int bus, pci_devfn_t de DEVTREE_CONST struct bus *pci_root_bus(void) { DEVTREE_CONST struct device *pci_domain; - MAYBE_STATIC DEVTREE_CONST struct bus *pci_root = NULL; + MAYBE_STATIC_BSS DEVTREE_CONST struct bus *pci_root = NULL; if (pci_root) return pci_root; diff --git a/src/device/device_util.c b/src/device/device_util.c index 38303126bc..df66f5c620 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -1,13 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003-2004 Linux Networx - * (Written by Eric Biederman for Linux Networx) - * Copyright (C) 2003 Greg Watson - * Copyright (C) 2004 Li-Ta Lo - * Copyright (C) 2005-2006 Tyan - * (Written by Yinghai Lu for Tyan) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc index c982ef49e8..f397a534f2 100644 --- a/src/device/dram/Makefile.inc +++ b/src/device/dram/Makefile.inc @@ -1 +1 @@ -romstage-y += ddr3.c ddr2.c +romstage-y += ddr4.c ddr3.c ddr2.c ddr_common.c diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index 60588b880b..5319806ae6 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Patrick Rudolph - * Copyright (C) 2017 Arthur Heymans - * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 2 of the License, or @@ -93,7 +90,7 @@ u16 spd_ddr2_calc_unique_crc(const u8 *spd, int len) for (i = 93; i <= 98; i++) id_bytes[j++] = spd[i]; - return ddr3_crc16(id_bytes, 15); + return ddr_crc16(id_bytes, 15); } /** diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 834dc83db6..3f0c0a703e 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2013 Alexandru Gagniuc - * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 2 of the License, or @@ -23,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -50,24 +49,6 @@ int spd_dimm_is_registered_ddr3(enum spd_dimm_type type) return 0; } -u16 ddr3_crc16(const u8 *ptr, int n_crc) -{ - int i; - u16 crc = 0; - - while (--n_crc >= 0) { - crc = crc ^ ((int)*ptr++ << 8); - for (i = 0; i < 8; ++i) - if (crc & 0x8000) { - crc = (crc << 1) ^ 0x1021; - } else { - crc = crc << 1; - } - } - - return crc; -} - /** * \brief Calculate the CRC of a DDR3 SPD * @@ -91,7 +72,7 @@ u16 spd_ddr3_calc_crc(u8 *spd, int len) /* Not enough bytes available to get the CRC */ return 0; - return ddr3_crc16(spd, n_crc); + return ddr_crc16(spd, n_crc); } /** @@ -108,7 +89,7 @@ u16 spd_ddr3_calc_unique_crc(u8 *spd, int len) /* Not enough bytes available to get the CRC */ return 0; - return ddr3_crc16(&spd[117], 11); + return ddr_crc16(&spd[117], 11); } /** diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c new file mode 100644 index 0000000000..4f99ecc925 --- /dev/null +++ b/src/device/dram/ddr4.c @@ -0,0 +1,246 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +typedef enum { + BLOCK_0, /* Base Configuration and DRAM Parameters */ + BLOCK_1, + BLOCK_1_L, /* Standard Module Parameters */ + BLOCK_1_H, /* Hybrid Module Parameters */ + BLOCK_2, + BLOCK_2_L, /* Hybrid Module Extended Function Parameters */ + BLOCK_2_H, /* Manufacturing Information */ + BLOCK_3 /* End user programmable */ +} spd_block_type; + +typedef struct { + spd_block_type type; + uint16_t start; /* starting offset from beginning of the spd */ + uint16_t len; /* size of the block */ + uint16_t crc_start; /* offset from start of crc bytes, 0 if none */ +} spd_block; + +/* 'SPD contents architecture' as per datasheet */ +const spd_block spd_blocks[] = { + {.type = BLOCK_0, 0, 128, 126}, {.type = BLOCK_1, 128, 128, 126}, + {.type = BLOCK_1_L, 128, 64, 0}, {.type = BLOCK_1_H, 192, 64, 0}, + {.type = BLOCK_2_L, 256, 64, 62}, {.type = BLOCK_2_H, 320, 64, 0}, + {.type = BLOCK_3, 384, 128, 0} }; + +static bool verify_block(const spd_block *block, spd_raw_data spd) +{ + uint16_t crc, spd_crc; + + spd_crc = (spd[block->start + block->crc_start + 1] << 8) + | spd[block->start + block->crc_start]; + crc = ddr_crc16(&spd[block->start], block->len - 2); + + return spd_crc == crc; +} + +/* Check if given block is 'reserved' for a given module type */ +static bool block_exists(spd_block_type type, u8 dimm_type) +{ + bool is_hybrid; + + switch (type) { + case BLOCK_0: /* fall-through */ + case BLOCK_1: /* fall-through */ + case BLOCK_1_L: /* fall-through */ + case BLOCK_1_H: /* fall-through */ + case BLOCK_2_H: /* fall-through */ + case BLOCK_3: /* fall-through */ + return true; + case BLOCK_2_L: + is_hybrid = (dimm_type >> 4) & ((1 << 3) - 1); + if (is_hybrid) + return true; + return false; + default: /* fall-through */ + return false; + } +} + + +/** + * \brief Decode the raw SPD data + * + * Decodes a raw SPD data from a DDR4 DIMM, and organizes it into a + * @ref dimm_attr structure. The SPD data must first be read in a contiguous + * array, and passed to this function. + * + * @param dimm pointer to @ref dimm_attr structure where the decoded data is to + * be stored + * @param spd array of raw data previously read from the SPD. + * + * @return @ref spd_status enumerator + * SPD_STATUS_OK -- decoding was successful + * SPD_STATUS_INVALID -- invalid SPD or not a DDR4 SPD + * SPD_STATUS_CRC_ERROR -- checksum mismatch + */ +int spd_decode_ddr4(dimm_attr *dimm, spd_raw_data spd) +{ + u8 reg8; + u8 bus_width, sdram_width; + u16 cap_per_die_mbit; + u16 spd_bytes_total, spd_bytes_used; + const uint16_t spd_bytes_used_table[] = {0, 128, 256, 384, 512}; + + /* Make sure that the SPD dump is indeed from a DDR4 module */ + if (spd[2] != SPD_MEMORY_TYPE_DDR4_SDRAM) { + printk(BIOS_ERR, "Not a DDR4 SPD!\n"); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return SPD_STATUS_INVALID; + } + + spd_bytes_total = (spd[0] >> 4) & ((1 << 3) - 1); + spd_bytes_used = spd[0] & ((1 << 4) - 1); + + if (!spd_bytes_total || !spd_bytes_used) { + printk(BIOS_ERR, "SPD failed basic sanity checks\n"); + return SPD_STATUS_INVALID; + } + + spd_bytes_total = 256 << (spd_bytes_total - 1); + spd_bytes_used = spd_bytes_used_table[spd_bytes_used]; + + /* Verify CRC of blocks that have them, do not step over 'used' length */ + for (int i = 0; i < ARRAY_SIZE(spd_blocks); i++) { + /* this block is not checksumed */ + if (spd_blocks[i].crc_start == 0) + continue; + /* we shouldn't have this block */ + if (spd_blocks[i].start + spd_blocks[i].len > spd_bytes_used) + continue; + /* check if block exists in the current schema */ + if (!block_exists(spd_blocks[i].type, spd[3])) + continue; + if (!verify_block(&spd_blocks[i], spd)) { + printk(BIOS_ERR, "CRC failed for block %d\n", i); + return SPD_STATUS_CRC_ERROR; + } + } + + dimm->dram_type = SPD_MEMORY_TYPE_DDR4_SDRAM; + dimm->dimm_type = spd[3] & ((1 << 4) - 1); + + reg8 = spd[13] & ((1 << 4) - 1); + dimm->bus_width = reg8; + bus_width = 8 << (reg8 & ((1 << 3) - 1)); + + reg8 = spd[12] & ((1 << 3) - 1); + dimm->sdram_width = reg8; + sdram_width = 4 << reg8; + + reg8 = spd[4] & ((1 << 4) - 1); + dimm->cap_per_die_mbit = reg8; + cap_per_die_mbit = (1 << reg8) * 256; + + reg8 = (spd[12] >> 3) & ((1 << 3) - 1); + dimm->ranks = reg8 + 1; + + if (!bus_width || !sdram_width) { + printk(BIOS_ERR, "SPD information is invalid"); + dimm->size_mb = 0; + return SPD_STATUS_INVALID; + } + + /* seems to be only one, in mV */ + dimm->vdd_voltage = 1200; + + /* calculate size */ + dimm->size_mb = cap_per_die_mbit / 8 * bus_width / sdram_width * dimm->ranks; + + /* make sure we have the manufacturing information block */ + if (spd_bytes_used > 320) { + dimm->manufacturer_id = (spd[351] << 8) | spd[350]; + memcpy(dimm->part_number, &spd[329], SPD_DDR4_PART_LEN); + dimm->part_number[SPD_DDR4_PART_LEN] = 0; + memcpy(dimm->serial_number, &spd[325], sizeof(dimm->serial_number)); + } + return SPD_STATUS_OK; +} + +enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, const u16 selected_freq, + const dimm_attr *info) +{ + struct memory_info *mem_info; + struct dimm_info *dimm; + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_find(CBMEM_ID_MEMINFO); + if (!mem_info) { + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + + printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); + if (!mem_info) + return CB_ERR; + + memset(mem_info, 0, sizeof(*mem_info)); + } + + if (mem_info->dimm_cnt >= ARRAY_SIZE(mem_info->dimm)) { + printk(BIOS_WARNING, "BUG: Too many DIMM infos for %s.\n", __func__); + return CB_ERR; + } + + dimm = &mem_info->dimm[mem_info->dimm_cnt]; + if (info->size_mb) { + dimm->ddr_type = MEMORY_TYPE_DDR4; + dimm->ddr_frequency = selected_freq; + dimm->dimm_size = info->size_mb; + dimm->channel_num = channel; + dimm->rank_per_dimm = info->ranks; + dimm->dimm_num = slot; + memcpy(dimm->module_part_number, info->part_number, SPD_DDR4_PART_LEN); + dimm->mod_id = info->manufacturer_id; + + switch (info->dimm_type) { + case SPD_DIMM_TYPE_SO_DIMM: + dimm->mod_type = SPD_SODIMM; + break; + case SPD_DIMM_TYPE_72B_SO_RDIMM: + dimm->mod_type = SPD_72B_SO_RDIMM; + break; + case SPD_DIMM_TYPE_UDIMM: + dimm->mod_type = SPD_UDIMM; + break; + case SPD_DIMM_TYPE_RDIMM: + dimm->mod_type = SPD_RDIMM; + break; + default: + dimm->mod_type = SPD_UNDEFINED; + break; + } + + dimm->bus_width = info->bus_width; + memcpy(dimm->serial, info->serial_number, + MIN(sizeof(dimm->serial), sizeof(info->serial_number))); + + dimm->vdd_voltage = info->vdd_voltage; + mem_info->dimm_cnt++; + } + + return CB_SUCCESS; +} diff --git a/src/cpu/x86/smm/stage_cache.c b/src/device/dram/ddr_common.c similarity index 56% rename from src/cpu/x86/smm/stage_cache.c rename to src/device/dram/ddr_common.c index 0a816ba732..bc87712ef6 100644 --- a/src/cpu/x86/smm/stage_cache.c +++ b/src/device/dram/ddr_common.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -14,20 +12,30 @@ */ #include -#include -#include +#include #include -int __weak smm_subregion(int sub, uintptr_t *base, size_t *size) +/** + * \brief Calculate the CRC of a DDR SPD data + * + * @param spd pointer to raw SPD data + * @param len length of data in SPD + * + * @return the CRC of the SPD data + */ +u16 ddr_crc16(const u8 *ptr, int n_crc) { - return -1; -} + int i; + u16 crc = 0; -void __weak stage_cache_external_region(void **base, size_t *size) -{ - if (smm_subregion(SMM_SUBREGION_CACHE, (uintptr_t *)base, size)) { - printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; - *size = 0; + while (--n_crc >= 0) { + crc = crc ^ ((int)*ptr++ << 8); + for (i = 0; i < 8; ++i) + if (crc & 0x8000) + crc = (crc << 1) ^ 0x1021; + else + crc = crc << 1; } + + return crc; } diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index 027c3ef1d4..1a8f7e6dc1 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -1,15 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003-2004 Linux Networx - * (Written by Eric Biederman for Linux Networx) - * Copyright (C) 2004 David Hendricks - * Copyright (C) 2004 Li-Ta Lo - * Copyright (C) 2005-2006 Tyan - * (Written by Yinghai Lu for Tyan) - * Copyright (C) 2005-2006 Stefan Reinauer - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/device/i2c.c b/src/device/i2c.c index aa695caf03..fb29b7291d 100644 --- a/src/device/i2c.c +++ b/src/device/i2c.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 MediaTek Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/device/mmio.c b/src/device/mmio.c new file mode 100644 index 0000000000..643ff0429a --- /dev/null +++ b/src/device/mmio.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +/* Helper functions for various MMIO access patterns. */ + +void buffer_from_fifo32(void *buffer, size_t size, void *fifo, + int fifo_stride, int fifo_width) +{ + u8 *p = buffer; + int i, j; + + assert(fifo_width > 0 && fifo_width <= sizeof(u32) && + fifo_stride % sizeof(u32) == 0); + + for (i = 0; i < size; i += fifo_width, fifo += fifo_stride) { + u32 val = read32(fifo); + for (j = 0; j < MIN(size - i, fifo_width); j++) + *p++ = (u8)(val >> (j * 8)); + } +} + +void buffer_to_fifo32_prefix(void *buffer, u32 prefix, int prefsz, size_t size, + void *fifo, int fifo_stride, int fifo_width) +{ + u8 *p = buffer; + int i, j = prefsz; + + assert(fifo_width > 0 && fifo_width <= sizeof(u32) && + fifo_stride % sizeof(u32) == 0 && prefsz <= fifo_width); + + uint32_t val = prefix; + for (i = 0; i < size; i += fifo_width, fifo += fifo_stride) { + for (; j < MIN(size - i, fifo_width); j++) + val |= *p++ << (j * 8); + write32(fifo, val); + val = 0; + j = 0; + } + +} diff --git a/src/device/oprom/Makefile.inc b/src/device/oprom/Makefile.inc index 61970ae16f..64b4b87da5 100644 --- a/src/device/oprom/Makefile.inc +++ b/src/device/oprom/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2010 coresystems GmbH -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/device/oprom/realmode/Makefile.inc b/src/device/oprom/realmode/Makefile.inc index 54172405a7..6f8cde3f6d 100644 --- a/src/device/oprom/realmode/Makefile.inc +++ b/src/device/oprom/realmode/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 secunet Security Networks AG -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 1a80a000e2..8ba0241ea4 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2009-2010 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -19,8 +16,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/src/device/oprom/realmode/x86.h b/src/device/oprom/realmode/x86.h index 052c9c0dbf..a68b50ecbf 100644 --- a/src/device/oprom/realmode/x86.h +++ b/src/device/oprom/realmode/x86.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2009-2010 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/device/oprom/realmode/x86_asm.S b/src/device/oprom/realmode/x86_asm.S index ec82e53ec5..8c9e12b143 100644 --- a/src/device/oprom/realmode/x86_asm.S +++ b/src/device/oprom/realmode/x86_asm.S @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009-2010 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/device/oprom/realmode/x86_interrupts.c b/src/device/oprom/realmode/x86_interrupts.c index 8e3a51e450..4e1c5ed5af 100644 --- a/src/device/oprom/realmode/x86_interrupts.c +++ b/src/device/oprom/realmode/x86_interrupts.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2001 Ronald G. Minnich - * Copyright (C) 2005 Nick.Barker9@btinternet.com - * Copyright (C) 2007-2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/device/pci_class.c b/src/device/pci_class.c index d9c3a4f90f..ca36154e44 100644 --- a/src/device/pci_class.c +++ b/src/device/pci_class.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 5765529f86..c043dd6591 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1,22 +1,6 @@ /* * This file is part of the coreboot project. * - * It was originally based on the Linux kernel (drivers/pci/pci.c). - * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, - * David Mosberger-Tang - * - * Copyright 1997 -- 1999 Martin Mares - * - * Copyright (C) 2003-2004 Linux Networx - * (Written by Eric Biederman for Linux Networx) - * Copyright (C) 2003-2006 Ronald G. Minnich - * Copyright (C) 2004-2005 Li-Ta Lo - * Copyright (C) 2005-2006 Tyan - * (Written by Yinghai Lu for Tyan) - * Copyright (C) 2005-2009 coresystems GmbH - * (Written by Stefan Reinauer for coresystems GmbH) - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -28,13 +12,13 @@ */ /* + * Originally based on the Linux kernel (drivers/pci/pci.c). * PCI Bus Services, see include/linux/pci.h for further explanation. */ #include #include #include -#include #include #include #include @@ -642,7 +626,7 @@ void pci_bus_enable_resources(struct device *dev) dev->command |= PCI_COMMAND_IO; ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); ctrl |= dev->link_list->bridge_ctrl; - ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* Error check. */ + ctrl |= (PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR); /* Error check. */ printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); @@ -766,9 +750,6 @@ void pci_dev_init(struct device *dev) gfx_set_init_done(1); printk(BIOS_DEBUG, "VGA Option ROM was run\n"); timestamp_add_now(TS_OPROM_END); - - if (CONFIG(BOOTSPLASH)) - set_vesa_bootsplash(); } /** Default device operation for PCI devices */ diff --git a/src/device/pci_early.c b/src/device/pci_early.c index 7c9ea005c6..880480d280 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 2b2d46d57b..01c02e58e6 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -1,12 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2005 Li-Ta Lo - * Copyright (C) 2005 Tyan - * (Written by Yinghai Lu for Tyan) - * Copyright (C) 2005 Ronald G. Minnich - * Copyright (C) 2005-2007 Stefan Reinauer - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index c20981625e..9a45be87a9 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2005 Linux Networx - * (Written by Eric Biederman for Linux Networx) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/device/pcix_device.c b/src/device/pcix_device.c index e327b88991..1db4d4adce 100644 --- a/src/device/pcix_device.c +++ b/src/device/pcix_device.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2005 Linux Networx - * (Written by Eric Biederman for Linux Networx) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index 402e5d1e83..164fc19960 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -1,14 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2004 Linux Networx - * (Written by Eric Biederman for Linux Networx) - * Copyright (C) 2004 Li-Ta Lo - * Copyright (C) 2005 Tyan - * (Written by Yinghai Lu for Tyan) - * Copyright (C) 2013 Nico Huber - * Copyright (C) 2018 Felix Held - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/device/root_device.c b/src/device/root_device.c index f8e2907ce4..beeead2dfb 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -1,13 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003-2004 Linux Networx - * (Written by Eric Biederman for Linux Networx) - * Copyright (C) 2003 Ronald G. Minnich - * Copyright (C) 2004-2005 Li-Ta Lo - * Copyright (C) 2005 Tyan - * (Written by Yinghai Lu for Tyan) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/device/smbus_ops.c b/src/device/smbus_ops.c index c91f415e6c..13e6cadd55 100644 --- a/src/device/smbus_ops.c +++ b/src/device/smbus_ops.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2004 Tyan - * (Written by Yinghai Lu for Tyan) - * Copyright (C) 2004 Li-Ta Lo - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/device/software_i2c.c b/src/device/software_i2c.c index 402f1d4131..5dc99906da 100644 --- a/src/device/software_i2c.c +++ b/src/device/software_i2c.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/amd/agesa/def_callouts.c b/src/drivers/amd/agesa/def_callouts.c index fa41500e40..d247e51240 100644 --- a/src/drivers/amd/agesa/def_callouts.c +++ b/src/drivers/amd/agesa/def_callouts.c @@ -160,18 +160,19 @@ AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINTN FchData, VOID *ConfigPrt) AGESA_STATUS agesa_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr) { - AGESA_STATUS Status = AGESA_UNSUPPORTED; -#ifdef __PRE_RAM__ - Status = AmdMemoryReadSPD (Func, Data, ConfigPtr); -#endif - return Status; + if (!ENV_ROMSTAGE) + return AGESA_UNSUPPORTED; + + return AmdMemoryReadSPD (Func, Data, ConfigPtr); } AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) { - AGESA_STATUS Status = AGESA_UNSUPPORTED; -#ifdef __PRE_RAM__ AGESA_READ_SPD_PARAMS *info = ConfigPtr; + + if (!ENV_ROMSTAGE) + return AGESA_UNSUPPORTED; + if (info->MemChannelId > 0) return AGESA_UNSUPPORTED; if (info->SocketId != 0) @@ -183,9 +184,7 @@ AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, 0) < 0) die("No SPD data\n"); - Status = AGESA_SUCCESS; -#endif - return Status; + return AGESA_SUCCESS; } #if HAS_AGESA_FCH_OEM_CALLOUT diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c index fcb353c601..bbb9eb0440 100644 --- a/src/drivers/amd/agesa/mtrr_fixme.c +++ b/src/drivers/amd/agesa/mtrr_fixme.c @@ -11,7 +11,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index adf6e0d0e3..fad49c305c 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include diff --git a/src/drivers/aspeed/ast2050/ast2050.c b/src/drivers/aspeed/ast2050/ast2050.c index 21af5c7c80..59659b8974 100644 --- a/src/drivers/aspeed/ast2050/ast2050.c +++ b/src/drivers/aspeed/ast2050/ast2050.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include "../common/aspeed_coreboot.h" diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index 9e2abb9ed7..99e599d5ea 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -28,6 +28,7 @@ struct drivers_i2c_generic_config { const char *desc; /* Device Description */ unsigned uid; /* ACPI _UID */ enum i2c_speed speed; /* Bus speed in Hz, default is I2C_SPEED_FAST */ + const char *compat_string; /* Compatible string for _HID=PRP0001 */ unsigned wake; /* Wake GPE */ struct acpi_irq irq; /* Interrupt */ diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 598f211ed8..9b4f00daa4 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -116,10 +116,13 @@ void i2c_generic_fill_ssdt(struct device *dev, } /* DSD */ - if (config->probed || config->property_count || + if (config->probed || config->property_count || config->compat_string || (reset_gpio_index != -1) || (enable_gpio_index != -1) || (irq_gpio_index != -1)) { dsd = acpi_dp_new_table("_DSD"); + if (config->compat_string) + acpi_dp_add_string(dsd, "compatible", + config->compat_string); if (config->probed) acpi_dp_add_integer(dsd, "linux,probed", 1); if (irq_gpio_index != -1) diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig index d72d331a96..aea6f1ff12 100644 --- a/src/drivers/intel/fsp1_0/Kconfig +++ b/src/drivers/intel/fsp1_0/Kconfig @@ -16,6 +16,7 @@ config PLATFORM_USES_FSP1_0 bool default n + select CAR_GLOBAL_MIGRATION help Selected for Intel processors/platform combinations that use the Intel Firmware Support Package (FSP) 1.0 for initialization. diff --git a/src/drivers/intel/fsp1_0/fastboot_cache.c b/src/drivers/intel/fsp1_0/fastboot_cache.c index 34761a05be..7eba875e51 100644 --- a/src/drivers/intel/fsp1_0/fastboot_cache.c +++ b/src/drivers/intel/fsp1_0/fastboot_cache.c @@ -116,10 +116,6 @@ static struct mrc_data_container *find_current_mrc_cache_local return mrc_cache; } -/* SPI code needs malloc/free. - * Also unknown if writing flash from XIP-flash code is a good idea - */ -#if !defined(__PRE_RAM__) /* find the first empty block in the MRC cache area. * If there's none, return NULL. * @@ -221,8 +217,6 @@ void update_mrc_cache(void *unused) current->mrc_data_size + sizeof(*current), current); } -#endif /* !defined(__PRE_RAM__) */ - void *find_and_set_fastboot_cache(void) { struct mrc_data_container *mrc_cache = NULL; diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index d787c7beca..a7f3017230 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -25,7 +25,6 @@ #include #include -#ifndef __PRE_RAM__ /* Globals pointers for FSP structures */ void *FspHobListPtr = NULL; FSP_INFO_HEADER *fsp_header_ptr = NULL; @@ -60,9 +59,6 @@ void FspNotify (u32 Phase) if (Status != 0) printk(BIOS_ERR,"FSP API NotifyPhase failed for phase 0x%x with status: 0x%x\n", Phase, Status); } -#endif /* #ifndef __PRE_RAM__ */ - -#ifdef __PRE_RAM__ /* The FSP returns here after the fsp_early_init call */ static void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) @@ -115,12 +111,10 @@ void __noreturn fsp_early_init (FSP_INFO_HEADER *fsp_ptr) /* Should never return. Control will continue from ContinuationFunc */ die("Uh Oh! FspInitApi returned"); } -#endif /* __PRE_RAM__ */ volatile u8 *find_fsp() { - -#ifdef __PRE_RAM__ +#if ENV_ROMSTAGE volatile register u8 *fsp_ptr asm ("eax"); /* Entry point for CAR assembly routine */ @@ -130,7 +124,7 @@ volatile u8 *find_fsp() ); #else volatile u8 *fsp_ptr; -#endif /* __PRE_RAM__ */ +#endif /* The FSP is stored in CBFS */ fsp_ptr = (u8 *) CONFIG_FSP_LOC; @@ -225,8 +219,6 @@ void *find_fsp_reserved_mem(void *hob_list_ptr) } #endif /* FSP_RESERVE_MEMORY_SIZE */ -#ifndef __PRE_RAM__ /* Only parse HOB data in ramstage */ - void print_fsp_info(void) { if (fsp_header_ptr == NULL) @@ -249,12 +241,10 @@ void print_fsp_info(void) { (u8)(fsp_header_ptr->ImageRevision & 0xff)); } - -#if CONFIG(ENABLE_MRC_CACHE) /** * Save the FSP memory HOB (mrc data) to the MRC area in CBMEM */ -int save_mrc_data(void *hob_start) +static int save_mrc_data(void *hob_start) { u32 *mrc_hob; u32 *mrc_hob_data; @@ -307,7 +297,6 @@ int save_mrc_data(void *hob_start) hexdump32(BIOS_SPEW, (void *)mrc_data->mrc_data, output_len / 4); return (1); } -#endif /* CONFIG_ENABLE_MRC_CACHE */ static void find_fsp_hob_update_mrc(void *unused) { @@ -319,13 +308,13 @@ static void find_fsp_hob_update_mrc(void *unused) } else { /* 0x0000: Print all types */ print_hob_type_structure(0x000, FspHobListPtr); + } - #if CONFIG(ENABLE_MRC_CACHE) + if (CONFIG(ENABLE_MRC_CACHE)) { if (save_mrc_data(FspHobListPtr)) update_mrc_cache(NULL); else printk(BIOS_DEBUG,"Not updating MRC data in flash.\n"); - #endif } } @@ -356,11 +345,10 @@ static void fsp_finalize(void *unused) printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseReadyToBoot)\n"); } + /* Set up for the ramstage FSP calls */ BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, fsp_after_pci_enum, NULL); BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, fsp_finalize, NULL); /* Update the MRC/fast boot cache as part of the late table writing stage */ -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - find_fsp_hob_update_mrc, NULL); -#endif /* #ifndef __PRE_RAM__ */ +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, find_fsp_hob_update_mrc, NULL); diff --git a/src/drivers/intel/fsp1_0/fsp_util.h b/src/drivers/intel/fsp1_0/fsp_util.h index e09bbd9b65..a368c7f089 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.h +++ b/src/drivers/intel/fsp1_0/fsp_util.h @@ -21,10 +21,7 @@ #include "fsp_values.h" -#if CONFIG(ENABLE_MRC_CACHE) -int save_mrc_data(void *hob_start); void *find_and_set_fastboot_cache(void); -#endif volatile u8 *find_fsp(void); void fsp_early_init(FSP_INFO_HEADER *fsp_info); @@ -65,7 +62,6 @@ void printguid(EFI_GUID *guid); #define EFI_HOB_TYPE_HANDOFF 0x0001 #define EFI_HOB_TYPE_MEMORY_POOL 0x0007 -#if CONFIG(ENABLE_MRC_CACHE) #define MRC_DATA_ALIGN 0x1000 #define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) @@ -79,11 +75,7 @@ struct mrc_data_container { struct mrc_data_container *find_current_mrc_cache(void); -#if !defined(__PRE_RAM__) void update_mrc_cache(void *unused); -#endif - -#endif /* The offset in bytes from the start of the info structure */ #define FSP_IMAGE_SIG_LOC 0 @@ -99,9 +91,7 @@ void update_mrc_cache(void *unused); #define ERROR_INFO_HEAD_SIG_MISMATCH 5 #define ERROR_FSP_SIG_MISMATCH 6 -#ifndef __PRE_RAM__ extern void *FspHobListPtr; -#endif #define UPD_DEFAULT_CHECK(member) \ if (config->member != UPD_DEFAULT) { \ diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index da9e1888e9..a8658ec7e6 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -18,8 +18,6 @@ config PLATFORM_USES_FSP1_1 bool select UEFI_2_4_BINDING select INTEL_GMA_ADD_VBT if RUN_FSP_GOP - select POSTCAR_STAGE - select POSTCAR_CONSOLE help Does the code require the Intel Firmware Support Package? diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 1b6f62c351..8957c99219 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -13,45 +13,31 @@ * GNU General Public License for more details. */ +#include #include #include #include #include -#include #include #include #include #include #include -/* platform_enter_postcar() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use, - * and continues execution in postcar stage. */ -void platform_enter_postcar(void) +void fill_postcar_frame(struct postcar_frame *pcf) { - struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); - run_postcar_phase(&pcf); } /* This is the romstage entry called from cpu/intel/car/romstage.c */ -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { /* Need to locate the current FSP_INFO_HEADER. The cache-as-ram * is still enabled. We can directly access work buffer here. */ diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 4b567da188..57068cf2e9 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -30,25 +30,6 @@ __weak void soc_after_silicon_init(void) { } -/* Display SMM memory map */ -static void smm_memory_map(void) -{ - uintptr_t base; - size_t size; - int i; - - printk(BIOS_SPEW, "SMM Memory Map\n"); - - smm_region(&base, &size); - printk(BIOS_SPEW, "SMRAM : 0x%zx 0x%zx\n", base, size); - - for (i = 0; i < SMM_SUBREGION_NUM; i++) { - if (smm_subregion(i, &base, &size)) - continue; - printk(BIOS_SPEW, " Subregion %d: 0x%zx 0x%zx\n", i, base, size); - } -} - static void display_hob_info(FSP_INFO_HEADER *fsp_info_header) { const EFI_GUID graphics_info_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID; @@ -147,9 +128,6 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup) static void fsp_cache_save(struct prog *fsp) { - if (CONFIG(DISPLAY_SMM_MEMORY_MAP)) - smm_memory_map(); - if (CONFIG(NO_STAGE_CACHE)) return; diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index d86d3ab484..67bea32eff 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -48,8 +48,7 @@ static void raminit_common(struct romstage_params *params) s3wake = params->power_state->prev_sleep_state == ACPI_S3; - if (CONFIG(ELOG_BOOT_COUNT) && !s3wake) - boot_count_increment(); + elog_boot_notify(s3wake); /* Perform remaining SOC initialization */ soc_pre_ram_init(params); diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 3fb39d5076..1e84dabbbe 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -152,6 +152,15 @@ config FSP_USES_CB_STACK without reinitializing stack pointer. This feature is supported Icelake onwards. +config FSP_TEMP_RAM_SIZE + hex + depends on FSP_USES_CB_STACK + help + The amount of anticipated heap usage in CAR by FSP to setup HOB. + This configuration is applicable for FSP specification using shared + stack with coreboot/bootloader. + Sync this value with Platform FSP integration guide recommendation. + config VERIFY_HOBS bool "Verify the FSP hand-off-blocks" default n diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 95b8020002..3539d18f73 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #define HOB_HEADER_LEN 8 diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index f248a58c77..a075f01879 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -34,6 +34,8 @@ #include #include +static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t)); + /* TPM MRC hash functionality depends on vboot starting before memory init. */ _Static_assert(!CONFIG(FSP2_0_USES_TPM_MRC_HASH) || CONFIG(VBOOT_STARTS_IN_BOOTBLOCK), @@ -161,23 +163,13 @@ static enum cb_err check_region_overlap(const struct memranges *ranges, return CB_SUCCESS; } + static enum cb_err setup_fsp_stack_frame(FSPM_ARCH_UPD *arch_upd, const struct memranges *memmap) { uintptr_t stack_begin; uintptr_t stack_end; - /* - * FSP 2.1 version would use same stack as coreboot instead of - * setting up seprate stack frame. FSP 2.1 would not relocate stack - * top and does not reinitialize stack pointer. - */ - if (CONFIG(FSP_USES_CB_STACK)) { - arch_upd->StackBase = (void *)_car_stack_start; - arch_upd->StackSize = CONFIG_DCACHE_BSP_STACK_SIZE; - return CB_SUCCESS; - } - /* * FSPM_UPD passed here is populated with default values * provided by the blob itself. We let FSPM use top of CAR @@ -197,8 +189,19 @@ static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd, bool s3wake, uint32_t fsp_version, const struct memranges *memmap) { - if (setup_fsp_stack_frame(arch_upd, memmap)) + /* + * FSP 2.1 version would use same stack as coreboot instead of + * setting up separate stack frame. FSP 2.1 would not relocate stack + * top and does not reinitialize stack pointer. The parameters passed + * as StackBase and StackSize are actually for temporary RAM and HOBs + * and are not related to FSP stack at all. + */ + if (CONFIG(FSP_USES_CB_STACK)) { + arch_upd->StackBase = temp_ram; + arch_upd->StackSize = sizeof(temp_ram); + } else if (setup_fsp_stack_frame(arch_upd, memmap)) { return CB_ERR; + } fsp_fill_mrc_cache(arch_upd, fsp_version); @@ -222,7 +225,7 @@ static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd, arch_upd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; } - printk(BIOS_SPEW, "bootmode is set to :%d\n", arch_upd->BootMode); + printk(BIOS_SPEW, "bootmode is set to: %d\n", arch_upd->BootMode); return CB_SUCCESS; } @@ -389,8 +392,7 @@ void fsp_memory_init(bool s3wake) struct memranges memmap; struct range_entry freeranges[2]; - if (CONFIG(ELOG_BOOT_COUNT) && !s3wake) - boot_count_increment(); + elog_boot_notify(s3wake); if (cbfs_boot_locate(&file_desc, name, NULL)) { printk(BIOS_CRIT, "Could not locate %s in CBFS\n", name); @@ -402,7 +404,7 @@ void fsp_memory_init(bool s3wake) /* Build up memory map of romstage address space including CAR. */ memranges_init_empty(&memmap, &freeranges[0], ARRAY_SIZE(freeranges)); memranges_insert(&memmap, (uintptr_t)_car_region_start, - _car_relocatable_data_end - _car_region_start, 0); + _car_unallocated_start - _car_region_start, 0); memranges_insert(&memmap, (uintptr_t)_program, REGION_SIZE(program), 0); if (!CONFIG(FSP_M_XIP)) @@ -416,5 +418,9 @@ void fsp_memory_init(bool s3wake) /* Signal that FSP component has been loaded. */ prog_segment_loaded(hdr.image_base, hdr.image_size, SEG_FINAL); + timestamp_add_now(TS_BEFORE_INITRAM); + do_fsp_memory_init(&hdr, s3wake, &memmap); + + timestamp_add_now(TS_AFTER_INITRAM); } diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index e72e4ac163..ecc6e96ace 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -39,9 +39,17 @@ static void do_silicon_init(struct fsp_header *hdr) die_with_post_code(POST_INVALID_VENDOR_BINARY, "Invalid FSPS signature\n"); - upd = xmalloc(sizeof(FSPS_UPD)); + /* Disallow invalid config regions. Default settings are likely bad + * choices for coreboot, and different sized UPD from what the region + * allows is potentially a build problem. + */ + if (!hdr->cfg_region_size || hdr->cfg_region_size != sizeof(FSPS_UPD)) + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "Invalid FSPS UPD region\n"); - memcpy(upd, supd, sizeof(FSPS_UPD)); + upd = xmalloc(hdr->cfg_region_size); + + memcpy(upd, supd, hdr->cfg_region_size); /* Give SoC/mainboard a chance to populate entries */ platform_fsp_silicon_init_params_cb(upd); diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c index 075e923f84..342fc357fa 100644 --- a/src/drivers/intel/fsp2_0/temp_ram_exit.c +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -9,7 +9,7 @@ * (at your option) any later version. */ -#include +#include #include #include #include diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index 471a5d2331..9e9bd9727c 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -30,10 +30,8 @@ #include #include #include -#include #include #include -#include #include #include #include diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c index bc1b6fa3c3..f506a7c4de 100644 --- a/src/drivers/intel/ish/ish.c +++ b/src/drivers/intel/ish/ish.c @@ -66,6 +66,7 @@ static const struct device_operations pci_ish_device_ops = { static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNL_ISHB, + PCI_DEVICE_ID_INTEL_CML_ISHB, 0 }; diff --git a/src/drivers/ipmi/Kconfig b/src/drivers/ipmi/Kconfig index 5851438714..0f7152d558 100644 --- a/src/drivers/ipmi/Kconfig +++ b/src/drivers/ipmi/Kconfig @@ -1,3 +1,10 @@ config IPMI_KCS bool default n + +config IPMI_KCS_REGISTER_SPACING + int + default 1 + depends on IPMI_KCS + help + KCS status and command register IO port address spacing diff --git a/src/drivers/ipmi/ipmi_kcs.c b/src/drivers/ipmi/ipmi_kcs.c index 397a800df3..4d1e3e105b 100644 --- a/src/drivers/ipmi/ipmi_kcs.c +++ b/src/drivers/ipmi/ipmi_kcs.c @@ -36,9 +36,9 @@ #define IPMI_KCS_STATE_WRITE 0x02 #define IPMI_KCS_STATE_ERROR 0x03 -#define IPMI_CMD(_x) ((_x) + 1) +#define IPMI_CMD(_x) ((_x) + CONFIG_IPMI_KCS_REGISTER_SPACING) #define IPMI_DATA(_x) ((_x)) -#define IPMI_STAT(_x) ((_x) + 1) +#define IPMI_STAT(_x) ((_x) + CONFIG_IPMI_KCS_REGISTER_SPACING) static unsigned char ipmi_kcs_status(int port) { diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 21102bb74e..baa72a82c5 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -128,8 +128,24 @@ ipmi_write_acpi_tables(struct device *dev, unsigned long current, .space_id = ACPI_ADDRESS_SPACE_IO, .access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS, .addrl = dev->path.pnp.port, + .bit_width = 8, }; + switch (CONFIG_IPMI_KCS_REGISTER_SPACING) { + case 4: + addr.bit_offset = 32; + break; + case 16: + addr.bit_offset = 128; + break; + default: + printk(BIOS_ERR, "IPMI: Unsupported register spacing for SPMI\n"); + /* fall through */ + case 1: + addr.bit_offset = 8; + break; + } + current = ALIGN_UP(current, 8); printk(BIOS_DEBUG, "ACPI: * SPMI at %lx\n", current); spmi = (struct acpi_spmi *)current; @@ -183,7 +199,9 @@ static void ipmi_ssdt(struct device *dev) acpigen_write_STA(0xf); acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); - acpigen_write_io16(dev->path.pnp.port, dev->path.pnp.port, 1, 2, 1); + acpigen_write_io16(dev->path.pnp.port, dev->path.pnp.port, 1, 1, 1); + acpigen_write_io16(dev->path.pnp.port + CONFIG_IPMI_KCS_REGISTER_SPACING, + dev->path.pnp.port + CONFIG_IPMI_KCS_REGISTER_SPACING, 1, 1, 1); if (conf) { // FIXME: is that correct? @@ -214,6 +232,8 @@ static int ipmi_smbios_data(struct device *dev, int *handle, struct drivers_ipmi_config *conf = NULL; u8 nv_storage = 0xff; u8 i2c_address = 0; + u8 register_spacing; + int len = 0; if (dev->chip_info) @@ -225,6 +245,21 @@ static int ipmi_smbios_data(struct device *dev, int *handle, i2c_address = conf->bmc_i2c_address; } + switch (CONFIG_IPMI_KCS_REGISTER_SPACING) { + case 4: + register_spacing = 1 << 6; + break; + case 16: + register_spacing = 2 << 6; + break; + default: + printk(BIOS_ERR, "IPMI: Unsupported register spacing for SMBIOS\n"); + /* fall through */ + case 1: + register_spacing = 0 << 6; + break; + } + // add IPMI Device Information len += smbios_write_type38( current, handle, @@ -233,7 +268,7 @@ static int ipmi_smbios_data(struct device *dev, int *handle, i2c_address, // I2C address nv_storage, // NV storage dev->path.pnp.port | 1, // IO interface - 0, + register_spacing, 0); // no IRQ return len; diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index e0869a9337..9ea5414f2d 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -100,7 +100,6 @@ static void cmos_set_checksum(int range_start, int range_end, int cks_loc) #define RTC_CONTROL_DEFAULT (RTC_24H) #define RTC_FREQ_SELECT_DEFAULT (RTC_REF_CLCK_32KHZ | RTC_RATE_1024HZ) -#ifndef __SMM__ static bool __cmos_init(bool invalid) { bool cmos_invalid; @@ -109,16 +108,14 @@ static bool __cmos_init(bool invalid) size_t i; uint8_t x; -#ifndef __PRE_RAM__ /* * Avoid clearing pending interrupts and resetting the RTC control * register in the resume path because the Linux kernel relies on * this to know if it should restart the RTC timer queue if the wake * was due to the RTC alarm. */ - if (acpi_is_wakeup_s3()) + if (ENV_RAMSTAGE && acpi_is_wakeup_s3()) return false; -#endif /* __PRE_RAM__ */ printk(BIOS_DEBUG, "RTC Init\n"); @@ -200,13 +197,14 @@ static void cmos_init_vbnv(bool invalid) void cmos_init(bool invalid) { + if (ENV_SMM) + return; + if (CONFIG(VBOOT_VBNV_CMOS)) cmos_init_vbnv(invalid); else __cmos_init(invalid); } -#endif /* __SMM__ */ - /* * This routine returns the value of the requested bits. diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index cfa500e6dd..5dbe1f4d8e 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -100,6 +100,7 @@ int spi_flash_cmd(const struct spi_slave *spi, u8 cmd, void *response, size_t le #pragma GCC diagnostic push #if defined(__GNUC__) && !defined(__clang__) #pragma GCC diagnostic ignored "-Wstack-usage=" +#pragma GCC diagnostic ignored "-Wvla" #endif int spi_flash_cmd_write(const struct spi_slave *spi, const u8 *cmd, size_t cmd_len, const void *data, size_t data_len) @@ -281,38 +282,38 @@ static struct { } flashes[] = { /* Keep it sorted by define name */ #if CONFIG(SPI_FLASH_AMIC) - { 0, 0x37, spi_flash_probe_amic, }, + { 0, VENDOR_ID_AMIC, spi_flash_probe_amic, }, #endif #if CONFIG(SPI_FLASH_ATMEL) - { 0, 0x1f, spi_flash_probe_atmel, }, + { 0, VENDOR_ID_ATMEL, spi_flash_probe_atmel, }, #endif #if CONFIG(SPI_FLASH_EON) - { 0, 0x1c, spi_flash_probe_eon, }, + { 0, VENDOR_ID_EON, spi_flash_probe_eon, }, #endif #if CONFIG(SPI_FLASH_GIGADEVICE) - { 0, 0xc8, spi_flash_probe_gigadevice, }, + { 0, VENDOR_ID_GIGADEVICE, spi_flash_probe_gigadevice, }, #endif #if CONFIG(SPI_FLASH_MACRONIX) - { 0, 0xc2, spi_flash_probe_macronix, }, + { 0, VENDOR_ID_MACRONIX, spi_flash_probe_macronix, }, #endif #if CONFIG(SPI_FLASH_SPANSION) - { 0, 0x01, spi_flash_probe_spansion, }, + { 0, VENDOR_ID_SPANSION, spi_flash_probe_spansion, }, #endif #if CONFIG(SPI_FLASH_SST) - { 0, 0xbf, spi_flash_probe_sst, }, + { 0, VENDOR_ID_SST, spi_flash_probe_sst, }, #endif #if CONFIG(SPI_FLASH_STMICRO) - { 0, 0x20, spi_flash_probe_stmicro, }, + { 0, VENDOR_ID_STMICRO, spi_flash_probe_stmicro, }, #endif #if CONFIG(SPI_FLASH_WINBOND) - { 0, 0xef, spi_flash_probe_winbond, }, + { 0, VENDOR_ID_WINBOND, spi_flash_probe_winbond, }, #endif /* Keep it sorted by best detection */ #if CONFIG(SPI_FLASH_STMICRO) - { 0, 0xff, spi_flash_probe_stmicro, }, + { 0, VENDOR_ID_STMICRO_FF, spi_flash_probe_stmicro, }, #endif #if CONFIG(SPI_FLASH_ADESTO) - { 0, 0x1f, spi_flash_probe_adesto, }, + { 0, VENDOR_ID_ADESTO, spi_flash_probe_adesto, }, #endif }; #define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN) diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index 4e3af52f89..ad00d7c3bd 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -49,7 +49,6 @@ unsigned char uart_rx_byte(int idx) return read8(®s->dr); } -#ifndef __PRE_RAM__ void uart_fill_lb(void *data) { struct lb_serial serial; @@ -63,4 +62,3 @@ void uart_fill_lb(void *data) lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } -#endif diff --git a/src/drivers/uart/pl011.h b/src/drivers/uart/pl011.h index 9247ef7725..2568dbcb80 100644 --- a/src/drivers/uart/pl011.h +++ b/src/drivers/uart/pl011.h @@ -10,7 +10,7 @@ #ifndef __DRIVERS_UART_PL011_H #define __DRIVERS_UART_PL011_H -#include +#include #include /* PL011 r1p5 registers */ diff --git a/src/drivers/uart/sifive.c b/src/drivers/uart/sifive.c index 1b0f75e3ff..ca8b73b59d 100644 --- a/src/drivers/uart/sifive.c +++ b/src/drivers/uart/sifive.c @@ -113,9 +113,7 @@ unsigned int uart_input_clock_divider(void) return 1; } -#ifndef __PRE_RAM__ void uart_fill_lb(void *data) { /* TODO */ } -#endif diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 638b7c7e58..059679590f 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -67,7 +67,7 @@ static struct ehci_debug_info * glob_dbg_info_p CAR_GLOBAL; static inline struct ehci_debug_info *dbgp_ehci_info(void) { - if (car_get_var(glob_dbg_info_p) == NULL) { + if (car_get_ptr(glob_dbg_info_p) == NULL) { struct ehci_debug_info *info; if (ENV_BOOTBLOCK || ENV_VERSTAGE || ENV_ROMSTAGE) { /* The message likely does not show if we hit this. */ @@ -77,9 +77,9 @@ static inline struct ehci_debug_info *dbgp_ehci_info(void) } else { info = &glob_dbg_info; } - car_set_var(glob_dbg_info_p, info); + car_set_ptr(glob_dbg_info_p, info); } - return car_get_var(glob_dbg_info_p); + return car_get_ptr(glob_dbg_info_p); } static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug) @@ -716,7 +716,7 @@ static void migrate_ehci_debug(int is_recovery) if (dbg_info_cbmem == NULL) return; memcpy(dbg_info_cbmem, dbg_info, sizeof(*dbg_info)); - car_set_var(glob_dbg_info_p, dbg_info_cbmem); + car_set_ptr(glob_dbg_info_p, dbg_info_cbmem); return; } @@ -724,7 +724,7 @@ static void migrate_ehci_debug(int is_recovery) /* Use state in CBMEM. */ dbg_info_cbmem = cbmem_find(CBMEM_ID_EHCI_DEBUG); if (dbg_info_cbmem) - car_set_var(glob_dbg_info_p, dbg_info_cbmem); + car_set_ptr(glob_dbg_info_p, dbg_info_cbmem); } rv = usbdebug_hw_init(false); diff --git a/src/drivers/vpd/Makefile.inc b/src/drivers/vpd/Makefile.inc index 17019b599b..cc276e4968 100644 --- a/src/drivers/vpd/Makefile.inc +++ b/src/drivers/vpd/Makefile.inc @@ -1,2 +1,2 @@ -romstage-$(CONFIG_VPD) += vpd_decode.c -ramstage-$(CONFIG_VPD) += vpd.c vpd_decode.c +romstage-$(CONFIG_VPD) += vpd_decode.c vpd_premem.c vpd.c +ramstage-$(CONFIG_VPD) += vpd_decode.c vpd_cbmem.c vpd.c diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c index c6dd339f61..10f5703e6a 100644 --- a/src/drivers/vpd/vpd.c +++ b/src/drivers/vpd/vpd.c @@ -4,6 +4,8 @@ * found in the LICENSE file. */ +#include +#include #include #include #include @@ -15,13 +17,6 @@ #include "vpd_decode.h" #include "vpd_tables.h" -/* Currently we only support Google VPD 2.0, which has a fixed offset. */ -enum { - GOOGLE_VPD_2_0_OFFSET = 0x600, - CROSVPD_CBMEM_MAGIC = 0x43524f53, - CROSVPD_CBMEM_VERSION = 0x0001, -}; - struct vpd_gets_arg { const uint8_t *key; const uint8_t *value; @@ -29,18 +24,12 @@ struct vpd_gets_arg { int matched; }; -struct vpd_cbmem { - uint32_t magic; - uint32_t version; - uint32_t ro_size; - uint32_t rw_size; - uint8_t blob[0]; - /* The blob contains both RO and RW data. It starts with RO (0 .. - * ro_size) and then RW (ro_size .. ro_size+rw_size). - */ -}; +struct vpd_blob g_vpd_blob CAR_GLOBAL = {0}; -/* returns the size of data in a VPD 2.0 formatted fmap region, or 0 */ +/* + * returns the size of data in a VPD 2.0 formatted fmap region, or 0. + * Also sets *base as the region's base address. + */ static int32_t get_vpd_size(const char *fmap_name, int32_t *base) { struct google_vpd_info info; @@ -86,34 +75,26 @@ static int32_t get_vpd_size(const char *fmap_name, int32_t *base) return size; } -static void cbmem_add_cros_vpd(int is_recovery) +static void vpd_get_blob(void) { + int32_t ro_vpd_base = 0; + int32_t rw_vpd_base = 0; + int32_t ro_vpd_size = get_vpd_size("RO_VPD", &ro_vpd_base); + int32_t rw_vpd_size = get_vpd_size("RW_VPD", &rw_vpd_base); + + /* Return if no VPD at all */ + if (ro_vpd_size == 0 && rw_vpd_size == 0) + return; + + struct vpd_blob *blob = car_get_var_ptr(&g_vpd_blob); + if (!blob) + return; + blob->ro_base = NULL; + blob->ro_size = 0; + blob->rw_base = NULL; + blob->rw_size = 0; + struct region_device vpd; - struct vpd_cbmem *cbmem; - int32_t ro_vpd_base = 0, rw_vpd_base = 0; - int32_t ro_vpd_size, rw_vpd_size; - - timestamp_add_now(TS_START_COPYVPD); - - ro_vpd_size = get_vpd_size("RO_VPD", &ro_vpd_base); - rw_vpd_size = get_vpd_size("RW_VPD", &rw_vpd_base); - - /* no VPD at all? nothing to do then */ - if ((ro_vpd_size == 0) && (rw_vpd_size == 0)) - return; - - cbmem = cbmem_add(CBMEM_ID_VPD, sizeof(*cbmem) + ro_vpd_size + - rw_vpd_size); - if (!cbmem) { - printk(BIOS_ERR, "%s: Failed to allocate CBMEM (%u+%u).\n", - __func__, ro_vpd_size, rw_vpd_size); - return; - } - - cbmem->magic = CROSVPD_CBMEM_MAGIC; - cbmem->version = CROSVPD_CBMEM_VERSION; - cbmem->ro_size = 0; - cbmem->rw_size = 0; if (ro_vpd_size) { if (fmap_locate_area_as_rdev("RO_VPD", &vpd)) { @@ -124,20 +105,10 @@ static void cbmem_add_cros_vpd(int is_recovery) } rdev_chain(&vpd, &vpd, GOOGLE_VPD_2_0_OFFSET, region_device_sz(&vpd) - GOOGLE_VPD_2_0_OFFSET); - - - if (rdev_readat(&vpd, cbmem->blob, ro_vpd_base, ro_vpd_size) == - ro_vpd_size) { - cbmem->ro_size = ro_vpd_size; - } else { - printk(BIOS_ERR, - "%s: Reading RO_VPD FMAP section failed.\n", - __func__); - ro_vpd_size = 0; - } - timestamp_add_now(TS_END_COPYVPD_RO); + blob->ro_base = (uint8_t *)(rdev_mmap_full(&vpd) + + sizeof(struct google_vpd_info)); + blob->ro_size = ro_vpd_size; } - if (rw_vpd_size) { if (fmap_locate_area_as_rdev("RW_VPD", &vpd)) { /* shouldn't happen, but let's be extra defensive */ @@ -147,17 +118,23 @@ static void cbmem_add_cros_vpd(int is_recovery) } rdev_chain(&vpd, &vpd, GOOGLE_VPD_2_0_OFFSET, region_device_sz(&vpd) - GOOGLE_VPD_2_0_OFFSET); - - if (rdev_readat(&vpd, cbmem->blob + ro_vpd_size, rw_vpd_base, - rw_vpd_size) == rw_vpd_size) { - cbmem->rw_size = rw_vpd_size; - } else { - printk(BIOS_ERR, - "%s: Reading RW_VPD FMAP section failed.\n", - __func__); - } - timestamp_add_now(TS_END_COPYVPD_RW); + blob->rw_base = (uint8_t *)(rdev_mmap_full(&vpd) + + sizeof(struct google_vpd_info)); + blob->rw_size = rw_vpd_size; } + blob->initialized = true; +} + +const struct vpd_blob *vpd_load_blob(void) +{ + struct vpd_blob *blob = NULL; + + blob = car_get_var_ptr(&g_vpd_blob); + + if (blob && blob->initialized == false) + vpd_get_blob(); + + return blob; } static int vpd_gets_callback(const uint8_t *key, uint32_t key_len, @@ -179,30 +156,29 @@ static int vpd_gets_callback(const uint8_t *key, uint32_t key_len, const void *vpd_find(const char *key, int *size, enum vpd_region region) { + struct vpd_blob blob = {0}; + + vpd_get_buffers(&blob); + if (blob.ro_size == 0 && blob.rw_size == 0) + return NULL; + struct vpd_gets_arg arg = {0}; uint32_t consumed = 0; - const struct vpd_cbmem *vpd; - - vpd = cbmem_find(CBMEM_ID_VPD); - if (!vpd || !vpd->ro_size) - return NULL; arg.key = (const uint8_t *)key; arg.key_len = strlen(key); - if (region == VPD_ANY || region == VPD_RO) { - while (vpd_decode_string( - vpd->ro_size, vpd->blob, &consumed, - vpd_gets_callback, &arg) == VPD_DECODE_OK) { - /* Iterate until found or no more entries. */ + if ((region == VPD_ANY || region == VPD_RO) && blob.ro_size != 0) { + while (vpd_decode_string(blob.ro_size, blob.ro_base, + &consumed, vpd_gets_callback, &arg) == VPD_DECODE_OK) { + /* Iterate until found or no more entries. */ } } - if (!arg.matched && region != VPD_RO) { - while (vpd_decode_string( - vpd->rw_size, vpd->blob + vpd->ro_size, - &consumed, vpd_gets_callback, - &arg) == VPD_DECODE_OK) { - /* Iterate until found or no more entries. */ + + if ((!arg.matched && region != VPD_RO) && blob.rw_size != 0) { + while (vpd_decode_string(blob.rw_size, blob.rw_base, + &consumed, vpd_gets_callback, &arg) == VPD_DECODE_OK) { + /* Iterate until found or no more entries. */ } } @@ -223,14 +199,40 @@ char *vpd_gets(const char *key, char *buffer, int size, enum vpd_region region) if (!string_address) return NULL; - if (size > (string_size + 1)) { - memcpy(buffer, string_address, string_size); - buffer[string_size] = '\0'; - } else { - memcpy(buffer, string_address, size - 1); - buffer[size - 1] = '\0'; - } + assert(size > 0); + int copy_size = MIN(size - 1, string_size); + memcpy(buffer, string_address, copy_size); + buffer[copy_size] = '\0'; return buffer; } -RAMSTAGE_CBMEM_INIT_HOOK(cbmem_add_cros_vpd) +/* + * Find value of boolean type vpd key. + * + * During the process, necessary checking is done, such as making + * sure the value length is 1, and value is either '1' or '0'. + */ +bool vpd_get_bool(const char *key, enum vpd_region region, uint8_t *val) +{ + int size; + const char *value; + + value = vpd_find(key, &size, region); + if (!value) { + printk(BIOS_CRIT, "problem returning from vpd_find.\n"); + return false; + } + + if (size != 1) + return false; + + /* Make sure the value is either '1' or '0' */ + if (*value == '1') { + *val = 1; + return true; + } else if (*value == '0') { + *val = 0; + return true; + } else + return false; +} diff --git a/src/drivers/vpd/vpd.h b/src/drivers/vpd/vpd.h index 6009b8bc0d..14b002c8f6 100644 --- a/src/drivers/vpd/vpd.h +++ b/src/drivers/vpd/vpd.h @@ -7,11 +7,37 @@ #ifndef __VPD_H__ #define __VPD_H__ +#define GOOGLE_VPD_2_0_OFFSET 0x600 + enum vpd_region { VPD_ANY = 0, VPD_RO = 1, VPD_RW = 2 }; + +/* VPD 2.0 data blob structure */ +struct vpd_blob { + bool initialized; + uint8_t *ro_base; + uint32_t ro_size; + uint8_t *rw_base; + uint32_t rw_size; +}; +extern struct vpd_blob g_vpd_blob; + +/* + * This function loads g_vpd_blob CAR_GLOBAL variable. + * The variable is initialized if it was not. + */ +const struct vpd_blob *vpd_load_blob(void); + +/* + * This function gets the base address and size of + * buffers for RO_VPD/RW_VPD binary blobs, and sets + * the struct. + */ +void vpd_get_buffers(struct vpd_blob *blob); + /* * Reads VPD string value by key. * @@ -39,4 +65,13 @@ char *vpd_gets(const char *key, char *buffer, int size, enum vpd_region region); const void *vpd_find(const char *key, int *size, enum vpd_region region); +/* + * Find value of boolean type vpd key. + * + * During the process, necessary checking is done, such as making + * sure the value length is 1, and value is either '1' or '0'. + */ +bool vpd_get_bool(const char *key, enum vpd_region region, + uint8_t *val); + #endif /* __VPD_H__ */ diff --git a/src/drivers/vpd/vpd_cbmem.c b/src/drivers/vpd/vpd_cbmem.c new file mode 100644 index 0000000000..5b685069aa --- /dev/null +++ b/src/drivers/vpd/vpd_cbmem.c @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include +#include +#include +#include +#include +#include + +#include "vpd_tables.h" +#include "vpd.h" + +/* Currently we only support Google VPD 2.0, which has a fixed offset. */ +enum { + CROSVPD_CBMEM_MAGIC = 0x43524f53, + CROSVPD_CBMEM_VERSION = 0x0001, +}; + +struct vpd_cbmem { + uint32_t magic; + uint32_t version; + uint32_t ro_size; + uint32_t rw_size; + uint8_t blob[0]; + /* The blob contains both RO and RW data. It starts with RO (0 .. + * ro_size) and then RW (ro_size .. ro_size+rw_size). + */ +}; + +static void cbmem_add_cros_vpd(int is_recovery) +{ + struct vpd_cbmem *cbmem; + const struct vpd_blob *blob; + + timestamp_add_now(TS_START_COPYVPD); + + blob = vpd_load_blob(); + + /* Return if no VPD at all */ + if (blob->ro_size == 0 && blob->rw_size == 0) + return; + + cbmem = cbmem_add(CBMEM_ID_VPD, sizeof(*cbmem) + blob->ro_size + + blob->rw_size); + if (!cbmem) { + printk(BIOS_ERR, "%s: Failed to allocate CBMEM (%u+%u).\n", + __func__, blob->ro_size, blob->rw_size); + return; + } + + cbmem->magic = CROSVPD_CBMEM_MAGIC; + cbmem->version = CROSVPD_CBMEM_VERSION; + cbmem->ro_size = blob->ro_size; + cbmem->rw_size = blob->rw_size; + + if (blob->ro_size) { + memcpy(cbmem->blob, blob->ro_base, blob->ro_size); + timestamp_add_now(TS_END_COPYVPD_RO); + } + + if (blob->rw_size) { + memcpy(cbmem->blob + blob->ro_size, blob->rw_base, + blob->rw_size); + timestamp_add_now(TS_END_COPYVPD_RW); + } +} + +void vpd_get_buffers(struct vpd_blob *blob) +{ + const struct vpd_cbmem *vpd; + + vpd = cbmem_find(CBMEM_ID_VPD); + if (!vpd || !vpd->ro_size) + return; + + blob->ro_base = (void *)vpd->blob; + blob->ro_size = vpd->ro_size; + blob->rw_base = (void *)vpd->blob + vpd->ro_size; + blob->rw_size = vpd->rw_size; +} + +RAMSTAGE_CBMEM_INIT_HOOK(cbmem_add_cros_vpd) diff --git a/src/soc/rockchip/rk3399/include/soc/bl31_plat_params.h b/src/drivers/vpd/vpd_premem.c similarity index 66% rename from src/soc/rockchip/rk3399/include/soc/bl31_plat_params.h rename to src/drivers/vpd/vpd_premem.c index c73d68753a..14e803281a 100644 --- a/src/soc/rockchip/rk3399/include/soc/bl31_plat_params.h +++ b/src/drivers/vpd/vpd_premem.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. + * Copyright (c) 2019 Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -11,14 +11,17 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * */ -#ifndef __BL31_PLAT_PARAMS_H__ -#define __BL31_PLAT_PARAMS_H__ +#include +#include -#include +#include "vpd.h" -void register_bl31_param(struct bl31_plat_param *param); +void vpd_get_buffers(struct vpd_blob *blob) +{ + const struct vpd_blob *b; -#endif/* __BL31_PLAT_PARAMS_H__ */ + b = vpd_load_blob(); + memcpy(blob, b, sizeof(*b)); +} diff --git a/src/drivers/vpd/vpd_tables.h b/src/drivers/vpd/vpd_tables.h index 0bd215a5a6..4add5bd49d 100644 --- a/src/drivers/vpd/vpd_tables.h +++ b/src/drivers/vpd/vpd_tables.h @@ -9,7 +9,7 @@ #ifndef __LIB_VPD_TABLES_H__ #define __LIB_VPD_TABLES_H__ -#include +#include #define VPD_ENTRY_MAGIC "_SM_" #define VPD_INFO_MAGIC \ diff --git a/src/drivers/wifi/generic.c b/src/drivers/wifi/generic.c index b593ffe8bc..fc88f4a629 100644 --- a/src/drivers/wifi/generic.c +++ b/src/drivers/wifi/generic.c @@ -239,7 +239,8 @@ const char *generic_wifi_acpi_name(const struct device *dev) { static char wifi_acpi_name[WIFI_ACPI_NAME_MAX_LEN]; - snprintf(wifi_acpi_name, sizeof(wifi_acpi_name), "WF%02x", + /* ACPI 6.3, ASL 20.2.2: (Name Objects Encoding). */ + snprintf(wifi_acpi_name, sizeof(wifi_acpi_name), "WF%02X", (dev_path_encode(dev) & 0xff)); return wifi_acpi_name; } diff --git a/src/ec/acpi/ec.c b/src/ec/acpi/ec.c index 61cad656eb..939ff781fa 100644 --- a/src/ec/acpi/ec.c +++ b/src/ec/acpi/ec.c @@ -18,19 +18,11 @@ #include #include #include +#include #include "ec.h" -#ifdef __PRE_RAM__ - -static const int ec_cmd_reg = EC_SC; -static const int ec_data_reg = EC_DATA; - -#else - -static int ec_cmd_reg = EC_SC; -static int ec_data_reg = EC_DATA; - -#endif +static u16 ec_cmd_reg = EC_SC; +static u16 ec_data_reg = EC_DATA; int send_ec_command(u8 command) { @@ -162,18 +154,15 @@ void ec_clr_bit(u8 addr, u8 bit) ec_write(addr, ec_read(addr) & ~(1 << bit)); } -#ifndef __PRE_RAM__ - void ec_set_ports(u16 cmd_reg, u16 data_reg) { + if (!ENV_STAGE_HAS_DATA_SECTION) + return; + ec_cmd_reg = cmd_reg; ec_data_reg = data_reg; } -#endif - -#if !defined(__SMM__) && !defined(__PRE_RAM__) struct chip_operations ec_acpi_ops = { CHIP_NAME("ACPI Embedded Controller") }; -#endif diff --git a/src/ec/compal/ene932/chip.h b/src/ec/compal/ene932/chip.h index c7e4f8d9be..94f975282b 100644 --- a/src/ec/compal/ene932/chip.h +++ b/src/ec/compal/ene932/chip.h @@ -17,11 +17,6 @@ #ifndef _EC_COMPAL_ENE932_CHIP_H #define _EC_COMPAL_ENE932_CHIP_H -#include - -struct chip_operations; -extern struct chip_operations ec_compal_ene932_ops; - struct ec_compal_ene932_config { }; diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c index cfabd8d12a..5bade10ea9 100644 --- a/src/ec/compal/ene932/ec.c +++ b/src/ec/compal/ene932/ec.c @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -#ifndef __PRE_RAM__ - #include #include #include @@ -125,7 +123,6 @@ static u8 ec_io_read(u16 addr) } */ -#ifndef __SMM__ static void ene932_init(struct device *dev) { if (!dev->enabled) @@ -155,5 +152,3 @@ struct chip_operations ec_compal_ene932_ops = { CHIP_NAME("COMPAL ENE932 EC") .enable_dev = enable_dev }; -#endif /* ! __SMM__ */ -#endif /* ! __PRE_RAM__ */ diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 3eb2c4807c..2242653ccc 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -47,6 +47,17 @@ config EC_GOOGLE_CHROMEEC_I2C_PROTO3 help Use only proto3 for i2c EC communication. +config EC_GOOGLE_CHROMEEC_ESPI + depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play. + def_bool n + select EC_GOOGLE_CHROMEEC_LPC + help + Google Chrome EC via eSPI bus. + + The EC communication code is the same between eSPI and LPC, so + this option simply enables the LPC EC code. The eSPI device + still needs to correctly configure the bus transactions. + config EC_GOOGLE_CHROMEEC_LPC depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play. def_bool y diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 4593c735d5..f2e0034bc2 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -63,6 +63,8 @@ CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME := $(call strip_quotes,$(CONFIG_EC_GOOGLE_CH $(obj)/mainboard/$(MAINBOARDDIR)/ecrw: $(MAKE) -C $(CHROMEEC_SOURCE) $(if $(CONFIG_CCACHE),,CCACHE=) \ out=$(abspath $(obj)/external/chromeec/$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME)) \ + REPRODUCIBLE_BUILD=1 \ + CC=$(GCC_CC_arm) \ CROSS_COMPILE=$(subst -cpp,-,$(CPP_arm)) \ HOST_CROSS_COMPILE= \ BOARD=$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME) \ @@ -100,6 +102,8 @@ CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME := $(call strip_quotes,$(CONFIG_EC_GOOGLE $(obj)/mainboard/$(MAINBOARDDIR)/pdrw: $(MAKE) -C $(CHROMEEC_SOURCE) $(if $(CONFIG_CCACHE),,CCACHE=) \ out=$(abspath $(obj)/external/chromeec/$(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME)) \ + REPRODUCIBLE_BUILD=1 \ + CC=$(GCC_CC_arm) \ CROSS_COMPILE=$(subst -cpp,-,$(CPP_arm)) \ HOST_CROSS_COMPILE= \ BOARD=$(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME) \ diff --git a/src/ec/google/chromeec/chip.h b/src/ec/google/chromeec/chip.h index 4eada16b0d..1c9a7f59e7 100644 --- a/src/ec/google/chromeec/chip.h +++ b/src/ec/google/chromeec/chip.h @@ -16,9 +16,6 @@ #ifndef EC_GOOGLE_CHROMEEC_CHIP_H #define EC_GOOGLE_CHROMEEC_CHIP_H -#include - -extern struct chip_operations ec_google_chromeec_ops; struct ec_google_chromeec_config { }; diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 5a2630ecb0..1b0f7eee03 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -428,30 +428,19 @@ static void google_chromeec_log_device_events(uint64_t mask) void google_chromeec_log_events(uint64_t mask) { - u8 event; - uint64_t wake_mask; - bool restore_wake_mask = false; + uint64_t events; + int i; if (!CONFIG(ELOG)) return; - /* - * If the EC supports unified wake masks, then there is no need to set - * wake mask before reading out the host events. - */ - if (google_chromeec_check_feature(EC_FEATURE_UNIFIED_WAKE_MASKS) != 1) { - wake_mask = google_chromeec_get_wake_mask(); - google_chromeec_set_wake_mask(mask); - restore_wake_mask = true; + events = google_chromeec_get_events_b() & mask; + for (i = 0; i < sizeof(events) * 8; i++) { + if (EC_HOST_EVENT_MASK(i) & events) + elog_add_event_byte(ELOG_TYPE_EC_EVENT, i); } - while ((event = google_chromeec_get_event()) != 0) { - if (EC_HOST_EVENT_MASK(event) & mask) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, event); - } - - if (restore_wake_mask) - google_chromeec_set_wake_mask(wake_mask); + google_chromeec_clear_events_b(events); } void google_chromeec_events_init(const struct google_chromeec_event_info *info, @@ -467,10 +456,6 @@ void google_chromeec_events_init(const struct google_chromeec_event_info *info, /* Disable SMI and wake events. */ google_chromeec_set_smi_mask(0); - /* Clear pending events. */ - while (google_chromeec_get_event() != 0) - ; - /* Restore SCI event mask. */ google_chromeec_set_sci_mask(info->sci_events); @@ -719,7 +704,28 @@ retry: return cec_cmd.cmd_code; } -#ifndef __PRE_RAM__ +static uint16_t google_chromeec_get_uptime_info( + struct ec_response_uptime_info *rsp) +{ + struct chromeec_command cmd = { + .cmd_code = EC_CMD_GET_UPTIME_INFO, + .cmd_version = 0, + .cmd_data_in = NULL, + .cmd_size_in = 0, + .cmd_data_out = rsp, + .cmd_size_out = sizeof(*rsp), + .cmd_dev_index = 0, + }; + google_chromeec_command(&cmd); + return cmd.cmd_code; +} + +bool google_chromeec_get_ap_watchdog_flag(void) +{ + struct ec_response_uptime_info rsp; + return (!google_chromeec_get_uptime_info(&rsp) && + (rsp.ec_reset_flags & EC_RESET_FLAG_AP_WATCHDOG)); +} int google_chromeec_i2c_xfer(uint8_t chip, uint8_t addr, int alen, uint8_t *buffer, int len, int is_read) @@ -961,6 +967,7 @@ static const char *reset_cause_to_str(uint16_t cause) "reset: debug warm reboot", "reset: at AP's request", "reset: during EC initialization", + "reset: AP watchdog", }; static const size_t shutdown_cause_begin = 1 << 15; @@ -995,7 +1002,7 @@ static const char *reset_cause_to_str(uint16_t cause) */ static void google_chromeec_log_uptimeinfo(void) { - /* See also ChromiumOS EC include/system.h RESET_FLAG for details. */ + /* See also ec_commands.h EC_RESET_FLAG_* for details. */ static const char * const reset_flag_strings[] = { "other", "reset-pin", @@ -1014,22 +1021,13 @@ static void google_chromeec_log_uptimeinfo(void) "usb-resume", "rdd", "rbox", - "security" + "security", + "ap-watchdog", }; struct ec_response_uptime_info cmd_resp; int i, flag, flag_count; - struct chromeec_command get_uptime_cmd = { - .cmd_code = EC_CMD_GET_UPTIME_INFO, - .cmd_version = 0, - .cmd_data_in = NULL, - .cmd_size_in = 0, - .cmd_data_out = &cmd_resp, - .cmd_size_out = sizeof(cmd_resp), - .cmd_dev_index = 0, - }; - google_chromeec_command(&get_uptime_cmd); - if (get_uptime_cmd.cmd_code) { + if (google_chromeec_get_uptime_info(&cmd_resp)) { /* * Deliberately say nothing for EC's that don't support this * command @@ -1109,8 +1107,6 @@ int google_ec_running_ro(void) return (ec_image_type == EC_IMAGE_RO); } -#endif /* ! __PRE_RAM__ */ - /** * Check if EC/TCPM is in an alternate mode or not. * diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 7a383364a2..019f9c1eb0 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -64,6 +64,7 @@ int google_chromeec_kbbacklight(int percent); void google_chromeec_post(u8 postcode); int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len); uint8_t google_chromeec_get_switches(void); +bool google_chromeec_get_ap_watchdog_flag(void); /* Temporary secure storage commands */ int google_chromeec_vstore_supported(void); @@ -94,13 +95,6 @@ int google_chromeec_cbi_get_oem_name(char *buf, size_t bufsize); #define MEC_EMI_RANGE_START EC_HOST_CMD_REGION0 #define MEC_EMI_RANGE_END (EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SIZE) -enum usb_charge_mode { - USB_CHARGE_MODE_DISABLED, - USB_CHARGE_MODE_CHARGE_AUTO, - USB_CHARGE_MODE_CHARGE_BC12, - USB_CHARGE_MODE_DOWNSTREAM_500MA, - USB_CHARGE_MODE_DOWNSTREAM_1500MA, -}; int google_chromeec_set_usb_charge_mode(u8 port_id, enum usb_charge_mode mode); int google_chromeec_set_usb_pd_role(u8 port, enum usb_pd_control_role role); /* diff --git a/src/ec/google/chromeec/ec_boardid.c b/src/ec/google/chromeec/ec_boardid.c index 01e3c90e3a..1307ce17b6 100644 --- a/src/ec/google/chromeec/ec_boardid.c +++ b/src/ec/google/chromeec/ec_boardid.c @@ -18,7 +18,7 @@ uint32_t board_id(void) { - MAYBE_STATIC uint32_t id = BOARD_ID_INIT; + MAYBE_STATIC_NONZERO uint32_t id = BOARD_ID_INIT; if (id == BOARD_ID_INIT) { if (google_chromeec_get_board_version(&id)) diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 140ba5a19a..acee2f58e6 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -35,15 +35,38 @@ #include #endif +#ifdef __cplusplus +extern "C" { +#endif + +/* + * CHROMIUM_EC is defined by the Makefile system of Chromium EC repository. + * It is used to not include macros that may cause conflicts in foreign + * projects (refer to crbug.com/984623). + */ +#ifdef CHROMIUM_EC /* * Include common.h for CONFIG_HOSTCMD_ALIGNED, if it's defined. This * generates more efficient code for accessing request/response structures on * ARM Cortex-M if the structures are guaranteed 32-bit aligned. */ -#ifdef CHROMIUM_EC #include "common.h" +#include "compile_time_macros.h" + +#else + +#define BUILD_ASSERT(_cond) + +#ifndef BIT +#define BIT(nr) (1UL << (nr)) #endif +#ifndef BIT_ULL +#define BIT_ULL(nr) (1ULL << (nr)) +#endif + +#endif /* CHROMIUM_EC */ + /* * Current version of this protocol * @@ -54,7 +77,7 @@ #define EC_PROTO_VERSION 0x00000002 /* Command version mask */ -#define EC_VER_MASK(version) (1UL << (version)) +#define EC_VER_MASK(version) BIT(version) /* I/O addresses for ACPI commands */ #define EC_LPC_ADDR_ACPI_DATA 0x62 @@ -68,25 +91,28 @@ /* Protocol version 2 */ #define EC_LPC_ADDR_HOST_ARGS 0x800 /* And 0x801, 0x802, 0x803 */ #define EC_LPC_ADDR_HOST_PARAM 0x804 /* For version 2 params; size is - * EC_PROTO2_MAX_PARAM_SIZE */ + * EC_PROTO2_MAX_PARAM_SIZE + */ /* Protocol version 3 */ #define EC_LPC_ADDR_HOST_PACKET 0x800 /* Offset of version 3 packet */ #define EC_LPC_HOST_PACKET_SIZE 0x100 /* Max size of version 3 packet */ -/* The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff - * and they tell the kernel that so we have to think of it as two parts. */ +/* + * The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff + * and they tell the kernel that so we have to think of it as two parts. + */ #define EC_HOST_CMD_REGION0 0x800 #define EC_HOST_CMD_REGION1 0x880 #define EC_HOST_CMD_REGION_SIZE 0x80 /* EC command register bit functions */ -#define EC_LPC_CMDR_DATA (1 << 0) /* Data ready for host to read */ -#define EC_LPC_CMDR_PENDING (1 << 1) /* Write pending to EC */ -#define EC_LPC_CMDR_BUSY (1 << 2) /* EC is busy processing a command */ -#define EC_LPC_CMDR_CMD (1 << 3) /* Last host write was a command */ -#define EC_LPC_CMDR_ACPI_BRST (1 << 4) /* Burst mode (not used) */ -#define EC_LPC_CMDR_SCI (1 << 5) /* SCI event is pending */ -#define EC_LPC_CMDR_SMI (1 << 6) /* SMI event is pending */ +#define EC_LPC_CMDR_DATA BIT(0) /* Data ready for host to read */ +#define EC_LPC_CMDR_PENDING BIT(1) /* Write pending to EC */ +#define EC_LPC_CMDR_BUSY BIT(2) /* EC is busy processing a command */ +#define EC_LPC_CMDR_CMD BIT(3) /* Last host write was a command */ +#define EC_LPC_CMDR_ACPI_BRST BIT(4) /* Burst mode (not used) */ +#define EC_LPC_CMDR_SCI BIT(5) /* SCI event is pending */ +#define EC_LPC_CMDR_SMI BIT(6) /* SMI event is pending */ #define EC_LPC_ADDR_MEMMAP 0x900 #define EC_MEMMAP_SIZE 255 /* ACPI IO buffer max is 255 bytes */ @@ -144,8 +170,8 @@ /* Define the format of the accelerometer mapped memory status byte. */ #define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK 0x0f -#define EC_MEMMAP_ACC_STATUS_BUSY_BIT (1 << 4) -#define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT (1 << 7) +#define EC_MEMMAP_ACC_STATUS_BUSY_BIT BIT(4) +#define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT BIT(7) /* Number of temp sensors at EC_MEMMAP_TEMP_SENSOR */ #define EC_TEMP_SENSOR_ENTRIES 16 @@ -320,8 +346,8 @@ * bit 1 enables/disables the selected threshold (0 = off, 1 = on) * Each write to the commit register affects one threshold. */ -#define EC_ACPI_MEM_TEMP_COMMIT_SELECT_MASK (1 << 0) -#define EC_ACPI_MEM_TEMP_COMMIT_ENABLE_MASK (1 << 1) +#define EC_ACPI_MEM_TEMP_COMMIT_SELECT_MASK BIT(0) +#define EC_ACPI_MEM_TEMP_COMMIT_ENABLE_MASK BIT(1) /* * Example: * @@ -347,10 +373,19 @@ /* * Report device orientation - * bit 0 device is tablet mode + * Bits Definition + * 3:1 Device DPTF Profile Number (DDPN) + * 0 = Reserved for backward compatibility (indicates no valid + * profile number. Host should fall back to using TBMD). + * 1..7 = DPTF Profile number to indicate to host which table needs + * to be loaded. + * 0 Tablet Mode Device Indicator (TBMD) */ #define EC_ACPI_MEM_DEVICE_ORIENTATION 0x09 -#define EC_ACPI_MEM_DEVICE_TABLET_MODE 0x01 +#define EC_ACPI_MEM_TBMD_SHIFT 0 +#define EC_ACPI_MEM_TBMD_MASK 0x1 +#define EC_ACPI_MEM_DDPN_SHIFT 1 +#define EC_ACPI_MEM_DDPN_MASK 0x7 /* * Report device features. Uses the same format as the host command, except: @@ -402,6 +437,7 @@ */ #ifndef __ACPI__ +#ifndef __KERNEL__ /* * Define __packed if someone hasn't beat us to it. Linux kernel style * checking prefers __packed over __attribute__((packed)). @@ -413,6 +449,7 @@ #ifndef __aligned #define __aligned(x) __attribute__((aligned(x))) #endif +#endif /* __KERNEL__ */ /* * Attributes for EC request and response packets. Just defining __packed @@ -521,7 +558,8 @@ #define EC_LPC_STATUS_BUSY_MASK \ (EC_LPC_STATUS_FROM_HOST | EC_LPC_STATUS_PROCESSING) -/* Host command response codes (16-bit). Note that response codes should be +/* + * Host command response codes (16-bit). Note that response codes should be * stored in a uint16_t rather than directly in a value of this type. */ enum ec_status { @@ -615,7 +653,12 @@ enum host_event_code { /* EC desires to change state of host-controlled USB mux */ EC_HOST_EVENT_USB_MUX = 28, - /* TABLET/LAPTOP mode event*/ + /* + * The device has changed "modes". This can be one of the following: + * + * - TABLET/LAPTOP mode + * - detachable base attach/detach event + */ EC_HOST_EVENT_MODE_CHANGE = 29, /* Keyboard recovery combo with hardware reinitialization */ @@ -631,19 +674,22 @@ enum host_event_code { EC_HOST_EVENT_INVALID = 32 }; /* Host event mask */ -#define EC_HOST_EVENT_MASK(event_code) (1ULL << ((event_code) - 1)) +#define EC_HOST_EVENT_MASK(event_code) BIT_ULL((event_code) - 1) -/* Arguments at EC_LPC_ADDR_HOST_ARGS */ -struct __ec_align4 ec_lpc_host_args { +/** + * struct ec_lpc_host_args - Arguments at EC_LPC_ADDR_HOST_ARGS + * @flags: The host argument flags. + * @command_version: Command version. + * @data_size: The length of data. + * @checksum: Checksum; sum of command + flags + command_version + data_size + + * all params/response data bytes. + */ +struct ec_lpc_host_args { uint8_t flags; uint8_t command_version; uint8_t data_size; - /* - * Checksum; sum of command + flags + command_version + data_size + - * all params/response data bytes. - */ uint8_t checksum; -}; +} __ec_align4; /* Flags for ec_lpc_host_args.flags */ /* @@ -795,56 +841,45 @@ struct __ec_align4 ec_lpc_host_args { #define EC_HOST_REQUEST_VERSION 3 -/* Version 3 request from host */ -struct __ec_align4 ec_host_request { - /* Structure version (=3) - * - * EC will return EC_RES_INVALID_HEADER if it receives a header with a - * version it doesn't know how to parse. - */ +/** + * struct ec_host_request - Version 3 request from host. + * @struct_version: Should be 3. The EC will return EC_RES_INVALID_HEADER if it + * receives a header with a version it doesn't know how to + * parse. + * @checksum: Checksum of request and data; sum of all bytes including checksum + * should total to 0. + * @command: Command to send (EC_CMD_...) + * @command_version: Command version. + * @reserved: Unused byte in current protocol version; set to 0. + * @data_len: Length of data which follows this header. + */ +struct ec_host_request { uint8_t struct_version; - - /* - * Checksum of request and data; sum of all bytes including checksum - * should total to 0. - */ uint8_t checksum; - - /* Command code */ uint16_t command; - - /* Command version */ uint8_t command_version; - - /* Unused byte in current protocol version; set to 0 */ uint8_t reserved; - - /* Length of data which follows this header */ uint16_t data_len; -}; +} __ec_align4; #define EC_HOST_RESPONSE_VERSION 3 -/* Version 3 response from EC */ -struct __ec_align4 ec_host_response { - /* Structure version (=3) */ +/** + * struct ec_host_response - Version 3 response from EC. + * @struct_version: Struct version (=3). + * @checksum: Checksum of response and data; sum of all bytes including + * checksum should total to 0. + * @result: EC's response to the command (separate from communication failure) + * @data_len: Length of data which follows this header. + * @reserved: Unused bytes in current protocol version; set to 0. + */ +struct ec_host_response { uint8_t struct_version; - - /* - * Checksum of response and data; sum of all bytes including checksum - * should total to 0. - */ uint8_t checksum; - - /* Result code (EC_RES_*) */ uint16_t result; - - /* Length of data which follows this header */ uint16_t data_len; - - /* Unused bytes in current protocol version; set to 0 */ uint16_t reserved; -}; +} __ec_align4; /*****************************************************************************/ @@ -907,7 +942,7 @@ struct __ec_align4 ec_host_response { */ /* Version 4 request from host */ -struct __ec_align4 ec_host_request4 { +struct ec_host_request4 { /* * bits 0-3: struct_version: Structure version (=4) * bit 4: is_response: Is response (=0) @@ -934,10 +969,10 @@ struct __ec_align4 ec_host_request4 { /* CRC-8 of above fields, using x^8 + x^2 + x + 1 polynomial */ uint8_t header_crc; -}; +} __ec_align4; /* Version 4 response from EC */ -struct __ec_align4 ec_host_response4 { +struct ec_host_response4 { /* * bits 0-3: struct_version: Structure version (=4) * bit 4: is_response: Is response (=1) @@ -963,7 +998,7 @@ struct __ec_align4 ec_host_response4 { /* CRC-8 of above fields, using x^8 + x^2 + x + 1 polynomial */ uint8_t header_crc; -}; +} __ec_align4; /* Fields in fields0 byte */ #define EC_PACKET4_0_STRUCT_VERSION_MASK 0x0f @@ -1000,9 +1035,13 @@ struct __ec_align4 ec_host_response4 { */ #define EC_CMD_PROTO_VERSION 0x0000 -struct __ec_align4 ec_response_proto_version { +/** + * struct ec_response_proto_version - Response to the proto version command. + * @version: The protocol version. + */ +struct ec_response_proto_version { uint32_t version; -}; +} __ec_align4; /* * Hello. This is a simple command to test the EC is responsive to @@ -1010,13 +1049,21 @@ struct __ec_align4 ec_response_proto_version { */ #define EC_CMD_HELLO 0x0001 -struct __ec_align4 ec_params_hello { - uint32_t in_data; /* Pass anything here */ -}; +/** + * struct ec_params_hello - Parameters to the hello command. + * @in_data: Pass anything here. + */ +struct ec_params_hello { + uint32_t in_data; +} __ec_align4; -struct __ec_align4 ec_response_hello { - uint32_t out_data; /* Output will be in_data + 0x01020304 */ -}; +/** + * struct ec_response_hello - Response to the hello command. + * @out_data: Output will be in_data + 0x01020304. + */ +struct ec_response_hello { + uint32_t out_data; +} __ec_align4; /* Get version number */ #define EC_CMD_GET_VERSION 0x0002 @@ -1027,25 +1074,40 @@ enum ec_current_image { EC_IMAGE_RW }; -struct __ec_align4 ec_response_get_version { - /* Null-terminated version strings for RO, RW */ +/** + * struct ec_response_get_version - Response to the get version command. + * @version_string_ro: Null-terminated RO firmware version string. + * @version_string_rw: Null-terminated RW firmware version string. + * @reserved: Unused bytes; was previously RW-B firmware version string. + * @current_image: One of ec_current_image. + */ +struct ec_response_get_version { char version_string_ro[32]; char version_string_rw[32]; - char reserved[32]; /* Was previously RW-B string */ - uint32_t current_image; /* One of ec_current_image */ -}; + char reserved[32]; + uint32_t current_image; +} __ec_align4; /* Read test */ #define EC_CMD_READ_TEST 0x0003 -struct __ec_align4 ec_params_read_test { - uint32_t offset; /* Starting value for read buffer */ - uint32_t size; /* Size to read in bytes */ -}; +/** + * struct ec_params_read_test - Parameters for the read test command. + * @offset: Starting value for read buffer. + * @size: Size to read in bytes. + */ +struct ec_params_read_test { + uint32_t offset; + uint32_t size; +} __ec_align4; -struct __ec_align4 ec_response_read_test { +/** + * struct ec_response_read_test - Response to the read test command. + * @data: Data returned by the read test command. + */ +struct ec_response_read_test { uint32_t data[32]; -}; +} __ec_align4; /* * Get build information @@ -1057,19 +1119,28 @@ struct __ec_align4 ec_response_read_test { /* Get chip info */ #define EC_CMD_GET_CHIP_INFO 0x0005 -struct __ec_align4 ec_response_get_chip_info { - /* Null-terminated strings */ +/** + * struct ec_response_get_chip_info - Response to the get chip info command. + * @vendor: Null-terminated string for chip vendor. + * @name: Null-terminated string for chip name. + * @revision: Null-terminated string for chip mask version. + */ +struct ec_response_get_chip_info { char vendor[32]; char name[32]; - char revision[32]; /* Mask version */ -}; + char revision[32]; +} __ec_align4; /* Get board HW version */ #define EC_CMD_GET_BOARD_VERSION 0x0006 -struct __ec_align2 ec_response_board_version { - uint16_t board_version; /* A monotonously incrementing number. */ -}; +/** + * struct ec_response_board_version - Response to the board version command. + * @board_version: A monotonously incrementing number. + */ +struct ec_response_board_version { + uint16_t board_version; +} __ec_align2; /* * Read memory-mapped data. @@ -1081,29 +1152,44 @@ struct __ec_align2 ec_response_board_version { */ #define EC_CMD_READ_MEMMAP 0x0007 -struct __ec_align1 ec_params_read_memmap { - uint8_t offset; /* Offset in memmap (EC_MEMMAP_*) */ - uint8_t size; /* Size to read in bytes */ -}; +/** + * struct ec_params_read_memmap - Parameters for the read memory map command. + * @offset: Offset in memmap (EC_MEMMAP_*). + * @size: Size to read in bytes. + */ +struct ec_params_read_memmap { + uint8_t offset; + uint8_t size; +} __ec_align1; /* Read versions supported for a command */ #define EC_CMD_GET_CMD_VERSIONS 0x0008 -struct __ec_align1 ec_params_get_cmd_versions { - uint8_t cmd; /* Command to check */ -}; +/** + * struct ec_params_get_cmd_versions - Parameters for the get command versions. + * @cmd: Command to check. + */ +struct ec_params_get_cmd_versions { + uint8_t cmd; +} __ec_align1; -struct __ec_align2 ec_params_get_cmd_versions_v1 { - uint16_t cmd; /* Command to check */ -}; +/** + * struct ec_params_get_cmd_versions_v1 - Parameters for the get command + * versions (v1) + * @cmd: Command to check. + */ +struct ec_params_get_cmd_versions_v1 { + uint16_t cmd; +} __ec_align2; -struct __ec_align4 ec_response_get_cmd_versions { - /* - * Mask of supported versions; use EC_VER_MASK() to compare with a - * desired version. - */ +/** + * struct ec_response_get_cmd_version - Response to the get command versions. + * @version_mask: Mask of supported versions; use EC_VER_MASK() to compare with + * a desired version. + */ +struct ec_response_get_cmd_versions { uint32_t version_mask; -}; +} __ec_align4; /* * Check EC communications status (busy). This is needed on i2c/spi but not @@ -1116,50 +1202,55 @@ struct __ec_align4 ec_response_get_cmd_versions { /* Avoid using ec_status which is for return values */ enum ec_comms_status { - EC_COMMS_STATUS_PROCESSING = 1 << 0, /* Processing cmd */ + EC_COMMS_STATUS_PROCESSING = BIT(0), /* Processing cmd */ }; -struct __ec_align4 ec_response_get_comms_status { +/** + * struct ec_response_get_comms_status - Response to the get comms status + * command. + * @flags: Mask of enum ec_comms_status. + */ +struct ec_response_get_comms_status { uint32_t flags; /* Mask of enum ec_comms_status */ -}; +} __ec_align4; /* Fake a variety of responses, purely for testing purposes. */ #define EC_CMD_TEST_PROTOCOL 0x000A /* Tell the EC what to send back to us. */ -struct __ec_align4 ec_params_test_protocol { +struct ec_params_test_protocol { uint32_t ec_result; uint32_t ret_len; uint8_t buf[32]; -}; +} __ec_align4; /* Here it comes... */ -struct __ec_align4 ec_response_test_protocol { +struct ec_response_test_protocol { uint8_t buf[32]; -}; +} __ec_align4; /* Get protocol information */ #define EC_CMD_GET_PROTOCOL_INFO 0x000B /* Flags for ec_response_get_protocol_info.flags */ /* EC_RES_IN_PROGRESS may be returned if a command is slow */ -#define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED (1 << 0) +#define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED BIT(0) -struct __ec_align4 ec_response_get_protocol_info { +/** + * struct ec_response_get_protocol_info - Response to the get protocol info. + * @protocol_versions: Bitmask of protocol versions supported (1 << n means + * version n). + * @max_request_packet_size: Maximum request packet size in bytes. + * @max_response_packet_size: Maximum response packet size in bytes. + * @flags: see EC_PROTOCOL_INFO_* + */ +struct ec_response_get_protocol_info { /* Fields which exist if at least protocol version 3 supported */ - - /* Bitmask of protocol versions supported (1 << n means version n)*/ uint32_t protocol_versions; - - /* Maximum request packet size, in bytes */ uint16_t max_request_packet_size; - - /* Maximum response packet size, in bytes */ uint16_t max_response_packet_size; - - /* Flags; see EC_PROTOCOL_INFO_* */ uint32_t flags; -}; +} __ec_align4; /*****************************************************************************/ @@ -1168,19 +1259,21 @@ struct __ec_align4 ec_response_get_protocol_info { /* The upper byte of .flags tells what to do (nothing means "get") */ #define EC_GSV_SET 0x80000000 -/* The lower three bytes of .flags identifies the parameter, if that has - meaning for an individual command. */ +/* + * The lower three bytes of .flags identifies the parameter, if that has + * meaning for an individual command. + */ #define EC_GSV_PARAM_MASK 0x00ffffff -struct __ec_align4 ec_params_get_set_value { +struct ec_params_get_set_value { uint32_t flags; uint32_t value; -}; +} __ec_align4; -struct __ec_align4 ec_response_get_set_value { +struct ec_response_get_set_value { uint32_t flags; uint32_t value; -}; +} __ec_align4; /* More than one command can use these structs to get/set parameters. */ #define EC_CMD_GSV_PAUSE_IN_S5 0x000C @@ -1286,13 +1379,26 @@ enum ec_feature_code { EC_FEATURE_CEC = 35, /* EC supports tight sensor timestamping. */ EC_FEATURE_MOTION_SENSE_TIGHT_TIMESTAMPS = 36, + /* + * EC supports tablet mode detection aligned to Chrome and allows + * setting of threshold by host command using + * MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE. + */ + EC_FEATURE_REFINED_TABLET_MODE_HYSTERESIS = 37, + /* EC supports audio codec. */ + EC_FEATURE_AUDIO_CODEC = 38, + /* The MCU is a System Companion Processor (SCP). */ + EC_FEATURE_SCP = 39, + /* The MCU is an Integrated Sensor Hub */ + EC_FEATURE_ISH = 40, }; -#define EC_FEATURE_MASK_0(event_code) (1UL << (event_code % 32)) -#define EC_FEATURE_MASK_1(event_code) (1UL << (event_code - 32)) -struct __ec_align4 ec_response_get_features { +#define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32) +#define EC_FEATURE_MASK_1(event_code) BIT(event_code - 32) + +struct ec_response_get_features { uint32_t flags[2]; -}; +} __ec_align4; /*****************************************************************************/ /* Get the board's SKU ID from EC */ @@ -1301,9 +1407,9 @@ struct __ec_align4 ec_response_get_features { /* Set SKU ID from AP */ #define EC_CMD_SET_SKU_ID 0x000F -struct __ec_align4 ec_sku_id_info { +struct ec_sku_id_info { uint32_t sku_id; -}; +} __ec_align4; /*****************************************************************************/ /* Flash commands */ @@ -1312,39 +1418,56 @@ struct __ec_align4 ec_sku_id_info { #define EC_CMD_FLASH_INFO 0x0010 #define EC_VER_FLASH_INFO 2 -/* Version 0 returns these fields */ -struct __ec_align4 ec_response_flash_info { - /* Usable flash size, in bytes */ +/** + * struct ec_response_flash_info - Response to the flash info command. + * @flash_size: Usable flash size in bytes. + * @write_block_size: Write block size. Write offset and size must be a + * multiple of this. + * @erase_block_size: Erase block size. Erase offset and size must be a + * multiple of this. + * @protect_block_size: Protection block size. Protection offset and size + * must be a multiple of this. + * + * Version 0 returns these fields. + */ +struct ec_response_flash_info { uint32_t flash_size; - /* - * Write block size. Write offset and size must be a multiple - * of this. - */ uint32_t write_block_size; - /* - * Erase block size. Erase offset and size must be a multiple - * of this. - */ uint32_t erase_block_size; - /* - * Protection block size. Protection offset and size must be a - * multiple of this. - */ uint32_t protect_block_size; -}; +} __ec_align4; -/* Flags for version 1+ flash info command */ -/* EC flash erases bits to 0 instead of 1 */ -#define EC_FLASH_INFO_ERASE_TO_0 (1 << 0) +/* + * Flags for version 1+ flash info command + * EC flash erases bits to 0 instead of 1. + */ +#define EC_FLASH_INFO_ERASE_TO_0 BIT(0) -/* Flash must be selected for read/write/erase operations to succeed. This may +/* + * Flash must be selected for read/write/erase operations to succeed. This may * be necessary on a chip where write/erase can be corrupted by other board * activity, or where the chip needs to enable some sort of programming voltage, * or where the read/write/erase operations require cleanly suspending other - * chip functionality. */ -#define EC_FLASH_INFO_SELECT_REQUIRED (1 << 1) + * chip functionality. + */ +#define EC_FLASH_INFO_SELECT_REQUIRED BIT(1) -/* +/** + * struct ec_response_flash_info_1 - Response to the flash info v1 command. + * @flash_size: Usable flash size in bytes. + * @write_block_size: Write block size. Write offset and size must be a + * multiple of this. + * @erase_block_size: Erase block size. Erase offset and size must be a + * multiple of this. + * @protect_block_size: Protection block size. Protection offset and size + * must be a multiple of this. + * @write_ideal_size: Ideal write size in bytes. Writes will be fastest if + * size is exactly this and offset is a multiple of this. + * For example, an EC may have a write buffer which can do + * half-page operations if data is aligned, and a slower + * word-at-a-time write mode. + * @flags: Flags; see EC_FLASH_INFO_* + * * Version 1 returns the same initial fields as version 0, with additional * fields following. * @@ -1358,7 +1481,7 @@ struct __ec_align4 ec_response_flash_info { * The EC returns the number of banks describing the flash memory. * It adds banks descriptions up to num_banks_desc. */ -struct __ec_align4 ec_response_flash_info_1 { +struct ec_response_flash_info_1 { /* Version 0 fields; see above for description */ uint32_t flash_size; uint32_t write_block_size; @@ -1366,24 +1489,16 @@ struct __ec_align4 ec_response_flash_info_1 { uint32_t protect_block_size; /* Version 1 adds these fields: */ - /* - * Ideal write size in bytes. Writes will be fastest if size is - * exactly this and offset is a multiple of this. For example, an EC - * may have a write buffer which can do half-page operations if data is - * aligned, and a slower word-at-a-time write mode. - */ uint32_t write_ideal_size; - - /* Flags; see EC_FLASH_INFO_* */ uint32_t flags; -}; +} __ec_align4; -struct __ec_align4 ec_params_flash_info_2 { +struct ec_params_flash_info_2 { /* Number of banks to describe */ uint16_t num_banks_desc; /* Reserved; set 0; ignore on read */ uint8_t reserved[2]; -}; +} __ec_align4; struct ec_flash_bank { /* Number of sector is in this bank. */ @@ -1400,7 +1515,7 @@ struct ec_flash_bank { uint8_t reserved[2]; }; -struct __ec_align4 ec_response_flash_info_2 { +struct ec_response_flash_info_2 { /* Total flash in the EC. */ uint32_t flash_size; /* Flags; see EC_FLASH_INFO_* */ @@ -1412,7 +1527,7 @@ struct __ec_align4 ec_response_flash_info_2 { /* Number of banks described in banks array. */ uint16_t num_banks_desc; struct ec_flash_bank banks[0]; -}; +} __ec_align4; /* * Read flash @@ -1421,10 +1536,15 @@ struct __ec_align4 ec_response_flash_info_2 { */ #define EC_CMD_FLASH_READ 0x0011 -struct __ec_align4 ec_params_flash_read { - uint32_t offset; /* Byte offset to read */ - uint32_t size; /* Size to read in bytes */ -}; +/** + * struct ec_params_flash_read - Parameters for the flash read command. + * @offset: Byte offset to read. + * @size: Size to read in bytes. + */ +struct ec_params_flash_read { + uint32_t offset; + uint32_t size; +} __ec_align4; /* Write flash */ #define EC_CMD_FLASH_WRITE 0x0012 @@ -1433,24 +1553,32 @@ struct __ec_align4 ec_params_flash_read { /* Version 0 of the flash command supported only 64 bytes of data */ #define EC_FLASH_WRITE_VER0_SIZE 64 -struct __ec_align4 ec_params_flash_write { - uint32_t offset; /* Byte offset to write */ - uint32_t size; /* Size to write in bytes */ +/** + * struct ec_params_flash_write - Parameters for the flash write command. + * @offset: Byte offset to write. + * @size: Size to write in bytes. + */ +struct ec_params_flash_write { + uint32_t offset; + uint32_t size; /* Followed by data to write */ -}; +} __ec_align4; /* Erase flash */ #define EC_CMD_FLASH_ERASE 0x0013 -/* v0 */ -struct __ec_align4 ec_params_flash_erase { - uint32_t offset; /* Byte offset to erase */ - uint32_t size; /* Size to erase in bytes */ -}; +/** + * struct ec_params_flash_erase - Parameters for the flash erase command, v0. + * @offset: Byte offset to erase. + * @size: Size to erase in bytes. + */ +struct ec_params_flash_erase { + uint32_t offset; + uint32_t size; +} __ec_align4; - -#define EC_VER_FLASH_WRITE 1 -/* v1 add async erase: +/* + * v1 add async erase: * subcommands can returns: * EC_RES_SUCCESS : erased (see ERASE_SECTOR_ASYNC case below). * EC_RES_INVALID_PARAM : offset/size are not aligned on a erase boundary. @@ -1472,16 +1600,19 @@ enum ec_flash_erase_cmd { FLASH_ERASE_GET_RESULT, /* Ask for last erase result */ }; -struct __ec_align4 ec_params_flash_erase_v1 { - /* One of ec_flash_erase_cmd. */ +/** + * struct ec_params_flash_erase_v1 - Parameters for the flash erase command, v1. + * @cmd: One of ec_flash_erase_cmd. + * @reserved: Pad byte; currently always contains 0. + * @flag: No flags defined yet; set to 0. + * @params: Same as v0 parameters. + */ +struct ec_params_flash_erase_v1 { uint8_t cmd; - /* Pad byte; currently always contains 0 */ uint8_t reserved; - /* No flags defined yet; set to 0 */ uint16_t flag; - /* Same as v0 parameters. */ struct ec_params_flash_erase params; -}; +} __ec_align4; /* * Get/set flash protection. @@ -1498,52 +1629,60 @@ struct __ec_align4 ec_params_flash_erase_v1 { /* Flags for flash protection */ /* RO flash code protected when the EC boots */ -#define EC_FLASH_PROTECT_RO_AT_BOOT (1 << 0) +#define EC_FLASH_PROTECT_RO_AT_BOOT BIT(0) /* * RO flash code protected now. If this bit is set, at-boot status cannot * be changed. */ -#define EC_FLASH_PROTECT_RO_NOW (1 << 1) +#define EC_FLASH_PROTECT_RO_NOW BIT(1) /* Entire flash code protected now, until reboot. */ -#define EC_FLASH_PROTECT_ALL_NOW (1 << 2) +#define EC_FLASH_PROTECT_ALL_NOW BIT(2) /* Flash write protect GPIO is asserted now */ -#define EC_FLASH_PROTECT_GPIO_ASSERTED (1 << 3) +#define EC_FLASH_PROTECT_GPIO_ASSERTED BIT(3) /* Error - at least one bank of flash is stuck locked, and cannot be unlocked */ -#define EC_FLASH_PROTECT_ERROR_STUCK (1 << 4) +#define EC_FLASH_PROTECT_ERROR_STUCK BIT(4) /* * Error - flash protection is in inconsistent state. At least one bank of * flash which should be protected is not protected. Usually fixed by * re-requesting the desired flags, or by a hard reset if that fails. */ -#define EC_FLASH_PROTECT_ERROR_INCONSISTENT (1 << 5) +#define EC_FLASH_PROTECT_ERROR_INCONSISTENT BIT(5) /* Entire flash code protected when the EC boots */ -#define EC_FLASH_PROTECT_ALL_AT_BOOT (1 << 6) +#define EC_FLASH_PROTECT_ALL_AT_BOOT BIT(6) /* RW flash code protected when the EC boots */ -#define EC_FLASH_PROTECT_RW_AT_BOOT (1 << 7) +#define EC_FLASH_PROTECT_RW_AT_BOOT BIT(7) /* RW flash code protected now. */ -#define EC_FLASH_PROTECT_RW_NOW (1 << 8) +#define EC_FLASH_PROTECT_RW_NOW BIT(8) /* Rollback information flash region protected when the EC boots */ -#define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT (1 << 9) +#define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT BIT(9) /* Rollback information flash region protected now */ -#define EC_FLASH_PROTECT_ROLLBACK_NOW (1 << 10) +#define EC_FLASH_PROTECT_ROLLBACK_NOW BIT(10) -struct __ec_align4 ec_params_flash_protect { - uint32_t mask; /* Bits in flags to apply */ - uint32_t flags; /* New flags to apply */ -}; -struct __ec_align4 ec_response_flash_protect { - /* Current value of flash protect flags */ +/** + * struct ec_params_flash_protect - Parameters for the flash protect command. + * @mask: Bits in flags to apply. + * @flags: New flags to apply. + */ +struct ec_params_flash_protect { + uint32_t mask; + uint32_t flags; +} __ec_align4; + +/** + * struct ec_response_flash_protect - Response to the flash protect command. + * @flags: Current value of flash protect flags. + * @valid_flags: Flags which are valid on this platform. This allows the + * caller to distinguish between flags which aren't set vs. flags + * which can't be set on this platform. + * @writable_flags: Flags which can be changed given the current protection + * state. + */ +struct ec_response_flash_protect { uint32_t flags; - /* - * Flags which are valid on this platform. This allows the caller - * to distinguish between flags which aren't set vs. flags which can't - * be set on this platform. - */ uint32_t valid_flags; - /* Flags which can be changed given the current protection state */ uint32_t writable_flags; -}; +} __ec_align4; /* * Note: commands 0x14 - 0x19 version 0 were old commands to get/set flash @@ -1577,18 +1716,25 @@ enum ec_flash_region { /* Number of regions */ EC_FLASH_REGION_COUNT, }; -/* 'RW' is vague if there are multiple RW images; we mean the active one, - * so the old constant is deprecated */ +/* + * 'RW' is vague if there are multiple RW images; we mean the active one, + * so the old constant is deprecated. + */ #define EC_FLASH_REGION_RW EC_FLASH_REGION_ACTIVE -struct __ec_align4 ec_params_flash_region_info { - uint32_t region; /* enum ec_flash_region */ -}; +/** + * struct ec_params_flash_region_info - Parameters for the flash region info + * command. + * @region: Flash region; see EC_FLASH_REGION_* + */ +struct ec_params_flash_region_info { + uint32_t region; +} __ec_align4; -struct __ec_align4 ec_response_flash_region_info { +struct ec_response_flash_region_info { uint32_t offset; uint32_t size; -}; +} __ec_align4; /* Read/write VbNvContext */ #define EC_CMD_VBNV_CONTEXT 0x0017 @@ -1600,20 +1746,20 @@ enum ec_vbnvcontext_op { EC_VBNV_CONTEXT_OP_WRITE, }; -struct __ec_align4 ec_params_vbnvcontext { +struct ec_params_vbnvcontext { uint32_t op; uint8_t block[EC_VBNV_BLOCK_SIZE]; -}; +} __ec_align4; -struct __ec_align4 ec_response_vbnvcontext { +struct ec_response_vbnvcontext { uint8_t block[EC_VBNV_BLOCK_SIZE]; -}; +} __ec_align4; /* Get SPI flash information */ #define EC_CMD_FLASH_SPI_INFO 0x0018 -struct __ec_align1 ec_response_flash_spi_info { +struct ec_response_flash_spi_info { /* JEDEC info from command 0x9F (manufacturer, memory type, size) */ uint8_t jedec[3]; @@ -1625,72 +1771,94 @@ struct __ec_align1 ec_response_flash_spi_info { /* Status registers from command 0x05 and 0x35 */ uint8_t sr1, sr2; -}; +} __ec_align1; /* Select flash during flash operations */ #define EC_CMD_FLASH_SELECT 0x0019 -struct __ec_align4 ec_params_flash_select { - /* 1 to select flash, 0 to deselect flash */ +/** + * struct ec_params_flash_select - Parameters for the flash select command. + * @select: 1 to select flash, 0 to deselect flash + */ +struct ec_params_flash_select { uint8_t select; -}; +} __ec_align4; +/** + * Request random numbers to be generated and returned. + * Can be used to test the random number generator is truly random. + * See https://csrc.nist.gov/publications/detail/sp/800-22/rev-1a/final and + * https://webhome.phy.duke.edu/~rgb/General/dieharder.php. + */ +#define EC_CMD_RAND_NUM 0x001A +#define EC_VER_RAND_NUM 0 + +struct ec_params_rand_num { + uint16_t num_rand_bytes; /**< num random bytes to generate */ +} __ec_align4; + +struct ec_response_rand_num { + uint8_t rand[0]; /**< generated random numbers */ +} __ec_align4; + +BUILD_ASSERT(sizeof(struct ec_response_rand_num) == 0); + /*****************************************************************************/ /* PWM commands */ /* Get fan target RPM */ #define EC_CMD_PWM_GET_FAN_TARGET_RPM 0x0020 -struct __ec_align4 ec_response_pwm_get_fan_rpm { +struct ec_response_pwm_get_fan_rpm { uint32_t rpm; -}; +} __ec_align4; /* Set target fan RPM */ #define EC_CMD_PWM_SET_FAN_TARGET_RPM 0x0021 /* Version 0 of input params */ -struct __ec_align4 ec_params_pwm_set_fan_target_rpm_v0 { +struct ec_params_pwm_set_fan_target_rpm_v0 { uint32_t rpm; -}; +} __ec_align4; /* Version 1 of input params */ -struct __ec_align_size1 ec_params_pwm_set_fan_target_rpm_v1 { +struct ec_params_pwm_set_fan_target_rpm_v1 { uint32_t rpm; uint8_t fan_idx; -}; +} __ec_align_size1; /* Get keyboard backlight */ /* OBSOLETE - Use EC_CMD_PWM_SET_DUTY */ #define EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT 0x0022 -struct __ec_align1 ec_response_pwm_get_keyboard_backlight { +struct ec_response_pwm_get_keyboard_backlight { uint8_t percent; uint8_t enabled; -}; +} __ec_align1; /* Set keyboard backlight */ /* OBSOLETE - Use EC_CMD_PWM_SET_DUTY */ #define EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT 0x0023 -struct __ec_align1 ec_params_pwm_set_keyboard_backlight { +struct ec_params_pwm_set_keyboard_backlight { uint8_t percent; -}; +} __ec_align1; /* Set target fan PWM duty cycle */ #define EC_CMD_PWM_SET_FAN_DUTY 0x0024 /* Version 0 of input params */ -struct __ec_align4 ec_params_pwm_set_fan_duty_v0 { +struct ec_params_pwm_set_fan_duty_v0 { uint32_t percent; -}; +} __ec_align4; /* Version 1 of input params */ -struct __ec_align_size1 ec_params_pwm_set_fan_duty_v1 { +struct ec_params_pwm_set_fan_duty_v1 { uint32_t percent; uint8_t fan_idx; -}; +} __ec_align_size1; #define EC_CMD_PWM_SET_DUTY 0x0025 /* 16 bit duty cycle, 0xffff = 100% */ @@ -1706,22 +1874,22 @@ enum ec_pwm_type { EC_PWM_TYPE_COUNT, }; -struct __ec_align4 ec_params_pwm_set_duty { +struct ec_params_pwm_set_duty { uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ uint8_t pwm_type; /* ec_pwm_type */ uint8_t index; /* Type-specific index, or 0 if unique */ -}; +} __ec_align4; #define EC_CMD_PWM_GET_DUTY 0x0026 -struct __ec_align1 ec_params_pwm_get_duty { +struct ec_params_pwm_get_duty { uint8_t pwm_type; /* ec_pwm_type */ uint8_t index; /* Type-specific index, or 0 if unique */ -}; +} __ec_align1; -struct __ec_align2 ec_response_pwm_get_duty { +struct ec_response_pwm_get_duty { uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ -}; +} __ec_align2; /*****************************************************************************/ /* @@ -1732,15 +1900,17 @@ struct __ec_align2 ec_response_pwm_get_duty { */ #define EC_CMD_LIGHTBAR_CMD 0x0028 -struct __ec_todo_unpacked rgb_s { +struct rgb_s { uint8_t r, g, b; -}; +} __ec_todo_unpacked; #define LB_BATTERY_LEVELS 4 -/* List of tweakable parameters. NOTE: It's __packed so it can be sent in a + +/* + * List of tweakable parameters. NOTE: It's __packed so it can be sent in a * host command, but the alignment is the same regardless. Keep it that way. */ -struct __ec_todo_packed lightbar_params_v0 { +struct lightbar_params_v0 { /* Timing */ int32_t google_ramp_up; int32_t google_ramp_down; @@ -1772,9 +1942,9 @@ struct __ec_todo_packed lightbar_params_v0 { /* Color palette */ struct rgb_s color[8]; /* 0-3 are Google colors */ -}; +} __ec_todo_packed; -struct __ec_todo_packed lightbar_params_v1 { +struct lightbar_params_v1 { /* Timing */ int32_t google_ramp_up; int32_t google_ramp_down; @@ -1821,7 +1991,7 @@ struct __ec_todo_packed lightbar_params_v1 { /* Color palette */ struct rgb_s color[8]; /* 0-3 are Google colors */ -}; +} __ec_todo_packed; /* Lightbar command params v2 * crbug.com/467716 @@ -1832,7 +2002,7 @@ struct __ec_todo_packed lightbar_params_v1 { * NOTE: Each of these groups must be less than 120 bytes. */ -struct __ec_todo_packed lightbar_params_v2_timing { +struct lightbar_params_v2_timing { /* Timing */ int32_t google_ramp_up; int32_t google_ramp_down; @@ -1848,9 +2018,9 @@ struct __ec_todo_packed lightbar_params_v2_timing { int32_t tap_tick_delay; int32_t tap_gate_delay; int32_t tap_display_time; -}; +} __ec_todo_packed; -struct __ec_todo_packed lightbar_params_v2_tap { +struct lightbar_params_v2_tap { /* Tap-for-battery params */ uint8_t tap_pct_red; uint8_t tap_pct_green; @@ -1858,28 +2028,28 @@ struct __ec_todo_packed lightbar_params_v2_tap { uint8_t tap_seg_max_on; uint8_t tap_seg_osc; uint8_t tap_idx[3]; -}; +} __ec_todo_packed; -struct __ec_todo_packed lightbar_params_v2_oscillation { +struct lightbar_params_v2_oscillation { /* Oscillation */ uint8_t osc_min[2]; /* AC=0/1 */ uint8_t osc_max[2]; /* AC=0/1 */ uint8_t w_ofs[2]; /* AC=0/1 */ -}; +} __ec_todo_packed; -struct __ec_todo_packed lightbar_params_v2_brightness { +struct lightbar_params_v2_brightness { /* Brightness limits based on the backlight and AC. */ uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ uint8_t bright_bl_on_min[2]; /* AC=0/1 */ uint8_t bright_bl_on_max[2]; /* AC=0/1 */ -}; +} __ec_todo_packed; -struct __ec_todo_packed lightbar_params_v2_thresholds { +struct lightbar_params_v2_thresholds { /* Battery level thresholds */ uint8_t battery_threshold[LB_BATTERY_LEVELS - 1]; -}; +} __ec_todo_packed; -struct __ec_todo_packed lightbar_params_v2_colors { +struct lightbar_params_v2_colors { /* Map [AC][battery_level] to color index */ uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ @@ -1889,16 +2059,16 @@ struct __ec_todo_packed lightbar_params_v2_colors { /* Color palette */ struct rgb_s color[8]; /* 0-3 are Google colors */ -}; +} __ec_todo_packed; -/* Lightbyte program. */ +/* Lightbar program. */ #define EC_LB_PROG_LEN 192 -struct __ec_todo_unpacked lightbar_program { +struct lightbar_program { uint8_t size; uint8_t data[EC_LB_PROG_LEN]; -}; +} __ec_todo_unpacked; -struct __ec_todo_packed ec_params_lightbar { +struct ec_params_lightbar { uint8_t cmd; /* Command (see enum lightbar_command) */ union { /* @@ -1945,9 +2115,9 @@ struct __ec_todo_packed ec_params_lightbar { struct lightbar_program set_program; }; -}; +} __ec_todo_packed; -struct __ec_todo_packed ec_response_lightbar { +struct ec_response_lightbar { union { struct __ec_todo_unpacked { struct __ec_todo_unpacked { @@ -1991,7 +2161,7 @@ struct __ec_todo_packed ec_response_lightbar { * set_v2par_thlds, set_v2par_colors */ }; -}; +} __ec_todo_packed; /* Lightbar commands */ enum lightbar_command { @@ -2060,8 +2230,8 @@ enum ec_led_id { }; /* LED control flags */ -#define EC_LED_FLAGS_QUERY (1 << 0) /* Query LED capability only */ -#define EC_LED_FLAGS_AUTO (1 << 1) /* Switch LED back to automatic control */ +#define EC_LED_FLAGS_QUERY BIT(0) /* Query LED capability only */ +#define EC_LED_FLAGS_AUTO BIT(1) /* Switch LED back to automatic control */ enum ec_led_colors { EC_LED_COLOR_RED = 0, @@ -2074,14 +2244,14 @@ enum ec_led_colors { EC_LED_COLOR_COUNT }; -struct __ec_align1 ec_params_led_control { +struct ec_params_led_control { uint8_t led_id; /* Which LED to control */ uint8_t flags; /* Control flags */ uint8_t brightness[EC_LED_COLOR_COUNT]; -}; +} __ec_align1; -struct __ec_align1 ec_response_led_control { +struct ec_response_led_control { /* * Available brightness value range. * @@ -2090,7 +2260,7 @@ struct __ec_align1 ec_response_led_control { * Other values means the LED is control by PWM. */ uint8_t brightness_range[EC_LED_COLOR_COUNT]; -}; +} __ec_align1; /*****************************************************************************/ /* Verified boot commands */ @@ -2103,7 +2273,7 @@ struct __ec_align1 ec_response_led_control { /* Verified boot hash command */ #define EC_CMD_VBOOT_HASH 0x002A -struct __ec_align4 ec_params_vboot_hash { +struct ec_params_vboot_hash { uint8_t cmd; /* enum ec_vboot_hash_cmd */ uint8_t hash_type; /* enum ec_vboot_hash_type */ uint8_t nonce_size; /* Nonce size; may be 0 */ @@ -2111,9 +2281,9 @@ struct __ec_align4 ec_params_vboot_hash { uint32_t offset; /* Offset in flash to hash */ uint32_t size; /* Number of bytes to hash */ uint8_t nonce_data[64]; /* Nonce data; ignored if nonce_size=0 */ -}; +} __ec_align4; -struct __ec_align4 ec_response_vboot_hash { +struct ec_response_vboot_hash { uint8_t status; /* enum ec_vboot_hash_status */ uint8_t hash_type; /* enum ec_vboot_hash_type */ uint8_t digest_size; /* Size of hash digest in bytes */ @@ -2121,7 +2291,7 @@ struct __ec_align4 ec_response_vboot_hash { uint32_t offset; /* Offset in flash which was hashed */ uint32_t size; /* Number of bytes hashed */ uint8_t hash_digest[64]; /* Hash digest data */ -}; +} __ec_align4; enum ec_vboot_hash_cmd { EC_VBOOT_HASH_GET = 0, /* Get current hash status */ @@ -2149,8 +2319,10 @@ enum ec_vboot_hash_status { #define EC_VBOOT_HASH_OFFSET_ACTIVE 0xfffffffd #define EC_VBOOT_HASH_OFFSET_UPDATE 0xfffffffc -/* 'RW' is vague if there are multiple RW images; we mean the active one, - * so the old constant is deprecated */ +/* + * 'RW' is vague if there are multiple RW images; we mean the active one, + * so the old constant is deprecated. + */ #define EC_VBOOT_HASH_OFFSET_RW EC_VBOOT_HASH_OFFSET_ACTIVE /*****************************************************************************/ @@ -2273,6 +2445,15 @@ enum motionsense_command { */ MOTIONSENSE_CMD_SPOOF = 16, + /* Set lid angle for tablet mode detection. */ + MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE = 17, + + /* + * Sensor Scale command is a setter/getter command for the calibration + * scale. + */ + MOTIONSENSE_CMD_SENSOR_SCALE = 18, + /* Number of motionsense sub-commands. */ MOTIONSENSE_NUM_CMDS }; @@ -2287,6 +2468,7 @@ enum motionsensor_type { MOTIONSENSE_TYPE_ACTIVITY = 5, MOTIONSENSE_TYPE_BARO = 6, MOTIONSENSE_TYPE_SYNC = 7, + MOTIONSENSE_TYPE_LIGHT_RGB = 8, MOTIONSENSE_TYPE_MAX, }; @@ -2316,6 +2498,13 @@ enum motionsensor_chip { MOTIONSENSE_CHIP_LIS2DH = 13, MOTIONSENSE_CHIP_LSM6DSM = 14, MOTIONSENSE_CHIP_LIS2DE = 15, + MOTIONSENSE_CHIP_LIS2MDL = 16, + MOTIONSENSE_CHIP_LSM6DS3 = 17, + MOTIONSENSE_CHIP_LSM6DSO = 18, + MOTIONSENSE_CHIP_LNG2DM = 19, + MOTIONSENSE_CHIP_TCS3400 = 20, + MOTIONSENSE_CHIP_LIS2DW12 = 21, + MOTIONSENSE_CHIP_LIS2DWL = 22, MOTIONSENSE_CHIP_MAX, }; @@ -2328,10 +2517,10 @@ enum motionsensor_orientation { MOTIONSENSE_ORIENTATION_UNKNOWN = 4, }; -struct __ec_todo_packed ec_response_motion_sensor_data { +struct ec_response_motion_sensor_data { /* Flags for each sensor. */ uint8_t flags; - /* sensor number the data comes from */ + /* Sensor number the data comes from. */ uint8_t sensor_num; /* Each sensor is up to 3-axis. */ union { @@ -2346,10 +2535,10 @@ struct __ec_todo_packed ec_response_motion_sensor_data { int16_t add_info[2]; }; }; -}; +} __ec_todo_packed; /* Note: used in ec_response_get_next_data */ -struct __ec_todo_packed ec_response_motion_sense_fifo_info { +struct ec_response_motion_sense_fifo_info { /* Size of the fifo */ uint16_t size; /* Amount of space used in the fifo */ @@ -2362,12 +2551,12 @@ struct __ec_todo_packed ec_response_motion_sense_fifo_info { uint16_t total_lost; /* Lost events since the last fifo_info, per sensors */ uint16_t lost[0]; -}; +} __ec_todo_packed; -struct __ec_todo_packed ec_response_motion_sense_fifo_data { +struct ec_response_motion_sense_fifo_data { uint32_t number_data; struct ec_response_motion_sensor_data data[0]; -}; +} __ec_todo_packed; /* List supported activity recognition */ enum motionsensor_activity { @@ -2377,28 +2566,29 @@ enum motionsensor_activity { MOTIONSENSE_ACTIVITY_ORIENTATION = 3, }; -struct __ec_todo_unpacked ec_motion_sense_activity { +struct ec_motion_sense_activity { uint8_t sensor_num; uint8_t activity; /* one of enum motionsensor_activity */ uint8_t enable; /* 1: enable, 0: disable */ uint8_t reserved; uint16_t parameters[3]; /* activity dependent parameters */ -}; +} __ec_todo_unpacked; /* Module flag masks used for the dump sub-command. */ -#define MOTIONSENSE_MODULE_FLAG_ACTIVE (1<<0) +#define MOTIONSENSE_MODULE_FLAG_ACTIVE BIT(0) /* Sensor flag masks used for the dump sub-command. */ -#define MOTIONSENSE_SENSOR_FLAG_PRESENT (1<<0) +#define MOTIONSENSE_SENSOR_FLAG_PRESENT BIT(0) /* * Flush entry for synchronization. * data contains time stamp */ -#define MOTIONSENSE_SENSOR_FLAG_FLUSH (1<<0) -#define MOTIONSENSE_SENSOR_FLAG_TIMESTAMP (1<<1) -#define MOTIONSENSE_SENSOR_FLAG_WAKEUP (1<<2) -#define MOTIONSENSE_SENSOR_FLAG_TABLET_MODE (1<<3) +#define MOTIONSENSE_SENSOR_FLAG_FLUSH BIT(0) +#define MOTIONSENSE_SENSOR_FLAG_TIMESTAMP BIT(1) +#define MOTIONSENSE_SENSOR_FLAG_WAKEUP BIT(2) +#define MOTIONSENSE_SENSOR_FLAG_TABLET_MODE BIT(3) +#define MOTIONSENSE_SENSOR_FLAG_ODR BIT(4) /* * Send this value for the data element to only perform a read. If you @@ -2411,7 +2601,10 @@ struct __ec_todo_unpacked ec_motion_sense_activity { /* MOTIONSENSE_CMD_SENSOR_OFFSET subcommand flag */ /* Set Calibration information */ -#define MOTION_SENSE_SET_OFFSET 1 +#define MOTION_SENSE_SET_OFFSET BIT(0) + +/* Default Scale value, factor 1. */ +#define MOTION_SENSE_DEFAULT_SCALE BIT(15) #define LID_ANGLE_UNRELIABLE 500 @@ -2429,10 +2622,10 @@ enum motionsense_spoof_mode { MOTIONSENSE_SPOOF_MODE_QUERY, }; -struct __ec_todo_packed ec_params_motion_sense { +struct ec_params_motion_sense { uint8_t cmd; union { - /* Used for MOTIONSENSE_CMD_DUMP */ + /* Used for MOTIONSENSE_CMD_DUMP. */ struct __ec_todo_unpacked { /* * Maximal number of sensor the host is expecting. @@ -2452,13 +2645,21 @@ struct __ec_todo_packed ec_params_motion_sense { int16_t data; } kb_wake_angle; - /* Used for MOTIONSENSE_CMD_INFO, MOTIONSENSE_CMD_DATA - * and MOTIONSENSE_CMD_PERFORM_CALIB. */ + /* + * Used for MOTIONSENSE_CMD_INFO, MOTIONSENSE_CMD_DATA + */ struct __ec_todo_unpacked { uint8_t sensor_num; - } info, info_3, data, fifo_flush, perform_calib, - list_activities; + } info, info_3, data, fifo_flush, list_activities; + /* + * Used for MOTIONSENSE_CMD_PERFORM_CALIB: + * Allow entering/exiting the calibration mode. + */ + struct __ec_todo_unpacked { + uint8_t sensor_num; + uint8_t enable; + } perform_calib; /* * Used for MOTIONSENSE_CMD_EC_RATE, MOTIONSENSE_CMD_SENSOR_ODR * and MOTIONSENSE_CMD_SENSOR_RANGE. @@ -2504,6 +2705,36 @@ struct __ec_todo_packed ec_params_motion_sense { int16_t offset[3]; } sensor_offset; + /* Used for MOTIONSENSE_CMD_SENSOR_SCALE */ + struct __ec_todo_packed { + uint8_t sensor_num; + + /* + * bit 0: If set (MOTION_SENSE_SET_OFFSET), set + * the calibration information in the EC. + * If unset, just retrieve calibration information. + */ + uint16_t flags; + + /* + * Temperature at calibration, in units of 0.01 C + * 0x8000: invalid / unknown. + * 0x0: 0C + * 0x7fff: +327.67C + */ + int16_t temp; + + /* + * Scale for calibration: + * By default scale is 1, it is encoded on 16bits: + * 1 = BIT(15) + * ~2 = 0xFFFF + * ~0 = 0. + */ + uint16_t scale[3]; + } sensor_scale; + + /* Used for MOTIONSENSE_CMD_FIFO_INFO */ /* (no params) */ @@ -2543,21 +2774,39 @@ struct __ec_todo_packed ec_params_motion_sense { /* Individual component values to spoof. */ int16_t components[3]; } spoof; - }; -}; -struct __ec_todo_packed ec_response_motion_sense { + /* Used for MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE. */ + struct __ec_todo_unpacked { + /* + * Lid angle threshold for switching between tablet and + * clamshell mode. + */ + int16_t lid_angle; + + /* + * Hysteresis degree to prevent fluctuations between + * clamshell and tablet mode if lid angle keeps + * changing around the threshold. Lid motion driver will + * use lid_angle + hys_degree to trigger tablet mode and + * lid_angle - hys_degree to trigger clamshell mode. + */ + int16_t hys_degree; + } tablet_mode_threshold; + }; +} __ec_todo_packed; + +struct ec_response_motion_sense { union { /* Used for MOTIONSENSE_CMD_DUMP */ struct __ec_todo_unpacked { /* Flags representing the motion sensor module. */ uint8_t module_flags; - /* Number of sensors managed directly by the EC */ + /* Number of sensors managed directly by the EC. */ uint8_t sensor_count; /* - * sensor data is truncated if response_max is too small + * Sensor data is truncated if response_max is too small * for holding all the data. */ struct ec_response_motion_sensor_data sensor[0]; @@ -2612,12 +2861,21 @@ struct __ec_todo_packed ec_response_motion_sense { } ec_rate, sensor_odr, sensor_range, kb_wake_angle, fifo_int_enable, spoof; - /* Used for MOTIONSENSE_CMD_SENSOR_OFFSET */ + /* + * Used for MOTIONSENSE_CMD_SENSOR_OFFSET, + * PERFORM_CALIB. + */ struct __ec_todo_unpacked { int16_t temp; int16_t offset[3]; } sensor_offset, perform_calib; + /* Used for MOTIONSENSE_CMD_SENSOR_SCALE */ + struct __ec_todo_unpacked { + int16_t temp; + uint16_t scale[3]; + } sensor_scale; + struct ec_response_motion_sense_fifo_info fifo_info, fifo_flush; struct ec_response_motion_sense_fifo_data fifo_read; @@ -2638,8 +2896,21 @@ struct __ec_todo_packed ec_response_motion_sense { */ uint16_t value; } lid_angle; + + /* Used for MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE. */ + struct __ec_todo_unpacked { + /* + * Lid angle threshold for switching between tablet and + * clamshell mode. + */ + uint16_t lid_angle; + + /* Hysteresis degree. */ + uint16_t hys_degree; + } tablet_mode_threshold; + }; -}; +} __ec_todo_packed; /*****************************************************************************/ /* Force lid open command */ @@ -2647,9 +2918,9 @@ struct __ec_todo_packed ec_response_motion_sense { /* Make lid event always open */ #define EC_CMD_FORCE_LID_OPEN 0x002C -struct __ec_align1 ec_params_force_lid_open { +struct ec_params_force_lid_open { uint8_t enabled; -}; +} __ec_align1; /*****************************************************************************/ /* Configure the behavior of the power button */ @@ -2657,13 +2928,13 @@ struct __ec_align1 ec_params_force_lid_open { enum ec_config_power_button_flags { /* Enable/Disable power button pulses for x86 devices */ - EC_POWER_BUTTON_ENABLE_PULSE = (1 << 0), + EC_POWER_BUTTON_ENABLE_PULSE = BIT(0), }; -struct __ec_align1 ec_params_config_power_button { +struct ec_params_config_power_button { /* See enum ec_config_power_button_flags */ uint8_t flags; -}; +} __ec_align1; /*****************************************************************************/ /* USB charging control commands */ @@ -2671,11 +2942,36 @@ struct __ec_align1 ec_params_config_power_button { /* Set USB port charging mode */ #define EC_CMD_USB_CHARGE_SET_MODE 0x0030 -struct __ec_align1 ec_params_usb_charge_set_mode { - uint8_t usb_port_id; - uint8_t mode; +enum usb_charge_mode { + /* Disable USB port. */ + USB_CHARGE_MODE_DISABLED, + /* Set USB port to Standard Downstream Port, USB 2.0 mode. */ + USB_CHARGE_MODE_SDP2, + /* Set USB port to Charging Downstream Port, BC 1.2. */ + USB_CHARGE_MODE_CDP, + /* Set USB port to Dedicated Charging Port, BC 1.2. */ + USB_CHARGE_MODE_DCP_SHORT, + /* Enable USB port (for dumb ports). */ + USB_CHARGE_MODE_ENABLED, + /* Set USB port to CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE. */ + USB_CHARGE_MODE_DEFAULT, + + USB_CHARGE_MODE_COUNT }; +enum usb_suspend_charge { + /* Enable charging in suspend */ + USB_ALLOW_SUSPEND_CHARGE, + /* Disable charging in suspend */ + USB_DISALLOW_SUSPEND_CHARGE +}; + +struct ec_params_usb_charge_set_mode { + uint8_t usb_port_id; + uint8_t mode:7; /* enum usb_charge_mode */ + uint8_t inhibit_charge:1; /* enum usb_suspend_charge */ +} __ec_align1; + /*****************************************************************************/ /* Persistent storage for host */ @@ -2685,12 +2981,12 @@ struct __ec_align1 ec_params_usb_charge_set_mode { /* Get persistent storage info */ #define EC_CMD_PSTORE_INFO 0x0040 -struct __ec_align4 ec_response_pstore_info { +struct ec_response_pstore_info { /* Persistent storage size, in bytes */ uint32_t pstore_size; /* Access size; read/write offset and size must be a multiple of this */ uint32_t access_size; -}; +} __ec_align4; /* * Read persistent storage @@ -2699,31 +2995,31 @@ struct __ec_align4 ec_response_pstore_info { */ #define EC_CMD_PSTORE_READ 0x0041 -struct __ec_align4 ec_params_pstore_read { +struct ec_params_pstore_read { uint32_t offset; /* Byte offset to read */ uint32_t size; /* Size to read in bytes */ -}; +} __ec_align4; /* Write persistent storage */ #define EC_CMD_PSTORE_WRITE 0x0042 -struct __ec_align4 ec_params_pstore_write { +struct ec_params_pstore_write { uint32_t offset; /* Byte offset to write */ uint32_t size; /* Size to write in bytes */ uint8_t data[EC_PSTORE_SIZE_MAX]; -}; +} __ec_align4; /*****************************************************************************/ /* Real-time clock */ /* RTC params and response structures */ -struct __ec_align4 ec_params_rtc { +struct ec_params_rtc { uint32_t time; -}; +} __ec_align4; -struct __ec_align4 ec_response_rtc { +struct ec_response_rtc { uint32_t time; -}; +} __ec_align4; /* These use ec_response_rtc */ #define EC_CMD_RTC_GET_VALUE 0x0044 @@ -2751,7 +3047,7 @@ enum ec_port80_subcmd { EC_PORT80_READ_BUFFER, }; -struct __ec_todo_packed ec_params_port80_read { +struct ec_params_port80_read { uint16_t subcmd; union { struct __ec_todo_unpacked { @@ -2759,9 +3055,9 @@ struct __ec_todo_packed ec_params_port80_read { uint32_t num_entries; } read_buffer; }; -}; +} __ec_todo_packed; -struct __ec_todo_packed ec_response_port80_read { +struct ec_response_port80_read { union { struct __ec_todo_unpacked { uint32_t writes; @@ -2772,11 +3068,11 @@ struct __ec_todo_packed ec_response_port80_read { uint16_t codes[EC_PORT80_SIZE_MAX]; } data; }; -}; +} __ec_todo_packed; -struct __ec_align2 ec_response_port80_last_boot { +struct ec_response_port80_last_boot { uint16_t code; -}; +} __ec_align2; /*****************************************************************************/ /* Temporary secure storage for host verified boot use */ @@ -2789,12 +3085,12 @@ struct __ec_align2 ec_response_port80_last_boot { /* Get persistent storage info */ #define EC_CMD_VSTORE_INFO 0x0049 -struct __ec_align_size1 ec_response_vstore_info { +struct ec_response_vstore_info { /* Indicates which slots are locked */ uint32_t slot_locked; /* Total number of slots available */ uint8_t slot_count; -}; +} __ec_align_size1; /* * Read temporary secure storage @@ -2803,23 +3099,23 @@ struct __ec_align_size1 ec_response_vstore_info { */ #define EC_CMD_VSTORE_READ 0x004A -struct __ec_align1 ec_params_vstore_read { +struct ec_params_vstore_read { uint8_t slot; /* Slot to read from */ -}; +} __ec_align1; -struct __ec_align1 ec_response_vstore_read { +struct ec_response_vstore_read { uint8_t data[EC_VSTORE_SLOT_SIZE]; -}; +} __ec_align1; /* * Write temporary secure storage and lock it. */ #define EC_CMD_VSTORE_WRITE 0x004B -struct __ec_align1 ec_params_vstore_write { +struct ec_params_vstore_write { uint8_t slot; /* Slot to write to */ uint8_t data[EC_VSTORE_SLOT_SIZE]; -}; +} __ec_align1; /*****************************************************************************/ /* Thermal engine commands. Note that there are two implementations. We'll @@ -2836,21 +3132,21 @@ struct __ec_align1 ec_params_vstore_write { */ /* Version 0 - set */ -struct __ec_align2 ec_params_thermal_set_threshold { +struct ec_params_thermal_set_threshold { uint8_t sensor_type; uint8_t threshold_id; uint16_t value; -}; +} __ec_align2; /* Version 0 - get */ -struct __ec_align1 ec_params_thermal_get_threshold { +struct ec_params_thermal_get_threshold { uint8_t sensor_type; uint8_t threshold_id; -}; +} __ec_align1; -struct __ec_align2 ec_response_thermal_get_threshold { +struct ec_response_thermal_get_threshold { uint16_t value; -}; +} __ec_align2; /* The version 1 structs are visible. */ @@ -2884,25 +3180,27 @@ enum ec_temp_thresholds { * Note that this structure is a sub-structure of * ec_params_thermal_set_threshold_v1, but maintains its alignment there. */ -struct __ec_align4 ec_thermal_config { +struct ec_thermal_config { uint32_t temp_host[EC_TEMP_THRESH_COUNT]; /* levels of hotness */ uint32_t temp_host_release[EC_TEMP_THRESH_COUNT]; /* release levels */ uint32_t temp_fan_off; /* no active cooling needed */ uint32_t temp_fan_max; /* max active cooling needed */ -}; +} __ec_align4; /* Version 1 - get config for one sensor. */ -struct __ec_align4 ec_params_thermal_get_threshold_v1 { +struct ec_params_thermal_get_threshold_v1 { uint32_t sensor_num; -}; +} __ec_align4; /* This returns a struct ec_thermal_config */ -/* Version 1 - set config for one sensor. - * Use read-modify-write for best results! */ -struct __ec_align4 ec_params_thermal_set_threshold_v1 { +/* + * Version 1 - set config for one sensor. + * Use read-modify-write for best results! + */ +struct ec_params_thermal_set_threshold_v1 { uint32_t sensor_num; struct ec_thermal_config cfg; -}; +} __ec_align4; /* This returns no data */ /****************************************************************************/ @@ -2911,9 +3209,9 @@ struct __ec_align4 ec_params_thermal_set_threshold_v1 { #define EC_CMD_THERMAL_AUTO_FAN_CTRL 0x0052 /* Version 1 of input params */ -struct __ec_align1 ec_params_auto_fan_ctrl_v1 { +struct ec_params_auto_fan_ctrl_v1 { uint8_t fan_idx; -}; +} __ec_align1; /* Get/Set TMP006 calibration data */ #define EC_CMD_TMP006_GET_CALIBRATION 0x0053 @@ -2929,55 +3227,55 @@ struct __ec_align1 ec_params_auto_fan_ctrl_v1 { */ /* This is the same struct for both v0 and v1. */ -struct __ec_align1 ec_params_tmp006_get_calibration { +struct ec_params_tmp006_get_calibration { uint8_t index; -}; +} __ec_align1; /* Version 0 */ -struct __ec_align4 ec_response_tmp006_get_calibration_v0 { +struct ec_response_tmp006_get_calibration_v0 { float s0; float b0; float b1; float b2; -}; +} __ec_align4; -struct __ec_align4 ec_params_tmp006_set_calibration_v0 { +struct ec_params_tmp006_set_calibration_v0 { uint8_t index; uint8_t reserved[3]; float s0; float b0; float b1; float b2; -}; +} __ec_align4; /* Version 1 */ -struct __ec_align4 ec_response_tmp006_get_calibration_v1 { +struct ec_response_tmp006_get_calibration_v1 { uint8_t algorithm; uint8_t num_params; uint8_t reserved[2]; float val[0]; -}; +} __ec_align4; -struct __ec_align4 ec_params_tmp006_set_calibration_v1 { +struct ec_params_tmp006_set_calibration_v1 { uint8_t index; uint8_t algorithm; uint8_t num_params; uint8_t reserved; float val[0]; -}; +} __ec_align4; /* Read raw TMP006 data */ #define EC_CMD_TMP006_GET_RAW 0x0055 -struct __ec_align1 ec_params_tmp006_get_raw { +struct ec_params_tmp006_get_raw { uint8_t index; -}; +} __ec_align1; -struct __ec_align4 ec_response_tmp006_get_raw { +struct ec_response_tmp006_get_raw { int32_t t; /* In 1/100 K */ int32_t v; /* In nV */ -}; +} __ec_align4; /*****************************************************************************/ /* MKBP - Matrix KeyBoard Protocol */ @@ -2999,17 +3297,17 @@ struct __ec_align4 ec_response_tmp006_get_raw { */ #define EC_CMD_MKBP_INFO 0x0061 -struct __ec_align_size1 ec_response_mkbp_info { +struct ec_response_mkbp_info { uint32_t rows; uint32_t cols; /* Formerly "switches", which was 0. */ uint8_t reserved; -}; +} __ec_align_size1; -struct __ec_align1 ec_params_mkbp_info { +struct ec_params_mkbp_info { uint8_t info_type; uint8_t event_type; -}; +} __ec_align1; enum ec_mkbp_info_type { /* @@ -3053,17 +3351,17 @@ enum ec_mkbp_info_type { /* Simulate key press */ #define EC_CMD_MKBP_SIMULATE_KEY 0x0062 -struct __ec_align1 ec_params_mkbp_simulate_key { +struct ec_params_mkbp_simulate_key { uint8_t col; uint8_t row; uint8_t pressed; -}; +} __ec_align1; #define EC_CMD_GET_KEYBOARD_ID 0x0063 -struct __ec_align4 ec_response_keyboard_id { +struct ec_response_keyboard_id { uint32_t keyboard_id; -}; +} __ec_align4; enum keyboard_id { KEYBOARD_ID_UNSUPPORTED = 0, @@ -3080,13 +3378,13 @@ enum mkbp_config_flags { }; enum mkbp_config_valid { - EC_MKBP_VALID_SCAN_PERIOD = 1 << 0, - EC_MKBP_VALID_POLL_TIMEOUT = 1 << 1, - EC_MKBP_VALID_MIN_POST_SCAN_DELAY = 1 << 3, - EC_MKBP_VALID_OUTPUT_SETTLE = 1 << 4, - EC_MKBP_VALID_DEBOUNCE_DOWN = 1 << 5, - EC_MKBP_VALID_DEBOUNCE_UP = 1 << 6, - EC_MKBP_VALID_FIFO_MAX_DEPTH = 1 << 7, + EC_MKBP_VALID_SCAN_PERIOD = BIT(0), + EC_MKBP_VALID_POLL_TIMEOUT = BIT(1), + EC_MKBP_VALID_MIN_POST_SCAN_DELAY = BIT(3), + EC_MKBP_VALID_OUTPUT_SETTLE = BIT(4), + EC_MKBP_VALID_DEBOUNCE_DOWN = BIT(5), + EC_MKBP_VALID_DEBOUNCE_UP = BIT(6), + EC_MKBP_VALID_FIFO_MAX_DEPTH = BIT(7), }; /* @@ -3095,7 +3393,7 @@ enum mkbp_config_valid { * Note that this is used as a sub-structure of * ec_{params/response}_mkbp_get_config. */ -struct __ec_align_size1 ec_mkbp_config { +struct ec_mkbp_config { uint32_t valid_mask; /* valid fields */ uint8_t flags; /* some flags (enum mkbp_config_flags) */ uint8_t valid_flags; /* which flags are valid */ @@ -3114,15 +3412,15 @@ struct __ec_align_size1 ec_mkbp_config { uint16_t debounce_up_us; /* time for debounce on key up */ /* maximum depth to allow for fifo (0 = no keyscan output) */ uint8_t fifo_max_depth; -}; +} __ec_align_size1; -struct __ec_align_size1 ec_params_mkbp_set_config { +struct ec_params_mkbp_set_config { struct ec_mkbp_config config; -}; +} __ec_align_size1; -struct __ec_align_size1 ec_response_mkbp_get_config { +struct ec_response_mkbp_get_config { struct ec_mkbp_config config; -}; +} __ec_align_size1; /* Run the key scan emulation */ #define EC_CMD_KEYSCAN_SEQ_CTRL 0x0066 @@ -3140,14 +3438,14 @@ enum ec_collect_flags { * Indicates this scan was processed by the EC. Due to timing, some * scans may be skipped. */ - EC_KEYSCAN_SEQ_FLAG_DONE = 1 << 0, + EC_KEYSCAN_SEQ_FLAG_DONE = BIT(0), }; -struct __ec_align1 ec_collect_item { +struct ec_collect_item { uint8_t flags; /* some flags (enum ec_collect_flags) */ -}; +} __ec_align1; -struct __ec_todo_packed ec_params_keyscan_seq_ctrl { +struct ec_params_keyscan_seq_ctrl { uint8_t cmd; /* Command to send (enum ec_keyscan_seq_cmd) */ union { struct __ec_align1 { @@ -3169,9 +3467,9 @@ struct __ec_todo_packed ec_params_keyscan_seq_ctrl { uint8_t num_items; /* Number of items to return */ } collect; }; -}; +} __ec_todo_packed; -struct __ec_todo_packed ec_result_keyscan_seq_ctrl { +struct ec_result_keyscan_seq_ctrl { union { struct __ec_todo_unpacked { uint8_t num_items; /* Number of items */ @@ -3179,7 +3477,7 @@ struct __ec_todo_packed ec_result_keyscan_seq_ctrl { struct ec_collect_item item[0]; } collect; }; -}; +} __ec_todo_packed; /* * Get the next pending MKBP event. @@ -3188,6 +3486,17 @@ struct __ec_todo_packed ec_result_keyscan_seq_ctrl { */ #define EC_CMD_GET_NEXT_EVENT 0x0067 +#define EC_MKBP_HAS_MORE_EVENTS_SHIFT 7 + +/* + * We use the most significant bit of the event type to indicate to the host + * that the EC has more MKBP events available to provide. + */ +#define EC_MKBP_HAS_MORE_EVENTS BIT(EC_MKBP_HAS_MORE_EVENTS_SHIFT) + +/* The mask to apply to get the raw event type */ +#define EC_MKBP_EVENT_TYPE_MASK (BIT(EC_MKBP_HAS_MORE_EVENTS_SHIFT) - 1) + enum ec_mkbp_event { /* Keyboard matrix changed. The event data is the new matrix state. */ EC_MKBP_EVENT_KEY_MATRIX = 0, @@ -3225,9 +3534,13 @@ enum ec_mkbp_event { /* Send an incoming CEC message to the AP */ EC_MKBP_EVENT_CEC_MESSAGE = 9, + /* We have entered DisplayPort Alternate Mode on a Type-C port. */ + EC_MKBP_EVENT_DP_ALT_MODE_ENTERED = 10, + /* Number of MKBP events */ EC_MKBP_EVENT_COUNT, }; +BUILD_ASSERT(EC_MKBP_EVENT_COUNT <= EC_MKBP_EVENT_TYPE_MASK); union __ec_align_offset1 ec_response_get_next_data { uint8_t key_matrix[13]; @@ -3280,18 +3593,19 @@ union __ec_align_offset1 ec_response_get_next_data_v1 { uint8_t cec_message[16]; }; +BUILD_ASSERT(sizeof(union ec_response_get_next_data_v1) == 16); -struct __ec_align1 ec_response_get_next_event { +struct ec_response_get_next_event { uint8_t event_type; /* Followed by event data if any */ union ec_response_get_next_data data; -}; +} __ec_align1; -struct __ec_align1 ec_response_get_next_event_v1 { +struct ec_response_get_next_event_v1 { uint8_t event_type; /* Followed by event data if any */ union ec_response_get_next_data_v1 data; -}; +} __ec_align1; /* Bit indices for buttons and switches.*/ /* Buttons */ @@ -3303,13 +3617,14 @@ struct __ec_align1 ec_response_get_next_event_v1 { /* Switches */ #define EC_MKBP_LID_OPEN 0 #define EC_MKBP_TABLET_MODE 1 +#define EC_MKBP_BASE_ATTACHED 2 /* Run keyboard factory test scanning */ #define EC_CMD_KEYBOARD_FACTORY_TEST 0x0068 -struct __ec_align2 ec_response_keyboard_factory_test { +struct ec_response_keyboard_factory_test { uint16_t shorted; /* Keyboard pins are shorted */ -}; +} __ec_align2; /* Fingerprint events in 'fp_events' for EC_MKBP_EVENT_FINGERPRINT */ #define EC_MKBP_FP_RAW_EVENT(fp_events) ((fp_events) & 0x00FFFFFF) @@ -3321,11 +3636,11 @@ struct __ec_align2 ec_response_keyboard_factory_test { #define EC_MKBP_FP_MATCH_IDX_MASK 0x0000F000 #define EC_MKBP_FP_MATCH_IDX(fpe) (((fpe) & EC_MKBP_FP_MATCH_IDX_MASK) \ >> EC_MKBP_FP_MATCH_IDX_OFFSET) -#define EC_MKBP_FP_ENROLL (1 << 27) -#define EC_MKBP_FP_MATCH (1 << 28) -#define EC_MKBP_FP_FINGER_DOWN (1 << 29) -#define EC_MKBP_FP_FINGER_UP (1 << 30) -#define EC_MKBP_FP_IMAGE_READY (1 << 31) +#define EC_MKBP_FP_ENROLL BIT(27) +#define EC_MKBP_FP_MATCH BIT(28) +#define EC_MKBP_FP_FINGER_DOWN BIT(29) +#define EC_MKBP_FP_FINGER_UP BIT(30) +#define EC_MKBP_FP_IMAGE_READY BIT(31) /* code given by EC_MKBP_FP_ERRCODE() when EC_MKBP_FP_ENROLL is set */ #define EC_MKBP_FP_ERR_ENROLL_OK 0 #define EC_MKBP_FP_ERR_ENROLL_LOW_QUALITY 1 @@ -3337,6 +3652,7 @@ struct __ec_align2 ec_response_keyboard_factory_test { /* code given by EC_MKBP_FP_ERRCODE() when EC_MKBP_FP_MATCH is set */ #define EC_MKBP_FP_ERR_MATCH_NO 0 #define EC_MKBP_FP_ERR_MATCH_NO_INTERNAL 6 +#define EC_MKBP_FP_ERR_MATCH_NO_TEMPLATES 7 #define EC_MKBP_FP_ERR_MATCH_NO_LOW_QUALITY 2 #define EC_MKBP_FP_ERR_MATCH_NO_LOW_COVERAGE 4 #define EC_MKBP_FP_ERR_MATCH_YES 1 @@ -3344,20 +3660,71 @@ struct __ec_align2 ec_response_keyboard_factory_test { #define EC_MKBP_FP_ERR_MATCH_YES_UPDATE_FAILED 5 +#define EC_CMD_MKBP_WAKE_MASK 0x0069 +enum ec_mkbp_event_mask_action { + /* Retrieve the value of a wake mask. */ + GET_WAKE_MASK = 0, + + /* Set the value of a wake mask. */ + SET_WAKE_MASK, +}; + +enum ec_mkbp_mask_type { + /* + * These are host events sent via MKBP. + * + * Some examples are: + * EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) + * EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) + * + * The only things that should be in this mask are: + * EC_HOST_EVENT_MASK(EC_HOST_EVENT_*) + */ + EC_MKBP_HOST_EVENT_WAKE_MASK = 0, + + /* + * These are MKBP events. Some examples are: + * + * EC_MKBP_EVENT_KEY_MATRIX + * EC_MKBP_EVENT_SWITCH + * + * The only things that should be in this mask are EC_MKBP_EVENT_*. + */ + EC_MKBP_EVENT_WAKE_MASK, +}; + +struct ec_params_mkbp_event_wake_mask { + /* One of enum ec_mkbp_event_mask_action */ + uint8_t action; + + /* + * Which MKBP mask are you interested in acting upon? This is one of + * ec_mkbp_mask_type. + */ + uint8_t mask_type; + + /* If setting a new wake mask, this contains the mask to set. */ + uint32_t new_wake_mask; +}; + +struct ec_response_mkbp_event_wake_mask { + uint32_t wake_mask; +}; + /*****************************************************************************/ /* Temperature sensor commands */ /* Read temperature sensor info */ #define EC_CMD_TEMP_SENSOR_GET_INFO 0x0070 -struct __ec_align1 ec_params_temp_sensor_get_info { +struct ec_params_temp_sensor_get_info { uint8_t id; -}; +} __ec_align1; -struct __ec_align1 ec_response_temp_sensor_get_info { +struct ec_response_temp_sensor_get_info { char sensor_name[32]; uint8_t sensor_type; -}; +} __ec_align1; /*****************************************************************************/ @@ -3376,13 +3743,13 @@ struct __ec_align1 ec_response_temp_sensor_get_info { * Host event mask params and response structures, shared by all of the host * event commands below. */ -struct __ec_align4 ec_params_host_event_mask { +struct ec_params_host_event_mask { uint32_t mask; -}; +} __ec_align4; -struct __ec_align4 ec_response_host_event_mask { +struct ec_response_host_event_mask { uint32_t mask; -}; +} __ec_align4; /* These all use ec_response_host_event_mask */ #define EC_CMD_HOST_EVENT_GET_B 0x0087 @@ -3402,7 +3769,7 @@ struct __ec_align4 ec_response_host_event_mask { * of BIOS/OS to program host events and masks */ -struct __ec_align4 ec_params_host_event { +struct ec_params_host_event { /* Action requested by host - one of enum ec_host_event_action. */ uint8_t action; @@ -3418,18 +3785,18 @@ struct __ec_align4 ec_params_host_event { /* Value to be used in case of set operations. */ uint64_t value; -}; +} __ec_align4; /* * Response structure returned by EC_CMD_HOST_EVENT. * Update the value on a GET request. Set to 0 on GET/CLEAR */ -struct __ec_align4 ec_response_host_event { +struct ec_response_host_event { /* Mask value in case of get operation */ uint64_t value; -}; +} __ec_align4; enum ec_host_event_action { /* @@ -3483,21 +3850,21 @@ enum ec_host_event_mask_type { /* Enable/disable LCD backlight */ #define EC_CMD_SWITCH_ENABLE_BKLIGHT 0x0090 -struct __ec_align1 ec_params_switch_enable_backlight { +struct ec_params_switch_enable_backlight { uint8_t enabled; -}; +} __ec_align1; /* Enable/disable WLAN/Bluetooth */ #define EC_CMD_SWITCH_ENABLE_WIRELESS 0x0091 #define EC_VER_SWITCH_ENABLE_WIRELESS 1 /* Version 0 params; no response */ -struct __ec_align1 ec_params_switch_enable_wireless_v0 { +struct ec_params_switch_enable_wireless_v0 { uint8_t enabled; -}; +} __ec_align1; /* Version 1 params */ -struct __ec_align1 ec_params_switch_enable_wireless_v1 { +struct ec_params_switch_enable_wireless_v1 { /* Flags to enable now */ uint8_t now_flags; @@ -3513,16 +3880,16 @@ struct __ec_align1 ec_params_switch_enable_wireless_v1 { /* Which flags to copy from suspend_flags */ uint8_t suspend_mask; -}; +} __ec_align1; /* Version 1 response */ -struct __ec_align1 ec_response_switch_enable_wireless_v1 { +struct ec_response_switch_enable_wireless_v1 { /* Flags to enable now */ uint8_t now_flags; /* Flags to leave enabled in S3 */ uint8_t suspend_flags; -}; +} __ec_align1; /*****************************************************************************/ /* GPIO commands. Only available on EC if write protect has been disabled. */ @@ -3530,25 +3897,25 @@ struct __ec_align1 ec_response_switch_enable_wireless_v1 { /* Set GPIO output value */ #define EC_CMD_GPIO_SET 0x0092 -struct __ec_align1 ec_params_gpio_set { +struct ec_params_gpio_set { char name[32]; uint8_t val; -}; +} __ec_align1; /* Get GPIO value */ #define EC_CMD_GPIO_GET 0x0093 /* Version 0 of input params and response */ -struct __ec_align1 ec_params_gpio_get { +struct ec_params_gpio_get { char name[32]; -}; +} __ec_align1; -struct __ec_align1 ec_response_gpio_get { +struct ec_response_gpio_get { uint8_t val; -}; +} __ec_align1; /* Version 1 of input params and response */ -struct __ec_align1 ec_params_gpio_get_v1 { +struct ec_params_gpio_get_v1 { uint8_t subcmd; union { struct __ec_align1 { @@ -3558,9 +3925,9 @@ struct __ec_align1 ec_params_gpio_get_v1 { uint8_t index; } get_info; }; -}; +} __ec_align1; -struct __ec_todo_packed ec_response_gpio_get_v1 { +struct ec_response_gpio_get_v1 { union { struct __ec_align1 { uint8_t val; @@ -3571,7 +3938,7 @@ struct __ec_todo_packed ec_response_gpio_get_v1 { uint32_t flags; } get_info; }; -}; +} __ec_todo_packed; enum gpio_get_subcmd { EC_GPIO_GET_BY_NAME = 0, @@ -3592,27 +3959,27 @@ enum gpio_get_subcmd { /* Read I2C bus */ #define EC_CMD_I2C_READ 0x0094 -struct __ec_align_size1 ec_params_i2c_read { +struct ec_params_i2c_read { uint16_t addr; /* 8-bit address (7-bit shifted << 1) */ uint8_t read_size; /* Either 8 or 16. */ uint8_t port; uint8_t offset; -}; +} __ec_align_size1; -struct __ec_align2 ec_response_i2c_read { +struct ec_response_i2c_read { uint16_t data; -}; +} __ec_align2; /* Write I2C bus */ #define EC_CMD_I2C_WRITE 0x0095 -struct __ec_align_size1 ec_params_i2c_write { +struct ec_params_i2c_write { uint16_t data; uint16_t addr; /* 8-bit address (7-bit shifted << 1) */ uint8_t write_size; /* Either 8 or 16. */ uint8_t port; uint8_t offset; -}; +} __ec_align_size1; /*****************************************************************************/ /* Charge state commands. Only available when flash write protect unlocked. */ @@ -3629,12 +3996,11 @@ enum ec_charge_control_mode { CHARGE_CONTROL_DISCHARGE, }; -struct __ec_align4 ec_params_charge_control { +struct ec_params_charge_control { uint32_t mode; /* enum charge_control_mode */ -}; +} __ec_align4; /*****************************************************************************/ -/* Console commands. Only available when flash write protect is unlocked. */ /* Snapshot console output buffer for use by EC_CMD_CONSOLE_READ. */ #define EC_CMD_CONSOLE_SNAPSHOT 0x0097 @@ -3658,9 +4024,9 @@ enum ec_console_read_subcmd { CONSOLE_READ_RECENT }; -struct __ec_align1 ec_params_console_read_v1 { +struct ec_params_console_read_v1 { uint8_t subcmd; /* enum ec_console_read_subcmd */ -}; +} __ec_align1; /*****************************************************************************/ @@ -3673,11 +4039,11 @@ struct __ec_align1 ec_params_console_read_v1 { */ #define EC_CMD_BATTERY_CUT_OFF 0x0099 -#define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN (1 << 0) +#define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN BIT(0) -struct __ec_align1 ec_params_battery_cutoff { +struct ec_params_battery_cutoff { uint8_t flags; -}; +} __ec_align1; /*****************************************************************************/ /* USB port mux control. */ @@ -3687,9 +4053,9 @@ struct __ec_align1 ec_params_battery_cutoff { */ #define EC_CMD_USB_MUX 0x009A -struct __ec_align1 ec_params_usb_mux { +struct ec_params_usb_mux { uint8_t mux; -}; +} __ec_align1; /*****************************************************************************/ /* LDOs / FETs control. */ @@ -3704,23 +4070,23 @@ enum ec_ldo_state { */ #define EC_CMD_LDO_SET 0x009B -struct __ec_align1 ec_params_ldo_set { +struct ec_params_ldo_set { uint8_t index; uint8_t state; -}; +} __ec_align1; /* * Get LDO state. */ #define EC_CMD_LDO_GET 0x009C -struct __ec_align1 ec_params_ldo_get { +struct ec_params_ldo_get { uint8_t index; -}; +} __ec_align1; -struct __ec_align1 ec_response_ldo_get { +struct ec_response_ldo_get { uint8_t state; -}; +} __ec_align1; /*****************************************************************************/ /* Power info. */ @@ -3730,13 +4096,13 @@ struct __ec_align1 ec_response_ldo_get { */ #define EC_CMD_POWER_INFO 0x009D -struct __ec_align4 ec_response_power_info { +struct ec_response_power_info { uint32_t usb_dev_type; uint16_t voltage_ac; uint16_t voltage_system; uint16_t current_system; uint16_t usb_current_limit; -}; +} __ec_align4; /*****************************************************************************/ /* I2C passthru command */ @@ -3744,34 +4110,34 @@ struct __ec_align4 ec_response_power_info { #define EC_CMD_I2C_PASSTHRU 0x009E /* Read data; if not present, message is a write */ -#define EC_I2C_FLAG_READ (1 << 15) +#define EC_I2C_FLAG_READ BIT(15) /* Mask for address */ #define EC_I2C_ADDR_MASK 0x3ff -#define EC_I2C_STATUS_NAK (1 << 0) /* Transfer was not acknowledged */ -#define EC_I2C_STATUS_TIMEOUT (1 << 1) /* Timeout during transfer */ +#define EC_I2C_STATUS_NAK BIT(0) /* Transfer was not acknowledged */ +#define EC_I2C_STATUS_TIMEOUT BIT(1) /* Timeout during transfer */ /* Any error */ #define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT) -struct __ec_align2 ec_params_i2c_passthru_msg { - uint16_t addr_flags; /* I2C slave address (7 or 10 bits) and flags */ +struct ec_params_i2c_passthru_msg { + uint16_t addr_flags; /* I2C slave address and flags */ uint16_t len; /* Number of bytes to read or write */ -}; +} __ec_align2; -struct __ec_align2 ec_params_i2c_passthru { +struct ec_params_i2c_passthru { uint8_t port; /* I2C port number */ uint8_t num_msgs; /* Number of messages */ struct ec_params_i2c_passthru_msg msg[]; /* Data to write for all messages is concatenated here */ -}; +} __ec_align2; -struct __ec_align1 ec_response_i2c_passthru { +struct ec_response_i2c_passthru { uint8_t i2c_status; /* Status flags (EC_I2C_STATUS_...) */ uint8_t num_msgs; /* Number of messages processed */ uint8_t data[]; /* Data read by messages concatenated here */ -}; +} __ec_align1; /*****************************************************************************/ /* Power button hang detect */ @@ -3780,27 +4146,27 @@ struct __ec_align1 ec_response_i2c_passthru { /* Reasons to start hang detection timer */ /* Power button pressed */ -#define EC_HANG_START_ON_POWER_PRESS (1 << 0) +#define EC_HANG_START_ON_POWER_PRESS BIT(0) /* Lid closed */ -#define EC_HANG_START_ON_LID_CLOSE (1 << 1) +#define EC_HANG_START_ON_LID_CLOSE BIT(1) /* Lid opened */ -#define EC_HANG_START_ON_LID_OPEN (1 << 2) +#define EC_HANG_START_ON_LID_OPEN BIT(2) /* Start of AP S3->S0 transition (booting or resuming from suspend) */ -#define EC_HANG_START_ON_RESUME (1 << 3) +#define EC_HANG_START_ON_RESUME BIT(3) /* Reasons to cancel hang detection */ /* Power button released */ -#define EC_HANG_STOP_ON_POWER_RELEASE (1 << 8) +#define EC_HANG_STOP_ON_POWER_RELEASE BIT(8) /* Any host command from AP received */ -#define EC_HANG_STOP_ON_HOST_COMMAND (1 << 9) +#define EC_HANG_STOP_ON_HOST_COMMAND BIT(9) /* Stop on end of AP S0->S3 transition (suspending or shutting down) */ -#define EC_HANG_STOP_ON_SUSPEND (1 << 10) +#define EC_HANG_STOP_ON_SUSPEND BIT(10) /* * If this flag is set, all the other fields are ignored, and the hang detect @@ -3808,16 +4174,16 @@ struct __ec_align1 ec_response_i2c_passthru { * without reconfiguring any of the other hang detect settings. Note that * you must previously have configured the timeouts. */ -#define EC_HANG_START_NOW (1 << 30) +#define EC_HANG_START_NOW BIT(30) /* * If this flag is set, all the other fields are ignored (including * EC_HANG_START_NOW). This provides the AP a way to stop the hang timer * without reconfiguring any of the other hang detect settings. */ -#define EC_HANG_STOP_NOW (1 << 31) +#define EC_HANG_STOP_NOW BIT(31) -struct __ec_align4 ec_params_hang_detect { +struct ec_params_hang_detect { /* Flags; see EC_HANG_* */ uint32_t flags; @@ -3826,7 +4192,7 @@ struct __ec_align4 ec_params_hang_detect { /* Timeout in msec before generating warm reboot, if enabled */ uint16_t warm_reboot_timeout_msec; -}; +} __ec_align4; /*****************************************************************************/ /* Commands for battery charging */ @@ -3881,7 +4247,7 @@ enum charge_state_params { /* Other custom param ranges go here... */ }; -struct __ec_todo_packed ec_params_charge_state { +struct ec_params_charge_state { uint8_t cmd; /* enum charge_state_command */ union { /* get_state has no args */ @@ -3895,9 +4261,9 @@ struct __ec_todo_packed ec_params_charge_state { uint32_t value; /* value to set */ } set_param; }; -}; +} __ec_todo_packed; -struct __ec_align4 ec_response_charge_state { +struct ec_response_charge_state { union { struct __ec_align4 { int ac; @@ -3913,7 +4279,7 @@ struct __ec_align4 ec_response_charge_state { /* set_param returns no args */ }; -}; +} __ec_align4; /* @@ -3921,9 +4287,9 @@ struct __ec_align4 ec_response_charge_state { */ #define EC_CMD_CHARGE_CURRENT_LIMIT 0x00A1 -struct __ec_align4 ec_params_current_limit { +struct ec_params_current_limit { uint32_t limit; /* in mA */ -}; +} __ec_align4; /* * Set maximum external voltage / current. @@ -3931,10 +4297,10 @@ struct __ec_align4 ec_params_current_limit { #define EC_CMD_EXTERNAL_POWER_LIMIT 0x00A2 /* Command v0 is used only on Spring and is obsolete + unsupported */ -struct __ec_align2 ec_params_external_power_limit_v1 { +struct ec_params_external_power_limit_v1 { uint16_t current_lim; /* in mA, or EC_POWER_LIMIT_NONE to clear limit */ uint16_t voltage_lim; /* in mV, or EC_POWER_LIMIT_NONE to clear limit */ -}; +} __ec_align2; #define EC_POWER_LIMIT_NONE 0xffff @@ -3943,10 +4309,10 @@ struct __ec_align2 ec_params_external_power_limit_v1 { */ #define EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT 0x00A3 -struct __ec_align2 ec_params_dedicated_charger_limit { +struct ec_params_dedicated_charger_limit { uint16_t current_lim; /* in mA */ uint16_t voltage_lim; /* in mV */ -}; +} __ec_align2; /*****************************************************************************/ /* Hibernate/Deep Sleep Commands */ @@ -3954,15 +4320,15 @@ struct __ec_align2 ec_params_dedicated_charger_limit { /* Set the delay before going into hibernation. */ #define EC_CMD_HIBERNATION_DELAY 0x00A8 -struct __ec_align4 ec_params_hibernation_delay { +struct ec_params_hibernation_delay { /* * Seconds to wait in G3 before hibernate. Pass in 0 to read the * current settings without changing them. */ uint32_t seconds; -}; +} __ec_align4; -struct __ec_align4 ec_response_hibernation_delay { +struct ec_response_hibernation_delay { /* * The current time in seconds in which the system has been in the G3 * state. This value is reset if the EC transitions out of G3. @@ -3980,7 +4346,7 @@ struct __ec_align4 ec_response_hibernation_delay { * hibernating. */ uint32_t hibernate_delay; -}; +} __ec_align4; /* Inform the EC when entering a sleep state */ #define EC_CMD_HOST_SLEEP_EVENT 0x00A9 @@ -3994,9 +4360,66 @@ enum host_sleep_event { HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND = 5, }; -struct __ec_align1 ec_params_host_sleep_event { +struct ec_params_host_sleep_event { uint8_t sleep_event; -}; +} __ec_align1; + +/* + * Use a default timeout value (CONFIG_SLEEP_TIMEOUT_MS) for detecting sleep + * transition failures + */ +#define EC_HOST_SLEEP_TIMEOUT_DEFAULT 0 + +/* Disable timeout detection for this sleep transition */ +#define EC_HOST_SLEEP_TIMEOUT_INFINITE 0xFFFF + +struct ec_params_host_sleep_event_v1 { + /* The type of sleep being entered or exited. */ + uint8_t sleep_event; + + /* Padding */ + uint8_t reserved; + union { + /* Parameters that apply for suspend messages. */ + struct { + /* + * The timeout in milliseconds between when this message + * is received and when the EC will declare sleep + * transition failure if the sleep signal is not + * asserted. + */ + uint16_t sleep_timeout_ms; + } suspend_params; + + /* No parameters for non-suspend messages. */ + }; +} __ec_align2; + +/* A timeout occurred when this bit is set */ +#define EC_HOST_RESUME_SLEEP_TIMEOUT 0x80000000 + +/* + * The mask defining which bits correspond to the number of sleep transitions, + * as well as the maximum number of suspend line transitions that will be + * reported back to the host. + */ +#define EC_HOST_RESUME_SLEEP_TRANSITIONS_MASK 0x7FFFFFFF + +struct ec_response_host_sleep_event_v1 { + union { + /* Response fields that apply for resume messages. */ + struct { + /* + * The number of sleep power signal transitions that + * occurred since the suspend message. The high bit + * indicates a timeout occurred. + */ + uint32_t sleep_transitions; + } resume_response; + + /* No response fields for non-resume messages. */ + }; +} __ec_align4; /*****************************************************************************/ /* Device events */ @@ -4017,16 +4440,16 @@ enum ec_device_event_param { EC_DEVICE_EVENT_PARAM_SET_ENABLED_EVENTS, }; -#define EC_DEVICE_EVENT_MASK(event_code) (1UL << (event_code % 32)) +#define EC_DEVICE_EVENT_MASK(event_code) BIT(event_code % 32) -struct __ec_align_size1 ec_params_device_event { +struct ec_params_device_event { uint32_t event_mask; uint8_t param; -}; +} __ec_align_size1; -struct __ec_align4 ec_response_device_event { +struct ec_response_device_event { uint32_t event_mask; -}; +} __ec_align4; /*****************************************************************************/ /* Smart battery pass-through */ @@ -4041,27 +4464,27 @@ struct __ec_align4 ec_response_device_event { #define EC_CMD_SB_READ_BLOCK 0x00B2 #define EC_CMD_SB_WRITE_BLOCK 0x00B3 -struct __ec_align1 ec_params_sb_rd { +struct ec_params_sb_rd { uint8_t reg; -}; +} __ec_align1; -struct __ec_align2 ec_response_sb_rd_word { +struct ec_response_sb_rd_word { uint16_t value; -}; +} __ec_align2; -struct __ec_align1 ec_params_sb_wr_word { +struct ec_params_sb_wr_word { uint8_t reg; uint16_t value; -}; +} __ec_align1; -struct __ec_align1 ec_response_sb_rd_block { +struct ec_response_sb_rd_block { uint8_t data[32]; -}; +} __ec_align1; -struct __ec_align1 ec_params_sb_wr_block { +struct ec_params_sb_wr_block { uint8_t reg; uint16_t data[32]; -}; +} __ec_align1; /*****************************************************************************/ /* Battery vendor parameters @@ -4079,15 +4502,15 @@ enum ec_battery_vendor_param_mode { BATTERY_VENDOR_PARAM_MODE_SET, }; -struct __ec_align_size1 ec_params_battery_vendor_param { +struct ec_params_battery_vendor_param { uint32_t param; uint32_t value; uint8_t mode; -}; +} __ec_align_size1; -struct __ec_align4 ec_response_battery_vendor_param { +struct ec_response_battery_vendor_param { uint32_t value; -}; +} __ec_align4; /*****************************************************************************/ /* @@ -4110,12 +4533,12 @@ enum ec_sb_fw_update_subcmd { #define SB_FW_UPDATE_CMD_STATUS_SIZE 2 #define SB_FW_UPDATE_CMD_INFO_SIZE 8 -struct __ec_align4 ec_sb_fw_update_header { +struct ec_sb_fw_update_header { uint16_t subcmd; /* enum ec_sb_fw_update_subcmd */ uint16_t fw_id; /* firmware id */ -}; +} __ec_align4; -struct __ec_align4 ec_params_sb_fw_update { +struct ec_params_sb_fw_update { struct ec_sb_fw_update_header hdr; union { /* EC_SB_FW_UPDATE_PREPARE = 0x0 */ @@ -4131,9 +4554,9 @@ struct __ec_align4 ec_params_sb_fw_update { uint8_t data[SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE]; } write; }; -}; +} __ec_align4; -struct __ec_align1 ec_response_sb_fw_update { +struct ec_response_sb_fw_update { union { /* EC_SB_FW_UPDATE_INFO = 0x1 */ struct __ec_align1 { @@ -4145,7 +4568,7 @@ struct __ec_align1 ec_response_sb_fw_update { uint8_t data[SB_FW_UPDATE_CMD_STATUS_SIZE]; } status; }; -}; +} __ec_align1; /* * Entering Verified Boot Mode Command @@ -4154,9 +4577,9 @@ struct __ec_align1 ec_response_sb_fw_update { */ #define EC_CMD_ENTERING_MODE 0x00B6 -struct __ec_align4 ec_params_entering_mode { +struct ec_params_entering_mode { int vboot_mode; -}; +} __ec_align4; #define VBOOT_MODE_NORMAL 0 #define VBOOT_MODE_DEVELOPER 1 @@ -4170,23 +4593,24 @@ struct __ec_align4 ec_params_entering_mode { #define EC_CMD_I2C_PASSTHRU_PROTECT 0x00B7 enum ec_i2c_passthru_protect_subcmd { - EC_CMD_I2C_PASSTHRU_PROTECT_STATUS = 0x0, - EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE = 0x1, + EC_CMD_I2C_PASSTHRU_PROTECT_STATUS = 0, + EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE = 1, + EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE_TCPCS = 2, }; -struct __ec_align1 ec_params_i2c_passthru_protect { +struct ec_params_i2c_passthru_protect { uint8_t subcmd; uint8_t port; /* I2C port number */ -}; +} __ec_align1; -struct __ec_align1 ec_response_i2c_passthru_protect { +struct ec_response_i2c_passthru_protect { uint8_t status; /* Status flags (0: unlocked, 1: locked) */ -}; +} __ec_align1; /*****************************************************************************/ /* - * HDMI CEC commands + * HDMI CEC commands * * These commands are for sending and receiving message via HDMI CEC */ @@ -4196,30 +4620,53 @@ struct __ec_align1 ec_response_i2c_passthru_protect { /* CEC message from the AP to be written on the CEC bus */ #define EC_CMD_CEC_WRITE_MSG 0x00B8 -/* Message to write to the CEC bus */ -struct __ec_align1 ec_params_cec_write { +/** + * struct ec_params_cec_write - Message to write to the CEC bus + * @msg: message content to write to the CEC bus + */ +struct ec_params_cec_write { uint8_t msg[MAX_CEC_MSG_LEN]; -}; +} __ec_align1; /* Set various CEC parameters */ #define EC_CMD_CEC_SET 0x00BA -struct __ec_align1 ec_params_cec_set { +/** + * struct ec_params_cec_set - CEC parameters set + * @cmd: parameter type, can be CEC_CMD_ENABLE or CEC_CMD_LOGICAL_ADDRESS + * @val: in case cmd is CEC_CMD_ENABLE, this field can be 0 to disable CEC + * or 1 to enable CEC functionality, in case cmd is + * CEC_CMD_LOGICAL_ADDRESS, this field encodes the requested logical + * address between 0 and 15 or 0xff to unregister + */ +struct ec_params_cec_set { uint8_t cmd; /* enum cec_command */ uint8_t val; -}; +} __ec_align1; /* Read various CEC parameters */ #define EC_CMD_CEC_GET 0x00BB -struct __ec_align1 ec_params_cec_get { +/** + * struct ec_params_cec_get - CEC parameters get + * @cmd: parameter type, can be CEC_CMD_ENABLE or CEC_CMD_LOGICAL_ADDRESS + */ +struct ec_params_cec_get { uint8_t cmd; /* enum cec_command */ -}; +} __ec_align1; -struct __ec_align1 ec_response_cec_get { +/** + * struct ec_response_cec_get - CEC parameters get response + * @val: in case cmd was CEC_CMD_ENABLE, this field will 0 if CEC is + * disabled or 1 if CEC functionality is enabled, + * in case cmd was CEC_CMD_LOGICAL_ADDRESS, this will encode the + * configured logical address between 0 and 15 or 0xff if unregistered + */ +struct ec_response_cec_get { uint8_t val; -}; +} __ec_align1; +/* CEC parameters command */ enum cec_command { /* CEC reading, writing and events enable */ CEC_CMD_ENABLE, @@ -4230,11 +4677,100 @@ enum cec_command { /* Events from CEC to AP */ enum mkbp_cec_event { /* Outgoing message was acknowledged by a follower */ - EC_MKBP_CEC_SEND_OK = 1 << 0, + EC_MKBP_CEC_SEND_OK = BIT(0), /* Outgoing message was not acknowledged */ - EC_MKBP_CEC_SEND_FAILED = 1 << 1, + EC_MKBP_CEC_SEND_FAILED = BIT(1), }; +/*****************************************************************************/ + +/* Commands for I2S recording on audio codec. */ + +#define EC_CMD_CODEC_I2S 0x00BC +#define EC_WOV_I2S_SAMPLE_RATE 48000 + +enum ec_codec_i2s_subcmd { + EC_CODEC_SET_SAMPLE_DEPTH = 0x0, + EC_CODEC_SET_GAIN = 0x1, + EC_CODEC_GET_GAIN = 0x2, + EC_CODEC_I2S_ENABLE = 0x3, + EC_CODEC_I2S_SET_CONFIG = 0x4, + EC_CODEC_I2S_SET_TDM_CONFIG = 0x5, + EC_CODEC_I2S_SET_BCLK = 0x6, + EC_CODEC_I2S_SUBCMD_COUNT = 0x7, +}; + +enum ec_sample_depth_value { + EC_CODEC_SAMPLE_DEPTH_16 = 0, + EC_CODEC_SAMPLE_DEPTH_24 = 1, +}; + +enum ec_i2s_config { + EC_DAI_FMT_I2S = 0, + EC_DAI_FMT_RIGHT_J = 1, + EC_DAI_FMT_LEFT_J = 2, + EC_DAI_FMT_PCM_A = 3, + EC_DAI_FMT_PCM_B = 4, + EC_DAI_FMT_PCM_TDM = 5, +}; + +/* + * For subcommand EC_CODEC_GET_GAIN. + */ +struct __ec_align1 ec_codec_i2s_gain { + uint8_t left; + uint8_t right; +}; + +struct __ec_todo_unpacked ec_param_codec_i2s_tdm { + int16_t ch0_delay; /* 0 to 496 */ + int16_t ch1_delay; /* -1 to 496 */ + uint8_t adjacent_to_ch0; + uint8_t adjacent_to_ch1; +}; + +struct __ec_todo_packed ec_param_codec_i2s { + /* enum ec_codec_i2s_subcmd */ + uint8_t cmd; + union { + /* + * EC_CODEC_SET_SAMPLE_DEPTH + * Value should be one of ec_sample_depth_value. + */ + uint8_t depth; + + /* + * EC_CODEC_SET_GAIN + * Value should be 0~43 for both channels. + */ + struct ec_codec_i2s_gain gain; + + /* + * EC_CODEC_I2S_ENABLE + * 1 to enable, 0 to disable. + */ + uint8_t i2s_enable; + + /* + * EC_CODEC_I2S_SET_CONFIG + * Value should be one of ec_i2s_config. + */ + uint8_t i2s_config; + + /* + * EC_CODEC_I2S_SET_TDM_CONFIG + * Value should be one of ec_i2s_config. + */ + struct ec_param_codec_i2s_tdm tdm_param; + + /* + * EC_CODEC_I2S_SET_BCLK + */ + uint32_t bclk; + }; +}; + + /*****************************************************************************/ /* System commands */ @@ -4257,14 +4793,14 @@ enum ec_reboot_cmd { }; /* Flags for ec_params_reboot_ec.reboot_flags */ -#define EC_REBOOT_FLAG_RESERVED0 (1 << 0) /* Was recovery request */ -#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN (1 << 1) /* Reboot after AP shutdown */ -#define EC_REBOOT_FLAG_SWITCH_RW_SLOT (1 << 2) /* Switch RW slot */ +#define EC_REBOOT_FLAG_RESERVED0 BIT(0) /* Was recovery request */ +#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN BIT(1) /* Reboot after AP shutdown */ +#define EC_REBOOT_FLAG_SWITCH_RW_SLOT BIT(2) /* Switch RW slot */ -struct __ec_align1 ec_params_reboot_ec { +struct ec_params_reboot_ec { uint8_t cmd; /* enum ec_reboot_cmd */ uint8_t flags; /* See EC_REBOOT_FLAG_* */ -}; +} __ec_align1; /* * Get information on last EC panic. @@ -4333,42 +4869,42 @@ enum pd_charge_state { }; /* Status of EC being sent to PD */ -#define EC_STATUS_HIBERNATING (1 << 0) +#define EC_STATUS_HIBERNATING BIT(0) -struct __ec_align1 ec_params_pd_status { +struct ec_params_pd_status { uint8_t status; /* EC status */ int8_t batt_soc; /* battery state of charge */ uint8_t charge_state; /* charging state (from enum pd_charge_state) */ -}; +} __ec_align1; /* Status of PD being sent back to EC */ -#define PD_STATUS_HOST_EVENT (1 << 0) /* Forward host event to AP */ -#define PD_STATUS_IN_RW (1 << 1) /* Running RW image */ -#define PD_STATUS_JUMPED_TO_IMAGE (1 << 2) /* Current image was jumped to */ -#define PD_STATUS_TCPC_ALERT_0 (1 << 3) /* Alert active in port 0 TCPC */ -#define PD_STATUS_TCPC_ALERT_1 (1 << 4) /* Alert active in port 1 TCPC */ -#define PD_STATUS_TCPC_ALERT_2 (1 << 5) /* Alert active in port 2 TCPC */ -#define PD_STATUS_TCPC_ALERT_3 (1 << 6) /* Alert active in port 3 TCPC */ +#define PD_STATUS_HOST_EVENT BIT(0) /* Forward host event to AP */ +#define PD_STATUS_IN_RW BIT(1) /* Running RW image */ +#define PD_STATUS_JUMPED_TO_IMAGE BIT(2) /* Current image was jumped to */ +#define PD_STATUS_TCPC_ALERT_0 BIT(3) /* Alert active in port 0 TCPC */ +#define PD_STATUS_TCPC_ALERT_1 BIT(4) /* Alert active in port 1 TCPC */ +#define PD_STATUS_TCPC_ALERT_2 BIT(5) /* Alert active in port 2 TCPC */ +#define PD_STATUS_TCPC_ALERT_3 BIT(6) /* Alert active in port 3 TCPC */ #define PD_STATUS_EC_INT_ACTIVE (PD_STATUS_TCPC_ALERT_0 | \ PD_STATUS_TCPC_ALERT_1 | \ PD_STATUS_HOST_EVENT) -struct __ec_align_size1 ec_response_pd_status { +struct ec_response_pd_status { uint32_t curr_lim_ma; /* input current limit */ uint16_t status; /* PD MCU status */ int8_t active_charge_port; /* active charging port */ -}; +} __ec_align_size1; /* AP to PD MCU host event status command, cleared on read */ #define EC_CMD_PD_HOST_EVENT_STATUS 0x0104 /* PD MCU host event status bits */ -#define PD_EVENT_UPDATE_DEVICE (1 << 0) -#define PD_EVENT_POWER_CHANGE (1 << 1) -#define PD_EVENT_IDENTITY_RECEIVED (1 << 2) -#define PD_EVENT_DATA_SWAP (1 << 3) -struct __ec_align4 ec_response_host_event_status { +#define PD_EVENT_UPDATE_DEVICE BIT(0) +#define PD_EVENT_POWER_CHANGE BIT(1) +#define PD_EVENT_IDENTITY_RECEIVED BIT(2) +#define PD_EVENT_DATA_SWAP BIT(3) +struct ec_response_host_event_status { uint32_t status; /* PD MCU host event status */ -}; +} __ec_align4; /* Set USB type-C port role and muxes */ #define EC_CMD_USB_PD_CONTROL 0x0101 @@ -4401,54 +4937,76 @@ enum usb_pd_control_swap { USB_PD_CTRL_SWAP_COUNT }; -struct __ec_align1 ec_params_usb_pd_control { +struct ec_params_usb_pd_control { uint8_t port; uint8_t role; uint8_t mux; uint8_t swap; -}; +} __ec_align1; -#define PD_CTRL_RESP_ENABLED_COMMS (1 << 0) /* Communication enabled */ -#define PD_CTRL_RESP_ENABLED_CONNECTED (1 << 1) /* Device connected */ -#define PD_CTRL_RESP_ENABLED_PD_CAPABLE (1 << 2) /* Partner is PD capable */ +#define PD_CTRL_RESP_ENABLED_COMMS BIT(0) /* Communication enabled */ +#define PD_CTRL_RESP_ENABLED_CONNECTED BIT(1) /* Device connected */ +#define PD_CTRL_RESP_ENABLED_PD_CAPABLE BIT(2) /* Partner is PD capable */ -#define PD_CTRL_RESP_ROLE_POWER (1 << 0) /* 0=SNK/1=SRC */ -#define PD_CTRL_RESP_ROLE_DATA (1 << 1) /* 0=UFP/1=DFP */ -#define PD_CTRL_RESP_ROLE_VCONN (1 << 2) /* Vconn status */ -#define PD_CTRL_RESP_ROLE_DR_POWER (1 << 3) /* Partner is dualrole power */ -#define PD_CTRL_RESP_ROLE_DR_DATA (1 << 4) /* Partner is dualrole data */ -#define PD_CTRL_RESP_ROLE_USB_COMM (1 << 5) /* Partner USB comm capable */ -#define PD_CTRL_RESP_ROLE_EXT_POWERED (1 << 6) /* Partner externally powerd */ +#define PD_CTRL_RESP_ROLE_POWER BIT(0) /* 0=SNK/1=SRC */ +#define PD_CTRL_RESP_ROLE_DATA BIT(1) /* 0=UFP/1=DFP */ +#define PD_CTRL_RESP_ROLE_VCONN BIT(2) /* Vconn status */ +#define PD_CTRL_RESP_ROLE_DR_POWER BIT(3) /* Partner is dualrole power */ +#define PD_CTRL_RESP_ROLE_DR_DATA BIT(4) /* Partner is dualrole data */ +#define PD_CTRL_RESP_ROLE_USB_COMM BIT(5) /* Partner USB comm capable */ +#define PD_CTRL_RESP_ROLE_EXT_POWERED BIT(6) /* Partner externally powerd */ -struct __ec_align1 ec_response_usb_pd_control { +struct ec_response_usb_pd_control { uint8_t enabled; uint8_t role; uint8_t polarity; uint8_t state; -}; +} __ec_align1; -struct __ec_align1 ec_response_usb_pd_control_v1 { +struct ec_response_usb_pd_control_v1 { uint8_t enabled; uint8_t role; uint8_t polarity; char state[32]; -}; +} __ec_align1; + +/* Values representing usbc PD CC state */ +#define USBC_PD_CC_NONE 0 /* No accessory connected */ +#define USBC_PD_CC_NO_UFP 1 /* No UFP accessory connected */ +#define USBC_PD_CC_AUDIO_ACC 2 /* Audio accessory connected */ +#define USBC_PD_CC_DEBUG_ACC 3 /* Debug accessory connected */ +#define USBC_PD_CC_UFP_ATTACHED 4 /* UFP attached to usbc */ +#define USBC_PD_CC_DFP_ATTACHED 5 /* DPF attached to usbc */ + +#define USBC_CABLE_TYPE_UNDEF 0 /* Undefined */ +#define USBC_CABLE_TYPE_PASSIVE 3 /* Passive cable attached */ +#define USBC_CABLE_TYPE_ACTIVE 4 /* Active cable attached */ + +struct ec_response_usb_pd_control_v2 { + uint8_t enabled; + uint8_t role; + uint8_t polarity; + char state[32]; + uint8_t cc_state; /* USBC_PD_CC_*Encoded cc state */ + uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */ + uint8_t cable_type; /* USBC_CABLE_TYPE_*cable_type */ +} __ec_align1; #define EC_CMD_USB_PD_PORTS 0x0102 /* Maximum number of PD ports on a device, num_ports will be <= this */ #define EC_USB_PD_MAX_PORTS 8 -struct __ec_align1 ec_response_usb_pd_ports { +struct ec_response_usb_pd_ports { uint8_t num_ports; -}; +} __ec_align1; #define EC_CMD_USB_PD_POWER_INFO 0x0103 #define PD_POWER_CHARGING_PORT 0xff -struct __ec_align1 ec_params_usb_pd_power_info { +struct ec_params_usb_pd_power_info { uint8_t port; -}; +} __ec_align1; enum usb_chg_type { USB_CHG_TYPE_NONE, @@ -4470,21 +5028,21 @@ enum usb_power_roles { USB_PD_PORT_POWER_SINK_NOT_CHARGING, }; -struct __ec_align2 usb_chg_measures { +struct usb_chg_measures { uint16_t voltage_max; uint16_t voltage_now; uint16_t current_max; uint16_t current_lim; -}; +} __ec_align2; -struct __ec_align4 ec_response_usb_pd_power_info { +struct ec_response_usb_pd_power_info { uint8_t role; uint8_t type; uint8_t dualrole; uint8_t reserved1; struct usb_chg_measures meas; uint32_t max_power; -}; +} __ec_align4; /* @@ -4493,9 +5051,9 @@ struct __ec_align4 ec_response_usb_pd_power_info { * EC_CMD_USB_PD_PORTS does NOT include the dedicated ports */ #define EC_CMD_CHARGE_PORT_COUNT 0x0105 -struct __ec_align1 ec_response_charge_port_count { +struct ec_response_charge_port_count { uint8_t port_count; -}; +} __ec_align1; /* Write USB-PD device FW */ #define EC_CMD_USB_PD_FW_UPDATE 0x0110 @@ -4507,41 +5065,43 @@ enum usb_pd_fw_update_cmds { USB_PD_FW_ERASE_SIG, }; -struct __ec_align4 ec_params_usb_pd_fw_update { +struct ec_params_usb_pd_fw_update { uint16_t dev_id; uint8_t cmd; uint8_t port; uint32_t size; /* Size to write in bytes */ /* Followed by data to write */ -}; +} __ec_align4; /* Write USB-PD Accessory RW_HASH table entry */ #define EC_CMD_USB_PD_RW_HASH_ENTRY 0x0111 /* RW hash is first 20 bytes of SHA-256 of RW section */ #define PD_RW_HASH_SIZE 20 -struct __ec_align1 ec_params_usb_pd_rw_hash_entry { +struct ec_params_usb_pd_rw_hash_entry { uint16_t dev_id; uint8_t dev_rw_hash[PD_RW_HASH_SIZE]; - uint8_t reserved; /* For alignment of current_image + uint8_t reserved; /* + * For alignment of current_image * TODO(rspangler) but it's not aligned! - * Should have been reserved[2]. */ + * Should have been reserved[2]. + */ uint32_t current_image; /* One of ec_current_image */ -}; +} __ec_align1; /* Read USB-PD Accessory info */ #define EC_CMD_USB_PD_DEV_INFO 0x0112 -struct __ec_align1 ec_params_usb_pd_info_request { +struct ec_params_usb_pd_info_request { uint8_t port; -}; +} __ec_align1; /* Read USB-PD Device discovery info */ #define EC_CMD_USB_PD_DISCOVERY 0x0113 -struct __ec_align_size1 ec_params_usb_pd_discovery_entry { +struct ec_params_usb_pd_discovery_entry { uint16_t vid; /* USB-IF VID */ uint16_t pid; /* USB-IF PID */ uint8_t ptype; /* product type (hub,periph,cable,ama) */ -}; +} __ec_align_size1; /* Override default charge behavior */ #define EC_CMD_PD_CHARGE_PORT_OVERRIDE 0x0114 @@ -4553,9 +5113,9 @@ enum usb_pd_override_ports { /* [0, CONFIG_USB_PD_PORT_COUNT): Port# */ }; -struct __ec_align2 ec_params_charge_port_override { +struct ec_params_charge_port_override { int16_t override_port; /* Override port# */ -}; +} __ec_align2; /* * Read (and delete) one entry of PD event log. @@ -4564,14 +5124,13 @@ struct __ec_align2 ec_params_charge_port_override { */ #define EC_CMD_PD_GET_LOG_ENTRY 0x0115 -struct __ec_align4 ec_response_pd_log { +struct ec_response_pd_log { uint32_t timestamp; /* relative timestamp in milliseconds */ uint8_t type; /* event type : see PD_EVENT_xx below */ uint8_t size_port; /* [7:5] port number [4:0] payload size in bytes */ uint16_t data; /* type-defined data payload */ uint8_t payload[0]; /* optional additional data payload: 0..16 bytes */ -}; - +} __ec_align4; /* The timestamp is the microsecond counter shifted to get about a ms. */ #define PD_LOG_TIMESTAMP_SHIFT 10 /* 1 LSB = 1024us */ @@ -4611,11 +5170,11 @@ struct __ec_align4 ec_response_pd_log { * the data field contains the port state flags as defined below : */ /* Port partner is a dual role device */ -#define CHARGE_FLAGS_DUAL_ROLE (1 << 15) +#define CHARGE_FLAGS_DUAL_ROLE BIT(15) /* Port is the pending override port */ -#define CHARGE_FLAGS_DELAYED_OVERRIDE (1 << 14) +#define CHARGE_FLAGS_DELAYED_OVERRIDE BIT(14) /* Port is the override port */ -#define CHARGE_FLAGS_OVERRIDE (1 << 13) +#define CHARGE_FLAGS_OVERRIDE BIT(13) /* Charger type */ #define CHARGE_FLAGS_TYPE_SHIFT 3 #define CHARGE_FLAGS_TYPE_MASK (0xf << CHARGE_FLAGS_TYPE_SHIFT) @@ -4633,18 +5192,18 @@ struct __ec_align4 ec_response_pd_log { /* * PD_EVENT_VIDEO_CODEC payload is "struct mcdp_info". */ -struct __ec_align4 mcdp_version { +struct mcdp_version { uint8_t major; uint8_t minor; uint16_t build; -}; +} __ec_align4; -struct __ec_align4 mcdp_info { +struct mcdp_info { uint8_t family[2]; uint8_t chipid[2]; struct mcdp_version irom; struct mcdp_version fw; -}; +} __ec_align4; /* struct mcdp_info field decoding */ #define MCDP_CHIPID(chipid) ((chipid[0] << 8) | chipid[1]) @@ -4652,16 +5211,16 @@ struct __ec_align4 mcdp_info { /* Get/Set USB-PD Alternate mode info */ #define EC_CMD_USB_PD_GET_AMODE 0x0116 -struct __ec_align_size1 ec_params_usb_pd_get_mode_request { +struct ec_params_usb_pd_get_mode_request { uint16_t svid_idx; /* SVID index to get */ uint8_t port; /* port */ -}; +} __ec_align_size1; -struct __ec_align4 ec_params_usb_pd_get_mode_response { +struct ec_params_usb_pd_get_mode_response { uint16_t svid; /* SVID */ uint16_t opos; /* Object Position */ uint32_t vdo[6]; /* Mode VDOs */ -}; +} __ec_align4; #define EC_CMD_USB_PD_SET_AMODE 0x0117 @@ -4672,20 +5231,20 @@ enum pd_mode_cmd { PD_MODE_CMD_COUNT, }; -struct __ec_align4 ec_params_usb_pd_set_mode_request { +struct ec_params_usb_pd_set_mode_request { uint32_t cmd; /* enum pd_mode_cmd */ uint16_t svid; /* SVID to set */ uint8_t opos; /* Object Position */ uint8_t port; /* port */ -}; +} __ec_align4; /* Ask the PD MCU to record a log of a requested type */ #define EC_CMD_PD_WRITE_LOG_ENTRY 0x0118 -struct __ec_align1 ec_params_pd_write_log_entry { +struct ec_params_pd_write_log_entry { uint8_t type; /* event type : see PD_EVENT_xx above */ uint8_t port; /* port#, or 0 for events unrelated to a given port */ -}; +} __ec_align1; /* Control USB-PD chip */ @@ -4699,36 +5258,43 @@ enum ec_pd_control_cmd { PD_CHIP_ON, /* Power on the PD chip */ }; -struct __ec_align1 ec_params_pd_control { +struct ec_params_pd_control { uint8_t chip; /* chip id */ uint8_t subcmd; -}; +} __ec_align1; /* Get info about USB-C SS muxes */ #define EC_CMD_USB_PD_MUX_INFO 0x011A -struct __ec_align1 ec_params_usb_pd_mux_info { +struct ec_params_usb_pd_mux_info { uint8_t port; /* USB-C port number */ -}; +} __ec_align1; /* Flags representing mux state */ -#define USB_PD_MUX_USB_ENABLED (1 << 0) -#define USB_PD_MUX_DP_ENABLED (1 << 1) -#define USB_PD_MUX_POLARITY_INVERTED (1 << 2) -#define USB_PD_MUX_HPD_IRQ (1 << 3) +#define USB_PD_MUX_USB_ENABLED BIT(0) /* USB connected */ +#define USB_PD_MUX_DP_ENABLED BIT(1) /* DP connected */ +#define USB_PD_MUX_POLARITY_INVERTED BIT(2) /* CC line Polarity inverted */ +#define USB_PD_MUX_HPD_IRQ BIT(3) /* HPD IRQ is asserted */ +#define USB_PD_MUX_HPD_LVL BIT(4) /* HPD level is asserted */ +#define USB_PD_MUX_SAFE_MODE BIT(5) /* DP is in safe mode */ -struct __ec_align1 ec_response_usb_pd_mux_info { +struct ec_response_usb_pd_mux_info { uint8_t flags; /* USB_PD_MUX_*-encoded USB mux state */ -}; +} __ec_align1; #define EC_CMD_PD_CHIP_INFO 0x011B -struct __ec_align1 ec_params_pd_chip_info { +struct ec_params_pd_chip_info { uint8_t port; /* USB-C port number */ - uint8_t renew; /* Force renewal */ -}; + /* + * Fetch the live chip info or hard-coded + cached chip info + * 0: hardcoded value for VID/PID, cached value for FW version + * 1: live chip value for VID/PID/FW Version + */ + uint8_t live; +} __ec_align1; -struct __ec_align2 ec_response_pd_chip_info { +struct ec_response_pd_chip_info { uint16_t vendor_id; uint16_t product_id; uint16_t device_id; @@ -4736,14 +5302,28 @@ struct __ec_align2 ec_response_pd_chip_info { uint8_t fw_version_string[8]; uint64_t fw_version_number; }; -}; +} __ec_align2; + +struct ec_response_pd_chip_info_v1 { + uint16_t vendor_id; + uint16_t product_id; + uint16_t device_id; + union { + uint8_t fw_version_string[8]; + uint64_t fw_version_number; + }; + union { + uint8_t min_req_fw_version_string[8]; + uint64_t min_req_fw_version_number; + }; +} __ec_align2; /* Run RW signature verification and get status */ #define EC_CMD_RWSIG_CHECK_STATUS 0x011C -struct __ec_align4 ec_response_rwsig_check_status { +struct ec_response_rwsig_check_status { uint32_t status; -}; +} __ec_align4; /* For controlling RWSIG task */ #define EC_CMD_RWSIG_ACTION 0x011D @@ -4753,16 +5333,16 @@ enum rwsig_action { RWSIG_ACTION_CONTINUE = 1, /* Jump to RW immediately */ }; -struct __ec_align4 ec_params_rwsig_action { +struct ec_params_rwsig_action { uint32_t action; -}; +} __ec_align4; /* Run verification on a slot */ #define EC_CMD_EFS_VERIFY 0x011E -struct __ec_align1 ec_params_efs_verify { +struct ec_params_efs_verify { uint8_t region; /* enum ec_flash_region */ -}; +} __ec_align1; /* * Retrieve info from Cros Board Info store. Response is based on the data @@ -4777,11 +5357,12 @@ struct __ec_align1 ec_params_efs_verify { #define EC_CMD_SET_CROS_BOARD_INFO 0x0120 enum cbi_data_tag { - CBI_TAG_BOARD_VERSION = 0, /* uint16_t or uint8_t[] = {minor,major} */ - CBI_TAG_OEM_ID = 1, /* uint8_t */ - CBI_TAG_SKU_ID = 2, /* uint8_t */ + CBI_TAG_BOARD_VERSION = 0, /* uint32_t or smaller */ + CBI_TAG_OEM_ID = 1, /* uint32_t or smaller */ + CBI_TAG_SKU_ID = 2, /* uint32_t or smaller */ CBI_TAG_DRAM_PART_NUM = 3, /* variable length ascii, nul terminated. */ CBI_TAG_OEM_NAME = 4, /* variable length ascii, nul terminated. */ + CBI_TAG_MODEL_ID = 5, /* uint32_t or smaller */ CBI_TAG_COUNT, }; @@ -4791,12 +5372,12 @@ enum cbi_data_tag { * RELOAD: Invalidate cache and read data from EEPROM. Useful to verify * write was successful without reboot. */ -#define CBI_GET_RELOAD (1 << 0) +#define CBI_GET_RELOAD BIT(0) -struct __ec_align4 ec_params_get_cbi { +struct ec_params_get_cbi { uint32_t tag; /* enum cbi_data_tag */ uint32_t flag; /* CBI_GET_* */ -}; +} __ec_align4; /* * Flags to control write behavior. @@ -4806,23 +5387,53 @@ struct __ec_align4 ec_params_get_cbi { * INIT: Need to be set when creating a new CBI from scratch. All fields * will be initialized to zero first. */ -#define CBI_SET_NO_SYNC (1 << 0) -#define CBI_SET_INIT (1 << 1) +#define CBI_SET_NO_SYNC BIT(0) +#define CBI_SET_INIT BIT(1) -struct __ec_align1 ec_params_set_cbi { +struct ec_params_set_cbi { uint32_t tag; /* enum cbi_data_tag */ uint32_t flag; /* CBI_SET_* */ uint32_t size; /* Data size */ uint8_t data[]; /* For string and raw data */ -}; +} __ec_align1; /* * Information about resets of the AP by the EC and the EC's own uptime. */ #define EC_CMD_GET_UPTIME_INFO 0x0121 -struct __ec_align4 ec_response_uptime_info { - /* Number of milliseconds since last EC reset */ +/* Reset causes */ +#define EC_RESET_FLAG_OTHER BIT(0) /* Other known reason */ +#define EC_RESET_FLAG_RESET_PIN BIT(1) /* Reset pin asserted */ +#define EC_RESET_FLAG_BROWNOUT BIT(2) /* Brownout */ +#define EC_RESET_FLAG_POWER_ON BIT(3) /* Power-on reset */ +#define EC_RESET_FLAG_WATCHDOG BIT(4) /* Watchdog timer reset */ +#define EC_RESET_FLAG_SOFT BIT(5) /* Soft reset trigger by core */ +#define EC_RESET_FLAG_HIBERNATE BIT(6) /* Wake from hibernate */ +#define EC_RESET_FLAG_RTC_ALARM BIT(7) /* RTC alarm wake */ +#define EC_RESET_FLAG_WAKE_PIN BIT(8) /* Wake pin triggered wake */ +#define EC_RESET_FLAG_LOW_BATTERY BIT(9) /* Low battery triggered wake */ +#define EC_RESET_FLAG_SYSJUMP BIT(10) /* Jumped directly to this image */ +#define EC_RESET_FLAG_HARD BIT(11) /* Hard reset from software */ +#define EC_RESET_FLAG_AP_OFF BIT(12) /* Do not power on AP */ +#define EC_RESET_FLAG_PRESERVED BIT(13) /* Some reset flags preserved from + * previous boot + */ +#define EC_RESET_FLAG_USB_RESUME BIT(14) /* USB resume triggered wake */ +#define EC_RESET_FLAG_RDD BIT(15) /* USB Type-C debug cable */ +#define EC_RESET_FLAG_RBOX BIT(16) /* Fixed Reset Functionality */ +#define EC_RESET_FLAG_SECURITY BIT(17) /* Security threat */ +#define EC_RESET_FLAG_AP_WATCHDOG BIT(18) /* AP experienced a watchdog reset */ + +struct ec_response_uptime_info { + /* + * Number of milliseconds since the last EC boot. Sysjump resets + * typically do not restart the EC's time_since_boot epoch. + * + * WARNING: The EC's sense of time is much less accurate than the AP's + * sense of time, in both phase and frequency. This timebase is similar + * to CLOCK_MONOTONIC_RAW, but with 1% or more frequency error. + */ uint32_t time_since_ec_boot_ms; /* @@ -4834,23 +5445,131 @@ struct __ec_align4 ec_response_uptime_info { uint32_t ap_resets_since_ec_boot; /* - * The set of flags which describe the EC's most recent reset. See - * include/system.h RESET_FLAG_* for details. + * The set of flags which describe the EC's most recent reset. + * See EC_RESET_FLAG_* for details. */ uint32_t ec_reset_flags; /* Empty log entries have both the cause and timestamp set to zero. */ struct ap_reset_log_entry { - /* See include/chipset.h for details */ + /* + * See include/chipset.h: enum chipset_{reset,shutdown}_reason + * for details. + */ uint16_t reset_cause; + /* Reserved for protocol growth. */ + uint16_t reserved; + /* * The time of the reset's assertion, in milliseconds since the - * last EC reset. Set to zero if the log entry is empty. + * last EC boot, in the same epoch as time_since_ec_boot_ms. + * Set to zero if the log entry is empty. */ uint32_t reset_time_ms; } recent_ap_reset[4]; +} __ec_align4; + +/* + * Add entropy to the device secret (stored in the rollback region). + * + * Depending on the chip, the operation may take a long time (e.g. to erase + * flash), so the commands are asynchronous. + */ +#define EC_CMD_ADD_ENTROPY 0x0122 + +enum add_entropy_action { + /* Add entropy to the current secret. */ + ADD_ENTROPY_ASYNC = 0, + /* + * Add entropy, and also make sure that the previous secret is erased. + * (this can be implemented by adding entropy multiple times until + * all rolback blocks have been overwritten). + */ + ADD_ENTROPY_RESET_ASYNC = 1, + /* Read back result from the previous operation. */ + ADD_ENTROPY_GET_RESULT = 2, }; + +struct ec_params_rollback_add_entropy { + uint8_t action; +} __ec_align1; + +/* + * Perform a single read of a given ADC channel. + */ +#define EC_CMD_ADC_READ 0x0123 + +struct ec_params_adc_read { + uint8_t adc_channel; +} __ec_align1; + +struct ec_response_adc_read { + int32_t adc_value; +} __ec_align4; + +/* + * Read back rollback info + */ +#define EC_CMD_ROLLBACK_INFO 0x0124 + +struct ec_response_rollback_info { + int32_t id; /* Incrementing number to indicate which region to use. */ + int32_t rollback_min_version; + int32_t rw_rollback_version; +} __ec_align4; + + +/* Issue AP reset */ +#define EC_CMD_AP_RESET 0x0125 + +/*****************************************************************************/ +/* Locate peripheral chips + * + * Return values: + * EC_RES_UNAVAILABLE: The chip type is supported but not found on system. + * EC_RES_INVALID_PARAM: The chip type was unrecognized. + * EC_RES_OVERFLOW: The index number exceeded the number of chip instances. + */ +#define EC_CMD_LOCATE_CHIP 0x0126 + +enum ec_chip_type { + EC_CHIP_TYPE_CBI_EEPROM = 0, + EC_CHIP_TYPE_TCPC = 1, + EC_CHIP_TYPE_COUNT, + EC_CHIP_TYPE_MAX = 0xFF, +}; + +enum ec_bus_type { + EC_BUS_TYPE_I2C = 0, + EC_BUS_TYPE_EMBEDDED = 1, + EC_BUS_TYPE_COUNT, + EC_BUS_TYPE_MAX = 0xFF, +}; + +struct ec_i2c_info { + uint16_t port; /* Physical port for device */ + uint16_t addr_flags; /* 7-bit (or 10-bit) address */ +}; + +struct ec_params_locate_chip { + uint8_t type; /* enum ec_chip_type */ + uint8_t index; /* Specifies one instance of chip type */ + /* Used for type specific parameters in future */ + union { + uint16_t reserved; + }; +} __ec_align2; + + +struct ec_response_locate_chip { + uint8_t bus_type; /* enum ec_bus_type */ + uint8_t reserved; /* Aligning the following union to 2 bytes */ + union { + struct ec_i2c_info i2c_info; + }; +} __ec_align2; + /*****************************************************************************/ /* The command range 0x200-0x2FF is reserved for Rotor. */ @@ -4869,89 +5588,95 @@ struct __ec_align4 ec_response_uptime_info { #define EC_FP_FLAG_NOT_COMPLETE 0x1 -struct __ec_align2 ec_params_fp_passthru { +struct ec_params_fp_passthru { uint16_t len; /* Number of bytes to write then read */ uint16_t flags; /* EC_FP_FLAG_xxx */ uint8_t data[]; /* Data to send */ -}; - -/* Fingerprint sensor configuration command: prototyping ONLY */ -#define EC_CMD_FP_SENSOR_CONFIG 0x0401 - -#define EC_FP_SENSOR_CONFIG_MAX_REGS 16 - -struct __ec_align2 ec_params_fp_sensor_config { - uint8_t count; /* Number of setup registers */ - /* - * the value to send to each of the 'count' setup registers - * is stored in the 'data' array for 'len' bytes just after - * the previous one. - */ - uint8_t len[EC_FP_SENSOR_CONFIG_MAX_REGS]; - uint8_t data[]; -}; +} __ec_align2; /* Configure the Fingerprint MCU behavior */ #define EC_CMD_FP_MODE 0x0402 /* Put the sensor in its lowest power mode */ -#define FP_MODE_DEEPSLEEP (1<<0) +#define FP_MODE_DEEPSLEEP BIT(0) /* Wait to see a finger on the sensor */ -#define FP_MODE_FINGER_DOWN (1<<1) +#define FP_MODE_FINGER_DOWN BIT(1) /* Poll until the finger has left the sensor */ -#define FP_MODE_FINGER_UP (1<<2) +#define FP_MODE_FINGER_UP BIT(2) /* Capture the current finger image */ -#define FP_MODE_CAPTURE (1<<3) +#define FP_MODE_CAPTURE BIT(3) +/* Finger enrollment session on-going */ +#define FP_MODE_ENROLL_SESSION BIT(4) +/* Enroll the current finger image */ +#define FP_MODE_ENROLL_IMAGE BIT(5) +/* Try to match the current finger image */ +#define FP_MODE_MATCH BIT(6) +/* Reset and re-initialize the sensor. */ +#define FP_MODE_RESET_SENSOR BIT(7) +/* special value: don't change anything just read back current mode */ +#define FP_MODE_DONT_CHANGE BIT(31) + +#define FP_VALID_MODES (FP_MODE_DEEPSLEEP | \ + FP_MODE_FINGER_DOWN | \ + FP_MODE_FINGER_UP | \ + FP_MODE_CAPTURE | \ + FP_MODE_ENROLL_SESSION | \ + FP_MODE_ENROLL_IMAGE | \ + FP_MODE_MATCH | \ + FP_MODE_RESET_SENSOR | \ + FP_MODE_DONT_CHANGE) + /* Capture types defined in bits [30..28] */ #define FP_MODE_CAPTURE_TYPE_SHIFT 28 -#define FP_MODE_CAPTURE_TYPE_MASK 0x7 -/* Full blown vendor-defined capture (produces 'frame_size' bytes) */ -#define FP_CAPTURE_VENDOR_FORMAT 0 -/* Simple raw image capture (produces width x height x bpp bits) */ -#define FP_CAPTURE_SIMPLE_IMAGE 1 -/* Self test pattern (e.g. checkerboard) */ -#define FP_CAPTURE_PATTERN0 2 -/* Self test pattern (e.g. inverted checkerboard) */ -#define FP_CAPTURE_PATTERN1 3 -/* Capture for Quality test with fixed contrast */ -#define FP_CAPTURE_QUALITY_TEST 4 -/* Capture for pixel reset value test */ -#define FP_CAPTURE_RESET_TEST 5 +#define FP_MODE_CAPTURE_TYPE_MASK (0x7 << FP_MODE_CAPTURE_TYPE_SHIFT) +/* + * This enum must remain ordered, if you add new values you must ensure that + * FP_CAPTURE_TYPE_MAX is still the last one. + */ +enum fp_capture_type { + /* Full blown vendor-defined capture (produces 'frame_size' bytes) */ + FP_CAPTURE_VENDOR_FORMAT = 0, + /* Simple raw image capture (produces width x height x bpp bits) */ + FP_CAPTURE_SIMPLE_IMAGE = 1, + /* Self test pattern (e.g. checkerboard) */ + FP_CAPTURE_PATTERN0 = 2, + /* Self test pattern (e.g. inverted checkerboard) */ + FP_CAPTURE_PATTERN1 = 3, + /* Capture for Quality test with fixed contrast */ + FP_CAPTURE_QUALITY_TEST = 4, + /* Capture for pixel reset value test */ + FP_CAPTURE_RESET_TEST = 5, + FP_CAPTURE_TYPE_MAX, +}; /* Extracts the capture type from the sensor 'mode' word */ -#define FP_CAPTURE_TYPE(mode) (((mode) >> FP_MODE_CAPTURE_TYPE_SHIFT) \ - & FP_MODE_CAPTURE_TYPE_MASK) -/* Finger enrollment session on-going */ -#define FP_MODE_ENROLL_SESSION (1<<4) -/* Enroll the current finger image */ -#define FP_MODE_ENROLL_IMAGE (1<<5) -/* Try to match the current finger image */ -#define FP_MODE_MATCH (1<<6) -/* special value: don't change anything just read back current mode */ -#define FP_MODE_DONT_CHANGE (1<<31) +#define FP_CAPTURE_TYPE(mode) (((mode) & FP_MODE_CAPTURE_TYPE_MASK) \ + >> FP_MODE_CAPTURE_TYPE_SHIFT) -struct __ec_align4 ec_params_fp_mode { +struct ec_params_fp_mode { uint32_t mode; /* as defined by FP_MODE_ constants */ -}; +} __ec_align4; -struct __ec_align4 ec_response_fp_mode { +struct ec_response_fp_mode { uint32_t mode; /* as defined by FP_MODE_ constants */ -}; +} __ec_align4; /* Retrieve Fingerprint sensor information */ #define EC_CMD_FP_INFO 0x0403 /* Number of dead pixels detected on the last maintenance */ #define FP_ERROR_DEAD_PIXELS(errors) ((errors) & 0x3FF) +/* Unknown number of dead pixels detected on the last maintenance */ +#define FP_ERROR_DEAD_PIXELS_UNKNOWN (0x3FF) /* No interrupt from the sensor */ -#define FP_ERROR_NO_IRQ (1 << 12) +#define FP_ERROR_NO_IRQ BIT(12) /* SPI communication error */ -#define FP_ERROR_SPI_COMM (1 << 13) +#define FP_ERROR_SPI_COMM BIT(13) /* Invalid sensor Hardware ID */ -#define FP_ERROR_BAD_HWID (1 << 14) +#define FP_ERROR_BAD_HWID BIT(14) /* Sensor initialization failed */ -#define FP_ERROR_INIT_FAIL (1 << 15) +#define FP_ERROR_INIT_FAIL BIT(15) -struct __ec_align4 ec_response_fp_info_v0 { +struct ec_response_fp_info_v0 { /* Sensor identification */ uint32_t vendor_id; uint32_t product_id; @@ -4964,9 +5689,9 @@ struct __ec_align4 ec_response_fp_info_v0 { uint16_t height; uint16_t bpp; uint16_t errors; /* see FP_ERROR_ flags above */ -}; +} __ec_align4; -struct __ec_align4 ec_response_fp_info { +struct ec_response_fp_info { /* Sensor identification */ uint32_t vendor_id; uint32_t product_id; @@ -4984,18 +5709,48 @@ struct __ec_align4 ec_response_fp_info { uint16_t template_max; /* maximum number of fingers/templates */ uint16_t template_valid; /* number of valid fingers/templates */ uint32_t template_dirty; /* bitmap of templates with MCU side changes */ -}; + uint32_t template_version; /* version of the template format */ +} __ec_align4; /* Get the last captured finger frame or a template content */ #define EC_CMD_FP_FRAME 0x0404 /* constants defining the 'offset' field which also contains the frame index */ #define FP_FRAME_INDEX_SHIFT 28 +/* Frame buffer where the captured image is stored */ #define FP_FRAME_INDEX_RAW_IMAGE 0 -#define FP_FRAME_TEMPLATE_INDEX(offset) ((offset) >> FP_FRAME_INDEX_SHIFT) +/* First frame buffer holding a template */ +#define FP_FRAME_INDEX_TEMPLATE 1 +#define FP_FRAME_GET_BUFFER_INDEX(offset) ((offset) >> FP_FRAME_INDEX_SHIFT) #define FP_FRAME_OFFSET_MASK 0x0FFFFFFF -struct __ec_align4 ec_params_fp_frame { +/* Version of the format of the encrypted templates. */ +#define FP_TEMPLATE_FORMAT_VERSION 3 + +/* Constants for encryption parameters */ +#define FP_CONTEXT_NONCE_BYTES 12 +#define FP_CONTEXT_USERID_WORDS (32 / sizeof(uint32_t)) +#define FP_CONTEXT_TAG_BYTES 16 +#define FP_CONTEXT_SALT_BYTES 16 +#define FP_CONTEXT_TPM_BYTES 32 + +struct ec_fp_template_encryption_metadata { + /* + * Version of the structure format (N=3). + */ + uint16_t struct_version; + /* Reserved bytes, set to 0. */ + uint16_t reserved; + /* + * The salt is *only* ever used for key derivation. The nonce is unique, + * a different one is used for every message. + */ + uint8_t nonce[FP_CONTEXT_NONCE_BYTES]; + uint8_t salt[FP_CONTEXT_SALT_BYTES]; + uint8_t tag[FP_CONTEXT_TAG_BYTES]; +}; + +struct ec_params_fp_frame { /* * The offset contains the template index or FP_FRAME_INDEX_RAW_IMAGE * in the high nibble, and the real offset within the frame in @@ -5003,7 +5758,7 @@ struct __ec_align4 ec_params_fp_frame { */ uint32_t offset; uint32_t size; -}; +} __ec_align4; /* Load a template into the MCU */ #define EC_CMD_FP_TEMPLATE 0x0405 @@ -5011,27 +5766,59 @@ struct __ec_align4 ec_params_fp_frame { /* Flag in the 'size' field indicating that the full template has been sent */ #define FP_TEMPLATE_COMMIT 0x80000000 -struct __ec_align4 ec_params_fp_template { +struct ec_params_fp_template { uint32_t offset; uint32_t size; uint8_t data[]; -}; +} __ec_align4; /* Clear the current fingerprint user context and set a new one */ #define EC_CMD_FP_CONTEXT 0x0406 -#define FP_CONTEXT_USERID_WORDS (32 / sizeof(uint32_t)) -#define FP_CONTEXT_NONCE_WORDS (32 / sizeof(uint32_t)) - -struct __ec_align4 ec_params_fp_context { +struct ec_params_fp_context { uint32_t userid[FP_CONTEXT_USERID_WORDS]; - /* TODO(b/73337313) mostly a placeholder, details to be implemented */ - uint32_t nonce[FP_CONTEXT_NONCE_WORDS]; -}; +} __ec_align4; -struct __ec_align4 ec_response_fp_context { - uint32_t nonce[FP_CONTEXT_NONCE_WORDS]; -}; +#define EC_CMD_FP_STATS 0x0407 + +#define FPSTATS_CAPTURE_INV BIT(0) +#define FPSTATS_MATCHING_INV BIT(1) + +struct ec_response_fp_stats { + uint32_t capture_time_us; + uint32_t matching_time_us; + uint32_t overall_time_us; + struct { + uint32_t lo; + uint32_t hi; + } overall_t0; + uint8_t timestamps_invalid; + int8_t template_matched; +} __ec_align2; + +#define EC_CMD_FP_SEED 0x0408 +struct ec_params_fp_seed { + /* + * Version of the structure format (N=3). + */ + uint16_t struct_version; + /* Reserved bytes, set to 0. */ + uint16_t reserved; + /* Seed from the TPM. */ + uint8_t seed[FP_CONTEXT_TPM_BYTES]; +} __ec_align4; + +#define EC_CMD_FP_ENC_STATUS 0x0409 + +/* FP TPM seed has been set or not */ +#define FP_ENC_STATUS_SEED_SET BIT(0) + +struct ec_response_fp_encryption_status { + /* Used bits in encryption engine status */ + uint32_t valid_flags; + /* Encryption engine status */ + uint32_t status; +} __ec_align4; /*****************************************************************************/ /* Touchpad MCU commands: range 0x0500-0x05FF */ @@ -5042,10 +5829,10 @@ struct __ec_align4 ec_response_fp_context { /* Get number of frame types, and the size of each type */ #define EC_CMD_TP_FRAME_INFO 0x0501 -struct __ec_align4 ec_response_tp_frame_info { +struct ec_response_tp_frame_info { uint32_t n_frames; uint32_t frame_sizes[0]; -}; +} __ec_align4; /* Create a snapshot of current frame readings */ #define EC_CMD_TP_FRAME_SNAPSHOT 0x0502 @@ -5053,11 +5840,11 @@ struct __ec_align4 ec_response_tp_frame_info { /* Read the frame */ #define EC_CMD_TP_FRAME_GET 0x0503 -struct __ec_align4 ec_params_tp_frame_get { +struct ec_params_tp_frame_get { uint32_t frame_index; uint32_t offset; uint32_t size; -}; +} __ec_align4; /*****************************************************************************/ /* EC-EC communication commands: range 0x0600-0x06FF */ @@ -5070,20 +5857,34 @@ struct __ec_align4 ec_params_tp_frame_get { */ #define EC_CMD_BATTERY_GET_STATIC 0x0600 -struct __ec_align_size1 ec_params_battery_static_info { - uint8_t index; /* Battery index. */ -}; +/** + * struct ec_params_battery_static_info - Battery static info parameters + * @index: Battery index. + */ +struct ec_params_battery_static_info { + uint8_t index; +} __ec_align_size1; -struct __ec_align4 ec_response_battery_static_info { - uint16_t design_capacity; /* Battery Design Capacity (mAh) */ - uint16_t design_voltage; /* Battery Design Voltage (mV) */ - char manufacturer[EC_COMM_TEXT_MAX]; /* Battery Manufacturer String */ - char model[EC_COMM_TEXT_MAX]; /* Battery Model Number String */ - char serial[EC_COMM_TEXT_MAX]; /* Battery Serial Number String */ - char type[EC_COMM_TEXT_MAX]; /* Battery Type String */ +/** + * struct ec_response_battery_static_info - Battery static info response + * @design_capacity: Battery Design Capacity (mAh) + * @design_voltage: Battery Design Voltage (mV) + * @manufacturer: Battery Manufacturer String + * @model: Battery Model Number String + * @serial: Battery Serial Number String + * @type: Battery Type String + * @cycle_count: Battery Cycle Count + */ +struct ec_response_battery_static_info { + uint16_t design_capacity; + uint16_t design_voltage; + char manufacturer[EC_COMM_TEXT_MAX]; + char model[EC_COMM_TEXT_MAX]; + char serial[EC_COMM_TEXT_MAX]; + char type[EC_COMM_TEXT_MAX]; /* TODO(crbug.com/795991): Consider moving to dynamic structure. */ - uint32_t cycle_count; /* Battery Cycle Count */ -}; + uint32_t cycle_count; +} __ec_align4; /* * Get battery dynamic information, i.e. information that is likely to change @@ -5091,39 +5892,54 @@ struct __ec_align4 ec_response_battery_static_info { */ #define EC_CMD_BATTERY_GET_DYNAMIC 0x0601 -struct __ec_align_size1 ec_params_battery_dynamic_info { - uint8_t index; /* Battery index. */ -}; +/** + * struct ec_params_battery_dynamic_info - Battery dynamic info parameters + * @index: Battery index. + */ +struct ec_params_battery_dynamic_info { + uint8_t index; +} __ec_align_size1; -struct __ec_align2 ec_response_battery_dynamic_info { - int16_t actual_voltage; /* Battery voltage (mV) */ - int16_t actual_current; /* Battery current (mA); negative=discharging */ - int16_t remaining_capacity; /* Remaining capacity (mAh) */ - int16_t full_capacity; /* Capacity (mAh, might change occasionally) */ - int16_t flags; /* Flags, see EC_BATT_FLAG_* */ - int16_t desired_voltage; /* Charging voltage desired by battery (mV) */ - int16_t desired_current; /* Charging current desired by battery (mA) */ -}; +/** + * struct ec_response_battery_dynamic_info - Battery dynamic info response + * @actual_voltage: Battery voltage (mV) + * @actual_current: Battery current (mA); negative=discharging + * @remaining_capacity: Remaining capacity (mAh) + * @full_capacity: Capacity (mAh, might change occasionally) + * @flags: Flags, see EC_BATT_FLAG_* + * @desired_voltage: Charging voltage desired by battery (mV) + * @desired_current: Charging current desired by battery (mA) + */ +struct ec_response_battery_dynamic_info { + int16_t actual_voltage; + int16_t actual_current; + int16_t remaining_capacity; + int16_t full_capacity; + int16_t flags; + int16_t desired_voltage; + int16_t desired_current; +} __ec_align2; /* * Control charger chip. Used to control charger chip on the slave. */ #define EC_CMD_CHARGER_CONTROL 0x0602 -struct __ec_align_size1 ec_params_charger_control { - /* - * Charger current (mA). Positive to allow base to draw up to - * max_current and (possibly) charge battery, negative to request - * current from base (OTG). - */ +/** + * struct ec_params_charger_control - Charger control parameters + * @max_current: Charger current (mA). Positive to allow base to draw up to + * max_current and (possibly) charge battery, negative to request current + * from base (OTG). + * @otg_voltage: Voltage (mV) to use in OTG mode, ignored if max_current is + * >= 0. + * @allow_charging: Allow base battery charging (only makes sense if + * max_current > 0). + */ +struct ec_params_charger_control { int16_t max_current; - - /* Voltage (mV) to use in OTG mode, ignored if max_current is >= 0. */ uint16_t otg_voltage; - - /* Allow base battery charging (only makes sense if max_current > 0). */ uint8_t allow_charging; -}; +} __ec_align_size1; /*****************************************************************************/ /* @@ -5201,4 +6017,8 @@ struct __ec_align_size1 ec_params_charger_control { #endif /* !__ACPI__ */ +#ifdef __cplusplus +} +#endif + #endif /* __CROS_EC_EC_COMMANDS_H */ diff --git a/src/ec/google/chromeec/ec_i2c.c b/src/ec/google/chromeec/ec_i2c.c index c3e1968c95..dc012fcd9e 100644 --- a/src/ec/google/chromeec/ec_i2c.c +++ b/src/ec/google/chromeec/ec_i2c.c @@ -252,10 +252,8 @@ int google_chromeec_command(struct chromeec_command *cec_command) #endif /* CONFIG_EC_GOOGLE_CHROMEEC_I2C_PROTO3 */ -#ifndef __PRE_RAM__ u8 google_chromeec_get_event(void) { printk(BIOS_ERR, "%s: Not supported.\n", __func__); return 0; } -#endif diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index b7d183ebb0..1d7e7ee7c8 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -399,24 +399,9 @@ void google_chromeec_ioport_range(uint16_t *out_base, size_t *out_size) *out_size = size; } -#ifdef __PRE_RAM__ - int google_chromeec_command(struct chromeec_command *cec_command) { - switch (google_chromeec_command_version()) { - case EC_HOST_CMD_FLAG_VERSION_3: - return google_chromeec_command_v3(cec_command); - case EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED: - return google_chromeec_command_v1(cec_command); - } - return -1; -} - -#else /* !__PRE_RAM__ */ - -int google_chromeec_command(struct chromeec_command *cec_command) -{ - static int command_version = 0; + MAYBE_STATIC_BSS int command_version = 0; if (command_version <= 0) command_version = google_chromeec_command_version(); @@ -430,7 +415,6 @@ int google_chromeec_command(struct chromeec_command *cec_command) return -1; } -#ifndef __SMM__ static void lpc_ec_init(struct device *dev) { if (!dev->enabled) @@ -485,8 +469,6 @@ struct chip_operations ec_google_chromeec_ops = { .enable_dev = enable_dev, }; -#endif /* __SMM__ */ - static int google_chromeec_data_ready(u16 port) { return google_chromeec_status_check(port, EC_LPC_CMDR_DATA, @@ -516,4 +498,3 @@ u8 google_chromeec_get_event(void) /* Event (or 0 if none) is returned directly in the data byte */ return read_byte(EC_LPC_ADDR_ACPI_DATA); } -#endif diff --git a/src/ec/google/chromeec/ec_spi.c b/src/ec/google/chromeec/ec_spi.c index 3611814b66..c47d419647 100644 --- a/src/ec/google/chromeec/ec_spi.c +++ b/src/ec/google/chromeec/ec_spi.c @@ -115,10 +115,8 @@ int google_chromeec_command(struct chromeec_command *cec_command) return crosec_command_proto(cec_command, crosec_spi_io, &slave); } -#ifndef __PRE_RAM__ u8 google_chromeec_get_event(void) { printk(BIOS_ERR, "%s: Not supported.\n", __func__); return 0; } -#endif diff --git a/src/ec/google/chromeec/switches.c b/src/ec/google/chromeec/switches.c index 7b3f4d4cf1..3fd38084f6 100644 --- a/src/ec/google/chromeec/switches.c +++ b/src/ec/google/chromeec/switches.c @@ -34,10 +34,9 @@ int get_recovery_mode_switch(void) (google_chromeec_get_switches() & EC_SWITCH_DEDICATED_RECOVERY)) return 1; - /* Check if the EC has posted the keyboard recovery/fastboot event. */ + /* Check if the EC has posted the keyboard recovery event. */ return !!(google_chromeec_get_events_b() & - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) | - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT))); + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); } int get_recovery_mode_retrain_switch(void) @@ -68,6 +67,5 @@ int clear_recovery_mode_switch(void) /* Clear all host event bits requesting recovery mode. */ return google_chromeec_clear_events_b( EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) | - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT) | - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT)); + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT)); } diff --git a/src/ec/google/wilco/boardid.c b/src/ec/google/wilco/boardid.c index e602e6e0c7..2a7e5755ea 100644 --- a/src/ec/google/wilco/boardid.c +++ b/src/ec/google/wilco/boardid.c @@ -18,7 +18,7 @@ uint32_t board_id(void) { - MAYBE_STATIC uint32_t id = BOARD_ID_INIT; + MAYBE_STATIC_NONZERO uint32_t id = BOARD_ID_INIT; if (id == BOARD_ID_INIT) { uint8_t ec_id; diff --git a/src/ec/google/wilco/chip.h b/src/ec/google/wilco/chip.h index 9b02ee346d..06d889c108 100644 --- a/src/ec/google/wilco/chip.h +++ b/src/ec/google/wilco/chip.h @@ -16,10 +16,6 @@ #ifndef EC_GOOGLE_WILCO_CHIP_H #define EC_GOOGLE_WILCO_CHIP_H -#include - -extern struct chip_operations ec_google_wilco_ops; - struct ec_google_wilco_config { }; diff --git a/src/ec/kontron/kempld/Kconfig b/src/ec/kontron/kempld/Kconfig index 647bd12d69..08401c949c 100644 --- a/src/ec/kontron/kempld/Kconfig +++ b/src/ec/kontron/kempld/Kconfig @@ -1,5 +1,6 @@ config EC_KONTRON_KEMPLD bool + select DRIVERS_UART_8250IO help Driver for Kontron's express module programmable logic device used on their COMexpress modules. diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig index d874975428..f3df56a6c5 100644 --- a/src/ec/lenovo/h8/Kconfig +++ b/src/ec/lenovo/h8/Kconfig @@ -40,6 +40,10 @@ config H8_FN_KEY_AS_VBOOT_RECOVERY_SW If VBOOT is enabled, press Fn-Key at power on to force a recovery mode boot instead of regular FW_MAIN_x boot. +config H8_HAS_PRIMARY_FN_KEYS + bool + default n + endif config H8_DOCK_EARLY_INIT diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 2b959ceea1..3a99b52dd8 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -86,6 +86,14 @@ static void h8_sticky_fn(int on) ec_clr_bit(0x0, 3); } +static void f1_to_f12_as_primary(int on) +{ + if (on) + ec_set_bit(0x3b, 3); + else + ec_clr_bit(0x3b, 3); +} + static void h8_log_ec_version(void) { char ecfw[17]; @@ -334,6 +342,12 @@ static void h8_enable(struct device *dev) val = 0; h8_sticky_fn(val); + if (CONFIG(H8_HAS_PRIMARY_FN_KEYS)) { + if (get_option(&val, "f1_to_f12_as_primary") != CB_SUCCESS) + val = 1; + f1_to_f12_as_primary(val); + } + if (get_option(&val, "first_battery") != CB_SUCCESS) val = PRIMARY_BATTERY; h8_charge_priority(val); diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index 30de6fe949..9dd668fd75 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -115,11 +115,9 @@ void pmh7_register_write(int reg, int val) outb(val, EC_LENOVO_PMH7_DATA); } -#ifndef __PRE_RAM__ -#ifndef __SMM__ static void enable_dev(struct device *dev) { - struct ec_lenovo_pmh7_config *conf = dev->chip_info; + const struct ec_lenovo_pmh7_config *conf = dev->chip_info; struct resource *resource; u8 val; @@ -150,5 +148,3 @@ struct chip_operations ec_lenovo_pmh7_ops = { CHIP_NAME("Lenovo Power Management Hardware Hub 7") .enable_dev = enable_dev, }; -#endif -#endif diff --git a/src/ec/quanta/ene_kb3940q/chip.h b/src/ec/quanta/ene_kb3940q/chip.h index 8348cc09ef..b812a18b36 100644 --- a/src/ec/quanta/ene_kb3940q/chip.h +++ b/src/ec/quanta/ene_kb3940q/chip.h @@ -17,11 +17,6 @@ #ifndef _EC_QUANTA_ENE_KB3940Q_CHIP_H #define _EC_QUANTA_ENE_KB3940Q_CHIP_H -#include - -struct chip_operations; -extern struct chip_operations ec_quanta_ene_kb3940q_ops; - struct ec_quanta_ene_kb3940q_config { }; diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index 1f8e36c661..4fc38da99d 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -#ifndef __PRE_RAM__ - #include #include #include @@ -125,7 +123,6 @@ void ec_mem_write(u8 addr, u8 data) return; } -#ifndef __SMM__ static void ene_kb3940q_log_events(void) { #if CONFIG(ELOG) @@ -165,5 +162,3 @@ struct chip_operations ec_quanta_ene_kb3940q_ops = { CHIP_NAME("QUANTA EnE KB3940Q EC") .enable_dev = enable_dev }; -#endif /* ! __SMM__ */ -#endif /* ! __PRE_RAM__ */ diff --git a/src/ec/quanta/it8518/chip.h b/src/ec/quanta/it8518/chip.h index ea9b4ac779..5dd14f6b29 100644 --- a/src/ec/quanta/it8518/chip.h +++ b/src/ec/quanta/it8518/chip.h @@ -17,11 +17,6 @@ #ifndef _EC_QUANTA_IT8518_CHIP_H #define _EC_QUANTA_IT8518_CHIP_H -#include - -struct chip_operations; -extern struct chip_operations ec_quanta_it8518_ops; - struct ec_quanta_it8518_config { }; diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index 5b9ba9f9bd..4853eb333f 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -124,7 +124,6 @@ void ec_write(u16 addr, u8 data) ec_write_ib(data); } -#ifndef __PRE_RAM__ u8 ec_it8518_get_event(void) { @@ -149,7 +148,6 @@ void ec_it8518_enable_wake_events(void) ec_write(EC_WAKE_SRC_ENABLE, reg8 | EC_LID_WAKE_ENABLE); } -#ifndef __SMM__ static void it8518_init(struct device *dev) { if (!dev->enabled) @@ -178,5 +176,3 @@ struct chip_operations ec_quanta_it8518_ops = { CHIP_NAME("QUANTA IT8518 EC") .enable_dev = enable_dev }; -#endif /* ! __SMM__ */ -#endif /* ! __PRE_RAM__ */ diff --git a/src/ec/roda/it8518/chip.h b/src/ec/roda/it8518/chip.h index 44891e84fa..8091525e9b 100644 --- a/src/ec/roda/it8518/chip.h +++ b/src/ec/roda/it8518/chip.h @@ -16,11 +16,6 @@ #ifndef _EC_RODA_IT8518_CHIP_H #define _EC_RODA_IT8518_CHIP_H -#include - -struct chip_operations; -extern struct chip_operations ec_roda_it8518_ops; - struct ec_roda_it8518_config { u8 cpuhot_limit; /* temperature in °C which asserts PROCHOT# */ }; diff --git a/src/ec/smsc/mec1308/ec.c b/src/ec/smsc/mec1308/ec.c index 83dd729825..c6e282a015 100644 --- a/src/ec/smsc/mec1308/ec.c +++ b/src/ec/smsc/mec1308/ec.c @@ -115,10 +115,9 @@ void ec_set_ports(u16 cmd_reg, u16 data_reg) ec_data_reg = data_reg; } -#if !defined(__PRE_RAM__) && !defined(__SMM__) static void mec1308_enable(struct device *dev) { - struct ec_smsc_mec1308_config *conf = dev->chip_info; + DEVTREE_CONST struct ec_smsc_mec1308_config *conf = dev->chip_info; if (conf->mailbox_port) { ec_cmd_reg = conf->mailbox_port; @@ -130,4 +129,3 @@ struct chip_operations ec_smsc_mec1308_ops = { CHIP_NAME("SMSC MEC1308 EC Mailbox Interface") .enable_dev = mec1308_enable }; -#endif diff --git a/src/include/bootblock_common.h b/src/include/bootblock_common.h index 08b2b7ad6d..1081f27453 100644 --- a/src/include/bootblock_common.h +++ b/src/include/bootblock_common.h @@ -38,16 +38,7 @@ void bootblock_soc_init(void); asmlinkage void bootblock_c_entry(uint64_t base_timestamp); asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist); -/* - * This is a the same as the bootblock main(), with the difference that it does - * not collect a timestamp. Instead it accepts the initial timestamp and - * possibly additional timestamp entries as arguments. This can be used in cases - * where earlier stamps are available. Note that this function is designed to be - * entered from C code. This function assumes that the timer has already been - * initialized, so it does not call init_timer(). - */ -asmlinkage void bootblock_main_with_timestamp(uint64_t base_timestamp, - struct timestamp_entry *timestamps, size_t num_timestamps); +void bootblock_main_with_basetime(uint64_t base_timestamp); /* This is the argument structure passed from decompressor to bootblock. */ struct bootblock_arg { diff --git a/src/include/bootsplash.h b/src/include/bootsplash.h index 84ba34cc90..af09922a5f 100644 --- a/src/include/bootsplash.h +++ b/src/include/bootsplash.h @@ -18,12 +18,6 @@ #include -/** - * Wraps bootsplash setup for vesa - */ -void set_vesa_bootsplash(void); - - /** * Sets up the framebuffer with the bootsplash.jpg from cbfs. * Returns 0 on success diff --git a/src/include/cbmem.h b/src/include/cbmem.h index f3df21d430..f972ba6503 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -106,7 +106,6 @@ void *cbmem_find(u32 id); /* Indicate to each hook if cbmem is being recovered or not. */ typedef void (* const cbmem_init_hook_t)(int is_recovery); void cbmem_run_init_hooks(int is_recovery); -void cbmem_fail_resume(void); /* Ramstage only functions. */ /* Add the cbmem memory used to the memory map at boot. */ diff --git a/src/include/cpu/amd/amd64_save_state.h b/src/include/cpu/amd/amd64_save_state.h new file mode 100644 index 0000000000..14149ece37 --- /dev/null +++ b/src/include/cpu/amd/amd64_save_state.h @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMD64_SAVE_STATE_H__ +#define __AMD64_SAVE_STATE_H__ +#endif + +#include +#include + +/* AMD64 x86 SMM State-Save Area + * starts @ 0x7e00 + */ +#define SMM_AMD64_ARCH_OFFSET 0x7e00 +#define SMM_AMD64_SAVE_STATE_OFFSET \ + SMM_SAVE_STATE_BEGIN(SMM_AMD64_ARCH_OFFSET) +typedef struct { + u16 es_selector; + u16 es_attributes; + u32 es_limit; + u64 es_base; + + u16 cs_selector; + u16 cs_attributcs; + u32 cs_limit; + u64 cs_base; + + u16 ss_selector; + u16 ss_attributss; + u32 ss_limit; + u64 ss_base; + + u16 ds_selector; + u16 ds_attributds; + u32 ds_limit; + u64 ds_base; + + u16 fs_selector; + u16 fs_attributfs; + u32 fs_limit; + u64 fs_base; + + u16 gs_selector; + u16 gs_attributgs; + u32 gs_limit; + u64 gs_base; + + u8 reserved0[4]; + u16 gdtr_limit; + u8 reserved1[2]; + u64 gdtr_base; + + u16 ldtr_selector; + u16 ldtr_attributes; + u32 ldtr_limit; + u64 ldtr_base; + + u8 reserved2[4]; + u16 idtr_limit; + u8 reserved3[2]; + u64 idtr_base; + + u16 tr_selector; + u16 tr_attributes; + u32 tr_limit; + u64 tr_base; + + u64 io_restart_rip; + u64 io_restart_rcx; + u64 io_restart_rsi; + u64 io_restart_rdi; + u32 smm_io_trap_offset; + u32 local_smi_status; + + u8 io_restart; + u8 autohalt_restart; + + u8 reserved5[6]; + + u64 efer; + + u8 reserved6[36]; + + u32 smm_revision; + u32 smbase; + + u8 reserved7[68]; + + u64 cr4; + u64 cr3; + u64 cr0; + u64 dr7; + u64 dr6; + + u64 rflags; + u64 rip; + u64 r15; + u64 r14; + u64 r13; + u64 r12; + u64 r11; + u64 r10; + u64 r9; + u64 r8; + + u64 rdi; + u64 rsi; + u64 rpb; + u64 rsp; + u64 rbx; + u64 rdx; + u64 rcx; + u64 rax; +} __packed amd64_smm_state_save_area_t; diff --git a/src/include/cpu/amd/lxdef.h b/src/include/cpu/amd/lxdef.h deleted file mode 100644 index 7daa294340..0000000000 --- a/src/include/cpu/amd/lxdef.h +++ /dev/null @@ -1,660 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Indrek Kruusa - * Copyright (C) 2006 Ronald G. Minnich - * Copyright (C) 2006 Stefan Reinauer - * Copyright (C) 2006 Andrei Birjukov - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef CPU_AMD_LXDEF_H -#define CPU_AMD_LXDEF_H - -/* Stepping ID 1.x CPUbug fix to change it to 5A0*/ -#define CPU_ID_1_X 0x00000560 -#define CPU_ID_2_0 0x000005A1 -#define CPU_ID_3_0 0x000005A2 - -#define CPU_REV_1_0 0x010 -#define CPU_REV_1_1 0x011 -#define CPU_REV_2_0 0x020 -#define CPU_REV_2_1 0x021 -#define CPU_REV_2_2 0x022 -#define CPU_REV_C_0 0x030 -#define CPU_REV_C_1 0x031 -#define CPU_REV_C_2 0x032 /* 3.2 part was never produced ...*/ -#define CPU_REV_C_3 0x033 - - -/* MSR routing as follows*/ -/* MSB = 1 means not for CPU*/ -/* next 3 bits 1st port*/ -/* next3 bits next port if through an GLIU*/ -/* etc...*/ - -/* GLIU0 ports */ -#define GL0_GLIU0 0 -#define GL0_MC 1 -#define GL0_GLIU1 2 -#define GL0_CPU 3 -#define GL0_VG 4 -#define GL0_GP 5 - -/* GLIU1 ports */ -#define GL1_GLIU0 1 -#define GL1_DF 2 -#define GL1_GLCP 3 -#define GL1_PCI 4 -#define GL1_VIP 5 -#define GL1_AES 6 - - -/* 1000xxxx, To get on GeodeLink one bit has to be set */ -#define MSR_GLIU0 ((GL0_GLIU0 << 29) + (1 << 28)) -#define MSR_MC (GL0_MC << 29) /* 2000xxxx */ -#define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */ -/* 0000xxxx this is not used for BIOS since code executing on CPU doesn't - * need to be routed - */ -#define MSR_CPU (GL0_CPU << 29) -#define MSR_VG (GL0_VG << 29) /* 8000xxxx */ -#define MSR_GP (GL0_GP << 29) /* A000xxxx */ - -#define MSR_DF ((GL1_DF << 26) + MSR_GLIU1) /* 4800xxxx */ -#define MSR_GLCP ((GL1_GLCP << 26) + MSR_GLIU1) /* 4C00xxxx */ -#define MSR_PCI ((GL1_PCI << 26) + MSR_GLIU1) /* 5000xxxx */ -#define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) /* 5400xxxx */ -#define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* 5800xxxx */ -#define MSR_FG MSR_GLCP - -/*GeodeLink Interface Unit 0 (GLIU0) port0*/ - -#define GLIU0_GLD_MSR_CAP (MSR_GLIU0 + 0x2000) -#define GLIU0_GLD_MSR_ERROR (MSR_GLIU0 + 0x2003) -#define GLIU0_GLD_MSR_PM (MSR_GLIU0 + 0x2004) - -#define GLIU0_DESC_BASE (MSR_GLIU0 + 0x20) -#define GLIU0_CAP (MSR_GLIU0 + 0x86) -#define GLIU0_GLD_MSR_COH (MSR_GLIU0 + 0x80) -#define GLIU0_ARB (MSR_GLIU0 + 0x82) -#define ARB_UPPER_QUACK_EN_SET (1 << 31) -#define ARB_UPPER_DACK_EN_SET (1 << 28) - - -/* Memory Controller GLIU0 port 1*/ - -#define MC_GLD_MSR_CAP (MSR_MC + 0x2000) -#define MC_GLD_MSR_PM (MSR_MC + 0x2004) - -#define MC_CF07_DATA (MSR_MC + 0x18) -#define CF07_UPPER_D1_SZ_SHIFT 28 -#define CF07_UPPER_D1_MB_SHIFT 24 -#define CF07_UPPER_D1_CB_SHIFT 20 -#define CF07_UPPER_D1_PSZ_SHIFT 16 -#define CF07_UPPER_D0_SZ_SHIFT 12 -#define CF07_UPPER_D0_MB_SHIFT 8 -#define CF07_UPPER_D0_CB_SHIFT 4 -#define CF07_UPPER_D0_PSZ_SHIFT 0 - -#define CF07_LOWER_REF_INT_SHIFT 8 -#define CF07_LOWER_LOAD_MODE_DDR_SET (1 << 28) -#define CF07_LOWER_LOAD_MODE_DLL_RESET (1 << 27) -#define CF07_LOWER_EMR_QFC_SET (1 << 26) -#define CF07_LOWER_EMR_DRV_SET (1 << 25) -#define CF07_LOWER_REF_TEST_SET (1 << 3) -#define CF07_LOWER_PROG_DRAM_SET (1 << 0) - - -#define MC_CF8F_DATA (MSR_MC + 0x19) -#define CF8F_UPPER_XOR_BS_SHIFT 19 -#define CF8F_UPPER_XOR_MB0_SHIFT 18 -#define CF8F_UPPER_XOR_BA1_SHIFT 17 -#define CF8F_UPPER_XOR_BA0_SHIFT 16 -#define CF8F_UPPER_REORDER_DIS_SET (1 << 8) -#define CF8F_LOWER_CAS_LAT_SHIFT 28 -#define CF8F_LOWER_ACT2ACTREF_SHIFT 24 -#define CF8F_LOWER_ACT2PRE_SHIFT 20 -#define CF8F_LOWER_PRE2ACT_SHIFT 16 -#define CF8F_LOWER_ACT2CMD_SHIFT 12 -#define CF8F_LOWER_ACT2ACT_SHIFT 8 -#define CF8F_UPPER_HOI_LOI_SET (1 << 1) - -#define MC_CF1017_DATA (MSR_MC + 0x1A) -#define CF1017_LOWER_WR_TO_RD_SHIFT 28 -#define CF1017_LOWER_RD_TMG_CTL_SHIFT 24 -#define CF1017_LOWER_REF2ACT_SHIFT 16 -#define CF1017_LOWER_PM1_UP_DLY_SET (1 << 8) -#define CF1017_LOWER_WR2DAT_SHIFT 0 - -#define MC_CFCLK_DBUG (MSR_MC + 0x1D) - -#define CFCLK_UPPER_MTST_B2B_DIS_SET (1 << 2) -#define CFCLK_UPPER_MTST_RBEX_EN_SET (1 << 1) -#define CFCLK_UPPER_MTEST_EN_SET (1 << 0) - -#define CFCLK_LOWER_FORCE_PRE_SET (1 << 16) -#define CFCLK_LOWER_TRISTATE_DIS_SET (1 << 12) -#define CFCLK_LOWER_MASK_CKE_SET1 (1 << 9) -#define CFCLK_LOWER_MASK_CKE_SET0 (1 << 8) -#define CFCLK_LOWER_SDCLK_SET (0x0F << 0) - -#define MC_CF_RDSYNC (MSR_MC + 0x1F) -#define MC_CF_PMCTR (MSR_MC + 0x20) - - -/* GLIU1 GLIU0 port2*/ - -#define GLIU1_GLD_MSR_CAP (MSR_GLIU1 + 0x2000) -#define GLIU1_GLD_MSR_ERROR (MSR_GLIU1 + 0x2003) -#define GLIU1_GLD_MSR_PM (MSR_GLIU1 + 0x2004) - -#define GLIU1_GLD_MSR_COH (MSR_GLIU1 + 0x80) -#define GLIU1_PORT_ACTIVE (MSR_GLIU1 + 0x81) -#define GLIU1_ARB (MSR_GLIU1 + 0x82) - - - -/* CPU ; does not need routing instructions since we are executing there.*/ - -#define CPU_GLD_MSR_CAP 0x2000 -#define CPU_GLD_MSR_CONFIG 0x2001 -#define CPU_GLD_MSR_PM 0x2004 - -#define CPU_GLD_MSR_DIAG 0x2005 -#define DIAG_SEL1_MODE_SHIFT 16 -#define DIAG_SEL1_SET (1 << 31) -#define DIAG_SEL0__MODE_SHIFT 0 -#define DIAG_SET0_SET (1 << 15) - -#define CPU_PF_CONF 0x1100 -#define RETURN_STACK_ENABLE_SET (1 << 4) -#define PF_CONF_CC_L1 (1 << 0) -#define CPU_PF_INVD 0x1102 -#define PF_RS_INVD_SET (1 << 1) -#define PF_CC_INVD_SET (1 << 0) -#define CPU_PF_BIST 0x1140 - -#define CPU_XC_CONFIG 0x1210 -#define XC_CONFIG_SUSP_ON_HLT (1 << 0) -#define XC_CONFIG_SUSP_ON_PAUSE (1 << 1) - -#define CPU_ID_CONFIG 0x1250 -#define ID_CONFIG_SERIAL_SET (1 << 0) - -#define CPU_AC_MSR 0x1301 - -/* SMM*/ -#define CPU_AC_SMM_CTL 0x1301 -#define SMM_NMI_EN_SET (1 << 0) -#define SMM_SUSP_EN_SET (1 << 1) -#define NEST_SMI_EN_SET (1 << 2) -#define SMM_INST_EN_SET (1 << 3) -#define INTL_SMI_EN_SET (1 << 4) -#define EXTL_SMI_EN_SET (1 << 5) - -#define CPU_EX_BIST 0x1428 - -/*IM*/ -#define CPU_IM_CONFIG 0x1700 -#define IM_CONFIG_LOWER_SERIAL_SET (1 << 2) -#define IM_CONFIG_LOWER_L0WE_SET (1 << 6) -#define IM_CONFIG_LOWER_ICD_SET (1 << 8) -#define IM_CONFIG_LOWER_EBE_SET (1 << 10) -#define IM_CONFIG_LOWER_ABSE_SET (1 << 11) -#define IM_CONFIG_LOWER_QWT_SET (1 << 20) -#define CPU_IC_INDEX 0x1710 -#define CPU_IC_DATA 0x1711 -#define CPU_IC_TAG 0x1712 -#define CPU_IC_TAG_I 0x1713 -#define CPU_ITB_INDEX 0x1720 -#define CPU_ITB_LRU 0x1721 -#define CPU_ITB_ENTRY 0x1722 -#define CPU_ITB_ENTRY_I 0x1723 -#define CPU_IM_BIST_TAG 0x1730 -#define CPU_IM_BIST_DATA 0x1731 - - -/*DM MSR MAP*/ -#define CPU_DM_CONFIG0 0x1800 -#define DM_CONFIG0_UPPER_WSREQ_SHIFT 12 -#define DM_CONFIG0_LOWER_EVCTONRPL_SET (1 << 14) -#define DM_CONFIG0_LOWER_WBINVD_SET (1<<5) -#define DM_CONFIG0_LOWER_DCDIS_SET (1 << 8) -#define DM_CONFIG0_LOWER_MISSER_SET (1<<1) - -#define CPU_RCONF_DEFAULT 0x1808 -#define RCONF_DEFAULT_UPPER_ROMRC_SHIFT 24 -#define RCONF_DEFAULT_UPPER_ROMBASE_SHIFT 4 -#define RCONF_DEFAULT_UPPER_DEVRC_HI_SHIFT 0 -#define RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT 28 -#define RCONF_DEFAULT_LOWER_SYSTOP_SHIFT 8 -#define RCONF_DEFAULT_LOWER_SYSRC_SHIFT 0 - -#define CPU_RCONF_BYPASS 0x180A -#define CPU_RCONF_A0_BF 0x180B -#define CPU_RCONF_C0_DF 0x180C -#define CPU_RCONF_E0_FF 0x180D - -#define CPU_RCONF_SMM 0x180E -#define RCONF_SMM_UPPER_SMMTOP_SHIFT 12 -#define RCONF_SMM_UPPER_RCSMM_SHIFT 0 -#define RCONF_SMM_LOWER_SMMBASE_SHIFT 12 -#define RCONF_SMM_LOWER_RCNORM_SHIFT 0 -#define RCONF_SMM_LOWER_EN_SET (1<<8) - -#define CPU_RCONF_DMM 0x180F -#define RCONF_DMM_UPPER_DMMTOP_SHIFT 12 -#define RCONF_DMM_UPPER_RCDMM_SHIFT 0 -#define RCONF_DMM_LOWER_DMMBASE_SHIFT 12 -#define RCONF_DMM_LOWER_RCNORM_SHIFT 0 -#define RCONF_DMM_LOWER_EN_SET (1<<8) - -#define CPU_RCONF0 0x1810 -#define CPU_RCONF1 0x1811 -#define CPU_RCONF2 0x1812 -#define CPU_RCONF3 0x1813 -#define CPU_RCONF4 0x1814 -#define CPU_RCONF5 0x1815 -#define CPU_RCONF6 0x1816 -#define CPU_RCONF7 0x1817 -#define CPU_CR1_MSR 0x1881 -#define CPU_CR2_MSR 0x1882 -#define CPU_CR3_MSR 0x1883 -#define CPU_CR4_MSR 0x1884 -#define CPU_DC_INDEX 0x1890 -#define CPU_DC_DATA 0x1891 -#define CPU_DC_TAG 0x1892 -#define CPU_DC_TAG_I 0x1893 -#define CPU_SNOOP 0x1894 -#define CPU_DTB_INDEX 0x1898 -#define CPU_DTB_LRU 0x1899 -#define CPU_DTB_ENTRY 0x189A -#define CPU_DTB_ENTRY_I 0x189B -#define CPU_L2TB_INDEX 0x189C -#define CPU_L2TB_LRU 0x189D -#define CPU_L2TB_ENTRY 0x189E -#define CPU_L2TB_ENTRY_I 0x189F -#define CPU_DM_BIST 0x18C0 - -#define CPU_BC_CONF_0 0x1900 -#define TSC_SUSP_SET (1<<5) -#define SUSP_EN_SET (1<<12) - -#define CPU_BC_CONF_1 0x1901 -#define CPU_BC_MSR_LOCK 0x1908 -#define CPU_BC_L2_CONF 0x1920 -#define BC_L2_ENABLE_SET (1 << 0) -#define BC_L2_ALLOC_ENABLE_SET (1 << 1) -#define BC_L2_DM_ALLOC_ENABLE_SET (1 << 2) -#define BC_L2_IM_ALLOC_ENABLE_SET (1 << 3) -#define BC_L2_INVALIDATE_SET (1 << 4) -#define CPU_BC_L2_STATUS 0x1921 -#define CPU_BC_L2_INDEX 0x1922 -#define CPU_BC_L2_DATA 0x1923 -#define CPU_BC_L2_TAG 0x1924 -#define CPU_BC_L2_TAG_AUTOINC 0x1925 -#define CPU_BC_L2_BIST 0x1926 -#define BC_L2_BIST_TAG_ENABLE_SET (1 << 0) -#define BC_L2_BIST_TAG_DRT_EN_SET (1 << 1) -#define BC_L2_BIST_DATA_ENABLE_SET (1 << 2) -#define BC_L2_BIST_DATA_DRT_EN_SET (1 << 3) -#define BC_L2_BIST_MRU_ENABLE_SET (1 << 4) -#define BC_L2_BIST_MRU_DRT_EN_SET (1 << 5) -#define CPU_BC_PMODE_MSR 0x1930 -#define CPU_BC_MSS_ARRAY_CTL_ENA 0x1980 -#define CPU_BC_MSS_ARRAY_CTL0 0x1981 -#define CPU_BC_MSS_ARRAY_CTL1 0x1982 -#define CPU_BC_MSS_ARRAY_CTL2 0x1983 - -#define CPU_FPU_MSR_MODE 0x1A00 -#define FPU_IE_SET (1 << 0) - -#define CPU_FP_UROM_BIST 0x1A03 - -#define CPU_CPUID0 0x3000 -#define CPU_CPUID1 0x3001 -#define CPU_CPUID2 0x3002 -#define CPU_CPUID3 0x3003 -#define CPU_CPUID4 0x3004 -#define CPU_CPUID5 0x3005 -#define CPU_CPUID6 0x3006 -#define CPU_CPUID7 0x3007 -#define CPU_CPUID8 0x3008 -#define CPU_CPUID9 0x3009 -#define CPU_CPUIDA 0x300A -#define CPU_CPUIDB 0x300B -#define CPU_CPUIDC 0x300C -#define CPU_CPUIDD 0x300D -#define CPU_CPUIDE 0x300E -#define CPU_CPUIDF 0x300F -#define CPU_CPUID10 0x3010 -#define CPU_CPUID11 0x3011 -#define CPU_CPUID12 0x3012 -#define CPU_CPUID13 0x3013 - - - - - /* VG GLIU0 port4*/ - - -#define VG_GLD_MSR_CAP (MSR_VG + 0x2000) -#define VG_GLD_MSR_CONFIG (MSR_VG + 0x2001) -#define VG_GLD_MSR_PM (MSR_VG + 0x2004) -#define VG_BIST (MSR_VG + 0x2010) - - - -/* GP GLIU0 port5*/ - - -#define GP_GLD_MSR_CAP (MSR_GP + 0x2000) -#define GP_GLD_MSR_CONFIG (MSR_GP + 0x2001) -#define GP_GLD_MSR_PM (MSR_GP + 0x2004) - - - -/* DF GLIU0 port6*/ - - -#define DF_GLD_MSR_CAP (MSR_DF + 0x2000) -#define DF_GLD_MSR_MASTER_CONF (MSR_DF + 0x2001) -#define DF_LOWER_LCD_SHIFT 6 -#define DF_GLD_MSR_PM (MSR_DF + 0x2004) -#define DF_BIST (MSR_DF + 0x2005) - - - -/* GeodeLink Control Processor GLIU1 port3*/ - -#define GLCP_GLD_MSR_CAP (MSR_GLCP + 0x2000) -#define GLCP_GLD_MSR_CONF (MSR_GLCP + 0x2001) -#define GLCP_GLD_MSR_SMI (MSR_GLCP + 0x2002) -#define GLCP_GLD_MSR_ERROR (MSR_GLCP + 0x2003) -#define GLCP_GLD_MSR_PM (MSR_GLCP + 0x2004) - -#define GLCP_DELAY_CONTROLS (MSR_GLCP + 0x0F) -#define GLCP_SYS_RSTPLL (MSR_GLCP + 0x14) /* R/W */ -#define RSTPLL_UPPER_GLMULT_SHIFT 7 -#define RSTPLL_UPPER_GLDIV_SHIFT 6 -#define RSTPLL_UPPER_CPUMULT_SHIFT 1 -#define RSTPLL_UPPER_CPUDIV_SHIFT 0 -#define RSTPLL_LOWER_SWFLAGS_SHIFT 26 -#define RSTPLL_LOWER_SWFLAGS_MASK \ - (0x03F << RSTPLL_LOWER_SWFLAGS_SHIFT) -#define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16 -#define RSTPPL_LOWER_COREBYPASS_SHIFT 12 -#define RSTPPL_LOWER_GLBYPASS_SHIFT 11 -#define RSTPPL_LOWER_PCISPEED_SHIFT 7 -#define RSTPPL_LOWER_BOOTSTRAP_SHIFT 1 -#define RSTPLL_LOWER_BOOTSTRAP_MASK \ - (0x07F << RSTPLL_LOWER_BOOTSTRAP_SHIFT) - -#define RSTPPL_LOWER_GLLOCK_SET (1 << 25) -#define RSTPPL_LOWER_CORELOCK_SET (1 << 24) -#define RSTPPL_LOWER_LOCKWAIT_SET (1 << 15) -#define RSTPPL_LOWER_CLPD_SET (1 << 14) -#define RSTPPL_LOWER_COREPD_SET (1 << 13) -#define RSTPPL_LOWER_MBBYPASS_SET (1 << 12) -#define RSTPPL_LOWER_COREBYPASS_SET (1 << 11) -#define RSTPPL_LOWER_LPFEN_SET (1 << 10) -#define RSTPPL_LOWER_CPU_SEMI_SYNC_SET (1<<9) -#define RSTPPL_LOWER_PCI_SEMI_SYNC_SET (1<<8) -#define RSTPPL_LOWER_CHIP_RESET_SET (1<<0) - -#define GLCP_DOWSER (MSR_GLCP + 0x0E) -#define GLCP_DBGCLKCTL (MSR_GLCP + 0x16) -#define GLCP_REVID (MSR_GLCP + 0x17) -#define GLCP_TH_OD (MSR_GLCP + 0x1E) -#define GLCP_FIFOCTL (MSR_GLCP + 0x5E) -#define GLCP_BIST GLCP_FIFOCTL - -#define MSR_INIT (MSR_GLCP + 0x33) - - -/* GLIU1 port 4*/ - -#define GLPCI_GLD_MSR_CAP (MSR_PCI + 0x2000) -#define GLPCI_GLD_MSR_CONFIG (MSR_PCI + 0x2001) -#define GLPCI_GLD_MSR_PM (MSR_PCI + 0x2004) - -#define GLPCI_CTRL (MSR_PCI + 0x2010) -#define GLPCI_CTRL_UPPER_FTH_SHIFT 28 -#define GLPCI_CTRL_UPPER_RTH_SHIFT 24 -#define GLPCI_CTRL_UPPER_SBRTH_SHIFT 20 -#define GLPCI_CTRL_UPPER_RTL_SHIFT 17 -#define GLPCI_CTRL_UPPER_DTL_SHIFT 14 -#define GLPCI_CTRL_UPPER_WTO_SHIFT 11 -#define GLPCI_CTRL_UPPER_SLTO_SHIFT 10 -#define GLPCI_CTRL_UPPER_ILTO_SHIFT 8 -#define GLPCI_CTRL_UPPER_LAT_SHIFT 3 - -#define GLPCI_CTRL_LOWER_IRFT_SHIFT 18 -#define GLPCI_CTRL_LOWER_IRFC_SHIFT 16 -#define GLPCI_CTRL_LOWER_ER_SET (1<<11) -#define GLPCI_CTRL_LOWER_LDE_SET (1<<9) -#define GLPCI_CTRL_LOWER_OWC_SET (1<<4) -#define GLPCI_CTRL_LOWER_IWC_SET (1<<3) -#define GLPCI_CTRL_LOWER_PCD_SET (1<<2) -#define GLPCI_CTRL_LOWER_ME_SET (1<<0) - -#define GLPCI_ARB (MSR_PCI + 0x2011) -#define GLPCI_ARB_UPPER_CR_SHIFT 28 -#define GLPCI_ARB_UPPER_R2_SHIFT 24 -#define GLPCI_ARB_UPPER_R1_SHIFT 20 -#define GLPCI_ARB_UPPER_R0_SHIFT 16 -#define GLPCI_ARB_UPPER_CH_SHIFT 12 -#define GLPCI_ARB_UPPER_H2_SHIFT 8 -#define GLPCI_ARB_UPPER_H1_SHIFT 4 -#define GLPCI_ARB_UPPER_H0_SHIFT 0 - -#define GLPCI_ARB_LOWER_COV_SET (1<<23) -#define GLPCI_ARB_LOWER_VO2_SET (1 << 22) -#define GLPCI_ARB_LOWER_OV1_SET (1 << 21) -#define GLPCI_ARB_LOWER_OV0_SET (1 << 20) -#define GLPCI_ARB_LOWER_MSK2_SET (1<<18) -#define GLPCI_ARB_LOWER_MSK1_SET (1<<17) -#define GLPCI_ARB_LOWER_MSK0_SET (1<<16) -#define GLPCI_ARB_LOWER_CPRE_SET (1<<11) -#define GLPCI_ARB_LOWER_PRE2_SET (1<<10) -#define GLPCI_ARB_LOWER_PRE1_SET (1<<9) -#define GLPCI_ARB_LOWER_PRE0_SET (1<<8) -#define GLPCI_ARB_LOWER_BM1_SET (1<<7) -#define GLPCI_ARB_LOWER_BM0_SET (1<<6) -#define GLPCI_ARB_LOWER_EA_SET (1 << 2) -#define GLPCI_ARB_LOWER_BMD_SET (1 << 1) -#define GLPCI_ARB_LOWER_PARK_SET (1<<0) - -#define GLPCI_REN (MSR_PCI + 0x2014) -#define GLPCI_A0_BF (MSR_PCI + 0x2015) -#define GLPCI_C0_DF (MSR_PCI + 0x2016) -#define GLPCI_E0_FF (MSR_PCI + 0x2017) -#define GLPCI_RC0 (MSR_PCI + 0x2018) -#define GLPCI_RC1 (MSR_PCI + 0x2019) -#define GLPCI_RC2 (MSR_PCI + 0x201A) -#define GLPCI_RC3 (MSR_PCI + 0x201B) -#define GLPCI_RC4 (MSR_PCI + 0x201C) -#define GLPCI_RC_UPPER_TOP_SHIFT 12 -#define GLPCI_RC_LOWER_BASE_SHIFT 12 -#define GLPCI_RC_LOWER_EN_SET (1<<8) -#define GLPCI_RC_LOWER_PF_SET (1<<5) -#define GLPCI_RC_LOWER_WC_SET (1<<4) -#define GLPCI_RC_LOWER_WP_SET (1<<2) -#define GLPCI_RC_LOWER_CD_SET (1<<0) - -#define GLPCI_ExtMSR (MSR_PCI + 0x201E) - -#define GLPCI_SPARE (MSR_PCI + 0x201F) -#define GLPCI_SPARE_LOWER_AILTO_SET (1<<6) -#define GLPCI_SPARE_LOWER_PPD_SET (1<<5) -#define GLPCI_SPARE_LOWER_PPC_SET (1<<4) -#define GLPCI_SPARE_LOWER_MPC_SET (1<<3) -#define GLPCI_SPARE_LOWER_MME_SET (1<<2) -#define GLPCI_SPARE_LOWER_NSE_SET (1<<1) -#define GLPCI_SPARE_LOWER_SUPO_SET (1<<0) - - - -/* VIP GLIU1 port 5*/ - -#define VIP_GLD_MSR_CAP (MSR_VIP + 0x2000) -#define VIP_GLD_MSR_CONFIG (MSR_VIP + 0x2001) -#define VIP_GLD_MSR_PM (MSR_VIP + 0x2004) -#define VIP_BIST (MSR_VIP + 0x2005) - -/* AES GLIU1 port 6*/ - -#define AES_GLD_MSR_CAP (MSR_AES + 0x2000) -#define AES_GLD_MSR_CONFIG (MSR_AES + 0x2001) -#define AES_GLD_MSR_PM (MSR_AES + 0x2004) -#define AES_CONTROL (MSR_AES + 0x2006) - - -/* from MC spec */ -#define MIN_MOD_BANKS 1 -#define MAX_MOD_BANKS 2 -#define MIN_DEV_BANKS 2 -#define MAX_DEV_BANKS 4 -#define MAX_COL_ADDR 17 - -/* GLIU typedefs */ -/* Base Mask - map power of 2 size aligned region*/ -#define BM 1 -#define BMO 2 /* BM with an offset*/ -#define R 3 /* Range - 4k range minimum*/ -#define RO 4 /* R with offset*/ -/* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R*/ -#define SC 5 -#define BMIO 6 /* Base Mask IO*/ -#define SCIO 7 /* Swiss 0xCeese IO*/ -/* Special marker for Shadow SC descriptors so setShadow proc is independent - * of CPU - */ -#define SC_SHADOW 8 -/* Special marker for SYSMEM R descriptors so GLIUInit proc is independent - * of CPU - */ -#define R_SYSMEM 9 -#define BMO_SMM 10 /* Special marker for SMM*/ -#define BM_SMM 11 /* Special marker for SMM*/ -#define BMO_DMM 12 /* Special marker for DMM*/ -#define BM_DMM 13 /* Special marker for DMM*/ -#define RO_FB 14 /* special for Frame buffer.*/ -#define R_FB 15 /* special for FB.*/ -#define OTHER 0x0FE /* Special marker for other*/ -#define GL_END 0x0FF /* end*/ - -#define MSR_GL0 (GL1_GLIU0 << 29) - - -/* Platform stuff but unlikely to change */ -/* Set up desc addresses from 20 - 3f*/ -/* This is chip specific!*/ -#define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM*/ -#define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM*/ -#define MSR_GLIU0_BASE3 (MSR_GLIU0 + 0x22) /* BM*/ -#define MSR_GLIU0_BASE4 (MSR_GLIU0 + 0x23) /* BM*/ -#define MSR_GLIU0_BASE5 (MSR_GLIU0 + 0x24) /* BM*/ -#define MSR_GLIU0_BASE6 (MSR_GLIU0 + 0x25) /* BM*/ - -#define GLIU0_P2D_BMO_0 (MSR_GLIU0 + 0x26) -#define GLIU0_P2D_BMO_1 (MSR_GLIU0 + 0x27) - -#define MSR_GLIU0_SMM (GLIU0_P2D_BMO_0) -#define MSR_GLIU0_DMM (GLIU0_P2D_BMO_1) - -#define GLIU0_P2D_R (MSR_GLIU0 + 0x28) -#define MSR_GLIU0_SYSMEM (GLIU0_P2D_R) - -#define GLIU0_P2D_RO_0 (MSR_GLIU0 + 0x29) -#define GLIU0_P2D_RO_1 (MSR_GLIU0 + 0x2A) -#define GLIU0_P2D_RO_2 (MSR_GLIU0 + 0x2B) - -/* SCO should only be SC*/ -#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) - -#define GLIU0_IOD_BM_0 (MSR_GLIU0 + 0xE0) -#define GLIU0_IOD_BM_1 (MSR_GLIU0 + 0xE1) -#define GLIU0_IOD_BM_2 (MSR_GLIU0 + 0xE2) - -#define GLIU0_IOD_SC_0 (MSR_GLIU0 + 0xE3) -#define GLIU0_IOD_SC_1 (MSR_GLIU0 + 0xE4) -#define GLIU0_IOD_SC_2 (MSR_GLIU0 + 0xE5) -#define GLIU0_IOD_SC_3 (MSR_GLIU0 + 0xE6) -#define GLIU0_IOD_SC_4 (MSR_GLIU0 + 0xE7) -#define GLIU0_IOD_SC_5 (MSR_GLIU0 + 0xE8) - - -#define MSR_GLIU1_BASE1 (MSR_GLIU1 + 0x20) /* BM*/ -#define MSR_GLIU1_BASE2 (MSR_GLIU1 + 0x21) /* BM*/ -#define MSR_GLIU1_BASE3 (MSR_GLIU1 + 0x22) /* BM*/ -#define MSR_GLIU1_BASE4 (MSR_GLIU1 + 0x23) /* BM*/ -#define MSR_GLIU1_BASE5 (MSR_GLIU1 + 0x24) /* BM*/ -#define MSR_GLIU1_BASE6 (MSR_GLIU1 + 0x25) /* BM*/ -#define MSR_GLIU1_BASE7 (MSR_GLIU1 + 0x26) /* BM*/ -#define MSR_GLIU1_BASE8 (MSR_GLIU1 + 0x27) /* BM*/ -#define MSR_GLIU1_BASE9 (MSR_GLIU1 + 0x28) /* BM*/ -#define MSR_GLIU1_BASE10 (MSR_GLIU1 + 0x29) /* BM*/ - -#define GLIU1_P2D_R_0 (MSR_GLIU1 + 0x2A) -#define GLIU1_P2D_R_1 (MSR_GLIU1 + 0x2B) -#define GLIU1_P2D_R_2 (MSR_GLIU1 + 0x2C) -#define GLIU1_P2D_R_3 (MSR_GLIU1 + 0x2D) - - -#define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2E) - -#define MSR_GLIU1_SYSMEM (GLIU1_P2D_R_0) - -#define MSR_GLIU1_SMM (MSR_GLIU1_BASE4) /* BM*/ -#define MSR_GLIU1_DMM (MSR_GLIU1_BASE5) /* BM*/ - -#define GLIU1_IOD_BM_0 (MSR_GLIU1 + 0xE0) -#define GLIU1_IOD_BM_1 (MSR_GLIU1 + 0xE1) -#define GLIU1_IOD_BM_2 (MSR_GLIU1 + 0xE2) - -#define GLIU1_IOD_SC_0 (MSR_GLIU1 + 0xE3) -#define GLIU1_IOD_SC_1 (MSR_GLIU1 + 0xE4) -#define GLIU1_IOD_SC_2 (MSR_GLIU1 + 0xE5) -#define GLIU1_IOD_SC_3 (MSR_GLIU1 + 0xE6) -/* FooGlue F0 for FPU*/ -#define MSR_GLIU1_FPU_TRAP (GLIU1_IOD_SC_0) - -/* ------------------------ */ - -#define SMM_OFFSET 0x80400000 /* above 2GB */ -#define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */ - -/* DRAM_TERMINATED affects how the DELAY register is set. */ -#define DRAM_TERMINATED 'T' -#define DRAM_UNTERMINATED 't' -/* Bitfield definitions for the DELAY register */ -#define DELAY_UPPER_DISABLE_CLK135 (1 << 23) -#define DELAY_LOWER_STATUS_MASK 0x7C0 - -#if !defined(__ASSEMBLER__) - -#include -#include - -#if defined(__PRE_RAM__) -void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated); -void SystemPreInit(void); -void asmlinkage mainboard_romstage_entry(unsigned long bist); -void done_cache_as_ram_main(void); -#endif -void cpubug(void); -#endif - -#endif diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index f6b213e69d..edbf7bb2aa 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -38,7 +38,7 @@ #define TOP_MEM_MASK 0x007fffff #define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10) -#if !defined(__PRE_RAM__) && !defined(__ASSEMBLER__) +#if !defined(__ROMCC__) && !defined(__ASSEMBLER__) #include diff --git a/src/include/cpu/amd/multicore.h b/src/include/cpu/amd/multicore.h index b8680933ae..79bea66f68 100644 --- a/src/include/cpu/amd/multicore.h +++ b/src/include/cpu/amd/multicore.h @@ -17,6 +17,7 @@ #define CPU_AMD_QUADCORE_H #include +#include u32 read_nb_cfg_54(void); @@ -29,17 +30,14 @@ struct node_core_id { struct node_core_id get_node_core_id(u32 nb_cfg_54); struct node_core_id get_node_core_id_x(void); -#if !defined(__PRE_RAM__) -struct device; u32 get_apicid_base(u32 ioapic_num); void amd_sibling_init(struct device *cpu); -#else + void wait_all_core0_started(void); void wait_all_other_cores_started(u32 bsp_apicid); void wait_all_aps_started(u32 bsp_apicid); void wait_all_other_cores_stopped(uint32_t bsp_apicid); void allow_all_aps_stop(u32 bsp_apicid); -#endif u32 get_initial_apicid(void); #endif /* CPU_AMD_QUADCORE_H */ diff --git a/src/include/cpu/amd/vr.h b/src/include/cpu/amd/vr.h deleted file mode 100644 index b5a1fe44ba..0000000000 --- a/src/include/cpu/amd/vr.h +++ /dev/null @@ -1,500 +0,0 @@ -/* -* -* Copyright (C) 2007 Advanced Micro Devices -* -*/ - -#ifndef CPU_AMD_VR_H -#define CPU_AMD_VR_H - -#include -#include - -#define VRC_INDEX 0xAC1C // Index register -#define VRC_DATA 0xAC1E // Data register -#define VR_UNLOCK 0xFC53 // Virtual register unlock code -#define NO_VR -1 // No virtual registers - -#define VRC_MISCELLANEOUS 0x00 // Miscellaneous Class - #define VSA_VERSION_NUM 0x00 - #define HIGH_MEM_ACCESS 0x01 - #define GET_VSM_INFO 0x02 // Used by INFO - #define GET_BASICS 0x00 - #define GET_EVENT 0x01 - #define GET_STATISTICS 0x02 - #define GET_HISTORY 0x03 - #define GET_HARDWARE 0x04 - #define GET_ERROR 0x05 - #define SET_VSM_TYPE 0x06 - #define SIGNATURE 0x03 - #define VSA2_SIGNATURE 0x56534132 // 'VSA2' returned in EAX - - #define GET_HW_INFO 0x04 - #define VSM_VERSION 0x05 - #define CTRL_ALT_DEL 0x06 - #define MSR_ACCESS 0x07 - #define GET_DESCR_INFO 0x08 - #define PCI_INT_AB 0x09 // GPIO pins for INTA# and INTB# - #define PCI_INT_CD 0x0A // GPIO pins for INTC# and INTD# - #define WATCHDOG 0x0B // Watchdog timer - - #define MAX_MISC WATCHDOG - - -// NOTE: Do not change the order of the following registers: -#define VRC_AUDIO 0x01 // XpressAudio Class - #define AUDIO_VERSION 0x00 - #define PM_STATE 0x01 - #define SB_16_IO_BASE 0x02 - #define MIDI_BASE 0x03 - #define CPU_USAGE 0x04 - #define CODEC_TYPE 0x05 - #define STATE_INDEX 0x06 - #define STATE_DATA 0x07 - #define AUDIO_IRQ 0x08 // For use by native audio drivers - #define STATUS_PTR 0x09 // For use by native audio drivers - #define MAX_AUDIO STATUS_PTR - -#define VRC_VG 0x02 // SoftVG Class -#define VRC_VGA 0x02 // SoftVGA Class - #define VG_MEM_SIZE 0x00 // bits 7:0 - 512K unit size, bit 8 controller priority - #define VG_CONFIG 0x00 // Main configuration register - #define VG_CFG_BYPASS 0x0001 // DOTPLL bypass bit - #define VG_MEM_MASK 0x00FE // Memory size mask bits, 2MB increment - #define VG_CFG_DSMASK 0x0700 // Active display mask bits - #define VG_CFG_DSCRT 0x0000 // Active display is CRT - #define VG_CFG_DSPAN 0x0100 // Active display is panel - #define VG_CFG_DSTV 0x0200 // Active display is TV - #define VG_CFG_DSSIM 0x0400 // Simultaneous CRT - #define VG_CFG_PRIORITY 0x0800 // Controller priority bit - #define VG_CFG_MONO 0x1000 // External monochrome card support bit - #define VG_CFG_DRIVER 0x2000 // Driver active bit - #define VG_CRTC_DIAG 0x8000 // Enable CRTC emulation - - // Defined for GX3/GX3VG - #define VG_REFRESH 0x01 // Mode refresh, a mode switch without changing modes - #define VG_FRSH_REF_MASK 0xE000 // Refresh rate mask - #define VG_FRSH_REF_GO 0x1000 // Refresh rate GO bit - // Uses CFP_REF_xxx values from below - #define VG_FRSH_BPP_MASK 0x0E00 // Color depth mask - #define VG_FRSH_BPP_GO 0x0100 // Color depth GO bit - #define FRSH_BPP_8RGB 0x0200 // 8 bits per pixel, RGB - #define FRSH_BPP_16ARGB 0x0400 // 16BPP, ARGB (4:4:4:4) - #define FRSH_BPP_15RGB 0x0600 // 15BPP, RGB (1:5:5:5) - #define FRSH_BPP_16RGB 0x0800 // 16BPP, RGB (5:6:5) - #define FRSH_BPP_24RGB 0x0A00 // 24BPP, RGB (0:8:8:8) - #define FRSH_BPP_32ARGB 0x0C00 // 32BPP, ARGB (8:8:8:8) - #define VG_CFG_DPMS 0x00C0 // DPMS mask bits - #define VG_CFG_DPMS_H 0x0040 // HSYNC mask bit - #define VG_CFG_DPMS_V 0x0080 // VSYNC mask bit - #define VG_VESA_SV_RST 0x0020 // VESA Save/Restore state flag - #define VG_VESA_RST 0x0000 // VESA Restore state - #define VG_VESA_SV 0x0020 // VESA Save state - #define VG_FRSH_MODE 0x0002 // Mode refresh flag - #define VG_FRSH_TIMINGS 0x0001 // Timings only refresh flag - - // Defined for GX2/SoftVG - #define VG_PLL_REF 0x01 // PLL reference frequency selection register - #define PLL_14MHZ 0x0000 // 14.31818MHz PLL reference frequency (Default) - #define PLL_48MHZ 0x0100 // 48MHz PLL reference frequency - - // Defined for GX1/SoftVGA - #define VGA_MEM_SIZE 0x01 // bits 7:1 - 128K unit size, bit 0 controller enable - - #define VG_FP_TYPE 0x02 // Flat panel type data - // VG_FP_TYPE definitions for GX2/SoftVG - #define FP_TYPE_SSTN 0x0000 // SSTN panel type value - #define FP_TYPE_DSTN 0x0001 // DSTN panel type value - #define FP_TYPE_TFT 0x0002 // TFT panel type value - #define FP_TYPE_LVDS 0x0003 // LVDS panel type value - #define FP_RES_6X4 0x0000 // 640x480 resolution value - #define FP_RES_8X6 0x0008 // 800x600 resolution value - #define FP_RES_10X7 0x0010 // 1024x768 resolution value - #define FP_RES_11X8 0x0018 // 1152x864 resolution value - #define FP_RES_12X10 0x0020 // 1280x1024 resolution value - #define FP_RES_16X12 0x0028 // 1600x1200 resolution value - #define FP_WIDTH_8 0x0000 // 8 bit data bus width - #define FP_WIDTH_9 0x0040 // 9 bit data bus width - #define FP_WIDTH_12 0x0080 // 12 bit data bus width - #define FP_WIDTH_18 0x00C0 // 18 bit data bus width - #define FP_WIDTH_24 0x0100 // 24 bit data bus width - #define FP_WIDTH_16 0x0140 // 16 bit data bus width - 16 bit Mono DSTN only - #define FP_COLOR_COLOR 0x0000 // Color panel - #define FP_COLOR_MONO 0x0200 // Mono Panel - #define FP_PPC_1PPC 0x0000 // One pixel per clock - #define FP_PPC_2PPC 0x0400 // Two pixels per clock - #define FP_H_POL_LGH 0x0000 // HSync at panel, normally low, active high - #define FP_H_POL_HGL 0x0800 // HSync at panel, normally high, active low - #define FP_V_POL_LGH 0x0000 // VSync at panel, normally low, active high - #define FP_V_POL_HGL 0x1000 // VSync at panel, normally high, active low - #define FP_REF_60 0x0000 // 60Hz refresh rate - #define FP_REF_65 0x2000 // 65Hz refresh rate - #define FP_REF_70 0x4000 // 70Hz refresh rate - #define FP_REF_72 0x6000 // 72Hz refresh rate - #define FP_REF_75 0x8000 // 75Hz refresh rate - #define FP_REF_85 0xA000 // 85Hz refresh rate - - // VG_FP_TYPE definitions for GX3/GX3VG - #define FP_TYPE_TYPE 0x0003 // Flat panel type bits mask - #define CFP_TYPE_TFT 0x0000 // TFT panel type value - #define CFP_TYPE_LVDS 0x0001 // LVDS panel type value - #define FP_TYPE_RES 0x0038 // Panel resolution bits mask - #define CFP_RES_3X2 0x0000 // 320x240 resolution value - #define CFP_RES_6X4 0x0008 // 640x480 resolution value - #define CFP_RES_8X6 0x0010 // 800x600 resolution value - #define CFP_RES_10X7 0x0018 // 1024x768 resolution value - #define CFP_RES_11X8 0x0020 // 1152x864 resolution value - #define CFP_RES_12X10 0x0028 // 1280x1024 resolution value - #define CFP_RES_16X12 0x0030 // 1600x1200 resolution value - #define FP_TYPE_BUS 0x00C0 // Data bus width and pixels/clock mask - #define CFP_BUS_1PPC 0x0040 // 9, 12, 18 or 24 bit data bus, 1 pixel per clock - #define CFP_BUS_2PPC 0x0080 // 18 or 24 bit data bus, 2 pixels per clock - #define FP_TYPE_HPOL 0x0800 // HSYNC polarity into the panel - #define CFP_HPOL_HGL 0x0000 // HSync at panel, normally high, active low - #define CFP_HPOL_LGH 0x0800 // HSync at panel, normally low, active high - #define FP_TYPE_VPOL 0x1000 // VSYNC polarity into the panel - #define CFP_VPOL_HGL 0x0000 // VSync at panel, normally high, active low - #define CFP_VPOL_LGH 0x1000 // VSync at panel, normally low, active high - #define FP_TYPE_REF 0xE000 // Panel refresh rate - #define CFP_REF_60 0x0000 // 60Hz refresh rate - #define CFP_REF_70 0x2000 // 70Hz refresh rate - #define CFP_REF_75 0x4000 // 75Hz refresh rate - #define CFP_REF_85 0x6000 // 85Hz refresh rate - #define CFP_REF_100 0x8000 // 100Hz refresh rate - - #define VG_FP_OPTION 0x03 // Flat panel option data - #define FP_OPT_SCLK_NORMAL 0x0000 // SHFTClk not inverted to panel - #define FP_OPT_SCLK_INVERTED 0x0010 // SHFTClk inverted to panel - #define FP_OPT_SCLK_ACT_ACTIVE 0x0000 // SHFTClk active during "active" only - #define FP_OPT_SCLK_ACT_FREE 0x0020 // SHFTClk free-running - #define FP_OPT_LP_ACT_FREE 0x0000 // LP free-running - #define FP_OPT_LP_ACT_ACTIVE 0x0040 // LP active during "active" only - #define FP_OPT_LDE_POL_LGH 0x0000 // LDE/MOD, normally low, active high - #define FP_OPT_LDE_POL_HGL 0x0080 // LDE/MOD, normally high, active low - #define FP_OPT_PWR_DLY_32MS 0x0000 // 32MS delay for each step of pwr seq. - #define FP_OPT_PWR_DLY_128MS 0x0100 // 128MS delay for each step of pwr seq. - - #define VG_TV_CONFIG 0x04 // TV configuration register - #define VG_TV_ENC 0x000F // TV encoder select mask - #define VG_TV_ADV7171 0x0000 // ADV7171 Encoder - #define VG_TV_SAA7127 0x0001 // ADV7171 Encoder - #define VG_TV_ADV7300 0x0002 // ADV7300 Encoder - #define VG_TV_FS454 0x0003 // FS454 Encoder - #define VG_TV_FMT 0x0070 // TV encoder output format mask - #define VG_TV_FMT_SHIFT 0x0004 // Right shift value - #define VG_TV_NTSC 0x0000 // NTSC output format - #define VG_TV_PAL 0x0010 // PAL output format - #define VG_TV_HDTV 0x0020 // HDTV output format - - // The meaning of the VG_TV_RES field is dependent on the selected - // encoder and output format. The translations are: - // ADV7171 - Not Used - // SAA7127 - Not Used - // ADV7300 - HDTV resolutions only - // LO -> 720x480p - // MED -> 1280x720p - // HI -> 1920x1080i - // FS454 - Both SD and HD resolutions - // SD Resolutions - NTSC and PAL - // LO -> 640x480 - // MED -> 800x600 - // HI -> 1024x768 - // HD Resolutions - // LO -> 720x480p - // MED -> 1280x720p - // HI -> 1920x1080i - #define VG_TV_RES 0x0780 // TV resolution select mask - #define VG_TV_RES_SHIFT 0x0007 // Right shift value - #define VG_TV_RES_LO 0x0000 // Low resolution - #define VG_TV_RES_MED 0x0080 // Medium resolution - #define VG_TV_RES_HI 0x0100 // High resolution - #define VG_TV_PASSTHRU 0x0800 // TV passthru mode - - #define VG_TV_SCALE_ADJ 0x05 // Modifies scaling factors for TV resolutions - #define VG_TV_HACT_ADJ 0x00FF // Horizontal active scale adjust value mask - #define VG_TV_VACT_ADJ 0xFF00 // Vertical active scale adjust value mask - - #define VG_DEBUG 0x0F // A debug register - - #define VG_FT_HTOT 0x10 // Fixed timings, horizontal total - #define VG_FT_HACT 0x11 // Fixed timings, horizontal active - #define VG_FT_HBST 0x12 // Fixed timings, horizontal blank start - #define VG_FT_HBND 0x13 // Fixed timings, horizontal blank end - #define VG_FT_HSST 0x14 // Fixed timings, horizontal sync start - #define VG_FT_HSND 0x15 // Fixed timings, horizontal sync end - - #define VG_FT_VTOT 0x16 // Fixed timings, vertical total - #define VG_FT_VACT 0x17 // Fixed timings, vertical active - #define VG_FT_VBST 0x18 // Fixed timings, vertical blank start - #define VG_FT_VBND 0x19 // Fixed timings, vertical blank end - #define VG_FT_VSST 0x1A // Fixed timings, vertical sync start - #define VG_FT_VSND 0x1B // Fixed timings, vertical sync end - - #define VG_START_OFFS_LO 0x20 // Framebuffer start offset bits 15:0 - #define VG_START_OFFS_HI 0x21 // Framebuffer start offset bits 27:16 - - #define VG_FT_VEACT 0x28 // Fixed timings, vertical active - #define VG_FT_VETOT 0x29 // Fixed timings, vertical total - #define VG_FT_VEBST 0x2A // Fixed timings, vertical blank start - #define VG_FT_VEBND 0x2B // Fixed timings, vertical blank end - #define VG_FT_VESST 0x2C // Fixed timings, vertical sync start - #define VG_FT_VESND 0x2D // Fixed timings, vertical sync end - - #define MAX_VGA VGA_MEM_SIZE -// #define MAX_VG VG_FP_OPTION -// #define MAX_VG VG_START_OFFS_HI - #define MAX_VG VG_FT_VESND - -#define VRC_APM 0x03 - #define REPORT_EVENT 0x00 - #define CAPABILITIES 0x01 - #define APM_PRESENT 0x02 - #define MAX_APM APM_PRESENT - - -#define VRC_PM 0x04 // Legacy PM Class - #define POWER_MODE 0x00 - #define POWER_STATE 0x01 - #define DOZE_TIMEOUT 0x02 - #define STANDBY_TIMEOUT 0x03 - #define SUSPEND_TIMEOUT 0x04 - #define PS2_TIMEOUT 0x05 - #define RESUME_ON_RING 0x06 - #define VIDEO_TIMEOUT 0x07 - #define DISK_TIMEOUT 0x08 - #define FLOPPY_TIMEOUT 0x09 - #define SERIAL_TIMEOUT 0x0A - #define PARALLEL_TIMEOUT 0x0B - #define IRQ_WAKEUP_MASK 0x0C -// #define SUSPEND_MODULATION 0x0D - #define SLEEP_PIN 0x0E - #define SLEEP_PIN_ATTR 0x0F -// #define SMI_WAKEUP_MASK 0x10 - #define INACTIVITY_CONTROL 0x11 - #define PM_S1_CLOCKS 0x12 - #define S1_CLOCKS_ON 0x00 - #define S1_CLOCKS_OFF 0x01 -// #define PM_S2_CLOCKS 0x13 -// #define PM_S3_CLOCKS 0x14 -// #define PM_S4_CLOCKS 0x15 -// #define PM_S5_CLOCKS 0x16 - #define PM_S0_LED 0x17 - #define PM_S1_LED 0x18 - #define PM_S2_LED 0x19 - #define PM_S3_LED 0x1A - #define PM_S4_LED 0x1B - #define PM_S5_LED 0x1C - #define PM_LED_GPIO 0x1D - #define PM_IMM_LED 0x1E - #define PM_PWR_LEDS 0x1F - #define MB_LED0 0x01 - #define MB_LED1 0x02 - #define MB_LED2 0x04 - #define MB_LED3 0x08 - #define SIO_LED0 0x10 - #define SIO_LED1 0x20 - #define SIO_LED2 0x40 - #define SIO_LED3 0x80 - #define PM_PME_MASK 0x20 - #define MAX_PM PM_PME_MASK - - -#define VRC_INFRARED 0x05 - #define MAX_INFRARED NO_VR - -#define VRC_TV 0x06 // TV Encoder Class - #define TV_ENCODER_TYPE 0x00 - #define TV_CALLBACK_MASK 0x01 - #define TV_MODE 0x02 - #define TV_POSITION 0x03 - #define TV_BRIGHTNESS 0x04 - #define TV_CONTRAST 0x05 - #define TV_OUTPUT 0x06 - #define TV_TIMING 0x10 // 0x10...0x1D are all timings - #define MAX_TV TV_TIMING - - - -#define VRC_EXTERNAL_AMP 0x07 - #define EAPD_VERSION 0x00 - #define AMP_POWER 0x01 - #define AMP_OFF 0x00 - #define AMP_ON 0x01 - #define AMP_TYPE 0x02 - #define MAX_EXTERNAL_AMP AMP_TYPE - - -#define VRC_ACPI 0x08 - #define ENABLE_ACPI 0x00 // Enable ACPI Mode - #define SCI_IRQ 0x01 // Set the IRQ the SCI is mapped to, sysbios use. - #define ACPINVS_LO 0x02 // new calls to send 32bit physAddress of - #define ACPINVS_HI 0x03 // ACPI NVS region to VSA - #define GLOBAL_LOCK 0x04 // read requests semaphore, write clears - #define ACPI_UNUSED1 0x05 - #define RW_PIRQ 0x06 // read/write PCI IRQ router regs in SB Func0 cfg space - #define SLPB_CLEAR 0x07 // clear sleep button GPIO status's - #define PIRQ_ROUTING 0x08 // read the PCI IRQ routing based on BIOS setup - #define ACPI_UNUSED2 0x09 - #define ACPI_UNUSED3 0x0A - #define PIC_INTERRUPT 0x0B - #define ACPI_PRESENT 0x0C - #define ACPI_GEN_COMMAND 0x0D - #define ACPI_GEN_PARAM1 0x0E - #define ACPI_GEN_PARAM2 0x0F - #define ACPI_GEN_PARAM3 0x10 - #define ACPI_GEN_RETVAL 0x11 - #define MAX_ACPI ACPI_GEN_RETVAL - -#define VRC_ACPI_OEM 0x09 - #define MAX_ACPI_OEM NO_VR - -#define VRC_POWER 0x0A - #define BATTERY_UNITS 0x00 // No. battery units - #define BATTERY_SELECT 0x01 - #define AC_STATUS 0x02 - #define BATTERY_STATUS 0x03 - #define BATTERY_FLAG 0x04 - #define BATTERY_PERCENTAGE 0x05 - #define BATTERY_TIME 0x06 - #define MAX_POWER BATTERY_TIME - - - -#define VRC_OHCI 0x0B // OHCI Class - #define SET_LED 0x00 - #define INIT_OHCI 0x01 - #define MAX_OHCI INIT_OHCI - -#define VRC_KEYBOARD 0x0C // Kbd Controller Class - #define KEYBOARD_PRESENT 0x00 - #define SCANCODE 0x01 - #define MOUSE_PRESENT 0x02 - #define MOUSE_BUTTONS 0x03 - #define MOUSE_XY 0x04 - #define MAX_KEYBOARD MOUSE_XY - - -#define VRC_DDC 0x0D // Video DDC Class - #define VRC_DDC_ENABLE 0x00 // Enable/disable register - #define DDC_DISABLE 0x00 - #define DDC_ENABLE 0x01 - #define VRC_DDC_IO 0x01 // A non-zero value for safety - #define MAX_DDC VRC_DDC_IO - -#define VRC_DEBUGGER 0x0E - #define MAX_DEBUGGER NO_VR - - -#define VRC_STR 0x0F // Virtual Register class - #define RESTORE_ADDR 0x00 // Physical address of MSR restore table - - -#define VRC_COP8 0x10 // Virtual Register class - #define VRC_HIB_ENABLE 0x00 // HIB enable/disable index - #define HIB_ENABLE 0x00 // HIB enable command - #define HIB_DISABLE 0x01 // HIB disable command - #define VRC_HIB_SEND 0x01 // Send packet to COP8 - #define VRC_HIB_READUART 0x02 // Read byte from COP8 UART - #define VRC_HIB_VERSION 0x03 // Read COP8 version - #define VRC_HIB_SERIAL 0x04 // Read 8 byte serial number - #define VRC_HIB_USRBTN 0x05 // Read POST button pressed status - #define MAX_COP8 NO_VR - -#define VRC_OWL 0x11 // Virtual Register class - #define VRC_OWL_DAC 0x00 // DAC (Backlight) Control - #define VRC_OWL_GPIO 0x01 // GPIO Control - #define MAX_OWL VRC_OWL_GPIO - -#define VRC_SYSINFO 0x12 // Virtual Register class - #define VRC_SI_VERSION 0x00 // Sysinfo VSM version - #define VRC_SI_CPU_MHZ 0x01 // CPU speed in MHZ - #define VRC_SI_CHIPSET_BASE_LOW 0x02 - #define VRC_SI_CHIPSET_BASE_HI 0x03 - #define VRC_SI_CHIPSET_ID 0x04 - #define VRC_SI_CHIPSET_REV 0x05 - #define VRC_SI_CPU_ID 0x06 - #define VRC_SI_CPU_REV 0x07 - #define MAX_SYSINFO VRC_SI_CPU_REV - -#define VRC_SUPERIO 0x13 - #define VRC_SIO_CHIPID 0x00 - #define VRC_SIO_NUMLD 0x01 - #define VRC_SIO_FDCEN 0x02 - #define VRC_SIO_FDCIO 0x03 - #define VRC_SIO_FDCIRQ 0x04 - #define VRC_SIO_FDCDMA 0x05 - #define VRC_SIO_FDCCFG1 0x06 - #define VRC_SIO_FDCCFG2 0x07 - #define VRC_SIO_PP1EN 0x08 - #define VRC_SIO_PP1IO 0x09 - #define VRC_SIO_PP1IRQ 0x0A - #define VRC_SIO_PP1DMA 0x0B - #define VRC_SIO_PP1CFG1 0x0C - #define VRC_SIO_SP1EN 0x0D - #define VRC_SIO_SP1IO 0x0E - #define VRC_SIO_SP1IRQ 0x0F - #define VRC_SIO_SP1CFG1 0x10 - #define VRC_SIO_SP2EN 0x11 - #define VRC_SIO_SP2IO 0x12 - #define VRC_SIO_SP2IRQ 0x13 - #define VRC_SIO_SP2CFG1 0x14 - #define VRC_SIO_KBEN 0x15 - #define VRC_SIO_KBIO1 0x16 - #define VRC_SIO_KBIO2 0x17 - #define VRC_SIO_KBIRQ 0x18 - #define VRC_SIO_KBCFG1 0x19 - #define VRC_SIO_MSEN 0x1A - #define VRC_SIO_MSIO 0x1B - #define VRC_SIO_MSIRQ 0x1C - #define VRC_SIO_RTCEN 0x1D - #define VRC_SIO_RTCIO1 0x1E - #define VRC_SIO_RTCIO2 0x1F - #define VRC_SIO_RTCIRQ 0x20 - #define VRC_SIO_RTCCFG1 0x21 - #define VRC_SIO_RTCCFG2 0x22 - #define VRC_SIO_RTCCFG3 0x23 - #define VRC_SIO_RTCCFG4 0x24 - #define MAX_SUPERIO VRC_SIO_RTCCFG4 - -#define VRC_CHIPSET 0x14 - #define VRC_CS_PWRBTN 0x00 - #define VRC_CS_UART1 0x01 - #define VRC_CS_UART2 0x02 - #define MAX_CHIPSET VRC_CS_UART2 - -#define VRC_THERMAL 0x15 - #define VRC_THERMAL_CURR_RTEMP 0x00 // read only - #define VRC_THERMAL_CURR_LTEMP 0x01 // read only - #define VRC_THERMAL_FAN 0x02 - #define VRC_THERMAL_LOW_THRESHOLD 0x03 - #define VRC_THERMAL_HIGH_THRESHOLD 0x04 - #define VRC_THERMAL_INDEX 0x05 - #define VRC_THERMAL_DATA 0x06 - #define VRC_THERMAL_SMB_ADDRESS 0x07 - #define VRC_THERMAL_SMB_INDEX 0x08 - #define VRC_THERMAL_SMB_DATA 0x09 - #define MAX_THERMAL VRC_THERMAL_SMB_DATA - -#define MAX_VR_CLASS VRC_THERMAL - -/* - * Write to a Virtual Register - */ -static inline void vrWrite(uint16_t wClassIndex, uint16_t wData) -{ - outl(((uint32_t) VR_UNLOCK << 16) | wClassIndex, VRC_INDEX); - outw(wData, VRC_DATA); -} - - /* - * Read from a Virtual Register - * Returns a 16-bit word of data - */ -static inline uint16_t vrRead(uint16_t wClassIndex) -{ - uint16_t wData; - outl(((uint32_t) VR_UNLOCK << 16) | wClassIndex, VRC_INDEX); - wData = inw(VRC_DATA); - return wData; -} -#endif diff --git a/src/include/cpu/intel/em64t100_save_state.h b/src/include/cpu/intel/em64t100_save_state.h new file mode 100644 index 0000000000..f76fa4badd --- /dev/null +++ b/src/include/cpu/intel/em64t100_save_state.h @@ -0,0 +1,106 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __EM64T100_SAVE_STATE_H__ +#define __EM64T100_SAVE_STATE_H__ + +#include +#include + +/* Intel Revision 30100 SMM State-Save Area + * The following processor architectures use this: + * - Bay Trail + */ +#define SMM_EM64T100_ARCH_OFFSET 0x7c00 +#define SMM_EM64T100_SAVE_STATE_OFFSET \ + SMM_SAVE_STATE_BEGIN(SMM_EM64T100_ARCH_OFFSET) +typedef struct { + u8 reserved0[256]; + u8 reserved1[208]; + + u32 gdtr_upper_base; + u32 ldtr_upper_base; + u32 idtr_upper_base; + + u8 reserved2[4]; + + u64 io_rdi; + u64 io_rip; + u64 io_rcx; + u64 io_rsi; + + u8 reserved3[64]; + u32 cr4; + + u8 reserved4[72]; + + u32 gdtr_base; + u8 reserved5[4]; + u32 idtr_base; + u8 reserved6[4]; + u32 ldtr_base; + + u8 reserved7[88]; + + u32 smbase; + u32 smm_revision; + + u16 io_restart; + u16 autohalt_restart; + + u8 reserved8[24]; + + u64 r15; + u64 r14; + u64 r13; + u64 r12; + u64 r11; + u64 r10; + u64 r9; + u64 r8; + + u64 rax; + u64 rcx; + u64 rdx; + u64 rbx; + + u64 rsp; + u64 rbp; + u64 rsi; + u64 rdi; + + + u64 io_mem_addr; + u32 io_misc_info; + + u32 es_sel; + u32 cs_sel; + u32 ss_sel; + u32 ds_sel; + u32 fs_sel; + u32 gs_sel; + + u32 ldtr_sel; + u32 tr_sel; + + u64 dr7; + u64 dr6; + u64 rip; + u64 efer; + u64 rflags; + + u64 cr3; + u64 cr0; +} __packed em64t100_smm_state_save_area_t; + +#endif diff --git a/src/include/cpu/intel/em64t101_save_state.h b/src/include/cpu/intel/em64t101_save_state.h new file mode 100644 index 0000000000..b8bb2db58f --- /dev/null +++ b/src/include/cpu/intel/em64t101_save_state.h @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __EM64T101_SAVE_STATE_H__ +#define __EM64T101_SAVE_STATE_H__ + +#include +#include + + +/* Intel Revision 30101 SMM State-Save Area + * The following processor architectures use this: + * - SandyBridge + * - IvyBridge + * - Haswell + */ +#define SMM_EM64T101_ARCH_OFFSET 0x7c00 +#define SMM_EM64T101_SAVE_STATE_OFFSET \ + SMM_SAVE_STATE_BEGIN(SMM_EM64T101_ARCH_OFFSET) +typedef struct { + u8 reserved0[256]; + u8 reserved1[208]; + + u32 gdtr_upper_base; + u32 ldtr_upper_base; + u32 idtr_upper_base; + + u32 io_cf8; + + u64 io_rdi; + u64 io_rip; + u64 io_rcx; + u64 io_rsi; + + u8 reserved2[52]; + u32 shutdown_auto_restart; + u8 reserved3[8]; + u32 cr4; + + u8 reserved4[72]; + + u32 gdtr_base; + u8 reserved5[4]; + u32 idtr_base; + u8 reserved6[4]; + u32 ldtr_base; + + u8 reserved7[56]; + /* EPTP fields are only on Haswell according to BWGs, but Intel was + * wise and reused the same revision number. */ + u64 eptp; + u32 eptp_en; + u32 cs_base; + u8 reserved8[4]; + u32 iedbase; + + u8 reserved9[8]; + + u32 smbase; + u32 smm_revision; + + u16 io_restart; + u16 autohalt_restart; + + u8 reserved10[24]; + + u64 r15; + u64 r14; + u64 r13; + u64 r12; + u64 r11; + u64 r10; + u64 r9; + u64 r8; + + u64 rax; + u64 rcx; + u64 rdx; + u64 rbx; + + u64 rsp; + u64 rbp; + u64 rsi; + u64 rdi; + + + u64 io_mem_addr; + u32 io_misc_info; + + u32 es_sel; + u32 cs_sel; + u32 ss_sel; + u32 ds_sel; + u32 fs_sel; + u32 gs_sel; + + u32 ldtr_sel; + u32 tr_sel; + + u64 dr7; + u64 dr6; + u64 rip; + u64 efer; + u64 rflags; + + u64 cr3; + u64 cr0; +} __packed em64t101_smm_state_save_area_t; + +#endif diff --git a/src/include/cpu/intel/em64t_save_state.h b/src/include/cpu/intel/em64t_save_state.h new file mode 100644 index 0000000000..1dd01a61a4 --- /dev/null +++ b/src/include/cpu/intel/em64t_save_state.h @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __EM64T_SAVE_STATE_H__ +#define __EM64T_SAVE_STATE_H__ + +#include +#include + +/* Intel Core 2 (EM64T) SMM State-Save Area + * starts @ 0x7c00 + */ +#define SMM_EM64T_ARCH_OFFSET 0x7c00 +#define SMM_EM64T_SAVE_STATE_OFFSET \ + SMM_SAVE_STATE_BEGIN(SMM_EM64T_ARCH_OFFSET) +typedef struct { + u8 reserved0[256]; + u8 reserved1[208]; + + u32 gdtr_upper_base; + u32 ldtr_upper_base; + u32 idtr_upper_base; + + u8 reserved2[4]; + + u64 io_rdi; + u64 io_rip; + u64 io_rcx; + u64 io_rsi; + u64 cr4; + + u8 reserved3[68]; + + u64 gdtr_base; + u64 idtr_base; + u64 ldtr_base; + + u8 reserved4[84]; + + u32 smm_revision; + u32 smbase; + + u16 io_restart; + u16 autohalt_restart; + + u8 reserved5[24]; + + u64 r15; + u64 r14; + u64 r13; + u64 r12; + u64 r11; + u64 r10; + u64 r9; + u64 r8; + + u64 rax; + u64 rcx; + u64 rdx; + u64 rbx; + + u64 rsp; + u64 rbp; + u64 rsi; + u64 rdi; + + + u64 io_mem_addr; + u32 io_misc_info; + + u32 es_sel; + u32 cs_sel; + u32 ss_sel; + u32 ds_sel; + u32 fs_sel; + u32 gs_sel; + + u32 ldtr_sel; + u32 tr_sel; + + u64 dr7; + u64 dr6; + u64 rip; + u64 efer; + u64 rflags; + + u64 cr3; + u64 cr0; +} __packed em64t_smm_state_save_area_t; + +#endif diff --git a/src/include/cpu/intel/fsb.h b/src/include/cpu/intel/fsb.h index 49f3b17aae..825cdd5761 100644 --- a/src/include/cpu/intel/fsb.h +++ b/src/include/cpu/intel/fsb.h @@ -15,15 +15,7 @@ #define CPU_INTEL_FSB_H /* - * This function returns: - * the system bus speed value in MHz - * -1 if FSB is not found - * -2 if the CPU is not supported - */ -int get_ia32_fsb(void); - -/* - * This function returns round up 3 * get_ia32_fsb() + * This function returns round up 3 * get_timer_fsb() */ int get_ia32_fsb_x3(void); diff --git a/src/include/cpu/intel/romstage.h b/src/include/cpu/intel/romstage.h deleted file mode 100644 index 47cd169e6a..0000000000 --- a/src/include/cpu/intel/romstage.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef _CPU_INTEL_ROMSTAGE_H -#define _CPU_INTEL_ROMSTAGE_H - -#include - -void mainboard_romstage_entry(unsigned long bist); - -void platform_enter_postcar(void); - -#endif /* _CPU_INTEL_ROMSTAGE_H */ diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h new file mode 100644 index 0000000000..cb196fcd82 --- /dev/null +++ b/src/include/cpu/intel/smm_reloc.h @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __INTEL_SMM_RELOC_H__ +#define __INTEL_SMM_RELOC_H__ + +#include + +struct ied_header { + char signature[10]; + u32 size; + u8 reserved[34]; +} __packed; + +/* These helpers are for performing SMM relocation. */ +void northbridge_write_smram(u8 smram); + +void smm_lock(void); +void smm_relocate(void); + +/* The initialization of the southbridge is split into 2 components. One is + * for clearing the state in the SMM registers. The other is for enabling + * SMIs. They are split so that other work between the 2 actions. */ +void smm_southbridge_clear_state(void); +void smm_southbridge_enable_smi(void); +void smm_southbridge_enable(uint16_t pm1_events); + +/* To be removed. */ +void smm_initialize(void); +void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size); +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); + +bool cpu_has_alternative_smrr(void); + +#endif diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index 7f135e5390..713ca323a8 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -84,9 +84,7 @@ static __always_inline void disable_cache(void) wbinvd(); } -#if !defined(__PRE_RAM__) void x86_enable_cache(void); -#endif #endif /* !__ASSEMBLER__ */ #endif /* CPU_X86_CACHE */ diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 8108174ecd..6fd1997e76 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -58,8 +58,6 @@ static __always_inline void stop_this_cpu(void) void stop_this_cpu(void); #endif -#if !defined(__PRE_RAM__) - #define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \ sizeof(*(ptr)))) @@ -113,30 +111,6 @@ static inline void lapic_write_atomic(unsigned long reg, unsigned long v) # define lapic_write_around(x, y) lapic_write_atomic((x), (y)) #endif -static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue) -{ - int timeout; - unsigned long status; - int result; - lapic_wait_icr_idle(); - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); - lapic_write_around(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4)); - timeout = 0; - do { -#if 0 - udelay(100); -#endif - status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK; - } while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000); - - result = -1; - if (status == LAPIC_ICR_RR_VALID) { - *pvalue = lapic_read(LAPIC_RRR); - result = 0; - } - return result; -} - void do_lapic_init(void); /* See if I need to initialize the local APIC */ @@ -156,6 +130,4 @@ static inline void setup_lapic(void) struct device; int start_cpu(struct device *cpu); -#endif /* !__PRE_RAM__ */ - #endif /* CPU_X86_LAPIC_H */ diff --git a/src/include/cpu/x86/legacy_save_state.h b/src/include/cpu/x86/legacy_save_state.h new file mode 100644 index 0000000000..7803db77de --- /dev/null +++ b/src/include/cpu/x86/legacy_save_state.h @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __X86_LEGACY_SAVE_STATE_H__ +#define __X86_LEGACY_SAVE_STATE_H__ + +#include + +/* Legacy x86 SMM State-Save Area + * starts @ 0x7e00 + */ +#define SMM_LEGACY_ARCH_OFFSET 0x7e00 + +typedef struct { + u8 reserved0[248]; + u32 smbase; + u32 smm_revision; + u16 io_restart; + u16 autohalt_restart; + u8 reserved1[132]; + u32 gdtbase; + u8 reserved2[8]; + u32 idtbase; + u8 reserved3[16]; + u32 es; + u32 cs; + u32 ss; + u32 ds; + u32 fs; + u32 gs; + u32 ldtbase; + u32 tr; + u32 dr7; + u32 dr6; + u32 eax; + u32 ecx; + u32 edx; + u32 ebx; + u32 esp; + u32 ebp; + u32 esi; + u32 edi; + u32 eip; + u32 eflags; + u32 cr3; + u32 cr0; +} __packed legacy_smm_state_save_area_t; + +#endif diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index c04252ec35..3ab45cd3c3 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -137,7 +137,7 @@ int mp_run_on_aps(void (*func)(void *), void *arg, int logical_cpu_num, long expire_us); /* Like mp_run_on_aps() but also runs func on BSP. */ -int mp_run_on_all_cpus(void (*func)(void *), void *arg, long expire_us); +int mp_run_on_all_cpus(void (*func)(void *), void *arg); /* * Park all APs to prepare for OS boot. This is handled automatically diff --git a/src/include/cpu/x86/smi_deprecated.h b/src/include/cpu/x86/smi_deprecated.h new file mode 100644 index 0000000000..2812bb0eab --- /dev/null +++ b/src/include/cpu/x86/smi_deprecated.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __X86_SMI_DEPRECATED_H__ +#define __X86_SMI_DEPRECATED_H__ + +#if CONFIG(PARALLEL_MP) || !CONFIG(HAVE_SMI_HANDLER) +/* Empty stubs for platforms without SMI handlers. */ +static inline void smm_init(void) { } +static inline void smm_init_completion(void) { } +#else +void smm_init(void); +void smm_init_completion(void); +#endif + +/* Entry from smmhandler.S. */ +void smi_handler(u32 smm_revision); + +#endif diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index b8b99ecdab..d8b9efeaa9 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -13,10 +13,6 @@ * GNU General Public License for more details. */ -/* AMD64 SMM State-Save Area - * starts @ 0x7e00 - */ - #ifndef CPU_X86_SMM_H #define CPU_X86_SMM_H @@ -32,438 +28,6 @@ #define SMM_ENTRY_OFFSET 0x8000 #define SMM_SAVE_STATE_BEGIN(x) (SMM_ENTRY_OFFSET + (x)) -/* AMD64 x86 SMM State-Save Area - * starts @ 0x7e00 - */ -#define SMM_AMD64_ARCH_OFFSET 0x7e00 -#define SMM_AMD64_SAVE_STATE_OFFSET \ - SMM_SAVE_STATE_BEGIN(SMM_AMD64_ARCH_OFFSET) -typedef struct { - u16 es_selector; - u16 es_attributes; - u32 es_limit; - u64 es_base; - - u16 cs_selector; - u16 cs_attributcs; - u32 cs_limit; - u64 cs_base; - - u16 ss_selector; - u16 ss_attributss; - u32 ss_limit; - u64 ss_base; - - u16 ds_selector; - u16 ds_attributds; - u32 ds_limit; - u64 ds_base; - - u16 fs_selector; - u16 fs_attributfs; - u32 fs_limit; - u64 fs_base; - - u16 gs_selector; - u16 gs_attributgs; - u32 gs_limit; - u64 gs_base; - - u8 reserved0[4]; - u16 gdtr_limit; - u8 reserved1[2]; - u64 gdtr_base; - - u16 ldtr_selector; - u16 ldtr_attributes; - u32 ldtr_limit; - u64 ldtr_base; - - u8 reserved2[4]; - u16 idtr_limit; - u8 reserved3[2]; - u64 idtr_base; - - u16 tr_selector; - u16 tr_attributes; - u32 tr_limit; - u64 tr_base; - - u64 io_restart_rip; - u64 io_restart_rcx; - u64 io_restart_rsi; - u64 io_restart_rdi; - u32 smm_io_trap_offset; - u32 local_smi_status; - - u8 io_restart; - u8 autohalt_restart; - - u8 reserved5[6]; - - u64 efer; - - u8 reserved6[36]; - - u32 smm_revision; - u32 smbase; - - u8 reserved7[68]; - - u64 cr4; - u64 cr3; - u64 cr0; - u64 dr7; - u64 dr6; - - u64 rflags; - u64 rip; - u64 r15; - u64 r14; - u64 r13; - u64 r12; - u64 r11; - u64 r10; - u64 r9; - u64 r8; - - u64 rdi; - u64 rsi; - u64 rpb; - u64 rsp; - u64 rbx; - u64 rdx; - u64 rcx; - u64 rax; -} __packed amd64_smm_state_save_area_t; - - -/* Intel Core 2 (EM64T) SMM State-Save Area - * starts @ 0x7c00 - */ -#define SMM_EM64T_ARCH_OFFSET 0x7c00 -#define SMM_EM64T_SAVE_STATE_OFFSET \ - SMM_SAVE_STATE_BEGIN(SMM_EM64T_ARCH_OFFSET) -typedef struct { - u8 reserved0[256]; - u8 reserved1[208]; - - u32 gdtr_upper_base; - u32 ldtr_upper_base; - u32 idtr_upper_base; - - u8 reserved2[4]; - - u64 io_rdi; - u64 io_rip; - u64 io_rcx; - u64 io_rsi; - u64 cr4; - - u8 reserved3[68]; - - u64 gdtr_base; - u64 idtr_base; - u64 ldtr_base; - - u8 reserved4[84]; - - u32 smm_revision; - u32 smbase; - - u16 io_restart; - u16 autohalt_restart; - - u8 reserved5[24]; - - u64 r15; - u64 r14; - u64 r13; - u64 r12; - u64 r11; - u64 r10; - u64 r9; - u64 r8; - - u64 rax; - u64 rcx; - u64 rdx; - u64 rbx; - - u64 rsp; - u64 rbp; - u64 rsi; - u64 rdi; - - - u64 io_mem_addr; - u32 io_misc_info; - - u32 es_sel; - u32 cs_sel; - u32 ss_sel; - u32 ds_sel; - u32 fs_sel; - u32 gs_sel; - - u32 ldtr_sel; - u32 tr_sel; - - u64 dr7; - u64 dr6; - u64 rip; - u64 efer; - u64 rflags; - - u64 cr3; - u64 cr0; -} __packed em64t_smm_state_save_area_t; - - -/* Intel Revision 30100 SMM State-Save Area - * The following processor architectures use this: - * - Bay Trail - */ -#define SMM_EM64T100_ARCH_OFFSET 0x7c00 -#define SMM_EM64T100_SAVE_STATE_OFFSET \ - SMM_SAVE_STATE_BEGIN(SMM_EM64T100_ARCH_OFFSET) -typedef struct { - u8 reserved0[256]; - u8 reserved1[208]; - - u32 gdtr_upper_base; - u32 ldtr_upper_base; - u32 idtr_upper_base; - - u8 reserved2[4]; - - u64 io_rdi; - u64 io_rip; - u64 io_rcx; - u64 io_rsi; - - u8 reserved3[64]; - u32 cr4; - - u8 reserved4[72]; - - u32 gdtr_base; - u8 reserved5[4]; - u32 idtr_base; - u8 reserved6[4]; - u32 ldtr_base; - - u8 reserved7[88]; - - u32 smbase; - u32 smm_revision; - - u16 io_restart; - u16 autohalt_restart; - - u8 reserved8[24]; - - u64 r15; - u64 r14; - u64 r13; - u64 r12; - u64 r11; - u64 r10; - u64 r9; - u64 r8; - - u64 rax; - u64 rcx; - u64 rdx; - u64 rbx; - - u64 rsp; - u64 rbp; - u64 rsi; - u64 rdi; - - - u64 io_mem_addr; - u32 io_misc_info; - - u32 es_sel; - u32 cs_sel; - u32 ss_sel; - u32 ds_sel; - u32 fs_sel; - u32 gs_sel; - - u32 ldtr_sel; - u32 tr_sel; - - u64 dr7; - u64 dr6; - u64 rip; - u64 efer; - u64 rflags; - - u64 cr3; - u64 cr0; -} __packed em64t100_smm_state_save_area_t; - -/* Intel Revision 30101 SMM State-Save Area - * The following processor architectures use this: - * - SandyBridge - * - IvyBridge - * - Haswell - */ -#define SMM_EM64T101_ARCH_OFFSET 0x7c00 -#define SMM_EM64T101_SAVE_STATE_OFFSET \ - SMM_SAVE_STATE_BEGIN(SMM_EM64T101_ARCH_OFFSET) -typedef struct { - u8 reserved0[256]; - u8 reserved1[208]; - - u32 gdtr_upper_base; - u32 ldtr_upper_base; - u32 idtr_upper_base; - - u32 io_cf8; - - u64 io_rdi; - u64 io_rip; - u64 io_rcx; - u64 io_rsi; - - u8 reserved2[52]; - u32 shutdown_auto_restart; - u8 reserved3[8]; - u32 cr4; - - u8 reserved4[72]; - - u32 gdtr_base; - u8 reserved5[4]; - u32 idtr_base; - u8 reserved6[4]; - u32 ldtr_base; - - u8 reserved7[56]; - /* EPTP fields are only on Haswell according to BWGs, but Intel was - * wise and reused the same revision number. */ - u64 eptp; - u32 eptp_en; - u32 cs_base; - u8 reserved8[4]; - u32 iedbase; - - u8 reserved9[8]; - - u32 smbase; - u32 smm_revision; - - u16 io_restart; - u16 autohalt_restart; - - u8 reserved10[24]; - - u64 r15; - u64 r14; - u64 r13; - u64 r12; - u64 r11; - u64 r10; - u64 r9; - u64 r8; - - u64 rax; - u64 rcx; - u64 rdx; - u64 rbx; - - u64 rsp; - u64 rbp; - u64 rsi; - u64 rdi; - - - u64 io_mem_addr; - u32 io_misc_info; - - u32 es_sel; - u32 cs_sel; - u32 ss_sel; - u32 ds_sel; - u32 fs_sel; - u32 gs_sel; - - u32 ldtr_sel; - u32 tr_sel; - - u64 dr7; - u64 dr6; - u64 rip; - u64 efer; - u64 rflags; - - u64 cr3; - u64 cr0; -} __packed em64t101_smm_state_save_area_t; - - -/* Legacy x86 SMM State-Save Area - * starts @ 0x7e00 - */ -#define SMM_LEGACY_ARCH_OFFSET 0x7e00 - -typedef struct { - u8 reserved0[248]; - u32 smbase; - u32 smm_revision; - u16 io_restart; - u16 autohalt_restart; - u8 reserved1[132]; - u32 gdtbase; - u8 reserved2[8]; - u32 idtbase; - u8 reserved3[16]; - u32 es; - u32 cs; - u32 ss; - u32 ds; - u32 fs; - u32 gs; - u32 ldtbase; - u32 tr; - u32 dr7; - u32 dr6; - u32 eax; - u32 ecx; - u32 edx; - u32 ebx; - u32 esp; - u32 ebp; - u32 esi; - u32 edi; - u32 eip; - u32 eflags; - u32 cr3; - u32 cr0; -} __packed legacy_smm_state_save_area_t; - -typedef enum { - AMD64, - EM64T, - EM64T101, - LEGACY -} save_state_type_t; - - -typedef struct { - save_state_type_t type; - union { - amd64_smm_state_save_area_t *amd64_state_save; - em64t_smm_state_save_area_t *em64t_state_save; - em64t101_smm_state_save_area_t *em64t101_state_save; - legacy_smm_state_save_area_t *legacy_state_save; - }; -} smm_state_save_area_t; - #define APM_CNT 0xb2 #define APM_CNT_CST_CONTROL 0x85 #define APM_CNT_PST_CONTROL 0x80 @@ -477,26 +41,18 @@ typedef struct { #define APM_CNT_ELOG_GSMI 0xef #define APM_STS 0xb3 -/* SMI handler function prototypes */ -void smi_handler(u32 smm_revision); - void io_trap_handler(int smif); int southbridge_io_trap_handler(int smif); int mainboard_io_trap_handler(int smif); void southbridge_smi_set_eos(void); -#if CONFIG(SMM_TSEG) void cpu_smi_handler(void); void northbridge_smi_handler(void); void southbridge_smi_handler(void); -#else -void cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save); -void northbridge_smi_handler(unsigned int node, - smm_state_save_area_t *state_save); -void southbridge_smi_handler(unsigned int node, - smm_state_save_area_t *state_save); -#endif /* CONFIG_SMM_TSEG */ + +void smm_setup_structures(void *gnvs, void *tcg, void *smi1); + void mainboard_smi_gpi(u32 gpi_sts); int mainboard_smi_apmc(u8 data); void mainboard_smi_sleep(u8 slp_typ); @@ -604,4 +160,7 @@ enum { * 0 on success, < 0 on failure. */ int smm_subregion(int sub, uintptr_t *start, size_t *size); +/* Print the SMM memory layout on console. */ +void smm_list_regions(void); + #endif /* CPU_X86_SMM_H */ diff --git a/src/include/delay.h b/src/include/delay.h index 8f894d2d30..1c481be917 100644 --- a/src/include/delay.h +++ b/src/include/delay.h @@ -1,6 +1,17 @@ #ifndef DELAY_H #define DELAY_H +#include + +#if CONFIG_UDELAY_LAPIC_FIXED_FSB != 0 +static inline u32 get_timer_fsb(void) +{ + return CONFIG_UDELAY_LAPIC_FIXED_FSB; +} +#else +u32 get_timer_fsb(void); +#endif + void init_timer(void); void udelay(unsigned int usecs); diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index 343e261d06..cbc5b4ec8e 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -19,7 +19,6 @@ #include #include #include -#include #include void azalia_audio_init(struct device *dev); diff --git a/src/include/device/device.h b/src/include/device/device.h index 8e1e62aa7c..b2221ccea2 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -62,6 +62,8 @@ struct device_operations { void (*acpi_fill_ssdt_generator)(struct device *dev); void (*acpi_inject_dsdt_generator)(struct device *dev); const char *(*acpi_name)(const struct device *dev); + /* Returns the optional _HID (Hardware ID) */ + const char *(*acpi_hid)(const struct device *dev); #endif const struct pci_operations *ops_pci; const struct i2c_bus_operations *ops_i2c_bus; @@ -220,6 +222,12 @@ void set_cpu_topology(struct device *cpu, unsigned int node, #define intel_cpu_topology(cpu, package, core, thread) \ set_cpu_topology(cpu, 0, package, core, thread) +void mp_init_cpus(DEVTREE_CONST struct bus *cpu_bus); +static inline void mp_cpu_bus_init(struct device *dev) +{ + mp_init_cpus(dev->link_list); +} + /* Debug functions */ void print_resource_tree(const struct device *root, int debug_level, const char *msg); diff --git a/src/include/device/dram/common.h b/src/include/device/dram/common.h index b1677c8a07..4c6f02eb00 100644 --- a/src/include/device/dram/common.h +++ b/src/include/device/dram/common.h @@ -67,6 +67,6 @@ enum spd_status { SPD_STATUS_INVALID_FIELD, }; -u16 ddr3_crc16(const u8 *ptr, int n_crc); +u16 ddr_crc16(const u8 *ptr, int n_crc); #endif /* DEVICE_DRAM_COMMON_H */ diff --git a/src/include/device/dram/ddr4.h b/src/include/device/dram/ddr4.h new file mode 100644 index 0000000000..faa32995f8 --- /dev/null +++ b/src/include/device/dram/ddr4.h @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * JEDEC Standard No. 21-C + * Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules + */ + +#ifndef DEVICE_DRAM_DDR4L_H +#define DEVICE_DRAM_DDR4L_H + +/** + * @file ddr4.h + * + * \brief Utilities for decoding DDR4 SPDs + */ + +#include +#include +#include +#include + +#define SPD_DDR4_PART_OFF 329 +#define SPD_DDR4_PART_LEN 20 + + +/* + * Module type (byte 3, bits 3:0) of SPD + * This definition is specific to DDR4. DDR2/3 SPDs have a different structure. + */ +enum spd_dimm_type { + SPD_DIMM_TYPE_EXTENDED = 0x0, + SPD_DIMM_TYPE_RDIMM = 0x1, + SPD_DIMM_TYPE_UDIMM = 0x2, + SPD_DIMM_TYPE_SO_DIMM = 0x3, + SPD_DIMM_TYPE_LRDIMM = 0x4, + SPD_DIMM_TYPE_MINI_RDIMM = 0x5, + SPD_DIMM_TYPE_MINI_UDIMM = 0x6, + SPD_DIMM_TYPE_72B_SO_RDIMM = 0x8, + SPD_DIMM_TYPE_72B_SO_UDIMM = 0x9, + SPD_DIMM_TYPE_16B_SO_DIMM = 0xc, + SPD_DIMM_TYPE_32B_SO_DIMM = 0xd, + /* Masks to bits 3:0 to give the dimm type */ + SPD_DIMM_TYPE_MASK = 0xf +}; + +/** + * \brief DIMM characteristics + * + * The characteristics of each DIMM, as presented by the SPD + */ +typedef struct dimm_attr_st { + enum spd_memory_type dram_type; + enum spd_dimm_type dimm_type; + char part_number[SPD_DDR4_PART_LEN + 1]; + u8 serial_number[4]; + u8 bus_width; + u8 ranks; + u8 sdram_width; + u16 cap_per_die_mbit; + u16 size_mb; + u16 manufacturer_id; + u16 vdd_voltage; + bool ecc_extension; +} dimm_attr; + +typedef u8 spd_raw_data[512]; + +int spd_decode_ddr4(dimm_attr *dimm, spd_raw_data spd); + +enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, + const u16 selected_freq, + const dimm_attr *info); + +#endif /* DEVICE_DRAM_DDR4L_H */ diff --git a/src/include/device/mmio.h b/src/include/device/mmio.h index 34be1e8172..7b95a3cd74 100644 --- a/src/include/device/mmio.h +++ b/src/include/device/mmio.h @@ -17,5 +17,160 @@ #include #include +#include -#endif +#ifndef __ROMCC__ +/* + * Reads a transfer buffer from 32-bit FIFO registers. fifo_stride is the + * distance in bytes between registers (e.g. pass 4 for a normal array of 32-bit + * registers or 0 to read everything from the same register). fifo_width is + * the amount of bytes read per register (can be 1 through 4). + */ +void buffer_from_fifo32(void *buffer, size_t size, void *fifo, + int fifo_stride, int fifo_width); + +/* + * Version of buffer_to_fifo32() that can prepend a prefix of up to fifo_width + * size to the transfer. This is often useful for protocols where a command word + * precedes the actual payload data. The prefix must be packed in the low-order + * bytes of the 'prefix' u32 parameter and any high-order bytes exceeding prefsz + * must be 0. Note that 'size' counts total bytes written, including 'prefsz'. + */ +void buffer_to_fifo32_prefix(void *buffer, u32 prefix, int prefsz, size_t size, + void *fifo, int fifo_stride, int fifo_width); + +/* + * Writes a transfer buffer into 32-bit FIFO registers. fifo_stride is the + * distance in bytes between registers (e.g. pass 4 for a normal array of 32-bit + * registers or 0 to write everything into the same register). fifo_width is + * the amount of bytes written per register (can be 1 through 4). + */ +static inline void buffer_to_fifo32(void *buffer, size_t size, void *fifo, + int fifo_stride, int fifo_width) +{ + buffer_to_fifo32_prefix(buffer, size, 0, 0, fifo, + fifo_stride, fifo_width); +} + +/* + * Utilities to help processing bit fields. + * + * To define a bit field (usually inside a register), do: + * + * DEFINE_BITFIELD(name, high_bit, low_bit) + * + * - name: Name of the field to access. + * - high_bit: highest bit that's part of the bit field. + * - low_bit: lowest bit in the bit field. + * + * To extract one field value from a raw reg value: + * + * EXTRACT_BITFIELD(value, name); + * + * To read from an MMIO register and extract one field from it: + * + * READ32_BITFIELD(®, name); + * + * To write into an MMIO register, set given fields (by names) to specified + * values, and all other bits to zero (usually used for resetting a register): + * + * WRITE32_BITFIELDS(®, name, value, [name, value, ...]) + * + * To write into an MMIO register, set given fields (by names) to specified + * values, and leaving all others "unchanged" (usually used for updating some + * settings): + * + * SET32_BITFIELDS(®, name, value, [name, value, ...]) + * + * Examples: + * + * DEFINE_BITFIELD(DISP_TYPE, 2, 1) + * DEFINE_BITFIELD(DISP_EN, 0, 0) + * + * SET32_BITFIELDS(&disp_regs.ctrl, DISP_TYPE, 2); + * SET32_BITFIELDS(&disp_regs.ctrl, DISP_EN, 0); + * + * SET32_BITFIELDS(&disp_regs.ctrl, DISP_TYPE, 1, DISP_EN, 1); + * WRITE32_BITFIELDS(&disp_regs.ctrl, DISP_TYPE, 1, DISP_EN, 1); + * + * READ32_BITFIELD(®, DISP_TYPE) + * EXTRACT_BITFIELD(value, DISP_TYPE) + * + * These will be translated to: + * + * clrsetbits_le32(&disp_regs.ctrl, 0x6, 0x4); + * clrsetbits_le32(&disp_regs.ctrl, 0x1, 0x0); + * + * clrsetbits_le32(&disp_regs.ctrl, 0x7, 0x3); + * write32(&disp_regs.ctrl, 0x3); + * + * (read32(®) & 0x6) >> 1 + * (value & 0x6) >> 1 + * + * The {WRITE,SET}32_BITFIELDS currently only allows setting up to 8 fields at + * one invocation. + */ + +#define DEFINE_BITFIELD(name, high_bit, low_bit) \ + _Static_assert(high_bit >= low_bit, "invalid bit field range"); \ + enum { \ + name##_BITFIELD_SHIFT = (low_bit), \ + name##_BITFIELD_SIZE = (high_bit) - (low_bit) + 1, \ + }; + +#define _BF_MASK(name, value) \ + (((1 << name##_BITFIELD_SIZE) - 1) << name##_BITFIELD_SHIFT) + +#define _BF_VALUE(name, value) \ + ((value) << name##_BITFIELD_SHIFT) + +#define _BF_APPLY1(op, name, value, ...) (op(name, value)) +#define _BF_APPLY2(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY1(op, __VA_ARGS__)) +#define _BF_APPLY3(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY2(op, __VA_ARGS__)) +#define _BF_APPLY4(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY3(op, __VA_ARGS__)) +#define _BF_APPLY5(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY4(op, __VA_ARGS__)) +#define _BF_APPLY6(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY5(op, __VA_ARGS__)) +#define _BF_APPLY7(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY6(op, __VA_ARGS__)) +#define _BF_APPLY8(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY7(op, __VA_ARGS__)) +#define _BF_APPLYINVALID(...) \ + _Static_assert(0, "Invalid arguments for {WRITE,SET}*_BITFIELDS") + +#define _BF_IMPL2(op, addr, \ + n1, v1, n2, v2, n3, v3, n4, v4, n5, v5, n6, v6, n7, v7, n8, v8, \ + NARGS, ...) \ + \ + op(addr, \ + _BF_APPLY##NARGS(_BF_MASK, n1, v1, n2, v2, n3, v3, n4, v4, \ + n5, v5, n6, v6, n7, v7, n8, v8), \ + _BF_APPLY##NARGS(_BF_VALUE, n1, v1, n2, v2, n3, v3, n4, v4, \ + n5, v5, n6, v6, n7, v7, n8, v8)) + +#define _BF_IMPL(op, addr, ...) \ + _BF_IMPL2(op, addr, __VA_ARGS__, \ + 8, INVALID, 7, INVALID, 6, INVALID, 5, INVALID, \ + 4, INVALID, 3, INVALID, 2, INVALID, 1, INVALID) + +#define _WRITE32_BITFIELDS_IMPL(addr, masks, values) write32(addr, values) + +#define WRITE32_BITFIELDS(addr, ...) \ + _BF_IMPL(_WRITE32_BITFIELDS_IMPL, addr, __VA_ARGS__) + +#define SET32_BITFIELDS(addr, ...) \ + _BF_IMPL(clrsetbits_le32, addr, __VA_ARGS__) + +#define EXTRACT_BITFIELD(value, name) \ + (((value) & _BF_MASK(name, 0)) >> name##_BITFIELD_SHIFT) + +#define READ32_BITFIELD(addr, name) \ + EXTRACT_BITFIELD(read32(addr), name) + +#endif /* !__ROMCC__ */ + +#endif /* __DEVICE_MMIO_H__ */ diff --git a/src/include/device/pci_ehci.h b/src/include/device/pci_ehci.h index 6e5985448a..e9a7776d46 100644 --- a/src/include/device/pci_ehci.h +++ b/src/include/device/pci_ehci.h @@ -31,7 +31,6 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx); u8 *pci_ehci_base_regs(pci_devfn_t dev); void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port); -#ifndef __PRE_RAM__ #if !CONFIG(USBDEBUG) #define pci_ehci_read_resources pci_dev_read_resources #else @@ -46,6 +45,5 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port); struct device; void pci_ehci_read_resources(struct device *dev); #endif -#endif #endif /* _PCI_EHCI_H_ */ diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 1aac48e9aa..905618cb66 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2102,6 +2102,7 @@ #define PCI_DEVICE_ID_INTEL_82437VX 0x7030 #define PCI_DEVICE_ID_INTEL_82439TX 0x7100 #define PCI_DEVICE_ID_INTEL_CNL_ISHB 0x9dfc +#define PCI_DEVICE_ID_INTEL_CML_ISHB 0x02fc /* Intel 82371FB (PIIX) */ #define PCI_DEVICE_ID_INTEL_82371FB_ISA 0x122e @@ -2713,6 +2714,19 @@ #define PCI_DEVICE_ID_INTEL_SPT_H_HM175 0xa152 #define PCI_DEVICE_ID_INTEL_SPT_H_QM175 0xa153 #define PCI_DEVICE_ID_INTEL_SPT_H_CM238 0xa154 +#define PCI_DEVICE_ID_INTEL_LWB_C621 0xa1c1 +#define PCI_DEVICE_ID_INTEL_LWB_C622 0xa1c2 +#define PCI_DEVICE_ID_INTEL_LWB_C624 0xa1c3 +#define PCI_DEVICE_ID_INTEL_LWB_C625 0xa1c4 +#define PCI_DEVICE_ID_INTEL_LWB_C626 0xa1c5 +#define PCI_DEVICE_ID_INTEL_LWB_C627 0xa1c6 +#define PCI_DEVICE_ID_INTEL_LWB_C628 0xa1c7 +#define PCI_DEVICE_ID_INTEL_LWB_C629 0xa1ca +#define PCI_DEVICE_ID_INTEL_LWB_C624_SUPER 0xa242 +#define PCI_DEVICE_ID_INTEL_LWB_C627_SUPER_1 0xa243 +#define PCI_DEVICE_ID_INTEL_LWB_C621_SUPER 0xa244 +#define PCI_DEVICE_ID_INTEL_LWB_C627_SUPER_2 0xa245 +#define PCI_DEVICE_ID_INTEL_LWB_C628_SUPER 0xa246 #define PCI_DEVICE_ID_INTEL_KBP_H_H270 0xa2c4 #define PCI_DEVICE_ID_INTEL_KBP_H_Z270 0xa2c5 #define PCI_DEVICE_ID_INTEL_KBP_H_Q270 0xa2c6 @@ -2788,6 +2802,48 @@ #define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP19 0xa169 #define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP20 0xa16a +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP1 0xa190 +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP2 0xa191 +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP3 0xa192 +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP4 0xa193 +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP5 0xa194 +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP6 0xa195 +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP7 0xa196 +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP8 0xa197 +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP9 0xa198 +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP10 0xa199 +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP11 0xa19a +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP12 0xa19b +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP13 0xa19c +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP14 0xa19d +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP15 0xa19e +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP16 0xa19f +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP17 0xa1e7 +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP18 0xa1e8 +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP19 0xa1e9 +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP20 0xa1ea + +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP1_SUPER 0xa210 +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP2_SUPER 0xa211 +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP3_SUPER 0xa212 +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP4_SUPER 0xa213 +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP5_SUPER 0xa214 +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP6_SUPER 0xa215 +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP7_SUPER 0xa216 +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP8_SUPER 0xa217 +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP9_SUPER 0xa218 +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP10_SUPER 0xa219 +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP11_SUPER 0xa21a +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP12_SUPER 0xa21b +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP13_SUPER 0xa21c +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP14_SUPER 0xa21d +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP15_SUPER 0xa21e +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP16_SUPER 0xa21f +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP17_SUPER 0xa267 +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP18_SUPER 0xa268 +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP19_SUPER 0xa269 +#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP20_SUPER 0xa26a + #define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1 0xa290 #define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP2 0xa291 #define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP3 0xa292 @@ -2892,6 +2948,18 @@ #define PCI_DEVICE_ID_INTEL_SPT_U_SATA 0x9d03 #define PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA 0x9d07 #define PCI_DEVICE_ID_INTEL_SPT_KBL_SATA 0x282a +#define PCI_DEVICE_ID_INTEL_LWB_SATA_AHCI 0xa182 +#define PCI_DEVICE_ID_INTEL_LWB_SATA_RAID 0xa186 +#define PCI_DEVICE_ID_INTEL_LWB_SSATA_AHCI 0xa1d2 +#define PCI_DEVICE_ID_INTEL_LWB_SSATA_RAID 0xa1d6 +#define PCI_DEVICE_ID_INTEL_LWB_SATA_ALT 0x2822 +#define PCI_DEVICE_ID_INTEL_LWB_SATA_ALT_RST 0x2826 +#define PCI_DEVICE_ID_INTEL_LWB_SATA_AHCI_SUPER 0xa202 +#define PCI_DEVICE_ID_INTEL_LWB_SATA_RAID_SUPER 0xa206 +#define PCI_DEVICE_ID_INTEL_LWB_SSATA_AHCI_SUPER 0xa252 +#define PCI_DEVICE_ID_INTEL_LWB_SSATA_RAID_SUPER 0xa256 +#define PCI_DEVICE_ID_INTEL_LWB_SSATA_ALT 0x2823 +#define PCI_DEVICE_ID_INTEL_LWB_SSATA_ALT_RST 0x2827 #define PCI_DEVICE_ID_INTEL_APL_SATA 0x5ae0 #define PCI_DEVICE_ID_INTEL_GLK_SATA 0x31e3 #define PCI_DEVICE_ID_INTEL_CNL_SATA 0x9dd5 @@ -2907,6 +2975,8 @@ /* Intel PMC device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21 #define PCI_DEVICE_ID_INTEL_SPT_H_PMC 0xa121 +#define PCI_DEVICE_ID_INTEL_LWB_PMC 0xa1a1 +#define PCI_DEVICE_ID_INTEL_LWB_PMC_SUPER 0xa221 #define PCI_DEVICE_ID_INTEL_KBP_H_PMC 0xa2a1 #define PCI_DEVICE_ID_INTEL_APL_PMC 0x5a94 #define PCI_DEVICE_ID_INTEL_GLK_PMC 0x3194 @@ -3011,6 +3081,8 @@ #define PCI_DEVICE_ID_INTEL_CNL_SPI1 0x9dab #define PCI_DEVICE_ID_INTEL_CNL_SPI2 0x9dfb #define PCI_DEVICE_ID_INTEL_CNL_HWSEQ_SPI 0x9da4 +#define PCI_DEVICE_ID_INTEL_LWB_SPI 0xa1a4 +#define PCI_DEVICE_ID_INTEL_LWB_SPI_SUPER 0xa224 #define PCI_DEVICE_ID_INTEL_CNP_H_SPI0 0xa32a #define PCI_DEVICE_ID_INTEL_CNP_H_SPI1 0xa32b #define PCI_DEVICE_ID_INTEL_CNP_H_SPI2 0xa37b @@ -3082,6 +3154,8 @@ #define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_2 0x9B4A #define PCI_DEVICE_ID_INTEL_CML_GT1_ULT_3 0x9B2B #define PCI_DEVICE_ID_INTEL_CML_GT1_ULT_4 0x9B2C +#define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_5 0x9BAA +#define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_6 0x9BCA #define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_3 0x9B4B #define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_4 0x9B4C #define PCI_DEVICE_ID_INTEL_CML_GT1_ULX_1 0x9B20 @@ -3107,7 +3181,6 @@ #define PCI_DEVICE_ID_INTEL_SKL_ID_S_4 0x191f #define PCI_DEVICE_ID_INTEL_KBL_ID_S 0x590f #define PCI_DEVICE_ID_INTEL_SKL_ID_H_EM 0x1918 -#define PCI_DEVICE_ID_INTEL_SKL_ID_DT 0x191f #define PCI_DEVICE_ID_INTEL_KBL_ID_U 0x5904 #define PCI_DEVICE_ID_INTEL_KBL_ID_Y 0x590c #define PCI_DEVICE_ID_INTEL_KBL_ID_H 0x5910 @@ -3119,12 +3192,20 @@ #define PCI_DEVICE_ID_INTEL_WHL_ID_W_4 0x3E34 #define PCI_DEVICE_ID_INTEL_WHL_ID_W_2 0x3E35 #define PCI_DEVICE_ID_INTEL_CFL_ID_U 0x3ED0 +#define PCI_DEVICE_ID_INTEL_CFL_ID_U_2 0x3ECC #define PCI_DEVICE_ID_INTEL_CFL_ID_H 0x3ec4 +#define PCI_DEVICE_ID_INTEL_CFL_ID_H_4 0x3e10 #define PCI_DEVICE_ID_INTEL_CFL_ID_H_8 0x3e20 #define PCI_DEVICE_ID_INTEL_CFL_ID_S 0x3ec2 +#define PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2 0x3e0f #define PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4 0x3e1f #define PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8 0x3e30 +#define PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_4 0x3e18 +#define PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6 0x3ec6 #define PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8 0x3e31 +#define PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4 0x3e33 +#define PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6 0x3eca +#define PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8 0x3e32 #define PCI_DEVICE_ID_INTEL_ICL_ID_U 0x8A12 #define PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2 0x8A02 #define PCI_DEVICE_ID_INTEL_ICL_ID_Y 0x8A10 @@ -3141,7 +3222,8 @@ /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 #define PCI_DEVICE_ID_INTEL_SPT_H_SMBUS 0xa123 -#define PCI_DEVICE_ID_INTEL_KBP_H_SMBUS 0xa1a3 +#define PCI_DEVICE_ID_INTEL_KBP_H_LWB_SMBUS 0xa1a3 +#define PCI_DEVICE_ID_INTEL_LWB_SMBUS_SUPER 0xa223 #define PCI_DEVICE_ID_INTEL_CNL_SMBUS 0x9da3 #define PCI_DEVICE_ID_INTEL_CNP_H_SMBUS 0xa323 #define PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS 0x34a3 @@ -3152,6 +3234,8 @@ #define PCI_DEVICE_ID_INTEL_GLK_XHCI 0x31a8 #define PCI_DEVICE_ID_INTEL_SPT_LP_XHCI 0x9d2f #define PCI_DEVICE_ID_INTEL_SPT_H_XHCI 0xa12f +#define PCI_DEVICE_ID_INTEL_LWB_XHCI 0xa1af +#define PCI_DEVICE_ID_INTEL_LWB_XHCI_SUPER 0xa22f #define PCI_DEVICE_ID_INTEL_KBP_H_XHCI 0xa2af #define PCI_DEVICE_ID_INTEL_CNL_LP_XHCI 0x9ded #define PCI_DEVICE_ID_INTEL_CNP_H_XHCI 0xa36d @@ -3161,6 +3245,8 @@ /* Intel P2SB device Ids */ #define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92 #define PCI_DEVICE_ID_INTEL_GLK_P2SB 0x3192 +#define PCI_DEVICE_ID_INTEL_LWB_P2SB 0xa1a0 +#define PCI_DEVICE_ID_INTEL_LWB_P2SB_SUPER 0xa220 #define PCI_DEVICE_ID_INTEL_CNL_P2SB 0x9da0 #define PCI_DEVICE_ID_INTEL_CNP_H_P2SB 0xa320 #define PCI_DEVICE_ID_INTEL_ICL_P2SB 0x34a0 @@ -3180,6 +3266,8 @@ #define PCI_DEVICE_ID_INTEL_CNL_AUDIO 0x9dc8 #define PCI_DEVICE_ID_INTEL_SKL_AUDIO 0x9d70 #define PCI_DEVICE_ID_INTEL_SKL_H_AUDIO 0xa171 +#define PCI_DEVICE_ID_INTEL_LWB_AUDIO 0xa1f0 +#define PCI_DEVICE_ID_INTEL_LWB_AUDIO_SUPER 0xa270 #define PCI_DEVICE_ID_INTEL_KBL_AUDIO 0x9d71 #define PCI_DEVICE_ID_INTEL_CNP_H_AUDIO 0xa348 #define PCI_DEVICE_ID_INTEL_ICL_AUDIO 0x34c8 @@ -3191,6 +3279,12 @@ #define PCI_DEVICE_ID_INTEL_GLK_CSE0 0x319a #define PCI_DEVICE_ID_INTEL_CNL_CSE0 0x9de0 #define PCI_DEVICE_ID_INTEL_SKL_CSE0 0x9d3a +#define PCI_DEVICE_ID_INTEL_LWB_CSE0 0xa1ba +#define PCI_DEVICE_ID_INTEL_LWB_CSE1 0xa1bb +#define PCI_DEVICE_ID_INTEL_LWB_CSE2 0xa1be +#define PCI_DEVICE_ID_INTEL_LWB_CSE0_SUPER 0xa23a +#define PCI_DEVICE_ID_INTEL_LWB_CSE1_SUPER 0xa23b +#define PCI_DEVICE_ID_INTEL_LWB_CSE2_SUPER 0xa23e #define PCI_DEVICE_ID_INTEL_CNP_H_CSE0 0xa360 #define PCI_DEVICE_ID_INTEL_ICL_CSE0 0x34e0 #define PCI_DEVICE_ID_INTEL_CMP_CSE0 0x02e0 @@ -3215,6 +3309,7 @@ /* Intel EMMC device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_EMMC 0x9d2b +#define PCI_DEVICE_ID_INTEL_CMP_EMMC 0x02c4 /* Intel WIFI Ids */ #define PCI_DEVICE_ID_1000_SERIES_WIFI 0x0084 diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index bc6391f1f5..ee92a32d08 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -18,6 +18,8 @@ void pnp_set_iobase(struct device *dev, u8 index, u16 iobase); void pnp_set_irq(struct device *dev, u8 index, u8 irq); void pnp_set_drq(struct device *dev, u8 index, u8 drq); +#endif /* __SIMPLE_DEVICE */ + /* PNP device operations */ void pnp_read_resources(struct device *dev); void pnp_set_resources(struct device *dev); @@ -108,5 +110,4 @@ static inline void pnp_write_index(u16 port, u8 reg, u8 value) outb(value, port + 1); } -#endif /* ! __SIMPLE_DEVICE__ */ #endif /* DEVICE_PNP_H */ diff --git a/src/include/edid.h b/src/include/edid.h index e5f7d98926..a97b99b579 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -95,6 +95,7 @@ struct edid { int hdmi_monitor_detected; char ascii_string[EDID_ASCII_STRING_LENGTH + 1]; + char manufacturer_name[3 + 1]; }; enum edid_status { diff --git a/src/include/elog.h b/src/include/elog.h index 9bb05ade3f..0574819e0d 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -274,6 +274,12 @@ static inline u32 boot_count_read(void) #endif u32 boot_count_increment(void); +static inline void elog_boot_notify(int s3_resume) +{ + if (CONFIG(ELOG_BOOT_COUNT) && !s3_resume) + boot_count_increment(); +} + /* * Callback from GSMI handler to allow platform to log any wake source * information. diff --git a/src/include/inttypes.h b/src/include/inttypes.h index 77c39c4199..4e2476dd03 100644 --- a/src/include/inttypes.h +++ b/src/include/inttypes.h @@ -1,4 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #ifndef INTTYPES_H #define INTTYPES_H + #include + +/* int8_t and uint8_t */ +#define PRId8 "d" +#define PRIi8 "i" +#define PRIu8 "u" +#define PRIo8 "o" +#define PRIx8 "x" +#define PRIX8 "X" + +/* int16_t and uint16_t */ +#define PRId16 "d" +#define PRIi16 "i" +#define PRIu16 "u" +#define PRIo16 "o" +#define PRIx16 "x" +#define PRIX16 "X" + +/* int32_t and uint32_t */ +#define PRId32 "d" +#define PRIi32 "i" +#define PRIu32 "u" +#define PRIo32 "o" +#define PRIx32 "x" +#define PRIX32 "X" + +/* int64_t and uint64_t */ +#define PRId64 "lld" +#define PRIi64 "lli" +#define PRIu64 "llu" +#define PRIo64 "llo" +#define PRIx64 "llx" +#define PRIX64 "llX" + +/* intptr_t and uintptr_t */ +#define PRIdPTR "ld" +#define PRIiPTR "li" +#define PRIuPTR "lu" +#define PRIoPTR "lo" +#define PRIxPTR "lx" +#define PRIXPTR "lX" + +/* intmax_t and uintmax_t */ +#define PRIdMAX "jd" +#define PRIiMAX "ji" +#define PRIuMAX "ju" +#define PRIoMAX "jo" +#define PRIxMAX "jx" +#define PRIXMAX "jX" + #endif /* INTTYPES_H */ diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 1ed87b61c9..0100e270c6 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -30,24 +30,6 @@ #define ARCH_CACHELINE_ALIGN_SIZE 64 #endif -/* Default to data as well as bss. */ -#ifndef ARCH_STAGE_HAS_DATA_SECTION -#define ARCH_STAGE_HAS_DATA_SECTION 1 -#endif - -#ifndef ARCH_STAGE_HAS_BSS_SECTION -#define ARCH_STAGE_HAS_BSS_SECTION 1 -#endif - -/* - * Default is that currently ENV_PAYLOAD_LOADER enable stage, smm, - * and rmodules have a heap. - */ -#ifndef ARCH_STAGE_HAS_HEAP_SECTION -#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_PAYLOAD_LOADER || ENV_SMM || \ - ENV_RMODULE) -#endif - #define STR(x) #x #define ALIGN_COUNTER(align) \ @@ -91,7 +73,7 @@ ALIAS_REGION(cbfs_cache, preram_cbfs_cache) \ ALIAS_REGION(cbfs_cache, postram_cbfs_cache) -#if defined(__PRE_RAM__) +#if ENV_ROMSTAGE_OR_BEFORE #define PRERAM_CBFS_CACHE(addr, size) \ REGION(preram_cbfs_cache, addr, size, 4) \ ALIAS_REGION(preram_cbfs_cache, cbfs_cache) diff --git a/src/include/ramdetect.h b/src/include/ramdetect.h index b63cdf14cf..e2a7eced67 100644 --- a/src/include/ramdetect.h +++ b/src/include/ramdetect.h @@ -11,6 +11,12 @@ * GNU General Public License for more details. */ + +/* + * Used in probe_ramsize(). This is a weak function and it's overridden for + * ARMv8. Return 1 when DRAM exists at the address, otherwise return 0. + */ +int probe_mb(const uintptr_t dram_start, const uintptr_t size); /* * Probe an area if it's read/writable. * Primary use case is the detection of DRAM amount on emulators. diff --git a/src/include/rules.h b/src/include/rules.h index d8f6e7438b..0436198363 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -266,6 +266,27 @@ #define ENV_PAYLOAD_LOADER ENV_RAMSTAGE #endif +#define ENV_ROMSTAGE_OR_BEFORE \ + (ENV_DECOMPRESSOR || ENV_BOOTBLOCK || ENV_ROMSTAGE || \ + (ENV_VERSTAGE && CONFIG(VBOOT_STARTS_IN_BOOTBLOCK))) + +#if CONFIG(ARCH_X86) +/* Indicates memory layout is determined with arch/x86/car.ld. */ +#define ENV_CACHE_AS_RAM (ENV_ROMSTAGE_OR_BEFORE && !CONFIG(RESET_VECTOR_IN_RAM)) +/* No .data sections with execute-in-place from ROM. */ +#define ENV_STAGE_HAS_DATA_SECTION !ENV_CACHE_AS_RAM +/* No .bss sections for stage with CAR teardown. */ +#define ENV_STAGE_HAS_BSS_SECTION !(ENV_ROMSTAGE && CONFIG(CAR_GLOBAL_MIGRATION)) +#else +/* Both .data and .bss, sometimes SRAM not DRAM. */ +#define ENV_STAGE_HAS_DATA_SECTION 1 +#define ENV_STAGE_HAS_BSS_SECTION 1 +#define ENV_CACHE_AS_RAM 0 +#endif + +/* Currently rmodules, ramstage and smm have heap. */ +#define ENV_STAGE_HAS_HEAP_SECTION (ENV_RMODULE || ENV_RAMSTAGE || ENV_SMM) + /** * For pre-DRAM stages and post-CAR always build with simple device model, ie. * PCI, PNP and CPU functions operate without use of devicetree. The reason @@ -277,16 +298,8 @@ * be built with simple device model. */ -#if (defined(__PRE_RAM__) || ENV_SMM || !ENV_PAYLOAD_LOADER) +#if !ENV_RAMSTAGE #define __SIMPLE_DEVICE__ #endif -/* x86 specific. Indicates that the current stage is running with cache-as-ram - * enabled from the beginning of the stage in C code. */ -#if defined(__PRE_RAM__) -#define ENV_CACHE_AS_RAM CONFIG(CACHE_AS_RAM) -#else -#define ENV_CACHE_AS_RAM 0 -#endif - #endif /* _RULES_H */ diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index e0a50ff45b..3de60a95ce 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -31,8 +31,10 @@ #define SPD_DRAM_DDR4 0x0C #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 +#define DDR3_ORGANIZATION 7 +#define DDR3_BUS_DEV_WIDTH 8 +#define DDR4_ORGANIZATION 12 +#define DDR4_BUS_DEV_WIDTH 13 #define DDR3_SPD_PART_OFF 128 #define DDR3_SPD_PART_LEN 18 #define LPDDR3_SPD_PART_OFF 128 diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index ffd3d2d008..c8dbb6798a 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -28,6 +28,19 @@ #include #include +/* SPI vendor IDs */ +#define VENDOR_ID_ADESTO 0x1f +#define VENDOR_ID_AMIC 0x37 +#define VENDOR_ID_ATMEL 0x1f +#define VENDOR_ID_EON 0x1c +#define VENDOR_ID_GIGADEVICE 0xc8 +#define VENDOR_ID_MACRONIX 0xc2 +#define VENDOR_ID_SPANSION 0x01 +#define VENDOR_ID_SST 0xbf +#define VENDOR_ID_STMICRO 0x20 +#define VENDOR_ID_STMICRO_FF 0xff +#define VENDOR_ID_WINBOND 0xef + /* Controller-specific definitions: */ struct spi_ctrlr; diff --git a/src/include/stddef.h b/src/include/stddef.h index 7cae2e6dc8..a2c9c50cd2 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -35,11 +35,16 @@ typedef unsigned int wint_t; #define DEVTREE_CONST #endif -/* Work around non-writable data segment in execute-in-place romstage on x86. */ -#if defined(__PRE_RAM__) && CONFIG(ARCH_X86) -#define MAYBE_STATIC +#if ENV_STAGE_HAS_DATA_SECTION +#define MAYBE_STATIC_NONZERO static #else -#define MAYBE_STATIC static +#define MAYBE_STATIC_NONZERO +#endif + +#if ENV_STAGE_HAS_BSS_SECTION +#define MAYBE_STATIC_BSS static +#else +#define MAYBE_STATIC_BSS #endif #ifndef __ROMCC__ diff --git a/src/include/stdint.h b/src/include/stdint.h index f363aab08a..0a8e153d6a 100644 --- a/src/include/stdint.h +++ b/src/include/stdint.h @@ -110,10 +110,4 @@ typedef _Bool bool; #define true 1 #define false 0 -/* TODO: move into inttypes.h */ -#ifndef __ROMCC__ -#define PRIu64 "llu" -#define PRIxPTR "lx" -#endif - #endif /* STDINT_H */ diff --git a/src/include/string.h b/src/include/string.h index 30241303eb..d3f09ff102 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -32,6 +32,9 @@ char *strncpy(char *to, const char *from, int count); char *strcpy(char *dst, const char *src); int strcmp(const char *s1, const char *s2); int strncmp(const char *s1, const char *s2, int maxlen); +int strspn(const char *str, const char *spn); +int strcspn(const char *str, const char *spn); +long atol(const char *str); /** * Find a character in a string. diff --git a/src/include/symbols.h b/src/include/symbols.h index cc27275f88..56df8d5734 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -72,7 +72,7 @@ DECLARE_REGION(bl31) * (Does not necessarily mean that the memory is accessible.) */ static inline int preram_symbols_available(void) { - return !CONFIG(CACHE_AS_RAM) || ENV_CACHE_AS_RAM; + return !CONFIG(ARCH_X86) || ENV_ROMSTAGE_OR_BEFORE; } #endif /* __SYMBOLS_H */ diff --git a/src/include/thread.h b/src/include/thread.h index e6af2efd55..b66803e3c0 100644 --- a/src/include/thread.h +++ b/src/include/thread.h @@ -20,7 +20,7 @@ #include #include -#if CONFIG(COOP_MULTITASKING) && !defined(__SMM__) && !defined(__PRE_RAM__) +#if ENV_RAMSTAGE && CONFIG(COOP_MULTITASKING) struct thread { int id; diff --git a/src/include/timestamp.h b/src/include/timestamp.h index 04d5c12761..f20fc6800a 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -21,17 +21,16 @@ #if CONFIG(COLLECT_TIMESTAMPS) /* - * timestamp_init() needs to be called once for each of these cases: - * 1. __PRE_RAM__ (bootblock, romstage, verstage, etc) and - * 2. !__PRE_RAM__ (ramstage) - * The latter is taken care of by the generic coreboot infrastructure so - * it's up to the chipset/arch to call timestamp_init() in *one* of - * the __PRE_RAM__ stages. If multiple calls are made timestamps will be lost. + * timestamp_init() needs to be called once in *one* of the ENV_ROMSTAGE_OR_BEFORE + * stages (bootblock, romstage, verstage, etc). It's up to the chipset/arch + * to make the call in the earliest stage, otherwise some timestamps will be lost. + * For x86 ENV_ROMSTAGE call must be made before CAR is torn down. */ void timestamp_init(uint64_t base); /* - * Add a new timestamp. Depending on cbmem is available or not, this timestamp - * will be stored to cbmem / timestamp cache. + * Add a new timestamp. For ENV_ROMSTAGE_OR_BEFORE, this timestamp will be stored + * inside REGION(timestamp) before cbmem comes online. For later stages, timestamps + * added before cbmem_[recovery|initialize] calls will be lost. */ void timestamp_add(enum timestamp_id id, uint64_t ts_time); /* Calls timestamp_add with current timestamp. */ diff --git a/src/include/trace.h b/src/include/trace.h index 4f5b8c4e04..aed69a8963 100644 --- a/src/include/trace.h +++ b/src/include/trace.h @@ -16,16 +16,7 @@ #ifndef __TRACE_H #define __TRACE_H - -#ifdef __PRE_RAM__ - -#define DISABLE_TRACE -#define ENABLE_TRACE -#define DISABLE_TRACE_ON_FUNCTION - -#else /* !__PRE_RAM__ */ - -#if CONFIG(TRACE) && !defined(__SMM__) +#if !ENV_ROMSTAGE_OR_BEFORE && CONFIG(TRACE) void __cyg_profile_func_enter(void *, void *) __attribute__((no_instrument_function)); @@ -46,5 +37,5 @@ extern volatile int trace_dis; #define DISABLE_TRACE_ON_FUNCTION #endif -#endif + #endif diff --git a/src/include/types.h b/src/include/types.h index d6fdc08588..5902bc268a 100644 --- a/src/include/types.h +++ b/src/include/types.h @@ -25,7 +25,9 @@ * from the MSB (e.g. PowerPC), but until we cross that bridge, this macro is * perfectly fine. */ +#ifndef BIT #define BIT(x) (1ul << (x)) +#endif /** * coreboot error codes diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 3925e90afe..19841c6931 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -30,7 +30,15 @@ __weak void bootblock_soc_early_init(void) { /* do nothing */ } __weak void bootblock_soc_init(void) { /* do nothing */ } __weak void bootblock_mainboard_init(void) { /* do nothing */ } -asmlinkage void bootblock_main_with_timestamp(uint64_t base_timestamp, +/* + * This is a the same as the bootblock main(), with the difference that it does + * not collect a timestamp. Instead it accepts the initial timestamp and + * possibly additional timestamp entries as arguments. This can be used in cases + * where earlier stamps are available. Note that this function is designed to be + * entered from C code. This function assumes that the timer has already been + * initialized, so it does not call init_timer(). + */ +static void bootblock_main_with_timestamp(uint64_t base_timestamp, struct timestamp_entry *timestamps, size_t num_timestamps) { /* Initialize timestamps if we have TIMESTAMP region in memlayout.ld. */ @@ -60,6 +68,11 @@ asmlinkage void bootblock_main_with_timestamp(uint64_t base_timestamp, run_romstage(); } +void bootblock_main_with_basetime(uint64_t base_timestamp) +{ + bootblock_main_with_timestamp(base_timestamp, NULL, 0); +} + void main(void) { uint64_t base_timestamp = 0; diff --git a/src/lib/bootsplash.c b/src/lib/bootsplash.c index 5527b233f5..812a3b7ccc 100644 --- a/src/lib/bootsplash.c +++ b/src/lib/bootsplash.c @@ -21,27 +21,12 @@ #include "jpeg.h" -void set_vesa_bootsplash(void) -{ - const vbe_mode_info_t *mode_info = vbe_mode_info(); - if (mode_info != NULL) { - printk(BIOS_INFO, "Setting up bootsplash\n"); - unsigned int x_resolution = le16_to_cpu(mode_info->vesa.x_resolution); - unsigned int y_resolution = le16_to_cpu(mode_info->vesa.y_resolution); - unsigned int fb_resolution = mode_info->vesa.bits_per_pixel; - unsigned char *framebuffer = - (unsigned char *)le32_to_cpu(mode_info->vesa.phys_base_ptr); - - set_bootsplash(framebuffer, x_resolution, y_resolution, fb_resolution); - } else { - printk(BIOS_ERR, "VBE modeinfo invalid\n"); - } -} - void set_bootsplash(unsigned char *framebuffer, unsigned int x_resolution, unsigned int y_resolution, unsigned int fb_resolution) { + printk(BIOS_INFO, "Setting up bootsplash in %dx%d@%d\n", x_resolution, y_resolution, + fb_resolution); struct jpeg_decdata *decdata; unsigned char *jpeg = cbfs_boot_map_with_leak("bootsplash.jpg", CBFS_TYPE_BOOTSPLASH, NULL); @@ -50,6 +35,11 @@ void set_bootsplash(unsigned char *framebuffer, unsigned int x_resolution, return; } + int image_width, image_height; + jpeg_fetch_size(jpeg, &image_width, &image_height); + + printk(BIOS_DEBUG, "Bootsplash image resolution: %dx%d\n", image_width, image_height); + decdata = malloc(sizeof(*decdata)); int ret = jpeg_decode(jpeg, framebuffer, x_resolution, y_resolution, fb_resolution, decdata); diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index d86edf013a..b018acb4fa 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -32,7 +32,3 @@ void cbmem_run_init_hooks(int is_recovery) init_hook_ptr++; } } - -void __weak cbmem_fail_resume(void) -{ -} diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index df2d1ffa96..7876ff510a 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -51,16 +51,11 @@ _Static_assert(CONFIG_CONSOLE_CBMEM_BUFFER_SIZE <= MAX_SIZE, static struct cbmem_console *cbmem_console_p CAR_GLOBAL; -#ifdef __PRE_RAM__ /* * While running from ROM, before DRAM is initialized, some area in cache as * RAM space is used for the console buffer storage. The size and location of * the area are defined by the linker script with _(e)preram_cbmem_console. - */ - -#else - -/* + * * When running from RAM, some console output is generated before CBMEM is * reinitialized. This static buffer is used to store that output temporarily, * to be concatenated with the CBMEM console buffer contents accumulated @@ -69,16 +64,15 @@ static struct cbmem_console *cbmem_console_p CAR_GLOBAL; #define STATIC_CONSOLE_SIZE 1024 static u8 static_console[STATIC_CONSOLE_SIZE]; -#endif static struct cbmem_console *current_console(void) { - return car_sync_var(cbmem_console_p); + return car_get_ptr(cbmem_console_p); } static void current_console_set(struct cbmem_console *new_console_p) { - car_set_var(cbmem_console_p, new_console_p); + car_set_ptr(cbmem_console_p, new_console_p); } static int buffer_valid(struct cbmem_console *cbm_cons_p, u32 total_space) @@ -107,14 +101,13 @@ static void init_console_ptr(void *storage, u32 total_space) void cbmemc_init(void) { -#ifdef __PRE_RAM__ - /* Pre-RAM environments use special buffer placed by linker script. */ - init_console_ptr(_preram_cbmem_console, - REGION_SIZE(preram_cbmem_console)); -#else - /* Post-RAM uses static (BSS) buffer before CBMEM is reinitialized. */ - init_console_ptr(static_console, sizeof(static_console)); -#endif + if (ENV_ROMSTAGE_OR_BEFORE) { + /* Pre-RAM environments use special buffer placed by linker script. */ + init_console_ptr(_preram_cbmem_console, REGION_SIZE(preram_cbmem_console)); + } else { + /* Post-RAM uses static (BSS) buffer before CBMEM is reinitialized. */ + init_console_ptr(static_console, sizeof(static_console)); + } } void cbmemc_tx_byte(unsigned char data) diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 95c2ae6e24..9c5942fa9d 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include @@ -144,6 +145,14 @@ static void lb_framebuffer(struct lb_header *header) memcpy(framebuffer, &fb, sizeof(*framebuffer)); framebuffer->tag = LB_TAG_FRAMEBUFFER; framebuffer->size = sizeof(*framebuffer); + + if (CONFIG(BOOTSPLASH)) { + uint8_t *fb_ptr = (uint8_t *)(uintptr_t)framebuffer->physical_address; + unsigned int width = framebuffer->x_resolution; + unsigned int height = framebuffer->y_resolution; + unsigned int depth = framebuffer->bits_per_pixel; + set_bootsplash(fb_ptr, width, height, depth); + } } void lb_add_gpios(struct lb_gpios *gpios, const struct lb_gpio *gpio_table, @@ -336,7 +345,8 @@ static void add_cbmem_pointers(struct lb_header *header) {CBMEM_ID_ACPI_GNVS, LB_TAG_ACPI_GNVS}, {CBMEM_ID_VPD, LB_TAG_VPD}, {CBMEM_ID_WIFI_CALIBRATION, LB_TAG_WIFI_CALIBRATION}, - {CBMEM_ID_TCPA_LOG, LB_TAG_TCPA_LOG} + {CBMEM_ID_TCPA_LOG, LB_TAG_TCPA_LOG}, + {CBMEM_ID_FMAP, LB_TAG_FMAP}, }; int i; diff --git a/src/lib/edid.c b/src/lib/edid.c index 3b81b5c30a..964dce260e 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -72,7 +72,6 @@ struct edid_context { /* Stuff that isn't used anywhere but is nice to pretty-print while we're decoding everything else. */ static struct { - char manuf_name[4]; unsigned int model; unsigned int serial; unsigned int year; @@ -94,20 +93,20 @@ static struct { static struct edid tmp_edid; -static char *manufacturer_name(unsigned char *x) +static int manufacturer_name(unsigned char *x, char *output) { - extra_info.manuf_name[0] = ((x[0] & 0x7C) >> 2) + '@'; - extra_info.manuf_name[1] = ((x[0] & 0x03) << 3) + ((x[1] & 0xE0) >> 5) - + '@'; - extra_info.manuf_name[2] = (x[1] & 0x1F) + '@'; - extra_info.manuf_name[3] = 0; + output[0] = ((x[0] & 0x7C) >> 2) + '@'; + output[1] = ((x[0] & 0x03) << 3) + ((x[1] & 0xE0) >> 5) + '@'; + output[2] = (x[1] & 0x1F) + '@'; + output[3] = 0; - if (isupper(extra_info.manuf_name[0]) && - isupper(extra_info.manuf_name[1]) && - isupper(extra_info.manuf_name[2])) - return extra_info.manuf_name; + if (isupper(output[0]) && + isupper(output[1]) && + isupper(output[2])) + return 1; - return NULL; + memset(output, 0, 4); + return 0; } static int @@ -1154,7 +1153,7 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) return EDID_ABSENT; } - if (manufacturer_name(edid + 0x08)) + if (manufacturer_name(edid + 0x08, out->manufacturer_name)) c.manufacturer_name_well_formed = 1; extra_info.model = (unsigned short)(edid[0x0A] + (edid[0x0B] << 8)); @@ -1162,7 +1161,7 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) + (edid[0x0E] << 16) + (edid[0x0F] << 24)); printk(BIOS_SPEW, "Manufacturer: %s Model %x Serial Number %u\n", - extra_info.manuf_name, + out->manufacturer_name, (unsigned short)(edid[0x0A] + (edid[0x0B] << 8)), (unsigned int)(edid[0x0C] + (edid[0x0D] << 8) + (edid[0x0E] << 16) + (edid[0x0F] << 24))); diff --git a/src/lib/fmap.c b/src/lib/fmap.c index 2b4e3bae2c..f0074186da 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -20,6 +20,7 @@ #include #include #include +#include #include "fmap_config.h" @@ -28,6 +29,7 @@ */ static int fmap_print_once CAR_GLOBAL; +static struct mem_region_device fmap_cache CAR_GLOBAL; int find_fmap_directory(struct region_device *fmrd) { @@ -36,6 +38,16 @@ int find_fmap_directory(struct region_device *fmrd) size_t fmap_size; size_t offset = FMAP_OFFSET; + if (cbmem_possibly_online() && !ENV_SMM) { + /* Try FMAP cache first */ + const struct mem_region_device *cache; + + cache = car_get_var_ptr(&fmap_cache); + if (region_device_sz(&cache->rdev)) + return rdev_chain(fmrd, &cache->rdev, 0, + region_device_sz(&cache->rdev)); + } + boot_device_init(); boot = boot_device_ro(); @@ -195,3 +207,53 @@ ssize_t fmap_overwrite_area(const char *name, const void *buffer, size_t size) return -1; return rdev_writeat(&rdev, buffer, 0, size); } + +static void fmap_register_cache(int unused) +{ + const struct cbmem_entry *e; + struct mem_region_device *mdev; + + mdev = car_get_var_ptr(&fmap_cache); + + /* Find the FMAP cache installed by previous stage */ + e = cbmem_entry_find(CBMEM_ID_FMAP); + /* Don't set fmap_cache so that find_fmap_directory will use regular path */ + if (!e) + return; + + mem_region_device_ro_init(mdev, cbmem_entry_start(e), cbmem_entry_size(e)); +} + +/* + * The main reason to copy the FMAP into CBMEM is to make it available to the + * OS on every architecture. As side effect use the CBMEM copy as cache. + */ +static void fmap_setup_cache(int unused) +{ + struct region_device fmrd; + + if (find_fmap_directory(&fmrd)) + return; + + /* Reloads the FMAP even on ACPI S3 resume */ + const size_t s = region_device_sz(&fmrd); + struct fmap *fmap = cbmem_add(CBMEM_ID_FMAP, s); + if (!fmap) { + printk(BIOS_ERR, "ERROR: Failed to allocate CBMEM\n"); + return; + } + + const ssize_t ret = rdev_readat(&fmrd, fmap, 0, s); + if (ret != s) { + printk(BIOS_ERR, "ERROR: Failed to read FMAP into CBMEM\n"); + cbmem_entry_remove(cbmem_entry_find(CBMEM_ID_FMAP)); + return; + } + + /* Finally advertise the cache for the current stage */ + fmap_register_cache(unused); +} + +ROMSTAGE_CBMEM_INIT_HOOK(fmap_setup_cache) +RAMSTAGE_CBMEM_INIT_HOOK(fmap_register_cache) +POSTCAR_CBMEM_INIT_HOOK(fmap_register_cache) diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 2881162a34..2ff2b8c874 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -187,8 +187,6 @@ static boot_state_t bs_os_resume_check(void *arg) boot_states[BS_OS_RESUME].arg = wake_vector; return BS_OS_RESUME; } - - acpi_prepare_resume_backup(); #endif timestamp_add_now(TS_CBMEM_POST); @@ -453,18 +451,16 @@ void main(void) /* console_init() MUST PRECEDE ALL printk()! Additionally, ensure * it is the very first thing done in ramstage.*/ console_init(); - post_code(POST_CONSOLE_READY); + exception_init(); + /* * CBMEM needs to be recovered because timestamps, ACPI, etc rely on * the cbmem infrastructure being around. Explicitly recover it. */ cbmem_initialize(); - /* Record current time, try to locate timestamps in CBMEM. */ - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_RAMSTAGE); post_code(POST_ENTRY_RAMSTAGE); @@ -472,8 +468,6 @@ void main(void) #if CONFIG(HAVE_ACPI_RESUME) acpi_is_wakeup(); #endif - - exception_init(); threads_initialize(); /* Schedule the static boot state entries. */ diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index b1b63f68b3..f04e0862fe 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -41,7 +41,7 @@ */ #define CAN_USE_GLOBALS \ (!CONFIG(ARCH_X86) || ENV_RAMSTAGE || ENV_POSTCAR || \ - CONFIG(NO_CAR_GLOBAL_MIGRATION)) + !CONFIG(CAR_GLOBAL_MIGRATION)) static inline struct imd *cbmem_get_imd(void) { @@ -172,14 +172,13 @@ int cbmem_initialize_id_size(u32 id, u64 size) if (imd_recover(imd)) return 1; -#if defined(__PRE_RAM__) /* * Lock the imd in romstage on a recovery. The assumption is that * if the imd area was recovered in romstage then S3 resume path * is being taken. */ - imd_lockdown(imd); -#endif + if (ENV_ROMSTAGE) + imd_lockdown(imd); /* Add the specified range first */ if (size) diff --git a/src/lib/lzma.c b/src/lib/lzma.c index eecbb267d2..71c016ebcd 100644 --- a/src/lib/lzma.c +++ b/src/lib/lzma.c @@ -26,7 +26,7 @@ size_t ulzman(const void *src, size_t srcn, void *dst, size_t dstn) int res; CLzmaDecoderState state; SizeT mallocneeds; - MAYBE_STATIC unsigned char scratchpad[15980]; + MAYBE_STATIC_BSS unsigned char scratchpad[15980]; const unsigned char *cp; memcpy(properties, src, LZMA_PROPERTIES_SIZE); diff --git a/src/lib/primitive_memtest.c b/src/lib/primitive_memtest.c index c699e8906b..aa013772a8 100644 --- a/src/lib/primitive_memtest.c +++ b/src/lib/primitive_memtest.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index dfabd31910..2ef6bdfc32 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -107,18 +107,6 @@ static int load_relocatable_ramstage(struct prog *ramstage) return rmodule_stage_load(&rmod_ram); } -static int load_nonrelocatable_ramstage(struct prog *ramstage) -{ - if (CONFIG(HAVE_ACPI_RESUME)) { - uintptr_t base = 0; - size_t size = cbfs_prog_stage_section(ramstage, &base); - if (size) - backup_ramstage_section(base, size); - } - - return cbfs_prog_stage_load(ramstage); -} - void run_ramstage(void) { struct prog ramstage = @@ -147,7 +135,7 @@ void run_ramstage(void) if (CONFIG(RELOCATABLE_RAMSTAGE)) { if (load_relocatable_ramstage(&ramstage)) goto fail; - } else if (load_nonrelocatable_ramstage(&ramstage)) + } else if (cbfs_prog_stage_load(&ramstage)) goto fail; stage_cache_add(STAGE_RAMSTAGE, &ramstage); diff --git a/src/lib/program.ld b/src/lib/program.ld index 851aa75d67..a9d4e48293 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -85,7 +85,7 @@ #endif /* Include data, bss, and heap in that order. Not defined for all stages. */ -#if ARCH_STAGE_HAS_DATA_SECTION +#if ENV_STAGE_HAS_DATA_SECTION .data . : { . = ALIGN(ARCH_CACHELINE_ALIGN_SIZE); _data = .; @@ -108,7 +108,7 @@ *(.sdata); *(.sdata.*); -#ifdef __PRE_RAM__ +#if ENV_ROMSTAGE_OR_BEFORE PROVIDE(_preram_cbmem_console = .); PROVIDE(_epreram_cbmem_console = _preram_cbmem_console); #elif ENV_RAMSTAGE @@ -125,7 +125,7 @@ } #endif -#if ARCH_STAGE_HAS_BSS_SECTION +#if ENV_STAGE_HAS_BSS_SECTION && !ENV_CACHE_AS_RAM .bss . : { . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _bss = .; @@ -138,7 +138,7 @@ } #endif -#if ARCH_STAGE_HAS_HEAP_SECTION +#if ENV_STAGE_HAS_HEAP_SECTION .heap . : { . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _heap = .; diff --git a/src/lib/ramdetect.c b/src/lib/ramdetect.c index 5416a580dd..2c83092ebc 100644 --- a/src/lib/ramdetect.c +++ b/src/lib/ramdetect.c @@ -19,7 +19,7 @@ #define OVERLAP(a, b, s, e) ((b) > (s) && (a) < (e)) -static int probe_mb(const uintptr_t dram_start, const uintptr_t size) +int __weak probe_mb(const uintptr_t dram_start, const uintptr_t size) { uintptr_t addr = dram_start + (size * MiB) - sizeof(uint32_t); static const uint32_t patterns[] = { diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index 50cf7b6d08..5f4fa9fa11 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -36,7 +36,8 @@ #endif #define POLL_DELAY 100 /* 100us */ -#if defined(__PRE_RAM__) + +#ifdef __SIMPLE_DEVICE__ #define EMPTY_DEV 0 #else #define EMPTY_DEV NULL @@ -68,7 +69,7 @@ reg_script_get_step(struct reg_script_context *ctx) static struct resource *reg_script_get_resource(struct reg_script_context *ctx) { -#if defined(__PRE_RAM__) +#ifdef __SIMPLE_DEVICE__ return NULL; #else struct resource *res; diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 1598ff162f..62e600b2c8 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -33,54 +33,146 @@ void dump_spd_info(struct spd_block *blk) } } -void print_spd_info(uint8_t spd[]) +static bool is_memory_type_ddr4(int dram_type) { - const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 128 }; - const int spd_rows[8] = {12, 13, 14, 15, 16, 17, -1, -1 }; - const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; - const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; - const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; - const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - char spd_name[DDR4_SPD_PART_LEN+1] = { 0 }; + return (dram_type == SPD_DRAM_DDR4); +} - int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; - int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; - int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; - int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; - int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; - int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; - int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; - - /* Module type */ - printk(BIOS_INFO, "SPD: module type is "); - switch (spd[SPD_DRAM_TYPE]) { +static const char *spd_get_module_type_string(int dram_type) +{ + switch (dram_type) { + case SPD_DRAM_DDR3: + return "DDR3"; + case SPD_DRAM_LPDDR3_INTEL: + case SPD_DRAM_LPDDR3_JEDEC: + return "LPDDR3"; + case SPD_DRAM_DDR4: + return "DDR4"; + } + return "UNKNOWN"; +} + +static int spd_get_banks(const uint8_t spd[], int dram_type) +{ + static const int ddr3_banks[4] = { 8, 16, 32, 64 }; + static const int ddr4_banks[10] = { 4, 8, -1, -1, 8, 16, -1, -1, 16, 32 }; + int index = (spd[SPD_DENSITY_BANKS] >> 4) & 0xf; + switch (dram_type) { + /* DDR3 and LPDDR3 has the same bank definition */ + case SPD_DRAM_DDR3: + case SPD_DRAM_LPDDR3_INTEL: + case SPD_DRAM_LPDDR3_JEDEC: + if (index >= ARRAY_SIZE(ddr3_banks)) + return -1; + return ddr3_banks[index]; + case SPD_DRAM_DDR4: + if (index >= ARRAY_SIZE(ddr4_banks)) + return -1; + return ddr4_banks[index]; + default: + return -1; + } +} + +static int spd_get_capmb(const uint8_t spd[]) +{ + static const int spd_capmb[10] = { 1, 2, 4, 8, 16, 32, 64, 128, 48, 96 }; + int index = spd[SPD_DENSITY_BANKS] & 0xf; + if (index >= ARRAY_SIZE(spd_capmb)) + return -1; + return spd_capmb[index] * 256; +} + +static int spd_get_rows(const uint8_t spd[]) +{ + static const int spd_rows[7] = { 12, 13, 14, 15, 16, 17, 18 }; + int index = (spd[SPD_ADDRESSING] >> 3) & 7; + if (index >= ARRAY_SIZE(spd_rows)) + return -1; + return spd_rows[index]; +} + +static int spd_get_cols(const uint8_t spd[]) +{ + static const int spd_cols[4] = { 9, 10, 11, 12 }; + int index = spd[SPD_ADDRESSING] & 7; + if (index >= ARRAY_SIZE(spd_cols)) + return -1; + return spd_cols[index]; +} + +static int spd_get_ranks(const uint8_t spd[], int dram_type) +{ + static const int spd_ranks[8] = { 1, 2, 3, 4, 5, 6, 7, 8 }; + int organ_offset = is_memory_type_ddr4(dram_type) ? DDR4_ORGANIZATION + : DDR3_ORGANIZATION; + int index = (spd[organ_offset] >> 3) & 7; + if (index >= ARRAY_SIZE(spd_ranks)) + return -1; + return spd_ranks[index]; +} + +static int spd_get_devw(const uint8_t spd[], int dram_type) +{ + static const int spd_devw[4] = { 4, 8, 16, 32 }; + int organ_offset = is_memory_type_ddr4(dram_type) ? DDR4_ORGANIZATION + : DDR3_ORGANIZATION; + int index = spd[organ_offset] & 7; + if (index >= ARRAY_SIZE(spd_devw)) + return -1; + return spd_devw[index]; +} + +static int spd_get_busw(const uint8_t spd[], int dram_type) +{ + static const int spd_busw[4] = { 8, 16, 32, 64 }; + int busw_offset = is_memory_type_ddr4(dram_type) ? DDR4_BUS_DEV_WIDTH + : DDR3_BUS_DEV_WIDTH; + int index = spd[busw_offset] & 7; + if (index >= ARRAY_SIZE(spd_busw)) + return -1; + return spd_busw[index]; +} + +static void spd_get_name(const uint8_t spd[], char spd_name[], int dram_type) +{ + switch (dram_type) { case SPD_DRAM_DDR3: - printk(BIOS_INFO, "DDR3\n"); - /* Module Part Number */ memcpy(spd_name, &spd[DDR3_SPD_PART_OFF], DDR3_SPD_PART_LEN); spd_name[DDR3_SPD_PART_LEN] = 0; break; case SPD_DRAM_LPDDR3_INTEL: case SPD_DRAM_LPDDR3_JEDEC: - printk(BIOS_INFO, "LPDDR3\n"); - /* Module Part Number */ memcpy(spd_name, &spd[LPDDR3_SPD_PART_OFF], LPDDR3_SPD_PART_LEN); spd_name[LPDDR3_SPD_PART_LEN] = 0; break; case SPD_DRAM_DDR4: - printk(BIOS_INFO, "DDR4\n"); memcpy(spd_name, &spd[DDR4_SPD_PART_OFF], DDR4_SPD_PART_LEN); spd_name[DDR4_SPD_PART_LEN] = 0; - ranks = (spd[SPD_ORGANIZATION] >> 3) & 7; - devw = spd_devw[spd[12] & 7]; - busw = spd_busw[spd[13] & 7]; break; default: - printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); break; } +} + +void print_spd_info(uint8_t spd[]) +{ + char spd_name[DDR4_SPD_PART_LEN+1] = { 0 }; + int type = spd[SPD_DRAM_TYPE]; + int banks = spd_get_banks(spd, type); + int capmb = spd_get_capmb(spd); + int rows = spd_get_rows(spd); + int cols = spd_get_cols(spd); + int ranks = spd_get_ranks(spd, type); + int devw = spd_get_devw(spd, type); + int busw = spd_get_busw(spd, type); + + /* Module type */ + printk(BIOS_INFO, "SPD: module type is %s\n", + spd_get_module_type_string(type)); + /* Module Part Number */ + spd_get_name(spd, spd_name, type); printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); diff --git a/src/lib/string.c b/src/lib/string.c index eb6adb67c7..f0c24edcfc 100644 --- a/src/lib/string.c +++ b/src/lib/string.c @@ -132,3 +132,55 @@ unsigned int skip_atoi(char **s) i = i*10 + *((*s)++) - '0'; return i; } + +int strspn(const char *str, const char *spn) +{ + int ret = 0; + + while (*str != 0) { + const char *p; + for (p = spn; *str != *p; p++) + if (*p == '\0') + return ret; + ret++; + str++; + } + return ret; +} + +int strcspn(const char *str, const char *spn) +{ + int ret = 0; + + while (*str != 0) { + const char *p; + for (p = spn; *p != '\0'; p++) + if (*p == *str) + return ret; + ret++; + str++; + } + return ret; +} + +long atol(const char *str) +{ + long ret = 0; + long sign = 1; + + str += strspn(str, " \t\n\r\f\v"); + + if (*str == '+') { + sign = 1; + str++; + } else if (*str == '-') { + sign = -1; + str++; + } + + while (isdigit(*str)) { + ret *= 10; + ret += *str++ - '0'; + } + return ret * sign; +} diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index adacf6b1b3..dcb3124567 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -27,67 +27,33 @@ #define MAX_TIMESTAMPS 192 -/* When changing this number, adjust TIMESTAMP() size ASSERT() in memlayout.h */ -#define MAX_BSS_TIMESTAMP_CACHE 16 - -struct __packed timestamp_cache { - uint32_t cache_state; - struct timestamp_table table; - /* The struct timestamp_table has a 0 length array as its last field. - * The following 'entries' array serves as the storage space for the - * cache when allocated in the BSS. */ - struct timestamp_entry entries[MAX_BSS_TIMESTAMP_CACHE]; -}; - DECLARE_OPTIONAL_REGION(timestamp); -#if defined(__PRE_RAM__) -#define USE_TIMESTAMP_REGION (REGION_SIZE(timestamp) > 0) -#else -#define USE_TIMESTAMP_REGION 0 -#endif +/* This points to the active timestamp_table and can change within a stage + as CBMEM comes available. */ +static struct timestamp_table *glob_ts_table CAR_GLOBAL; -/* The cache location will sit in BSS when in ramstage/postcar. */ -#define TIMESTAMP_CACHE_IN_BSS (ENV_RAMSTAGE || ENV_POSTCAR) - -#define HAS_CBMEM (ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_POSTCAR) - -/* - * Storage of cache entries during ramstage/postcar prior to cbmem coming - * online. - */ -static struct timestamp_cache timestamp_cache; - -enum { - TIMESTAMP_CACHE_UNINITIALIZED = 0, - TIMESTAMP_CACHE_INITIALIZED, - TIMESTAMP_CACHE_NOT_NEEDED, -}; - -static void timestamp_cache_init(struct timestamp_cache *ts_cache, +static void timestamp_cache_init(struct timestamp_table *ts_cache, uint64_t base) { - ts_cache->table.num_entries = 0; - ts_cache->table.max_entries = MAX_BSS_TIMESTAMP_CACHE; - ts_cache->table.base_time = base; - ts_cache->cache_state = TIMESTAMP_CACHE_INITIALIZED; - - if (USE_TIMESTAMP_REGION) - ts_cache->table.max_entries = (REGION_SIZE(timestamp) - - offsetof(struct timestamp_cache, entries)) - / sizeof(struct timestamp_entry); + ts_cache->num_entries = 0; + ts_cache->base_time = base; + ts_cache->max_entries = (REGION_SIZE(timestamp) - + offsetof(struct timestamp_table, entries)) + / sizeof(struct timestamp_entry); } -static struct timestamp_cache *timestamp_cache_get(void) +static struct timestamp_table *timestamp_cache_get(void) { - struct timestamp_cache *ts_cache = NULL; + struct timestamp_table *ts_cache = NULL; - if (TIMESTAMP_CACHE_IN_BSS) { - ts_cache = ×tamp_cache; - } else if (USE_TIMESTAMP_REGION) { - if (REGION_SIZE(timestamp) < sizeof(*ts_cache)) - BUG(); - ts_cache = car_get_var_ptr((void *)_timestamp); + if (!ENV_ROMSTAGE_OR_BEFORE) + return NULL; + + if (REGION_SIZE(timestamp) < sizeof(*ts_cache)) { + BUG(); + } else { + ts_cache = (void *)_timestamp; } return ts_cache; @@ -128,33 +94,23 @@ static int timestamp_should_run(void) static struct timestamp_table *timestamp_table_get(void) { - MAYBE_STATIC struct timestamp_table *ts_table = NULL; - struct timestamp_cache *ts_cache; + struct timestamp_table *ts_table; - if (ts_table != NULL) + ts_table = car_get_ptr(glob_ts_table); + if (ts_table) return ts_table; - ts_cache = timestamp_cache_get(); - - if (ts_cache == NULL) { - if (HAS_CBMEM) - ts_table = cbmem_find(CBMEM_ID_TIMESTAMP); - return ts_table; - } - - /* Cache is required. */ - if (ts_cache->cache_state != TIMESTAMP_CACHE_NOT_NEEDED) - return &ts_cache->table; - - /* Cache shouldn't be used but there's no backing store. */ - if (!HAS_CBMEM) - return NULL; - - ts_table = cbmem_find(CBMEM_ID_TIMESTAMP); + ts_table = timestamp_cache_get(); + car_set_ptr(glob_ts_table, ts_table); return ts_table; } +static void timestamp_table_set(struct timestamp_table *ts) +{ + car_set_ptr(glob_ts_table, ts); +} + static const char *timestamp_name(enum timestamp_id id) { int i; @@ -180,8 +136,7 @@ static void timestamp_add_table_entry(struct timestamp_table *ts_table, tse->entry_stamp = ts_time - ts_table->base_time; if (CONFIG(TIMESTAMPS_ON_CONSOLE)) - printk(BIOS_SPEW, "Timestamp - %s: %" PRIu64 "\n", - timestamp_name(id), ts_time); + printk(BIOS_SPEW, "Timestamp - %s: %llu\n", timestamp_name(id), ts_time); if (ts_table->num_entries == ts_table->max_entries) printk(BIOS_ERR, "ERROR: Timestamp table full\n"); @@ -211,7 +166,9 @@ void timestamp_add_now(enum timestamp_id id) void timestamp_init(uint64_t base) { - struct timestamp_cache *ts_cache; + struct timestamp_table *ts_cache; + + assert(ENV_ROMSTAGE_OR_BEFORE); if (!timestamp_should_run()) return; @@ -223,57 +180,21 @@ void timestamp_init(uint64_t base) return; } - /* Timestamps could have already been recovered. - * In those circumstances honor the cache which sits in BSS - * as it has already been initialized. */ - if (TIMESTAMP_CACHE_IN_BSS && - ts_cache->cache_state != TIMESTAMP_CACHE_UNINITIALIZED) - return; - timestamp_cache_init(ts_cache, base); + timestamp_table_set(ts_cache); } -static void timestamp_sync_cache_to_cbmem(int is_recovery) +static void timestamp_sync_cache_to_cbmem(struct timestamp_table *ts_cbmem_table) { uint32_t i; - struct timestamp_cache *ts_cache; struct timestamp_table *ts_cache_table; - struct timestamp_table *ts_cbmem_table = NULL; - if (!timestamp_should_run()) - return; - - ts_cache = timestamp_cache_get(); - - /* No timestamp cache found */ - if (ts_cache == NULL) { + ts_cache_table = timestamp_table_get(); + if (!ts_cache_table) { printk(BIOS_ERR, "ERROR: No timestamp cache found\n"); return; } - ts_cache_table = &ts_cache->table; - - /* cbmem is being recovered. */ - if (is_recovery) { - /* x86 resume path expects timestamps to be reset. */ - if (CONFIG(ARCH_ROMSTAGE_X86_32) && ENV_ROMSTAGE) - ts_cbmem_table = timestamp_alloc_cbmem_table(); - else { - /* Find existing table in cbmem. */ - ts_cbmem_table = cbmem_find(CBMEM_ID_TIMESTAMP); - /* No existing timestamp table. */ - if (ts_cbmem_table == NULL) - ts_cbmem_table = timestamp_alloc_cbmem_table(); - } - } else - /* First time sync. Add new table. */ - ts_cbmem_table = timestamp_alloc_cbmem_table(); - - if (ts_cbmem_table == NULL) { - printk(BIOS_ERR, "ERROR: No timestamp table allocated\n"); - return; - } - /* * There's no need to worry about the base_time fields being out of * sync because only the following configuration is used/supported: @@ -295,6 +216,7 @@ static void timestamp_sync_cache_to_cbmem(int is_recovery) * If timestamps only get initialized in ramstage, the base_time from * timestamp_init() will get ignored and all timestamps will be 0-based. */ + for (i = 0; i < ts_cache_table->num_entries; i++) { struct timestamp_entry *tse = &ts_cache_table->entries[i]; timestamp_add_table_entry(ts_cbmem_table, tse->entry_id, @@ -305,13 +227,40 @@ static void timestamp_sync_cache_to_cbmem(int is_recovery) if (ts_cbmem_table->base_time == 0) ts_cbmem_table->base_time = ts_cache_table->base_time; + /* Cache no longer required. */ + ts_cache_table->num_entries = 0; +} + +static void timestamp_reinit(int is_recovery) +{ + struct timestamp_table *ts_cbmem_table; + + if (!timestamp_should_run()) + return; + + /* First time into romstage we make a clean new table. For platforms that travel + through this path on resume, ARCH_X86 S3, timestamps are also reset. */ + if (ENV_ROMSTAGE) { + ts_cbmem_table = timestamp_alloc_cbmem_table(); + } else { + /* Find existing table in cbmem. */ + ts_cbmem_table = cbmem_find(CBMEM_ID_TIMESTAMP); + } + + if (ts_cbmem_table == NULL) { + printk(BIOS_ERR, "ERROR: No timestamp table allocated\n"); + timestamp_table_set(NULL); + return; + } + + if (ENV_ROMSTAGE) + timestamp_sync_cache_to_cbmem(ts_cbmem_table); + /* Seed the timestamp tick frequency in ENV_PAYLOAD_LOADER. */ if (ENV_PAYLOAD_LOADER) ts_cbmem_table->tick_freq_mhz = timestamp_tick_freq_mhz(); - /* Cache no longer required. */ - ts_cache_table->num_entries = 0; - ts_cache->cache_state = TIMESTAMP_CACHE_NOT_NEEDED; + timestamp_table_set(ts_cbmem_table); } void timestamp_rescale_table(uint16_t N, uint16_t M) @@ -355,9 +304,9 @@ uint32_t get_us_since_boot(void) return (timestamp_get() - ts->base_time) / ts->tick_freq_mhz; } -ROMSTAGE_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem) -POSTCAR_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem) -RAMSTAGE_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem) +ROMSTAGE_CBMEM_INIT_HOOK(timestamp_reinit) +POSTCAR_CBMEM_INIT_HOOK(timestamp_reinit) +RAMSTAGE_CBMEM_INIT_HOOK(timestamp_reinit) /* Provide default timestamp implementation using monotonic timer. */ uint64_t __weak timestamp_get(void) diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index ca32977e10..0589a0be77 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -17,7 +17,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index d318d0c43f..e9836904d3 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -117,9 +117,11 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) static AGESA_STATUS board_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr) { -#ifdef __PRE_RAM__ - int spdAddress; AGESA_READ_SPD_PARAMS *info = ConfigPtr; + int spdAddress; + + if (!ENV_ROMSTAGE) + return AGESA_UNSUPPORTED; DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2); @@ -154,6 +156,6 @@ static AGESA_STATUS board_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr) int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128); if (err) return AGESA_ERROR; -#endif + return AGESA_SUCCESS; } diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index e2142f2791..909f33ec93 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/src/cpu/intel/model_2065x/tsc_freq.c b/src/mainboard/amd/padmelon/BiosCallOuts.c similarity index 64% rename from src/cpu/intel/model_2065x/tsc_freq.c rename to src/mainboard/amd/padmelon/BiosCallOuts.c index 041785b7a3..3ac305db4c 100644 --- a/src/cpu/intel/model_2065x/tsc_freq.c +++ b/src/mainboard/amd/padmelon/BiosCallOuts.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,15 +13,9 @@ * GNU General Public License for more details. */ -#include -#include -#include -#include "model_2065x.h" +#include -unsigned long tsc_freq_mhz(void) +void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env) { - msr_t platform_info; - platform_info = rdmsr(MSR_PLATFORM_INFO); - return NEHALEM_BCLK * ((platform_info.lo >> 8) & 0xff); } diff --git a/src/mainboard/amd/padmelon/BiosCallOuts.h b/src/mainboard/amd/padmelon/BiosCallOuts.h new file mode 100644 index 0000000000..239f7d8f89 --- /dev/null +++ b/src/mainboard/amd/padmelon/BiosCallOuts.h @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define FAN_INPUT_INTERNAL_DIODE 0 +#define FAN_INPUT_TEMP0 1 +#define FAN_INPUT_TEMP1 2 +#define FAN_INPUT_TEMP2 3 +#define FAN_INPUT_TEMP3 4 +#define FAN_INPUT_TEMP0_FILTER 5 +#define FAN_INPUT_ZERO 6 +#define FAN_INPUT_DISABLED 7 + +#define FAN_AUTOMODE (1 << 0) +#define FAN_LINEARMODE (1 << 1) +#define FAN_STEPMODE ~(1 << 1) +#define FAN_POLARITY_HIGH (1 << 2) +#define FAN_POLARITY_LOW ~(1 << 2) + +/* Normally, 4-wire fans runs at 25KHz and 3-wire fans runs at 100Hz */ +#define FREQ_28KHZ 0x0 +#define FREQ_25KHZ 0x1 +#define FREQ_23KHZ 0x2 +#define FREQ_21KHZ 0x3 +#define FREQ_29KHZ 0x4 +#define FREQ_18KHZ 0x5 +#define FREQ_100HZ 0xF7 +#define FREQ_87HZ 0xF8 +#define FREQ_58HZ 0xF9 +#define FREQ_44HZ 0xFA +#define FREQ_35HZ 0xFB +#define FREQ_29HZ 0xFC +#define FREQ_22HZ 0xFD +#define FREQ_14HZ 0xFE +#define FREQ_11HZ 0xFF diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig new file mode 100644 index 0000000000..3d8efb1165 --- /dev/null +++ b/src/mainboard/amd/padmelon/Kconfig @@ -0,0 +1,65 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2018 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_AMD_PADMELON + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_AMD_MERLINFALCON + select BOARD_ROMSIZE_KB_8192 + select DRIVERS_I2C_GENERIC + select DRIVERS_PS2_KEYBOARD + select HAVE_ACPI_TABLES + select GFXUMA + select STONEYRIDGE_LEGACY_FREE + select ONBOARD_VGA_IS_PRIMARY + select BOOTBLOCK_CONSOLE + select SUPERIO_FINTEK_F81803A + select SUPERIO_FINTEK_COMMON_PRE_RAM + select SUPERIO_FINTEK_FAN_CONTROL + select SUPERIO_FINTEK_FAN_API_CALL + select VGA_BIOS + select AZALIA_PLUGIN_SUPPORT + +config MAINBOARD_DIR + string + default amd/padmelon + +config MAINBOARD_PART_NUMBER + string + default "Padmelon" + +config HAVE_S3_SUPPORT + bool + default n + +config MAX_CPUS + int + default 4 + +config IRQ_SLOT_COUNT + int + default 11 + +config HWM_PORT + hex + default 0x0225 + help + HWM base address must be an odd address. Hardware monitor used + addresses are HWM_PORT for index an HWM_PORT + 1 for data. + If changed, make sure fan_init.c IO window setting. The HWM + (Hardware Monitor) is used for fan control within padmelon. + +endif # BOARD_AMD_PADMELON diff --git a/src/mainboard/amd/padmelon/Kconfig.name b/src/mainboard/amd/padmelon/Kconfig.name new file mode 100644 index 0000000000..fb88c3906c --- /dev/null +++ b/src/mainboard/amd/padmelon/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_AMD_PADMELON + bool "Padmelon" diff --git a/src/mainboard/amd/padmelon/Makefile.inc b/src/mainboard/amd/padmelon/Makefile.inc new file mode 100644 index 0000000000..d73c854567 --- /dev/null +++ b/src/mainboard/amd/padmelon/Makefile.inc @@ -0,0 +1,27 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock/OemCustomize.c +bootblock-y += gpio.c + +romstage-y += BiosCallOuts.c +romstage-y += bootblock/OemCustomize.c +romstage-y += OemCustomize.c + +ramstage-y += BiosCallOuts.c +ramstage-y += gpio.c +ramstage-y += OemCustomize.c +ramstage-$(CONFIG_SUPERIO_FINTEK_FAN_API_CALL) += fan_init.c diff --git a/src/mainboard/amd/padmelon/OemCustomize.c b/src/mainboard/amd/padmelon/OemCustomize.c new file mode 100644 index 0000000000..bb92733e1e --- /dev/null +++ b/src/mainboard/amd/padmelon/OemCustomize.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#define DIMMS_PER_CHANNEL 1 +#if DIMMS_PER_CHANNEL > MAX_DIMMS_PER_CH +#error "Too many DIMM sockets defined for the mainboard" +#endif + +static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { + DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, CHANNEL_A, 1), + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, CHANNEL_B, 1), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH), + MOTHER_BOARD_LAYERS(LAYERS_6), + MEMCLK_DIS_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x02, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00), + MEMCLK_DIS_MAP(ANY_SOCKET, CHANNEL_B, 0x01, 0x02, 0x08, 0x04, + 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x02, 0x00, 0x00), + CKE_TRI_MAP(ANY_SOCKET, CHANNEL_B, 0x05, 0x0A, 0x00, 0x00), + ODT_TRI_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x00, 0x02, 0x00), + ODT_TRI_MAP(ANY_SOCKET, CHANNEL_B, 0x01, 0x04, 0x02, 0x08), + CS_TRI_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x02, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00), + CS_TRI_MAP(ANY_SOCKET, CHANNEL_B, 0x01, 0x02, 0x04, 0x08, 0x00, + 0x00, 0x00, 0x00), + PSO_END +}; + +void OemPostParams(AMD_POST_PARAMS *PostParams) +{ + PostParams->MemConfig.PlatformMemoryConfiguration = + (PSO_ENTRY *)DDR4PlatformMemoryConfiguration; + PostParams->MemConfig.CfgUmaAbove4G = TRUE; +} diff --git a/src/mainboard/amd/padmelon/acpi/gpe.asl b/src/mainboard/amd/padmelon/acpi/gpe.asl new file mode 100644 index 0000000000..c7ea19f8f1 --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi/gpe.asl @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L03\n") */ + Notify(\_SB.PWRB, 0x02) /* SIO psin -> NOTIFY_DEVICE_WAKE */ + } + + /* Power Button - PCIe Wake */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + \_SB.SIO0.CPSI() /* clear psin state in sio */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR8, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/amd/padmelon/acpi/mainboard.asl b/src/mainboard/amd/padmelon/acpi/mainboard.asl new file mode 100644 index 0000000000..db5731f088 --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi/mainboard.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +/* Some global data */ +Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ diff --git a/src/mainboard/amd/padmelon/acpi/routing.asl b/src/mainboard/amd/padmelon/acpi/routing.asl new file mode 100644 index 0000000000..64d975e107 --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi/routing.asl @@ -0,0 +1,216 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Routing is in System Bus scope */ +Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + + /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* FCH devices */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 18 Func 0 - USB: EHCI */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 16 Func 0 - USB: xHCI */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, +}) + +Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 43 }, + Package(){0x0001FFFF, 1, 0, 40 }, + + /* Bus 0, Dev 2 - PCIe Bridges */ + Package(){0x0002FFFF, 0, 0, 44 }, + Package(){0x0002FFFF, 1, 0, 45 }, + Package(){0x0002FFFF, 2, 0, 46 }, + Package(){0x0002FFFF, 3, 0, 47 }, + + Package(){0x0003FFFF, 0, 0, 49 }, + Package(){0x0003FFFF, 1, 0, 50 }, + Package(){0x0003FFFF, 2, 0, 51 }, + Package(){0x0003FFFF, 3, 0, 52 }, + + Package(){0x0008FFFF, 0, 0, 35 }, + Package(){0x0008FFFF, 1, 0, 32 }, + Package(){0x0008FFFF, 2, 0, 33 }, + Package(){0x0008FFFF, 3, 0, 34 }, + + /* SB devices in APIC mode */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ + /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 18}, + Package(){0x0010FFFF, 1, 0, 17}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* Bus 0, Dev 9, Func 2 - HDAudio */ + Package(){0x0009FFFF, 0, 0, 46 }, + Package(){0x0009FFFF, 1, 0, 47 }, + Package(){0x0009FFFF, 2, 0, 44 }, + Package(){0x0009FFFF, 3, 0, 45 }, +}) + +Name(PS4, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 24 }, + Package(){0x0000FFFF, 1, 0, 25 }, + Package(){0x0000FFFF, 2, 0, 26 }, + Package(){0x0000FFFF, 3, 0, 27 }, +}) + +/* GPP 1 */ +Name(PS5, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS5, Package(){ + Package(){0x0000FFFF, 0, 0, 32 }, + Package(){0x0000FFFF, 1, 0, 33 }, + Package(){0x0000FFFF, 2, 0, 34 }, + Package(){0x0000FFFF, 3, 0, 35 }, +}) + +/* GPP 2 */ +Name(PS6, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS6, Package(){ + Package(){0x0000FFFF, 0, 0, 40 }, + Package(){0x0000FFFF, 1, 0, 41 }, + Package(){0x0000FFFF, 2, 0, 42 }, + Package(){0x0000FFFF, 3, 0, 43 }, +}) + +/* GPP 3 */ +Name(PS7, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS7, Package(){ + Package(){0x0000FFFF, 0, 0, 48 }, + Package(){0x0000FFFF, 1, 0, 49 }, + Package(){0x0000FFFF, 2, 0, 50 }, + Package(){0x0000FFFF, 3, 0, 51 }, +}) + +/* GPP 4 */ +Name(PS8, Package(){ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, +}) +Name(APS8, Package(){ + Package(){0x0000FFFF, 0, 0, 27 }, + Package(){0x0000FFFF, 1, 0, 28 }, + Package(){0x0000FFFF, 2, 0, 28 }, + Package(){0x0000FFFF, 3, 0, 30 }, +}) + +/* GFX 2 */ +Name(PSA, Package(){ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, +}) +Name(APSA, Package(){ + Package(){0x0000FFFF, 0, 0, 51 }, + Package(){0x0000FFFF, 1, 0, 48 }, + Package(){0x0000FFFF, 2, 0, 49 }, + Package(){0x0000FFFF, 3, 0, 50 }, +}) + +/* GFX 3 */ +Name(PSB, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APSB, Package(){ + Package(){0x0000FFFF, 0, 0, 26 }, + Package(){0x0000FFFF, 1, 0, 27 }, + Package(){0x0000FFFF, 2, 0, 24 }, + Package(){0x0000FFFF, 3, 0, 25 }, +}) + +/* GFX 4 */ +Name(PSC, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APSC, Package(){ + Package(){0x0000FFFF, 0, 0, 34 }, + Package(){0x0000FFFF, 1, 0, 35 }, + Package(){0x0000FFFF, 2, 0, 32 }, + Package(){0x0000FFFF, 3, 0, 33 }, +}) diff --git a/src/mainboard/amd/padmelon/acpi/sleep.asl b/src/mainboard/amd/padmelon/acpi/sleep.asl new file mode 100644 index 0000000000..58f0752f30 --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi/sleep.asl @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear wake status structure. */ + Store(0, PEWD) + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + Store(7, UPWS) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/amd/padmelon/acpi/usb_oc.asl b/src/mainboard/amd/padmelon/acpi/usb_oc.asl new file mode 100644 index 0000000000..bd98ed26c9 --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi/usb_oc.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) diff --git a/src/mainboard/amd/padmelon/acpi_tables.c b/src/mainboard/amd/padmelon/acpi_tables.c new file mode 100644 index 0000000000..e06f6a648d --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi_tables.c @@ -0,0 +1,3 @@ +/* + * Blank file required by build system assumptions of this file being present. + */ diff --git a/src/mainboard/amd/padmelon/board_info.txt b/src/mainboard/amd/padmelon/board_info.txt new file mode 100644 index 0000000000..4bca78cd84 --- /dev/null +++ b/src/mainboard/amd/padmelon/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: AMD +Board name: Padmelon +Category: desktop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: dediprog header diff --git a/src/mainboard/amd/padmelon/bootblock/OemCustomize.c b/src/mainboard/amd/padmelon/bootblock/OemCustomize.c new file mode 100644 index 0000000000..02f83cc1bd --- /dev/null +++ b/src/mainboard/amd/padmelon/bootblock/OemCustomize.c @@ -0,0 +1,159 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +static const PCIe_PORT_DESCRIPTOR PortList[] = { + /* + * Init Port descriptor (PCIe port, Lanes 8-15, + * PCI Device Number 3, ...) + */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 15), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, + 3, 1, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x02, 0) + }, + + /* + * Initialize Port descriptor (PCIe port, Lane 7, + * PCI Device Number 2, ...) + */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, + 2, 5, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x03, 0) + }, + /* + * Initialize Port descriptor (PCIe port, Lane 6, + * PCI Device Number 2, ...) + */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, + 2, 4, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x04, 0) + }, + /* + * Initialize Port descriptor (PCIe port, Lane 5, + * PCI Device Number 2, ...) + */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db, + 2, 3, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x04, 0) + }, + /* + * Initialize Port descriptor (PCIe port, Lane4, + * PCI Device Number 2, ...) + */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, + 2, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x06, 0) + }, + /* + * Initialize Port descriptor (PCIe port, Lanes 0-3, + * PCI Device Number 2, ...) + */ + { + /* + * Descriptor flags !!!IMPORTANT!!! Terminate last element + * of array + */ + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db, + 2, 1, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x07, 0) + }, + +}; + + +static const PCIe_DDI_DESCRIPTOR DdiList[] = { + /* DP0 */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) + }, + /* DP1 */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 20, 23), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) + }, + /* DP2 */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3) + }, +}; + +static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = (void *)PortList, + .DdiLinkList = (void *)DdiList +}; + +/*---------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This is the stub function will call the host environment through the + * binary block interface (call-out port) to provide a user hook opportunity. + * + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------*/ +VOID OemCustomizeInitEarly(AMD_EARLY_PARAMS *InitEarly) +{ + InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex; +} diff --git a/src/mainboard/amd/padmelon/bootblock/bootblock.c b/src/mainboard/amd/padmelon/bootblock/bootblock.c new file mode 100644 index 0000000000..864928732c --- /dev/null +++ b/src/mainboard/amd/padmelon/bootblock/bootblock.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017-2018 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "../gpio.h" + +/* Enable IO access to port, then enable UART HW control pins */ +static void enable_serial(unsigned int base_port, unsigned int io_enable) +{ + u32 temp; + u8 reg; + temp = pci_read_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE); + temp |= io_enable; + pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, temp); + + /* + * Remove this section if HW handshake is not needed. This is needed + * only for those who don't have a modified serial cable (connecting + * DCD to DTR and DSR, plus connecting RTS to CTS). When you buy cables + * on any store, they don't have these modification. + */ + reg = inb(base_port + UART8250_MCR); + reg |= UART8250_MCR_DTR | UART8250_MCR_RTS; + outb(reg, base_port + UART8250_MCR); +} + +void bootblock_mainboard_early_init(void) +{ + sb_clk_output_48Mhz(2); + /* + * UARTs enabled by default at reset, just need RTS, CTS + * and access to the IO address. + */ + enable_serial(0x03f8, DECODE_ENABLE_SERIAL_PORT0); + enable_serial(0x02f8, DECODE_ENABLE_SERIAL_PORT1); +} + +void bootblock_mainboard_init(void) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + + gpios = early_gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); +} diff --git a/src/mainboard/amd/padmelon/devicetree.cb b/src/mainboard/amd/padmelon/devicetree.cb new file mode 100644 index 0000000000..9baee2f2cf --- /dev/null +++ b/src/mainboard/amd/padmelon/devicetree.cb @@ -0,0 +1,84 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip soc/amd/stoneyridge + + register "spd_addr_lookup" = " + { +#if CONFIG(HAVE_MERLINFALCON_BINARIES) + { {0xA0, 0x00}, {0xA4, 0x00} }, // socket 0 - Channel 0 & 1, slot 0 +#else + { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 +#endif + }" + + register "uma_mode" = "UMAMODE_AUTO_LEGACY" + + device cpu_cluster 0 on + device lapic 10 on end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9874 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # mini PCIe slot x1 + device pci 2.3 on end # LAN RTL8111F + device pci 2.4 on end # LAN RTL8111F + device pci 3.0 on end # GFX host bridge + device pci 8.0 on end # PSP + device pci 9.0 on end # HDA + device pci 9.2 on end # HDA + device pci 10.0 on end # USB xHCI + device pci 11.0 on end # SATA + device pci 12.0 on end # USB EHCI + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + end # SM + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81803a + device pnp 4e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.2 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.4 on # HWM + io 0x60 = 0x220 + irq 0x70 = 0 + end + device pnp 4e.5 off end # KBC + device pnp 4e.6 off end # GPIO + device pnp 4e.7 off end # WDT + device pnp 4e.a off end # PME + end # f81803a + end # LPC + device pci 14.7 on end # SD + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + end #domain +end #soc/amd/stoneyridge diff --git a/src/mainboard/amd/padmelon/dsdt.asl b/src/mainboard/amd/padmelon/dsdt.asl new file mode 100644 index 0000000000..493c4acd78 --- /dev/null +++ b/src/mainboard/amd/padmelon/dsdt.asl @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* DefinitionBlock Statement */ +#include +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include */ /* as needed */ + + /* global NVS and variables */ + #include + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include + + /* Describe the processor tree (\_PR) */ + #include + + /* Contains the supported sleep states for this chipset */ + #include + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include + + /* IRQ Routing mapping for this platform (in \_SB scope) */ + #include "acpi/routing.asl" + + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + + /* Describe the SOC */ + #include + + /* Describe the Fintek F81803A SIO */ + #define SUPERIO_DEV SIO0 + #define SUPERIO_PNP_BASE 0x4E + #define F81803A_SHOW_UARTA + #define F81803A_SHOW_PME + #include + + } /* End \_SB scope */ + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" +} +/* End of ASL file */ diff --git a/src/mainboard/amd/padmelon/fan_init.c b/src/mainboard/amd/padmelon/fan_init.c new file mode 100644 index 0000000000..2c3200525d --- /dev/null +++ b/src/mainboard/amd/padmelon/fan_init.c @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Richard Spiegel + * Copyright (C) 2019 Silverback ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#define CPU_FAN 1 +#define SYSTEM_FAN 2 + +/* Boundaries in celsius, sections in percent */ +static u8 cpu_boudaries[FINTEK_BOUNDARIES_SIZE] = { + 80, + 65, + 50, + 35 +}; + +static u8 system_boudaries[FINTEK_BOUNDARIES_SIZE] = { + 70, + 55, + 40, + 25 +}; + +static u8 cpu_section[FINTEK_SECTIONS_SIZE] = { + 100, + 85, + 70, + 55, + 40 +}; + +static u8 system_section[FINTEK_SECTIONS_SIZE] = { + 100, + 85, + 70, + 55, + 40 +}; + +struct fintek_fan cpu_fan = { + CPU_FAN, + IGNORE_SENSOR, + TEMP_SENSOR_DEFAULT, + FAN_TEMP_TSI, + FAN_TYPE_PWM_PUSH_PULL, + FAN_MODE_DEFAULT, + FAN_PWM_FREQ_23500, + FAN_UP_RATE_10HZ, + FAN_DOWN_RATE_10HZ, + FAN_FOLLOW_INTERPOLATION, + cpu_boudaries, + cpu_section +}; + +struct fintek_fan system_fan = { + SYSTEM_FAN, + EXTERNAL_SENSOR2, + TEMP_SENSOR_BJT, + FAN_TEMP_EXTERNAL_2, + FAN_TYPE_DAC_POWER, + FAN_MODE_DEFAULT, + FAN_PWM_FREQ_23500, + FAN_UP_RATE_10HZ, + FAN_DOWN_RATE_10HZ, + FAN_FOLLOW_INTERPOLATION, + system_boudaries, + system_section +}; + +static void init_fan_control(void *unused) +{ + u32 temp; + /* Open a LPC IO access to 0x0220-0x0227 */ + temp = pci_read_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE); + temp |= DECODE_ENABLE_SERIAL_PORT2; + pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, temp); + + set_fan(&cpu_fan); + set_fan(&system_fan); +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, init_fan_control, NULL); diff --git a/src/mainboard/amd/padmelon/gpio.c b/src/mainboard/amd/padmelon/gpio.c new file mode 100644 index 0000000000..e738618924 --- /dev/null +++ b/src/mainboard/amd/padmelon/gpio.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include "gpio.h" + +/* + * As a rule of thumb, GPIO pins used by coreboot should be initialized at + * bootblock while GPIO pins used only by the OS should be initialized at + * ramstage. + */ +static const struct soc_amd_gpio gpio_set_stage_reset[] = { + /* GFX presense detect */ + PAD_GPI(GPIO_9, PULL_DOWN), + /* VDDP_VCTRL */ + PAD_GPO(GPIO_40, HIGH), + /* PC SPKR */ + PAD_NF(GPIO_91, SPKR, PULL_NONE), +}; + +static const struct soc_amd_gpio gpio_set_stage_ram[] = { +#if CONFIG(HAVE_S3_SUPPORT) + /* PCIE_WAKE - default, do not program */ + + /* DEVSLP1 */ + PAD_NF(GPIO_70, DEVSLP1, PULL_UP), + /* WLAND */ + PAD_SCI(GPIO_137, PULL_UP, LEVEL_LOW), + PAD_WAKE(GPIO_137, PULL_UP, LEVEL_LOW, S3), +#else + /* PCIE_WAKE */ + PAD_GPI(GPIO_2, PULL_DOWN), + /* DEVSLP1 - default as GPIO, do not program */ + + /* WLAND - default as GPIO, do not program */ + +#endif /* HAVE_S3_SUPPORT */ + /* BLINK - reselect GPIO OUTPUT HIGH to force BLINK */ + PAD_GPO(GPIO_11, HIGH), +}; + +const struct soc_amd_gpio *early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_reset); + return gpio_set_stage_reset; +} + +const struct soc_amd_gpio *gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_ram); + return gpio_set_stage_ram; +} diff --git a/src/mainboard/amd/padmelon/gpio.h b/src/mainboard/amd/padmelon/gpio.h new file mode 100644 index 0000000000..b448d3c733 --- /dev/null +++ b/src/mainboard/amd/padmelon/gpio.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +const struct soc_amd_gpio *early_gpio_table(size_t *size); +const struct soc_amd_gpio *gpio_table(size_t *size); + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/amd/padmelon/hda_verb.c b/src/mainboard/amd/padmelon/hda_verb.c new file mode 100644 index 0000000000..23d566de96 --- /dev/null +++ b/src/mainboard/amd/padmelon/hda_verb.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + /* Realtek ALC662 rev1 */ + 0x10ec0662, /* Vendor ID */ + 0x80865756, /* Subsystem ID */ + 10, /* Number of entries */ + + /* Pin Widget Verb Table */ + + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c50), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x593301f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(0, 0x1e, 0x01441130), +}; + +const u32 pc_beep_verbs[0] = {}; + +const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs); +const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data); diff --git a/src/mainboard/amd/padmelon/mainboard.c b/src/mainboard/amd/padmelon/mainboard.c new file mode 100644 index 0000000000..e106b4a170 --- /dev/null +++ b/src/mainboard/amd/padmelon/mainboard.c @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "gpio.h" + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + * + * These values are used by the PCI configuration space, + * MP Tables. + */ +const u8 mainboard_picr_data[] = { + [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, + [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + [0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, + [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, + [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, + [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x40] = 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, + [0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + [0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + [0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, + [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, +}; + +const u8 mainboard_intr_data[] = { + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10, + [0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, + [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, + [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, + [0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, + [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +/* + * This table defines the index into the picr/intr_data tables for each + * device. Any enabled device and slot that uses hardware interrupts should + * have an entry in this table to define its index into the FCH PCI_INTR + * register 0xC00/0xC01. This index will define the interrupt that it should + * use. Putting PIRQ_A into the PIN A index for a device will tell that + * device to use PIC IRQ 10 if it uses PIN A for its hardware INT. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + { GFX_DEVFN, { PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { HDA0_DEVFN, { PIRQ_NC, PIRQ_HDA, PIRQ_NC, PIRQ_NC } }, + { PCIE0_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE1_DEVFN, { PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A } }, + { PCIE2_DEVFN, { PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B } }, + { PCIE3_DEVFN, { PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C } }, + { PCIE4_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PSP_DEVFN, { PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { HDA1_DEVFN, { PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { SD_DEVFN, { PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { SMBUS_DEVFN, { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { SATA_DEVFN, { PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { EHCI1_DEVFN, { PIRQ_EHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { XHCI_DEVFN, { PIRQ_XHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +static void mainboard_init(void *chip_info) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + gpios = gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); +} + +/************************************************* + * enable the dedicated function in padmelon board. + *************************************************/ +static void padmelon_enable(struct device *dev) +{ + printk(BIOS_INFO, "Mainboard " + CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = padmelon_enable, +}; diff --git a/src/mainboard/amd/padmelon/romstage.c b/src/mainboard/amd/padmelon/romstage.c new file mode 100644 index 0000000000..68bf0e8133 --- /dev/null +++ b/src/mainboard/amd/padmelon/romstage.c @@ -0,0 +1,4 @@ +/* + * This is a placeholder, if there ever is something platform specific to + * add to romstage, do it here. + */ diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c index e1f2409504..82670bd586 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c @@ -37,6 +37,9 @@ static u32 get_hcid(u32 i) dev = dev_find_slot(busn, PCI_DEVFN(devn,0)); + if (dev == NULL) + die("ERROR - could not find PCI %02x:%02x.0\n", busn, PCI_DEVFN(devn, 0)); + switch (dev->device) { case 0x7458: /* 8132 */ id = 1; diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 2929c0dc58..7f66fc5aea 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include @@ -26,7 +26,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { static const struct mem_controller memctrl[] = { { diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c index 798fc12caf..0423837736 100644 --- a/src/mainboard/apple/macbook21/mainboard.c +++ b/src/mainboard/apple/macbook21/mainboard.c @@ -17,8 +17,6 @@ #include #include -#include -#include #include #include #include diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 1c84c8432b..32a7871ecf 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -15,16 +15,13 @@ * GNU General Public License for more details. */ -/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ - #include #include #include #include -#include +#include #include #include -#include #include #include #include @@ -225,22 +222,18 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 }; - if (bist == 0) - enable_lapic(); + enable_lapic(); ich7_enable_lpc(); /* Set up the console */ console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "Soft reset detected, rebooting properly.\n"); diff --git a/src/mainboard/apple/macbookair4_2/gma-mainboard.ads b/src/mainboard/apple/macbookair4_2/gma-mainboard.ads index d4a5d7d990..e45320f36e 100644 --- a/src/mainboard/apple/macbookair4_2/gma-mainboard.ads +++ b/src/mainboard/apple/macbookair4_2/gma-mainboard.ads @@ -28,7 +28,6 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal, - others => Disabled); + Internal); end GMA.Mainboard; diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index de73d016d3..0228499181 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -18,8 +18,7 @@ #include #include #include -#include -#include +#include #include #include #include @@ -82,7 +81,7 @@ static void ich7_enable_lpc(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0291); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; @@ -95,7 +94,6 @@ void mainboard_romstage_entry(unsigned long bist) console_init(); - report_bist_failure(bist); enable_smbus(); x4x_early_init(); diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 3067ffe53c..572cd6ab52 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -33,6 +33,9 @@ chip soc/intel/skylake register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" + # Set @0x280-0x2ff I/O Range for SuperIO HWM + register "gen1_dec" = "0x007c0281" + # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" @@ -89,64 +92,63 @@ chip soc/intel/skylake #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | #| ImonSlope | 0 | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | + #| IccMax* | 0 | 0 | 0 | 0 | 0 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | #+----------------+-------+-------+-------------+-------------+-------+ + # * - is set automatically for the KBL-S/KBL-DT CPUs in the vr_config.c register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x10, \ - .psi3threshold = 0x4, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(4), \ + .psi3threshold = VR_CFG_AMP(1), \ .psi3enable = 1, \ .psi4enable = 1, \ .imon_slope = 0x0, \ .imon_offset = 0x0, \ .icc_max = 0x0, \ - .voltage_limit = 0x0 \ + .voltage_limit = 1520 \ }" register "domain_vr_config[VR_IA_CORE]" = "{ .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ .psi3enable = 1, \ .psi4enable = 1, \ .imon_slope = 0x0, \ .imon_offset = 0x0, \ .icc_max = 0x0, \ - .voltage_limit = 0x0 \ + .voltage_limit = 1520 \ }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ .psi3enable = 1, \ .psi4enable = 1, \ .imon_slope = 0x0, \ .imon_offset = 0x0, \ .icc_max = 0x0 ,\ - .voltage_limit = 0x0 \ + .voltage_limit = 1520 \ }" register "domain_vr_config[VR_GT_SLICED]" = "{ .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ .psi3enable = 1, \ .psi4enable = 1, \ .imon_slope = 0x0, \ .imon_offset = 0x0, \ .icc_max = 0x0, \ - .voltage_limit = 0x0 \ + .voltage_limit = 1520 \ }" register "EnableLan" = "0" - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V - register "PmTimerDisabled" = "0" # USB @@ -183,21 +185,23 @@ chip soc/intel/skylake [1] = 1, \ [2] = 1, \ [3] = 1, \ - [4] = 1, \ - [5] = 1, \ - [6] = 1, \ - [7] = 1, \ + [4] = 0, \ + [5] = 0, \ + [6] = 0, \ + [7] = 0, \ }" + # SATA4 and SATA5 are located in the lower right corner + # of the board, but there is no connector for this # PCH UART, SPI, I2C register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoPci, \ - [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi0] = PchSerialIoPci, \ + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ @@ -274,6 +278,8 @@ chip soc/intel/skylake device pci 02.0 on # Integrated Graphics Device subsystemid 0x1849 0x1912 end + device pci 04.0 on end # Thermal Subsystem + device pci 08.0 off end # Gaussian Mixture Model device pci 14.0 on # USB xHCI subsystemid 0x1849 0xa131 end @@ -321,12 +327,22 @@ chip soc/intel/skylake subsystemid 0x1849 0x1a43 chip superio/nuvoton/nct6791d device pnp 2e.0 off end # Floppy - device pnp 2e.1 on # Parallel - # global - irq 0x1c = 0x10 + device pnp 2e.1 on + # Global Control Registers + # Device IRQ Polarity + irq 0x13 = 0x00 + irq 0x14 = 0x00 + # Global Option + irq 0x24 = 0xfb irq 0x27 = 0x10 - irq 0x2a = 0x64 - # parallel port + # Multi Function + irq 0x1a = 0xb0 + irq 0x1b = 0xe6 + irq 0x2a = 0x04 + irq 0x2c = 0x40 + irq 0x2d = 0x03 + + # Parallel Port io 0x60 = 0x0378 irq 0x70 = 7 drq 0x74 = 4 # No DMA @@ -347,19 +363,46 @@ chip soc/intel/skylake irq 0x72 = 12 # Mouse end device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GPIO6 - device pnp 2e.107 off end # GPIO7 - device pnp 2e.207 off end # GPIO8 + device pnp 2e.7 on # GPIO6 + irq 0xf6 = 0xff + irq 0xf7 = 0xff + irq 0xf8 = 0xff + end + device pnp 2e.107 on # GPIO7 + irq 0xe0 = 0x7f + irq 0xe1 = 0x0d + end + device pnp 2e.207 on # GPIO8 + irq 0xe6 = 0xff + irq 0xe7 = 0xff + irq 0xed = 0xff + end device pnp 2e.8 off end # WDT - device pnp 2e.108 off end # GPIO0 + device pnp 2e.108 on end # GPIO0 device pnp 2e.308 off end # GPIO base device pnp 2e.408 off end # WDTMEM - device pnp 2e.708 off end # GPIO1 - device pnp 2e.9 off end # GPIO2 - device pnp 2e.109 off end # GPIO3 - device pnp 2e.209 off end # GPIO4 - device pnp 2e.309 off end # GPIO5 - device pnp 2e.a off end # ACPI + device pnp 2e.708 on end # GPIO1 + device pnp 2e.9 on end # GPIO2 + device pnp 2e.109 on # GPIO3 + irq 0xe4 = 0x7b + irq 0xe5 = 0x02 + irq 0xea = 0x04 + end + device pnp 2e.209 on # GPIO4 + irq 0xf0 = 0x7f + irq 0xf1 = 0x80 + end + device pnp 2e.309 on # GPIO5 + irq 0xf4 = 0xdf + irq 0xf5 = 0xd5 + end + device pnp 2e.a on + # Power RAM in S3 and let the PCH + # handle power failure actions + irq 0xe4 = 0x70 + # Set HWM reset source to LRESET# + irq 0xe7 = 0x01 + end # ACPI device pnp 2e.b on # HWM, LED io 0x60 = 0x0290 io 0x62 = 0 diff --git a/src/mainboard/asrock/h110m/include/gpio.h b/src/mainboard/asrock/h110m/include/gpio.h index 4ae99119f0..0b330782c7 100644 --- a/src/mainboard/asrock/h110m/include/gpio.h +++ b/src/mainboard/asrock/h110m/include/gpio.h @@ -13,260 +13,496 @@ * GNU General Public License for more details. */ -#ifndef _GPIO_DVS_H -#define _GPIO_DVS_H +#ifndef _PCH_GPIO_H +#define _PCH_GPIO_H #include #include -#define H110_PAD_DW0_DW1_CFG(val, config0, config1) \ - _PAD_CFG_STRUCT(val, config0, config1) - -/* Pad configuration in ramstage. */ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { - /* GPIO Group GPP_A */ - H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ - H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ - H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ - H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ - H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ - H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ - H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ - H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ - H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ - H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ - H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN# */ - H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ - H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ - H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */ - /* GPIO Group GPP_B */ - H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B4, 0x84000502, 0x00000034), /* CPU_GP3 */ - H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B12, 0x44000600, 0x0000003c), /* SLP_S0# */ - H110_PAD_DW0_DW1_CFG(GPP_B13, 0x44000600, 0x0000003d), /* PLTRST# */ - H110_PAD_DW0_DW1_CFG(GPP_B14, 0x84000600, 0x0000103e), /* SPKR */ - H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B23, 0x84000a01, 0x00001047), /* PCHHOT# */ - /* GPIO Group GPP_C */ - H110_PAD_DW0_DW1_CFG(GPP_C0, 0x44000502, 0x00000048), /* SMBCLK */ - H110_PAD_DW0_DW1_CFG(GPP_C1, 0x44000502, 0x00000049), /* SMBDATA */ - H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C3, 0x44000502, 0x0000004b), /* SML0CLK */ - H110_PAD_DW0_DW1_CFG(GPP_C4, 0x44000502, 0x0000004c), /* SML0DATA */ - H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ + /* ------- GPIO Group GPP_A ------- */ + /* GPP_A0 - RCIN# */ + PAD_CFG_NF_BUF_TRIG(GPP_A0, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_A1 - LAD0 */ + PAD_CFG_NF_BUF_TRIG(GPP_A1, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A2 - LAD1 */ + PAD_CFG_NF_BUF_TRIG(GPP_A2, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A3 - LAD2 */ + PAD_CFG_NF_BUF_TRIG(GPP_A3, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A4 - LAD3 */ + PAD_CFG_NF_BUF_TRIG(GPP_A4, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A5 - LFRAME# */ + PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_A6 - SERIRQ */ + PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A7 - GPIO */ + PAD_CFG_GPI_INT(GPP_A7, NONE, PLTRST, OFF), + /* GPP_A8 - CLKRUN# */ + PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_A9 - CLKOUT_LPC0 */ + PAD_CFG_NF_BUF_TRIG(GPP_A9, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_A10 - CLKOUT_LPC1 */ + PAD_CFG_NF_BUF_TRIG(GPP_A10, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_A11 - GPIO */ + PAD_CFG_GPI_INT(GPP_A11, NONE, PLTRST, OFF), + /* GPP_A12 - GPIO */ + PAD_CFG_GPI_INT(GPP_A12, NONE, PLTRST, OFF), + /* GPP_A13 - SUSWARN#/SUSPWRDNACK */ + PAD_CFG_NF_BUF_TRIG(GPP_A13, NONE, DEEP, NF1, RX_DISABLE, OFF), + /* GPP_A14 - SUS_STAT# */ + PAD_CFG_NF_BUF_TRIG(GPP_A14, NONE, DEEP, NF1, RX_DISABLE, OFF), + /* GPP_A15 - SUS_ACK# */ + PAD_CFG_NF_BUF_TRIG(GPP_A15, 20K_PU, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_A16 - GPIO */ + PAD_CFG_GPI_INT(GPP_A16, NONE, PLTRST, OFF), + /* GPP_A17 - GPIO */ + PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, OFF), + /* GPP_A18 - GPIO */ + PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF), + /* GPP_A19 - GPIO */ + PAD_CFG_GPI_INT(GPP_A19, NONE, PLTRST, OFF), + /* GPP_A20 - GPIO */ + PAD_CFG_GPI_INT(GPP_A20, NONE, PLTRST, OFF), + /* GPP_A21 - GPIO */ + PAD_CFG_GPI_INT(GPP_A21, NONE, PLTRST, OFF), + /* GPP_A22 - GPIO */ + PAD_CFG_GPI_INT(GPP_A22, NONE, PLTRST, OFF), + /* GPP_A23 - GPIO */ + PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, OFF), + + /* ------- GPIO Group GPP_B ------- */ + /* GPP_B0 - GPIO */ + PAD_CFG_GPI_INT(GPP_B0, NONE, PLTRST, OFF), + /* GPP_B1 - GPIO */ + PAD_CFG_GPI_INT(GPP_B1, NONE, PLTRST, OFF), + /* GPP_B2 - GPIO */ + PAD_CFG_GPI_INT(GPP_B2, NONE, PLTRST, OFF), + /* GPP_B3 - GPIO */ + PAD_CFG_GPO(GPP_B3, 1, DEEP), + /* GPP_B4 - CPU_GP3 */ + PAD_CFG_NF_BUF_TRIG(GPP_B4, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_B5 - GPIO */ + PAD_CFG_GPI_INT(GPP_B5, NONE, PLTRST, OFF), + /* GPP_B6 - GPIO */ + PAD_CFG_GPI_INT(GPP_B6, NONE, PLTRST, OFF), + /* GPP_B7 - NC */ + PAD_NC(GPP_B7, NONE), + /* GPP_B8 - GPIO */ + PAD_CFG_GPI_INT(GPP_B8, 5K_PU, PLTRST, OFF), + /* GPP_B9 - GPIO */ + PAD_CFG_GPI_INT(GPP_B9, NONE, PLTRST, OFF), + /* GPP_B10 - GPIO */ + PAD_CFG_GPI_INT(GPP_B10, NONE, PLTRST, OFF), + /* GPP_B11 - GPIO */ + _PAD_CFG_STRUCT(GPP_B11, + PAD_FUNC(GPIO) | PAD_RESET(PWROK) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | + PAD_BUF(NO_DISABLE), + PAD_PULL(NONE)), + /* GPP_B12 - SLP_S0# */ + PAD_CFG_NF_BUF_TRIG(GPP_B12, NONE, DEEP, NF1, RX_DISABLE, OFF), + /* GPP_B13 - PLTRST# */ + PAD_CFG_NF_BUF_TRIG(GPP_B13, NONE, DEEP, NF1, RX_DISABLE, OFF), + /* GPP_B14 - SPKR */ + PAD_CFG_NF_BUF_TRIG(GPP_B14, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_B15 - GPIO */ + PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, OFF), + /* GPP_B16 - GPIO */ + PAD_CFG_GPI_INT(GPP_B16, NONE, PLTRST, OFF), + /* GPP_B17 - GPIO */ + PAD_CFG_GPO(GPP_B17, 1, DEEP), + /* GPP_B18 - GPIO */ + PAD_CFG_GPI_INT(GPP_B18, NONE, PLTRST, OFF), + /* GPP_B19 - GPIO */ + PAD_CFG_GPI_INT(GPP_B19, NONE, PLTRST, OFF), + /* GPP_B20 - GPIO */ + PAD_CFG_GPI_INT(GPP_B20, NONE, PLTRST, OFF), + /* GPP_B21 - GPIO */ + PAD_CFG_GPI_INT(GPP_B21, NONE, PLTRST, OFF), + /* GPP_B22 - GPIO */ + PAD_CFG_GPI_INT(GPP_B22, NONE, PLTRST, OFF), + /* GPP_B23 - PCHHOT# */ + _PAD_CFG_STRUCT(GPP_B23, + PAD_FUNC(NF2) | PAD_RESET(PLTRST) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | + PAD_BUF(RX_DISABLE) | 1, + PAD_PULL(20K_PD)), + + /* ------- GPIO Group GPP_C ------- */ + /* GPP_C0 - SMBCLK */ + PAD_CFG_NF_BUF_TRIG(GPP_C0, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_C1 - SMBDATA */ + PAD_CFG_NF_BUF_TRIG(GPP_C1, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_C2 - GPIO */ + PAD_CFG_GPO(GPP_C2, 1, DEEP), + /* GPP_C3 - SML0CLK */ + PAD_CFG_NF_BUF_TRIG(GPP_C3, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_C4 - SML0DATA */ + PAD_CFG_NF_BUF_TRIG(GPP_C4, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_C5 - GPIO */ + PAD_CFG_GPI_INT(GPP_C5, NONE, PLTRST, OFF), /* GPP_C6 - RESERVED */ /* GPP_C7 - RESERVED */ - H110_PAD_DW0_DW1_CFG(GPP_C8, 0x84000502, 0x00000050), /* UART0_RXD */ - H110_PAD_DW0_DW1_CFG(GPP_C9, 0x84000600, 0x00000051), /* UART0_TXD */ - H110_PAD_DW0_DW1_CFG(GPP_C10, 0x84000600, 0x00000052), /* UART0_RTS# */ - H110_PAD_DW0_DW1_CFG(GPP_C11, 0x84000502, 0x00000053), /* UART0_CTS# */ - H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C20, 0x84000502, 0x0000005c), /* UART2_RXD */ - H110_PAD_DW0_DW1_CFG(GPP_C21, 0x84000600, 0x0000005d), /* UART2_TXD */ - H110_PAD_DW0_DW1_CFG(GPP_C22, 0x84000600, 0x0000005e), /* UART2_RTS# */ - H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */ - /* GPIO Group GPP_D */ - H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D5, 0x84000402, 0x00000065), /* I2S_SFRM */ - H110_PAD_DW0_DW1_CFG(GPP_D6, 0x84000600, 0x00000066), /* I2S_TXD */ - H110_PAD_DW0_DW1_CFG(GPP_D7, 0x84000502, 0x00000067), /* I2S_RXD */ - H110_PAD_DW0_DW1_CFG(GPP_D8, 0x84000402, 0x00000068), /* I2S_SCLK */ - H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D19, 0x84000500, 0x00003073), /* DMIC_CLK0 */ - H110_PAD_DW0_DW1_CFG(GPP_D20, 0x84000500, 0x00003074), /* DMIC_DATA0 */ - H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */ - /* GPIO Group GPP_E */ - H110_PAD_DW0_DW1_CFG(GPP_E0, 0x84000502, 0x00003018), /* SATAXPCIE0 */ - H110_PAD_DW0_DW1_CFG(GPP_E1, 0x84000502, 0x00003019), /* SATAXPCIE1 */ - H110_PAD_DW0_DW1_CFG(GPP_E2, 0x84000502, 0x0000301a), /* SATAXPCIE2 */ - H110_PAD_DW0_DW1_CFG(GPP_E3, 0x84000500, 0x0000001b), /* CPU_GP0 */ - /* SATA_DEVSLP0 */ - H110_PAD_DW0_DW1_CFG(GPP_E4, 0x84000500, 0x0000001c), - /* SATA_DEVSLP1 */ - H110_PAD_DW0_DW1_CFG(GPP_E5, 0x84000500, 0x0000001d), - /* SATA_DEVSLP2 */ - H110_PAD_DW0_DW1_CFG(GPP_E6, 0x84000500, 0x0000001e), - H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_E8, 0x84000600, 0x00000020), /* SATA_LED# */ - H110_PAD_DW0_DW1_CFG(GPP_E9, 0x44000502, 0x00000021), /* USB_OC0# */ - H110_PAD_DW0_DW1_CFG(GPP_E10, 0x44000502, 0x00000022), /* USB_OC1# */ - H110_PAD_DW0_DW1_CFG(GPP_E11, 0x44000502, 0x00000023), /* USB_OC2# */ - H110_PAD_DW0_DW1_CFG(GPP_E12, 0x44000502, 0x00000024), /* USB_OC3# */ - /* GPIO Group GPP_F */ - H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F1, 0x84000502, 0x00003026), /* SATAXPCIE4 */ - H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F15, 0x44000502, 0x00000034), /* USB_OC4# */ - H110_PAD_DW0_DW1_CFG(GPP_F16, 0x44000502, 0x00000035), /* USB_OC5# */ - H110_PAD_DW0_DW1_CFG(GPP_F17, 0x44000502, 0x00000036), /* USB_OC6# */ - H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */ - /* GPIO Group GPP_G */ - H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G19, 0x84000500, 0x00000050), /* SMI# */ - H110_PAD_DW0_DW1_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */ - /* GPIO Group GPP_H */ - H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */ - /* GPIO Group GPD */ - H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPD2, 0x00000602, 0x00003c1a), /* LAN_WAKE# */ - H110_PAD_DW0_DW1_CFG(GPD3, 0x04000502, 0x0000301b), /* PWRBTN# */ - H110_PAD_DW0_DW1_CFG(GPD4, 0x04000600, 0x0000001c), /* SLP_S3# */ - H110_PAD_DW0_DW1_CFG(GPD5, 0x04000600, 0x0000001d), /* SLP_S4# */ - H110_PAD_DW0_DW1_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPD8, 0x04000600, 0x00000020), /* SUSCLK */ - H110_PAD_DW0_DW1_CFG(GPD9, 0x04000600, 0x00000021), /* SLP_WLAN# */ - H110_PAD_DW0_DW1_CFG(GPD10, 0x04000600, 0x00000022), /* SLP_S5# */ - H110_PAD_DW0_DW1_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */ - /* GPIO Group GPP_I */ - H110_PAD_DW0_DW1_CFG(GPP_I0, 0x84000502, 0x0000006d), /* DDPB_HPD0 */ - H110_PAD_DW0_DW1_CFG(GPP_I1, 0x84000502, 0x0000006e), /* DDPC_HPD1 */ - H110_PAD_DW0_DW1_CFG(GPP_I2, 0x84000500, 0x0000006f), /* DDPD_HPD2 */ - H110_PAD_DW0_DW1_CFG(GPP_I3, 0x84000502, 0x00000070), /* DDPE_HPD3 */ - H110_PAD_DW0_DW1_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */ - /* DDPB_CTRLCLK */ - H110_PAD_DW0_DW1_CFG(GPP_I5, 0x84000500, 0x00000072), - /* DDPB_CTRLDATA */ - H110_PAD_DW0_DW1_CFG(GPP_I6, 0x84000500, 0x00001073), - /* DDPC_CTRLCLK */ - H110_PAD_DW0_DW1_CFG(GPP_I7, 0x84000500, 0x00000074), - /* DDPC_CTRLDATA */ - H110_PAD_DW0_DW1_CFG(GPP_I8, 0x84000500, 0x00001075), - /* DDPD_CTRLCLK */ - H110_PAD_DW0_DW1_CFG(GPP_I9, 0x84000500, 0x00000076), - /* DDPD_CTRLDATA */ - H110_PAD_DW0_DW1_CFG(GPP_I10, 0x84000500, 0x00001077), + /* GPP_C8 - UART0_RXD */ + PAD_CFG_NF_BUF_TRIG(GPP_C8, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_C9 - UART0_TXD */ + PAD_CFG_NF_BUF_TRIG(GPP_C9, NONE, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_C10 - UART0_RTS# */ + PAD_CFG_NF_BUF_TRIG(GPP_C10, NONE, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_C11 - UART0_CTS# */ + PAD_CFG_NF_BUF_TRIG(GPP_C11, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_C12 - GPIO */ + PAD_CFG_GPI_INT(GPP_C12, NONE, PLTRST, OFF), + /* GPP_C13 - GPIO */ + PAD_CFG_GPI_INT(GPP_C13, NONE, PLTRST, OFF), + /* GPP_C14 - GPIO */ + PAD_CFG_GPI_INT(GPP_C14, NONE, PLTRST, OFF), + /* GPP_C15 - GPIO */ + PAD_CFG_GPI_INT(GPP_C15, NONE, PLTRST, OFF), + /* GPP_C16 - GPIO */ + PAD_CFG_GPI_INT(GPP_C16, NONE, PLTRST, OFF), + /* GPP_C17 - GPIO */ + PAD_CFG_GPI_INT(GPP_C17, NONE, PLTRST, OFF), + /* GPP_C18 - GPIO */ + PAD_CFG_GPI_INT(GPP_C18, NONE, PLTRST, OFF), + /* GPP_C19 - GPIO */ + PAD_CFG_GPI_INT(GPP_C19, NONE, PLTRST, OFF), + /* GPP_C20 - UART2_RXD */ + PAD_CFG_NF_BUF_TRIG(GPP_C20, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_C21 - UART2_TXD */ + PAD_CFG_NF_BUF_TRIG(GPP_C21, NONE, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_C22 - UART2_RTS# */ + PAD_CFG_NF_BUF_TRIG(GPP_C22, NONE, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_C23 - GPIO */ + PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, LEVEL, YES), + + /* ------- GPIO Group GPP_D ------- */ + /* GPP_D0 - GPIO */ + PAD_CFG_GPI_INT(GPP_D0, NONE, PLTRST, OFF), + /* GPP_D1 - GPIO */ + PAD_CFG_GPI_INT(GPP_D1, NONE, PLTRST, OFF), + /* GPP_D2 - GPIO */ + PAD_CFG_GPI_INT(GPP_D2, NONE, PLTRST, OFF), + /* GPP_D3 - GPIO */ + PAD_CFG_GPI_INT(GPP_D3, NONE, PLTRST, OFF), + /* GPP_D4 - GPIO */ + PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, OFF), + /* GPP_D5 - I2S_SFRM */ + PAD_CFG_NF_BUF_TRIG(GPP_D5, NONE, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_D6 - I2S_TXD */ + PAD_CFG_NF_BUF_TRIG(GPP_D6, NONE, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_D7 - I2S_RXD */ + PAD_CFG_NF_BUF_TRIG(GPP_D7, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_D8 - I2S_SCLK */ + PAD_CFG_NF_BUF_TRIG(GPP_D8, NONE, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_D9 - GPIO */ + PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, OFF), + /* GPP_D10 - GPIO */ + PAD_CFG_GPI_INT(GPP_D10, NONE, PLTRST, OFF), + /* GPP_D11 - GPIO */ + PAD_CFG_GPI_INT(GPP_D11, NONE, PLTRST, OFF), + /* GPP_D12 - GPIO */ + PAD_CFG_GPI_INT(GPP_D12, NONE, PLTRST, OFF), + /* GPP_D13 - GPIO */ + PAD_CFG_GPI_INT(GPP_D13, NONE, PLTRST, OFF), + /* GPP_D14 - GPIO */ + PAD_CFG_GPI_INT(GPP_D14, NONE, PLTRST, OFF), + /* GPP_D15 - GPIO */ + PAD_CFG_GPI_INT(GPP_D15, NONE, PLTRST, OFF), + /* GPP_D16 - GPIO */ + PAD_CFG_GPI_INT(GPP_D16, NONE, PLTRST, OFF), + /* GPP_D17 - GPIO */ + PAD_CFG_GPI_INT(GPP_D17, NONE, PLTRST, OFF), + /* GPP_D18 - GPIO */ + PAD_CFG_GPI_INT(GPP_D18, NONE, PLTRST, OFF), + /* GPP_D19 - DMIC_CLK0 */ + PAD_CFG_NF_BUF_TRIG(GPP_D19, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_D20 - DMIC_DATA0 */ + PAD_CFG_NF_BUF_TRIG(GPP_D20, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_D21 - GPIO */ + PAD_CFG_GPI_INT(GPP_D21, NONE, PLTRST, OFF), + /* GPP_D22 - GPIO */ + PAD_CFG_GPI_INT(GPP_D22, NONE, PLTRST, OFF), + /* GPP_D23 - GPIO */ + PAD_CFG_GPI_INT(GPP_D23, NONE, PLTRST, OFF), + + /* ------- GPIO Group GPP_E ------- */ + /* GPP_E0 - SATAXPCIE0 */ + PAD_CFG_NF_BUF_TRIG(GPP_E0, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_E1 - SATAXPCIE1 */ + PAD_CFG_NF_BUF_TRIG(GPP_E1, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_E2 - SATAXPCIE2 */ + PAD_CFG_NF_BUF_TRIG(GPP_E2, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_E3 - CPU_GP0 */ + PAD_CFG_NF_BUF_TRIG(GPP_E3, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_E4 - SATA_DEVSLP0 */ + PAD_CFG_NF_BUF_TRIG(GPP_E4, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_E5 - SATA_DEVSLP1 */ + PAD_CFG_NF_BUF_TRIG(GPP_E5, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_E6 - SATA_DEVSLP2 */ + PAD_CFG_NF_BUF_TRIG(GPP_E6, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_E7 - GPIO */ + PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, OFF), + /* GPP_E8 - SATA_LED# */ + PAD_CFG_NF_BUF_TRIG(GPP_E8, NONE, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_E9 - USB_OC0# */ + PAD_CFG_NF_BUF_TRIG(GPP_E9, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_E10 - USB_OC1# */ + PAD_CFG_NF_BUF_TRIG(GPP_E10, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_E11 - USB_OC2# */ + PAD_CFG_NF_BUF_TRIG(GPP_E11, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_E12 - USB_OC3# */ + PAD_CFG_NF_BUF_TRIG(GPP_E12, NONE, DEEP, NF1, TX_DISABLE, OFF), + + /* ------- GPIO Group GPP_F ------- */ + /* GPP_F0 - GPIO */ + PAD_CFG_GPI_INT(GPP_F0, NONE, PLTRST, OFF), + /* GPP_F1 - SATAXPCIE4 */ + PAD_CFG_NF_BUF_TRIG(GPP_F1, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_F2 - GPIO */ + PAD_NC(GPP_F2, NONE), + /* GPP_F3 - GPIO */ + PAD_CFG_GPI_INT(GPP_F3, NONE, PLTRST, OFF), + /* GPP_F4 - GPIO */ + PAD_CFG_GPI_INT(GPP_F4, NONE, PLTRST, OFF), + /* GPP_F5 - GPIO */ + PAD_CFG_GPI_INT(GPP_F5, NONE, PLTRST, OFF), + /* GPP_F6 - GPIO */ + PAD_CFG_GPI_INT(GPP_F6, NONE, PLTRST, OFF), + /* GPP_F7 - GPIO */ + PAD_CFG_GPI_INT(GPP_F7, NONE, PLTRST, OFF), + /* GPP_F8 - GPIO */ + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, OFF), + /* GPP_F9 - GPIO */ + PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), + /* GPP_F10 - GPIO */ + PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), + /* GPP_F11 - GPIO */ + PAD_CFG_GPI_INT(GPP_F11, NONE, PLTRST, OFF), + /* GPP_F12 - GPIO */ + PAD_CFG_GPI_APIC_INVERT(GPP_F12, NONE, PLTRST), + /* GPP_F13 - GPIO */ + PAD_CFG_GPI_APIC(GPP_F13, NONE, PLTRST), + /* GPP_F14 - GPIO */ + PAD_CFG_GPI_APIC_INVERT(GPP_F14, NONE, DEEP), + /* GPP_F15 - USB_OC4# */ + PAD_CFG_NF_BUF_TRIG(GPP_F15, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_F16 - USB_OC5# */ + PAD_CFG_NF_BUF_TRIG(GPP_F16, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_F17 - USB_OC6# */ + PAD_CFG_NF_BUF_TRIG(GPP_F17, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_F18 - GPIO */ + PAD_CFG_GPO(GPP_F18, 1, PLTRST), + /* GPP_F19 - GPIO */ + PAD_CFG_GPI_INT(GPP_F19, NONE, PLTRST, OFF), + /* GPP_F20 - GPIO */ + PAD_CFG_GPI_INT(GPP_F20, NONE, PLTRST, OFF), + /* GPP_F21 - GPIO */ + PAD_CFG_GPI_INT(GPP_F21, NONE, PLTRST, OFF), + /* GPP_F22 - GPIO */ + PAD_CFG_GPI_INT(GPP_F22, NONE, PLTRST, OFF), + /* GPP_F23 - GPIO */ + PAD_CFG_GPI_INT(GPP_F23, NONE, PLTRST, OFF), + + /* ------- GPIO Group GPP_G ------- */ + /* GPP_G0 - GPIO */ + PAD_CFG_GPI_INT(GPP_G0, NONE, PWROK, OFF), + /* GPP_G1 - GPIO */ + PAD_CFG_GPI_INT(GPP_G1, NONE, PWROK, OFF), + /* GPP_G2 - GPIO */ + PAD_CFG_GPI_INT(GPP_G2, NONE, PWROK, OFF), + /* GPP_G3 - GPIO */ + PAD_CFG_GPI_INT(GPP_G3, NONE, PWROK, OFF), + /* GPP_G4 - GPIO */ + PAD_CFG_GPO(GPP_G4, 0, DEEP), + /* GPP_G5 - GPIO */ + PAD_CFG_GPI_INT(GPP_G5, NONE, PWROK, OFF), + /* GPP_G6 - GPIO */ + _PAD_CFG_STRUCT(GPP_G6, + PAD_FUNC(GPIO) | PAD_RESET(PWROK) | + PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_YES | + PAD_BUF(TX_DISABLE), + PAD_PULL(NONE)), + /* GPP_G7 - GPIO */ + PAD_CFG_GPI_INT(GPP_G7, NONE, PWROK, OFF), + /* GPP_G8 - GPIO */ + PAD_CFG_GPI_INT(GPP_G8, NONE, PLTRST, OFF), + /* GPP_G9 - GPIO */ + PAD_CFG_GPI_INT(GPP_G9, NONE, PLTRST, OFF), + /* GPP_G10 - GPIO */ + PAD_CFG_GPI_INT(GPP_G10, NONE, PLTRST, OFF), + /* GPP_G11 - GPIO */ + PAD_CFG_GPI_INT(GPP_G11, NONE, PLTRST, OFF), + /* GPP_G12 - GPIO */ + _PAD_CFG_STRUCT(GPP_G12, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | + PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_YES | + PAD_BUF(TX_DISABLE), + PAD_PULL(NONE)), + /* GPP_G13 - GPIO */ + PAD_CFG_GPO(GPP_G13, 1, PLTRST), + /* GPP_G14 - GPIO */ + _PAD_CFG_STRUCT(GPP_G14, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | + PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_YES | + PAD_BUF(TX_DISABLE), + PAD_PULL(NONE)), + /* GPP_G15 - GPIO */ + PAD_CFG_GPO(GPP_G15, 0, PLTRST), + /* GPP_G16 - GPIO */ + PAD_CFG_TERM_GPO(GPP_G16, 1, 20K_PD, PLTRST), + /* GPP_G17 - GPIO */ + PAD_CFG_GPI_INT(GPP_G17, NONE, PLTRST, OFF), + /* GPP_G18 - GPIO */ + PAD_CFG_GPI_APIC(GPP_G18, NONE, PLTRST), + /* GPP_G19 - SMI# */ + PAD_CFG_NF_BUF_TRIG(GPP_G19, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_G20 - GPIO */ + PAD_CFG_GPI_INT(GPP_G20, NONE, PLTRST, OFF), + /* GPP_G21 - GPIO */ + PAD_CFG_GPI_INT(GPP_G21, NONE, PLTRST, OFF), + /* GPP_G22 - GPIO */ + PAD_CFG_GPI_INT(GPP_G22, NONE, PLTRST, OFF), + /* GPP_G23 - GPIO */ + PAD_CFG_GPI_INT(GPP_G23, NONE, PLTRST, OFF), + + /* ------- GPIO Group GPP_H ------- */ + /* GPP_H0 - GPIO */ + PAD_CFG_GPI_INT(GPP_H0, NONE, PLTRST, OFF), + /* GPP_H1 - GPIO */ + PAD_NC(GPP_H1, NONE), + /* GPP_H2 - GPIO */ + PAD_CFG_GPI_INT(GPP_H2, NONE, PLTRST, OFF), + /* GPP_H3 - GPIO */ + PAD_CFG_GPI_INT(GPP_H3, NONE, PLTRST, OFF), + /* GPP_H4 - GPIO */ + PAD_CFG_GPI_INT(GPP_H4, NONE, PLTRST, OFF), + /* GPP_H5 - GPIO */ + PAD_CFG_GPI_INT(GPP_H5, NONE, PLTRST, OFF), + /* GPP_H6 - GPIO */ + PAD_CFG_GPI_INT(GPP_H6, NONE, PLTRST, OFF), + /* GPP_H7 - GPIO */ + PAD_CFG_GPI_INT(GPP_H7, NONE, PLTRST, OFF), + /* GPP_H8 - GPIO */ + PAD_CFG_GPI_INT(GPP_H8, NONE, PLTRST, OFF), + /* GPP_H9 - GPIO */ + PAD_CFG_GPI_INT(GPP_H9, NONE, PLTRST, OFF), + /* GPP_H10 - GPIO */ + PAD_CFG_GPI_INT(GPP_H10, NONE, PLTRST, OFF), + /* GPP_H11 - GPIO */ + PAD_CFG_GPI_INT(GPP_H11, NONE, PLTRST, OFF), + /* GPP_H12 - GPIO */ + PAD_CFG_GPI_INT(GPP_H12, NONE, PLTRST, OFF), + /* GPP_H13 - GPIO */ + PAD_CFG_GPI_APIC(GPP_H13, NONE, PLTRST), + /* GPP_H14 - GPIO */ + PAD_CFG_GPI_APIC(GPP_H14, NONE, PLTRST), + /* GPP_H15 - GPIO */ + PAD_CFG_GPI_APIC(GPP_H15, NONE, PLTRST), + /* GPP_H16 - GPIO */ + PAD_CFG_GPI(GPP_H16, NONE, PLTRST), + /* GPP_H17 - GPIO */ + PAD_CFG_GPO(GPP_H17, 1, PLTRST), + /* GPP_H18 - GPIO */ + PAD_CFG_GPI_INT(GPP_H18, NONE, PLTRST, OFF), + /* GPP_H19 - GPIO */ + PAD_CFG_GPI_INT(GPP_H19, NONE, PLTRST, OFF), + /* GPP_H20 - GPIO */ + PAD_CFG_GPI_INT(GPP_H20, NONE, PLTRST, OFF), + /* GPP_H21 - GPIO */ + PAD_CFG_GPI_INT(GPP_H21, NONE, PLTRST, OFF), + /* GPP_H22 - GPIO */ + PAD_CFG_GPI_INT(GPP_H22, NONE, PLTRST, OFF), + /* GPP_H23 - GPIO */ + PAD_CFG_GPI_INT(GPP_H23, NONE, PWROK, OFF), + + /* -------- GPIO Group GPD -------- */ + /* GPD0 - GPIO */ + PAD_CFG_GPI_INT(GPD0, NONE, PLTRST, OFF), + /* GPD1 - GPIO */ + PAD_CFG_GPO(GPD1, 0, PWROK), + /* GPD2 - LAN_WAKE# */ + PAD_CFG_NF_BUF_TRIG(GPD2, NATIVE, PWROK, NF1, RX_DISABLE, LEVEL), + /* GPD3 - PWRBTN# */ + PAD_CFG_NF_BUF_TRIG(GPD3, 20K_PU, PWROK, NF1, TX_DISABLE, OFF), + /* GPD4 - SLP_S3# */ + PAD_CFG_NF_BUF_TRIG(GPD4, NONE, PWROK, NF1, RX_DISABLE, OFF), + /* GPD5 - SLP_S4# */ + PAD_CFG_NF_BUF_TRIG(GPD5, NONE, PWROK, NF1, RX_DISABLE, OFF), + /* GPD6 - GPIO */ + PAD_CFG_GPI_INT(GPD6, NONE, PLTRST, OFF), + /* GPD7 - GPIO */ + _PAD_CFG_STRUCT(GPD7, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | + PAD_BUF(TX_DISABLE) | 1, + PAD_PULL(NONE)), + /* GPD8 - SUSCLK */ + PAD_CFG_NF_BUF_TRIG(GPD8, NONE, PWROK, NF1, RX_DISABLE, OFF), + /* GPD9 - SLP_WLAN# */ + PAD_CFG_NF_BUF_TRIG(GPD9, NONE, PWROK, NF1, RX_DISABLE, OFF), + /* GPD10 - SLP_S5# */ + PAD_CFG_NF_BUF_TRIG(GPD10, NONE, PWROK, NF1, RX_DISABLE, OFF), + /* GPD11 - GPIO */ + PAD_CFG_GPO(GPD11, 0, PWROK), + + /* ------- GPIO Group GPP_I ------- */ + /* GPP_I0 - DDPB_HPD0 */ + PAD_CFG_NF_BUF_TRIG(GPP_I0, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I1 - DDPC_HPD1 */ + PAD_CFG_NF_BUF_TRIG(GPP_I1, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I2 - DDPD_HPD2 */ + PAD_CFG_NF_BUF_TRIG(GPP_I2, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I3 - DDPE_HPD3 */ + PAD_CFG_NF_BUF_TRIG(GPP_I3, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I4 - GPIO */ + PAD_CFG_GPI_INT(GPP_I4, NONE, PLTRST, OFF), + /* GPP_I5 - DDPB_CTRLCLK */ + PAD_CFG_NF_BUF_TRIG(GPP_I5, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I6 - DDPB_CTRLDATA */ + PAD_CFG_NF_BUF_TRIG(GPP_I6, 20K_PD, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I7 - DDPC_CTRLCLK */ + PAD_CFG_NF_BUF_TRIG(GPP_I7, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I8 - DDPC_CTRLDATA */ + PAD_CFG_NF_BUF_TRIG(GPP_I8, 20K_PD, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I9 - DDPD_CTRLCLK */ + PAD_CFG_NF_BUF_TRIG(GPP_I9, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I10 - DDPD_CTRLDATA */ + PAD_CFG_NF_BUF_TRIG(GPP_I10, 20K_PD, PLTRST, NF1, TX_DISABLE, OFF), }; -/* Early pad configuration in romstage. */ +/* Early pad configuration in romstage */ static const struct pad_config early_gpio_table[] = { - /* GPIO Group GPP_A */ - H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ - H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ - H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ - H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ - H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ - H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ - H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ - H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ - H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ - H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ - /* ---- */ - /* SUSWARN#/SUSPWRDNACK */ - H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), - H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ - H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ + /* ------- GPIO Group GPP_A ------- */ + /* GPP_A0 - RCIN# */ + PAD_CFG_NF_BUF_TRIG(GPP_A0, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_A1 - LAD0 */ + PAD_CFG_NF_BUF_TRIG(GPP_A1, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A2 - LAD1 */ + PAD_CFG_NF_BUF_TRIG(GPP_A2, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A3 - LAD2 */ + PAD_CFG_NF_BUF_TRIG(GPP_A3, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A4 - LAD3 */ + PAD_CFG_NF_BUF_TRIG(GPP_A4, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A5 - LFRAME# */ + PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_A6 - SERIRQ */ + PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, PLTRST, NF1, NO_DISABLE, OFF), + + /* GPP_A8 - CLKRUN# */ + PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_A9 - CLKOUT_LPC0 */ + PAD_CFG_NF_BUF_TRIG(GPP_A9, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_A10 - CLKOUT_LPC1 */ + PAD_CFG_NF_BUF_TRIG(GPP_A10, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + + /* GPP_A13 - SUSWARN#/SUSPWRDNACK */ + PAD_CFG_NF_BUF_TRIG(GPP_A13, NONE, DEEP, NF1, RX_DISABLE, OFF), + /* GPP_A14 - SUS_STAT# */ + PAD_CFG_NF_BUF_TRIG(GPP_A14, NONE, DEEP, NF1, RX_DISABLE, OFF), + /* GPP_A15 - SUS_ACK# */ + PAD_CFG_NF_BUF_TRIG(GPP_A15, 20K_PU, DEEP, NF1, TX_DISABLE, OFF), }; #endif diff --git a/src/mainboard/asrock/h110m/romstage.c b/src/mainboard/asrock/h110m/romstage.c index 4961a792ad..efbc650bf3 100644 --- a/src/mainboard/asrock/h110m/romstage.c +++ b/src/mainboard/asrock/h110m/romstage.c @@ -20,7 +20,7 @@ #define RCOMP_TARGET_PARAMS 0x5 -static void mainboard_fill_dq_map_data(void *dq_map_ptr) +static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -28,16 +28,18 @@ static void mainboard_fill_dq_map_data(void *dq_map_ptr) 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); + memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); + memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); } -static void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1) { /* DQS CPU<>DRAM map */ const u8 dqs_map[2][8] = { { 0, 1, 3, 2, 4, 5, 6, 7 }, { 1, 0, 4, 5, 2, 3, 6, 7 } }; - memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); + memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); + memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); } static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) @@ -64,8 +66,10 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; mem_cfg = &mupd->FspmConfig; - mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); - mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, + &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, + &mem_cfg->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 3af82f2907..3deae7510f 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -16,7 +16,7 @@ */ #include -#include +#include #include #include #include @@ -39,7 +39,7 @@ static const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -94,7 +94,6 @@ void mainboard_romstage_entry(unsigned long bist) .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], - .bist = bist, }; romstage_common(&romstage_params); diff --git a/src/mainboard/asus/kcma-d8/Kconfig b/src/mainboard/asus/kcma-d8/Kconfig index 1a2dd904e3..d568ff579b 100644 --- a/src/mainboard/asus/kcma-d8/Kconfig +++ b/src/mainboard/asus/kcma-d8/Kconfig @@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_2048 select ENABLE_APIC_EXT_ID select SPI_FLASH - select HAVE_ACPI_RESUME select DRIVERS_I2C_W83795 select DRIVERS_ASPEED_AST2050 select MAINBOARD_FORCE_NATIVE_VGA_INIT diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 7b20243863..22eb1157b9 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -132,8 +132,10 @@ static void ck804_control(const unsigned int *values, u32 size, } } - if (ck804_num < 1) + if (ck804_num < 1) { printk(BIOS_WARNING, "CK804 not found at device base unit id %02x!\n", bus_unit_id); + return; + } ck804_early_set_port(ck804_num, busn, io_base); diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig index 32c4dbc85a..ffbfd53169 100644 --- a/src/mainboard/asus/kgpe-d16/Kconfig +++ b/src/mainboard/asus/kgpe-d16/Kconfig @@ -28,11 +28,11 @@ config BOARD_SPECIFIC_OPTIONS select ENABLE_APIC_EXT_ID select SPI_FLASH select MAINBOARD_HAS_LPC_TPM - select HAVE_ACPI_RESUME select DRIVERS_I2C_W83795 select DRIVERS_ASPEED_AST2050 select MAINBOARD_FORCE_NATIVE_VGA_INIT select POWER_STATE_DEFAULT_ON_AFTER_FAILURE + select IPMI_KCS config MAINBOARD_DIR string diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb index 0ea4216417..31bd3e349f 100644 --- a/src/mainboard/asus/kgpe-d16/devicetree.cb +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb @@ -217,7 +217,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex chip drivers/pc80/tpm device pnp 4e.0 on end # TPM module end - chip drivers/generic/generic # BMC KCS + chip drivers/ipmi # BMC KCS device pnp ca2.0 on end end end diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl index ea524887cb..efb67a558c 100644 --- a/src/mainboard/asus/kgpe-d16/dsdt.asl +++ b/src/mainboard/asus/kgpe-d16/dsdt.asl @@ -53,9 +53,6 @@ DefinitionBlock ( #include - /* IPMI KCS enable */ - Name (KCSE, 0x1) - /* The _PIC method is called by the OS to choose between interrupt * routing via the i8259 interrupt controller or the APIC. * @@ -489,13 +486,6 @@ DefinitionBlock ( Name (_HID, EisaId ("PNP0A05")) Name (_ADR, 0x00140003) - OperationRegion (BMRG, SystemIO, 0xca2, 0x02) /* BMC KCS registers */ - Field (BMRG, AnyAcc, NoLock, Preserve) - { - BMRI, 8, /* Index */ - BMRD, 8, /* Data */ - } - /* Real Time Clock Device */ Device(RTC0) { Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ @@ -617,27 +607,6 @@ DefinitionBlock ( }) } } - - Device (KCS1) { /* IPMI KCS */ - Name (_HID, EISAID ("IPI0001")) /* ASpeed BMC */ - Method (_STA, 0, NotSerialized) { - If (KCSE) { /* Detection enabled */ - If (LNotEqual (BMRD, 0xff)) { - Return (0x0f) /* Device present */ - } - Return (Zero) - } - Return (Zero) - } - Method (_CRS, 0) { - Return (ResourceTemplate() { - IO(Decode16, 0x0ca2, 0x0ca2, 0x01, 0x02) - }) - } - Method (_IFT, 0, NotSerialized) { /* Interface type */ - Return (One) /* KCS interface */ - } - } } /* High Precision Event Timer */ diff --git a/src/mainboard/asus/kgpe-d16/mainboard.c b/src/mainboard/asus/kgpe-d16/mainboard.c index 14bb986485..a03953be77 100644 --- a/src/mainboard/asus/kgpe-d16/mainboard.c +++ b/src/mainboard/asus/kgpe-d16/mainboard.c @@ -47,7 +47,6 @@ void set_pcie_dereset(void) * enable the dedicated function in kgpe-d16 board. * This function is called earlier than sr5650_enable. *************************************************/ -#define BMC_KCS_BASE 0xca2 static void mainboard_enable(struct device *dev) { @@ -69,13 +68,6 @@ static void mainboard_enable(struct device *dev) set_pcie_dereset(); /* get_ide_dma66(); */ - - /* Enable access to the BMC IPMI via KCS */ - struct device *lpc_sio_dev = dev_find_slot_pnp(BMC_KCS_BASE, 0); - struct resource *res = new_resource(lpc_sio_dev, BMC_KCS_BASE); - res->base = BMC_KCS_BASE; - res->size = 1; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } /* override the default SATA PHY setup */ diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 1309d67d88..52de343b95 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -19,7 +19,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index 91834cd5f6..5b3a30b4f9 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -18,8 +18,7 @@ #include #include #include -#include -#include +#include #include #include #include @@ -31,11 +30,10 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); - report_bist_failure(bist); enable_smbus(); sdram_initialize(); diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index 753f64076e..f933c772d2 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -18,8 +18,7 @@ #include #include #include -#include -#include +#include #include /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ #include @@ -32,11 +31,10 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); - report_bist_failure(bist); enable_smbus(); sdram_initialize(); diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index 88f61f85b6..1d7c928f17 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -18,8 +18,7 @@ #include #include #include -#include -#include +#include #include #include #include @@ -31,11 +30,10 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); - report_bist_failure(bist); enable_smbus(); sdram_initialize(); diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index 387cecb5dd..8fc135d1c8 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -19,8 +19,7 @@ #include #include #include -#include -#include +#include #include /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ #include @@ -65,11 +64,10 @@ static void disable_spd(void) outb(0x67, PM_IO_BASE + 0x37); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); - report_bist_failure(bist); enable_smbus(); enable_pm(); diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index b076b9d7fb..632ef05573 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -15,8 +15,6 @@ * GNU General Public License for more details. */ -// __PRE_RAM__ means: use "unsigned" for device, not a struct. - #include #include #include @@ -26,8 +24,7 @@ #include #include #include -#include -#include +#include #include #include #include @@ -175,14 +172,13 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0, boot_mode = 0; u8 c_bsel = msr_get_fsb(); - if (bist == 0) - enable_lapic(); + enable_lapic(); ich7_enable_lpc(); @@ -191,9 +187,6 @@ void mainboard_romstage_entry(unsigned long bist) /* Set up the console */ console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected.\n"); boot_mode = 1; diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c index a818b746c7..1477d80ea3 100644 --- a/src/mainboard/asus/p5qc/romstage.c +++ b/src/mainboard/asus/p5qc/romstage.c @@ -20,8 +20,7 @@ #include #include #include -#include -#include +#include #include #include #include @@ -66,7 +65,7 @@ static void ich10_enable_lpc(void) pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0x001c4701); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; u8 boot_path = 0; @@ -79,7 +78,6 @@ void mainboard_romstage_entry(unsigned long bist) console_init(); - report_bist_failure(bist); enable_smbus(); x4x_early_init(); diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index 7d028434d6..dc589a5918 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -19,9 +19,8 @@ #include #include #include -#include +#include #include -#include #include #include #include @@ -162,7 +161,7 @@ static void ich7_enable_lpc(void) pci_write_config32(LPC_DEV, 0x84, 0x000295); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; @@ -176,7 +175,6 @@ void mainboard_romstage_entry(unsigned long bist) console_init(); - report_bist_failure(bist); enable_smbus(); x4x_early_init(); diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index b4b536e1e4..8d7366e534 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -17,7 +17,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c index 4f5ab88232..abe300e731 100644 --- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c @@ -191,11 +191,12 @@ void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) { - AGESA_STATUS Status = AGESA_UNSUPPORTED; -#ifdef __PRE_RAM__ AGESA_READ_SPD_PARAMS *info = ConfigPtr; u8 index; + if (!ENV_ROMSTAGE) + return AGESA_UNSUPPORTED; + if (CONFIG(BAP_E20_DDR3_1066)) index = 1; else /* CONFIG_BAP_E20_DDR3_800 */ @@ -212,7 +213,5 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi if (read_ddr3_spd_from_cbfs((u8 *)info->Buffer, index) < 0) die("No SPD data\n"); - Status = AGESA_SUCCESS; -#endif - return Status; + return AGESA_SUCCESS; } diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c index 6458b974ff..6ff38cbe77 100644 --- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c @@ -299,11 +299,12 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) { - AGESA_STATUS Status = AGESA_UNSUPPORTED; -#ifdef __PRE_RAM__ AGESA_READ_SPD_PARAMS *info = ConfigPtr; u8 index; + if (!ENV_ROMSTAGE) + return AGESA_UNSUPPORTED; + if (CONFIG(BAP_E21_DDR3_1066)) index = 1; else if (CONFIG(BAP_E21_DDR3_1333)) @@ -322,7 +323,5 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi if (read_ddr3_spd_from_cbfs((u8 *)info->Buffer, index) < 0) die("No SPD data\n"); - Status = AGESA_SUCCESS; -#endif - return Status; + return AGESA_SUCCESS; } diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c index 6c3d980b65..74f00c21d1 100644 --- a/src/mainboard/compulab/intense_pc/romstage.c +++ b/src/mainboard/compulab/intense_pc/romstage.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #define SIO_PORT 0x164e diff --git a/src/mainboard/emulation/qemu-aarch64/Kconfig b/src/mainboard/emulation/qemu-aarch64/Kconfig index 7d8d7b2f00..ebdbf16e8c 100644 --- a/src/mainboard/emulation/qemu-aarch64/Kconfig +++ b/src/mainboard/emulation/qemu-aarch64/Kconfig @@ -46,6 +46,6 @@ config MAINBOARD_VENDOR config DRAM_SIZE_MB int - default 1024 + default 261120 # The maximum dram size is 255GiB. endif # BOARD_EMULATION_QEMU_AARCH64 diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 23526f96d9..3c5e3252f8 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -12,8 +12,6 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_256 select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT - select POSTCAR_STAGE - select POSTCAR_CONSOLE config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-i440fx/Makefile.inc b/src/mainboard/emulation/qemu-i440fx/Makefile.inc index e3ca3002ff..cac74ee435 100644 --- a/src/mainboard/emulation/qemu-i440fx/Makefile.inc +++ b/src/mainboard/emulation/qemu-i440fx/Makefile.inc @@ -1,8 +1,10 @@ -ramstage-y += northbridge.c -ramstage-y += fw_cfg.c romstage-y += fw_cfg.c -romstage-y += memory.c -ramstage-y += memory.c -postcar-y += memory.c +romstage-y += memmap.c + postcar-y += fw_cfg.c +postcar-y += memmap.c postcar-y += exit_car.S + +ramstage-y += fw_cfg.c +ramstage-y += memmap.c +ramstage-y += northbridge.c diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 3acb11e5f5..580e09ad45 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -24,20 +24,29 @@ #define FW_CFG_PORT_CTL 0x0510 #define FW_CFG_PORT_DATA 0x0511 +#define FW_CFG_DMA_ADDR_HIGH 0x0514 +#define FW_CFG_DMA_ADDR_LOW 0x0518 static int fw_cfg_detected; +static uint8_t fw_ver; + +static void fw_cfg_dma(int control, void *buf, int len); static int fw_cfg_present(void) { static const char qsig[] = "QEMU"; - unsigned char sig[4]; + unsigned char sig[FW_CFG_SIG_SIZE]; int detected = 0; if (fw_cfg_detected == 0) { fw_cfg_get(FW_CFG_SIGNATURE, sig, sizeof(sig)); - detected = memcmp(sig, qsig, 4) == 0; + detected = memcmp(sig, qsig, FW_CFG_SIG_SIZE) == 0; printk(BIOS_INFO, "QEMU: firmware config interface %s\n", detected ? "detected" : "not found"); + if (detected) { + fw_cfg_get(FW_CFG_ID, &fw_ver, sizeof(fw_ver)); + printk(BIOS_INFO, "Firmware config version id: %d\n", fw_ver); + } fw_cfg_detected = detected + 1; } return fw_cfg_detected - 1; @@ -50,7 +59,10 @@ static void fw_cfg_select(uint16_t entry) static void fw_cfg_read(void *dst, int dstlen) { - insb(FW_CFG_PORT_DATA, dst, dstlen); + if (fw_ver & FW_CFG_VERSION_DMA) + fw_cfg_dma(FW_CFG_DMA_CTL_READ, dst, dstlen); + else + insb(FW_CFG_PORT_DATA, dst, dstlen); } void fw_cfg_get(uint16_t entry, void *dst, int dstlen) @@ -500,3 +512,31 @@ void smbios_system_set_uuid(u8 *uuid) fw_cfg_smbios_init(); memcpy(uuid, type1_uuid, 16); } + +/* + * Configure DMA setup + */ + +static void fw_cfg_dma(int control, void *buf, int len) +{ + volatile FwCfgDmaAccess dma; + uintptr_t dma_desc_addr; + uint32_t dma_desc_addr_hi, dma_desc_addr_lo; + + dma.control = be32_to_cpu(control); + dma.length = be32_to_cpu(len); + dma.address = be64_to_cpu((uintptr_t)buf); + + dma_desc_addr = (uintptr_t)&dma; + dma_desc_addr_lo = (uint32_t)(dma_desc_addr & 0xFFFFFFFFU); + dma_desc_addr_hi = sizeof(uintptr_t) > sizeof(uint32_t) + ? (uint32_t)(dma_desc_addr >> 32) : 0; + + // Skip writing high half if unnecessary. + if (dma_desc_addr_hi) + outl(be32_to_cpu(dma_desc_addr_hi), FW_CFG_DMA_ADDR_HIGH); + outl(be32_to_cpu(dma_desc_addr_lo), FW_CFG_DMA_ADDR_LOW); + + while (be32_to_cpu(dma.control) & ~FW_CFG_DMA_CTL_ERROR) + ; +} diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h index 46aee9b3d6..dad6ca9e7f 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h @@ -13,40 +13,43 @@ */ /* - * This are the qemu firmware config interface defines and structs. - * Copyed over from qemu soure tree, include/hw/nvram/fw_cfg.h + * These are the qemu firmware config interface defines and structs. + * Copied over from qemu soure tree, + * include/standard-headers/linux/qemu_fw_cfg.h and modified accordingly. */ #ifndef FW_CFG_IF_H #define FW_CFG_IF_H #include -#define FW_CFG_SIGNATURE 0x00 -#define FW_CFG_ID 0x01 -#define FW_CFG_UUID 0x02 -#define FW_CFG_RAM_SIZE 0x03 -#define FW_CFG_NOGRAPHIC 0x04 -#define FW_CFG_NB_CPUS 0x05 -#define FW_CFG_MACHINE_ID 0x06 -#define FW_CFG_KERNEL_ADDR 0x07 -#define FW_CFG_KERNEL_SIZE 0x08 -#define FW_CFG_KERNEL_CMDLINE 0x09 -#define FW_CFG_INITRD_ADDR 0x0a -#define FW_CFG_INITRD_SIZE 0x0b -#define FW_CFG_BOOT_DEVICE 0x0c -#define FW_CFG_NUMA 0x0d -#define FW_CFG_BOOT_MENU 0x0e -#define FW_CFG_MAX_CPUS 0x0f -#define FW_CFG_KERNEL_ENTRY 0x10 -#define FW_CFG_KERNEL_DATA 0x11 -#define FW_CFG_INITRD_DATA 0x12 -#define FW_CFG_CMDLINE_ADDR 0x13 -#define FW_CFG_CMDLINE_SIZE 0x14 -#define FW_CFG_CMDLINE_DATA 0x15 -#define FW_CFG_SETUP_ADDR 0x16 -#define FW_CFG_SETUP_SIZE 0x17 -#define FW_CFG_SETUP_DATA 0x18 -#define FW_CFG_FILE_DIR 0x19 +enum fw_cfg_enum { + FW_CFG_SIGNATURE, + FW_CFG_ID, + FW_CFG_UUID, + FW_CFG_RAM_SIZE, + FW_CFG_NOGRAPHIC, + FW_CFG_NB_CPUS, + FW_CFG_MACHINE_ID, + FW_CFG_KERNEL_ADDR, + FW_CFG_KERNEL_SIZE, + FW_CFG_KERNEL_CMDLINE, + FW_CFG_INITRD_ADDR, + FW_CFG_INITRD_SIZE, + FW_CFG_BOOT_DEVICE, + FW_CFG_NUMA, + FW_CFG_BOOT_MENU, + FW_CFG_MAX_CPUS, + FW_CFG_KERNEL_ENTRY, + FW_CFG_KERNEL_DATA, + FW_CFG_INITRD_DATA, + FW_CFG_CMDLINE_ADDR, + FW_CFG_CMDLINE_SIZE, + FW_CFG_CMDLINE_DATA, + FW_CFG_SETUP_ADDR, + FW_CFG_SETUP_SIZE, + FW_CFG_SETUP_DATA, + FW_CFG_FILE_DIR +}; #define FW_CFG_FILE_FIRST 0x20 #define FW_CFG_FILE_SLOTS 0x10 @@ -64,11 +67,20 @@ #define FW_CFG_INVALID 0xffff +/* width in bytes of fw_cfg control register */ +#define FW_CFG_CTL_SIZE 0x02 + +/* fw_cfg "file name" is up to 56 characters (including terminating nul) */ +#define FW_CFG_MAX_FILE_PATH 56 + +/* size in bytes of fw_cfg signature */ +#define FW_CFG_SIG_SIZE 4 + typedef struct FWCfgFile { uint32_t size; /* file size */ uint16_t select; /* write this to 0x510 to read it */ uint16_t reserved; - char name[56]; + char name[FW_CFG_MAX_FILE_PATH]; } FWCfgFile; typedef struct FWCfgFiles { @@ -93,4 +105,26 @@ typedef struct FwCfgSmbios { uint16_t fieldoffset; } FwCfgSmbios; +/* FW_CFG_ID bits */ +#define FW_CFG_VERSION 0x01 +#define FW_CFG_VERSION_DMA 0x02 + +/* FW_CFG_DMA_CONTROL bits */ +#define FW_CFG_DMA_CTL_ERROR 0x01 +#define FW_CFG_DMA_CTL_READ 0x02 +#define FW_CFG_DMA_CTL_SKIP 0x04 +#define FW_CFG_DMA_CTL_SELECT 0x08 +#define FW_CFG_DMA_CTL_WRITE 0x10 + +#define FW_CFG_DMA_SIGNATURE 0x51454d5520434647ULL /* "QEMU CFG" */ + +/* Control as first field allows for different structures selected by this + * field, which might be useful in the future + */ +typedef struct FwCfgDmaAccess { + uint32_t control; + uint32_t length; + uint64_t address; +} FwCfgDmaAccess; + #endif /* FW_CFG_IF_H */ diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memmap.c similarity index 92% rename from src/mainboard/emulation/qemu-i440fx/memory.c rename to src/mainboard/emulation/qemu-i440fx/memmap.c index aa1ceba410..8209379bef 100644 --- a/src/mainboard/emulation/qemu-i440fx/memory.c +++ b/src/mainboard/emulation/qemu-i440fx/memmap.c @@ -15,6 +15,7 @@ #include #include +#include #include "memory.h" #include "fw_cfg.h" @@ -61,3 +62,8 @@ void *cbmem_top(void) return (void *)top; } + +/* Nothing to do, MTRRs are no-op on QEMU. */ +void fill_postcar_frame(struct postcar_frame *pcf) +{ +} diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 852800dc4d..0bff4d7dd8 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -72,7 +72,7 @@ static void cpu_pci_domain_read_resources(struct device *dev) for (i = 0; i < f.size / sizeof(*list); i++) { switch (list[i].type) { case 1: /* RAM */ - printk(BIOS_DEBUG, "QEMU: e820/ram: 0x%08llx +0x%08llx\n", + printk(BIOS_DEBUG, "QEMU: e820/ram: 0x%08llx + 0x%08llx\n", list[i].address, list[i].length); if (list[i].address == 0) { tomk = list[i].length / 1024; diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index 6b1883ccbd..8e5691fc71 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -14,31 +14,10 @@ * GNU General Public License for more details. */ -#include -#include +#include #include -#include -#include -#include -#include -asmlinkage void car_stage_entry(void) +void mainboard_romstage_entry(void) { - struct postcar_frame pcf; - - console_init(); - cbmem_recovery(0); - - timestamp_add_now(TS_START_ROMSTAGE); - - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - /** - * Run postcar to tear down CAR and load relocatable ramstage. - * There's no CAR on qemu, but for educational purposes and - * testing the postcar stage is used on qemu, too. - */ - run_postcar_phase(&pcf); } diff --git a/src/mainboard/emulation/qemu-power8/Makefile.inc b/src/mainboard/emulation/qemu-power8/Makefile.inc index db005bbab8..5c6c56e5de 100644 --- a/src/mainboard/emulation/qemu-power8/Makefile.inc +++ b/src/mainboard/emulation/qemu-power8/Makefile.inc @@ -17,6 +17,7 @@ bootblock-y += uart.c romstage-y += cbmem.c ramstage-y += cbmem.c romstage-y += romstage.c +ramstage-y += timer.c romstage-y += uart.c ramstage-y += uart.c diff --git a/src/arch/ppc64/misc.c b/src/mainboard/emulation/qemu-power8/timer.c similarity index 100% rename from src/arch/ppc64/misc.c rename to src/mainboard/emulation/qemu-power8/timer.c diff --git a/src/mainboard/emulation/qemu-power8/uart.c b/src/mainboard/emulation/qemu-power8/uart.c index 9548b7c696..27eb2f4f8f 100644 --- a/src/mainboard/emulation/qemu-power8/uart.c +++ b/src/mainboard/emulation/qemu-power8/uart.c @@ -41,7 +41,6 @@ void uart_tx_flush(int idx) { } -#ifndef __PRE_RAM__ void uart_fill_lb(void *data) { struct lb_serial serial; @@ -50,7 +49,9 @@ void uart_fill_lb(void *data) serial.baseaddr = 0; serial.baud = 115200; serial.regwidth = 1; + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } -#endif diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 815b93b012..bfa38ed84e 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -11,8 +11,6 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_2048 select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT - select POSTCAR_STAGE - select POSTCAR_CONSOLE config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc index b18d2e4f97..133a213cc6 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.inc +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -1,11 +1,12 @@ -ramstage-y += ../qemu-i440fx/northbridge.c -ramstage-y += ../qemu-i440fx/memory.c -ramstage-y += ../qemu-i440fx/fw_cfg.c -romstage-y += ../qemu-i440fx/memory.c -romstage-y += ../qemu-i440fx/fw_cfg.c - -postcar-y += ../qemu-i440fx/memory.c -postcar-y += ../qemu-i440fx/exit_car.S -postcar-y += ../qemu-i440fx/fw_cfg.c - bootblock-y += bootblock.c + +romstage-y += ../qemu-i440fx/fw_cfg.c +romstage-y += ../qemu-i440fx/memmap.c + +postcar-y += ../qemu-i440fx/fw_cfg.c +postcar-y += ../qemu-i440fx/memmap.c +postcar-y += ../qemu-i440fx/exit_car.S + +ramstage-y += ../qemu-i440fx/fw_cfg.c +ramstage-y += ../qemu-i440fx/memmap.c +ramstage-y += ../qemu-i440fx/northbridge.c diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index dbaead982a..b7fdac2552 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -14,14 +14,10 @@ * GNU General Public License for more details. */ -#include -#include +#include #include #include -#include -#include #include -#include #include #define D0F0_PCIEXBAR_LO 0x60 @@ -35,26 +31,11 @@ static void mainboard_machine_check(void) die("You must run qemu for machine Q35 (-M q35)"); } -asmlinkage void car_stage_entry(void) +void mainboard_romstage_entry(void) { - struct postcar_frame pcf; i82801ix_early_init(); - console_init(); mainboard_machine_check(); cbmem_recovery(0); - - timestamp_add_now(TS_START_ROMSTAGE); - - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - /** - * Run postcar to tear down CAR and load relocatable ramstage. - * There's no CAR on qemu, but for educational purposes and - * testing the postcar stage is used on qemu, too. - */ - - run_postcar_phase(&pcf); } diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index 177393e749..ce90758462 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM2 select SOC_INTEL_BRASWELL + select SOC_INTEL_COMMON_BLOCK_HDA_VERB select PCIEXP_L1_SUB_STATE select HAVE_FSP_BIN select CACHE_MRC_SETTINGS diff --git a/src/mainboard/facebook/fbg1701/data.vbt b/src/mainboard/facebook/fbg1701/data.vbt index 39eba56e71..356c087653 100644 Binary files a/src/mainboard/facebook/fbg1701/data.vbt and b/src/mainboard/facebook/fbg1701/data.vbt differ diff --git a/src/mainboard/facebook/watson/Kconfig b/src/mainboard/facebook/watson/Kconfig index 6c2f9542e4..3235b6cc99 100644 --- a/src/mainboard/facebook/watson/Kconfig +++ b/src/mainboard/facebook/watson/Kconfig @@ -11,6 +11,15 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_USES_IFD_GBE_REGION select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 + select NO_UART_ON_SUPERIO + +config VBOOT + select VBOOT_VBNV_CMOS + select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP config MAINBOARD_DIR string diff --git a/src/mainboard/facebook/watson/cmos.layout b/src/mainboard/facebook/watson/cmos.layout index 85506ebe26..675370df70 100644 --- a/src/mainboard/facebook/watson/cmos.layout +++ b/src/mainboard/facebook/watson/cmos.layout @@ -72,6 +72,7 @@ entries #392 3 r 0 unused 395 4 e 6 debug_level #399 1 r 0 unused +416 128 r 0 vbnv # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/facebook/watson/vboot-ro.fmd b/src/mainboard/facebook/watson/vboot-ro.fmd new file mode 100644 index 0000000000..cc6a7c57a8 --- /dev/null +++ b/src/mainboard/facebook/watson/vboot-ro.fmd @@ -0,0 +1,26 @@ +FLASH 16M { + SI_ALL@0x0 0x600000 { + SI_DESC@0x0 0x1000 + UNUSED_1@0x1000 0x1000 + IDPROM@0x2000 0x400 + UNUSED_2@0x2400 0x1ec00 + SI_ME@0x21000 0x3de000 + UNUSED_3@0x400000 0x200000 + } + SI_BIOS@0x600000 0xA00000 { + MISC_RW@0x0 0x20000 { + RW_MRC_CACHE@0x0 0x10000 + RW_VPD(PRESERVE)@0x010000 0x4000 + } + WP_RO@0x20000 0x9e0000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x9dc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x4000 + COREBOOT(CBFS)@0x5000 0x9d7000 + } + } + } +} diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index ec4541f92e..a22c90c1f1 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -17,8 +17,7 @@ */ #include -#include -#include +#include #include #include #include @@ -81,7 +80,7 @@ static void ich7_enable_lpc(void) pci_write_config32(LPC_DEV, GEN1_DEC, 0x003c0a01); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { // ch0 ch1 #if CONFIG(BOARD_FOXCONN_G41S_K) @@ -101,7 +100,6 @@ void mainboard_romstage_entry(unsigned long bist) console_init(); - report_bist_failure(bist); enable_smbus(); x4x_early_init(); diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index 9fe40bcb8f..f1c7d4550d 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_MP_TABLE select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select UDELAY_LAPIC select BOARD_ROMSIZE_KB_1024 select INTEL_INT15 select I945_LVDS diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index d14b1c8719..ff4c99ed4d 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -24,8 +24,7 @@ #include #include #include -#include -#include +#include #include #include #include @@ -232,12 +231,11 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0; - if (bist == 0) - enable_lapic(); + enable_lapic(); #if 0 /* Force PCIRST# */ @@ -252,9 +250,6 @@ void mainboard_romstage_entry(unsigned long bist) /* Set up the console */ console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); system_reset(); diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index 2c7800fcf7..eaf05a2c38 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -// __PRE_RAM__ means: use "unsigned" for device, not a struct. - #include #include #include @@ -23,8 +21,7 @@ #include #include #include -#include -#include +#include #include #include #include @@ -137,12 +134,10 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0, boot_mode = 0; - - if (bist == 0) - enable_lapic(); + enable_lapic(); ich7_enable_lpc(); /* Enable SuperIO PM */ @@ -155,9 +150,6 @@ void mainboard_romstage_entry(unsigned long bist) /* Set up the console */ console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected.\n"); boot_mode = 1; diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index e20fb7a888..989a0cb941 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -22,8 +22,7 @@ #include #include #include -#include -#include +#include #include #include #include @@ -122,7 +121,7 @@ static void ich7_enable_lpc(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x007c0291); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; @@ -139,7 +138,6 @@ void mainboard_romstage_entry(unsigned long bist) console_init(); - report_bist_failure(bist); enable_smbus(); x4x_early_init(); diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c index 27fbb2ccc7..a51595f4ff 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c @@ -25,14 +25,11 @@ void pch_enable_lpc(void) { - if (CONFIG(BOARD_GIGABYTE_GA_H61M_S2PV)) { - pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | - CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | CNF1_LPC_EN); - } else if (CONFIG(BOARD_GIGABYTE_GA_H61MA_D3V)) { - pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | - CNF1_LPC_EN); + if (!CONFIG(NO_UART_ON_SUPERIO)) { + pci_or_config16(PCH_LPC_DEV, LPC_EN, COMA_LPC_EN); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); } } diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index 0147a317fe..c82e37d635 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -13,15 +13,13 @@ * GNU General Public License for more details. */ +#include #include #include /* SPI Write protect is GPIO 16 */ #define CROS_WP_GPIO 58 -#ifndef __PRE_RAM__ -#include - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -33,7 +31,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif int get_write_protect_state(void) { diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl index e9fd212e8d..5ca7cfb64b 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl @@ -19,7 +19,7 @@ Scope (\_SB.PCI0.I2C0) Device (RTEK) { Name (_HID, "10EC5650") - Name (_CID, "10EC5650") + Name (_CID, "INTCCFFD") Name (_DDN, "RTEK Codec Controller ") Name (_UID, 1) diff --git a/src/mainboard/google/beltino/mainboard.c b/src/mainboard/google/beltino/mainboard.c index 7bda2f6694..f193d83de9 100644 --- a/src/mainboard/google/beltino/mainboard.c +++ b/src/mainboard/google/beltino/mainboard.c @@ -17,11 +17,9 @@ #include #include #include -#include #include #include #include -#include #include #include diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 70a8c1928a..f2066647d0 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -16,7 +16,7 @@ #include #include -#include +#include #include #include #include @@ -67,7 +67,7 @@ const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -130,7 +130,6 @@ void mainboard_romstage_entry(unsigned long bist) .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], - .bist = bist, }; /* Early SuperIO setup */ diff --git a/src/mainboard/google/beltino/smihandler.c b/src/mainboard/google/beltino/smihandler.c index e786ef56fd..d2f923a7cf 100644 --- a/src/mainboard/google/beltino/smihandler.c +++ b/src/mainboard/google/beltino/smihandler.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include "onboard.h" diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 2825aae553..1f5939eddb 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include @@ -66,18 +65,17 @@ int get_recovery_mode_switch(void) { int ec_rec_mode = 0; -#if FORCE_RECOVERY_MODE - printk(BIOS_DEBUG,"FORCING RECOVERY MODE.\n"); - return 1; -#endif - - -#ifndef __PRE_RAM__ - if (ec_mem_read(EC_CODE_STATE) == EC_COS_EC_RO) { - ec_rec_mode = 1; + if (FORCE_RECOVERY_MODE) { + printk(BIOS_DEBUG, "FORCING RECOVERY MODE.\n"); + return 1; + } + + if (ENV_RAMSTAGE) { + if (ec_mem_read(EC_CODE_STATE) == EC_COS_EC_RO) + ec_rec_mode = 1; + + printk(BIOS_DEBUG, "RECOVERY MODE FROM EC: %x\n", ec_rec_mode); } - printk(BIOS_DEBUG,"RECOVERY MODE FROM EC: %x\n", ec_rec_mode); -#endif return ec_rec_mode; } diff --git a/src/mainboard/google/butterfly/gma-mainboard.ads b/src/mainboard/google/butterfly/gma-mainboard.ads index d4a5d7d990..e45320f36e 100644 --- a/src/mainboard/google/butterfly/gma-mainboard.ads +++ b/src/mainboard/google/butterfly/gma-mainboard.ads @@ -28,7 +28,6 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal, - others => Disabled); + Internal); end GMA.Mainboard; diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index c298689639..067ea4ef94 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include "onboard.h" #include "ec.h" diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index 7c66e947fc..f73b9e6539 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -122,9 +122,9 @@ static void set_dimm_info(const uint8_t *spd, struct dimm_info *dimm) const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; - int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; - int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; - int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; + int ranks = spd_ranks[(spd[DDR3_ORGANIZATION] >> 3) & 7]; + int devw = spd_devw[spd[DDR3_ORGANIZATION] & 7]; + int busw = spd_busw[spd[DDR3_BUS_DEV_WIDTH] & 7]; void *hob_list_ptr; EFI_HOB_GUID_TYPE *hob_ptr; diff --git a/src/mainboard/google/dragonegg/smihandler.c b/src/mainboard/google/dragonegg/smihandler.c index 9c72cb694e..8d2afd60b7 100644 --- a/src/mainboard/google/dragonegg/smihandler.c +++ b/src/mainboard/google/dragonegg/smihandler.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include void mainboard_smi_espi_handler(void) diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index deeca1503f..a2ed3d86f9 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -8,7 +8,6 @@ config BOARD_GOOGLE_BASEBOARD_DRALLION select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI select EC_GOOGLE_WILCO - select GENERIC_SPD_BIN select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES @@ -19,11 +18,9 @@ config BOARD_GOOGLE_BASEBOARD_DRALLION select SOC_INTEL_COMETLAKE select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE - select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP select TPM2 select MAINBOARD_USES_IFD_EC_REGION - select MAINBOARD_USES_IFD_GBE_REGION select USE_SAR select SAR_ENABLE @@ -64,7 +61,9 @@ config POWER_OFF_ON_CR50_UPDATE config GBB_HWID string depends on CHROMEOS - default "DRALLION TEST 3556" + default "ARCADACML TEST 2699" if BOARD_GOOGLE_ARCADA_CML + default "SARIENCML TEST 3111" if BOARD_GOOGLE_SARIEN_CML + default "DRALLION TEST 4932" if BOARD_GOOGLE_DRALLION config MAINBOARD_DIR string @@ -72,11 +71,15 @@ config MAINBOARD_DIR config MAINBOARD_FAMILY string - default "Google_Drallion" + default "Google_Arcada_cml" if BOARD_GOOGLE_ARCADA_CML + default "Google_Sarien_cml" if BOARD_GOOGLE_SARIEN_CML + default "Google_Drallion" if BOARD_GOOGLE_DRALLION config MAINBOARD_PART_NUMBER string - default "Drallion" + default "Arcada_cml" if BOARD_GOOGLE_ARCADA_CML + default "Sarien_cml" if BOARD_GOOGLE_SARIEN_CML + default "Drallion" if BOARD_GOOGLE_DRALLION config MAINBOARD_VENDOR string @@ -92,7 +95,9 @@ config UART_FOR_CONSOLE config VARIANT_DIR string - default "drallion" + default "arcada_cml" if BOARD_GOOGLE_ARCADA_CML + default "sarien_cml" if BOARD_GOOGLE_SARIEN_CML + default "drallion" if BOARD_GOOGLE_DRALLION config DEVICETREE string diff --git a/src/mainboard/google/drallion/Kconfig.name b/src/mainboard/google/drallion/Kconfig.name index bd5d9032d2..e67b9156b8 100644 --- a/src/mainboard/google/drallion/Kconfig.name +++ b/src/mainboard/google/drallion/Kconfig.name @@ -1,5 +1,13 @@ comment "Drallion" +config BOARD_GOOGLE_ARCADA_CML + bool "-> Arcada_cml" + select BOARD_GOOGLE_BASEBOARD_DRALLION + +config BOARD_GOOGLE_SARIEN_CML + bool "-> Sarien_cml" + select BOARD_GOOGLE_BASEBOARD_DRALLION + config BOARD_GOOGLE_DRALLION bool "-> Drallion" select BOARD_GOOGLE_BASEBOARD_DRALLION diff --git a/src/mainboard/google/drallion/Makefile.inc b/src/mainboard/google/drallion/Makefile.inc index c16e7d203d..6f4f169f0e 100644 --- a/src/mainboard/google/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/Makefile.inc @@ -16,7 +16,6 @@ bootblock-y += bootblock.c ramstage-y += ramstage.c -ramstage-y += sku.c romstage-y += romstage.c @@ -34,5 +33,10 @@ ramstage-y += ec.c romstage-y += ec.c verstage-y += ec.c +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +subdirs-y += spd diff --git a/src/mainboard/google/drallion/chromeos.c b/src/mainboard/google/drallion/chromeos.c index 7aaf4015b5..0eb311bb9d 100644 --- a/src/mainboard/google/drallion/chromeos.c +++ b/src/mainboard/google/drallion/chromeos.c @@ -122,6 +122,6 @@ void mainboard_prepare_cr50_reset(void) { #if ENV_RAMSTAGE /* Ensure system powers up after CR50 reset */ - pmc_set_afterg3(MAINBOARD_POWER_STATE_ON); + pmc_soc_set_afterg3_en(true); #endif } diff --git a/src/mainboard/google/drallion/chromeos.fmd b/src/mainboard/google/drallion/chromeos.fmd index ece0eda099..8bab919c6d 100644 --- a/src/mainboard/google/drallion/chromeos.fmd +++ b/src/mainboard/google/drallion/chromeos.fmd @@ -1,27 +1,26 @@ FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x400000 { + SI_ALL@0x0 0x438000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x100000 - SI_GBE(PRESERVE)@0x101000 0x2000 - SI_ME@0x103000 0x2f9000 - SI_PDR(PRESERVE)@0x3fc000 0x4000 + SI_ME@0x101000 0x333000 + SI_PDR(PRESERVE)@0x434000 0x4000 } - SI_BIOS@0x400000 0x1c00000 { - RW_DIAG@0x0 0x12d0000 { - RW_LEGACY(CBFS)@0x0 0x12c0000 - DIAG_NVRAM@0x12c0000 0x10000 + SI_BIOS@0x438000 0x1bc8000 { + RW_DIAG@0x0 0x1298000 { + RW_LEGACY(CBFS)@0x0 0x1288000 + DIAG_NVRAM@0x1288000 0x10000 } - RW_SECTION_A@0x12d0000 0x280000 { + RW_SECTION_A@0x1298000 0x280000 { VBLOCK_A@0x0 0x10000 FW_MAIN_A(CBFS)@0x10000 0x26ffc0 RW_FWID_A@0x27ffc0 0x40 } - RW_SECTION_B@0x1550000 0x280000 { + RW_SECTION_B@0x1518000 0x280000 { VBLOCK_B@0x0 0x10000 FW_MAIN_B(CBFS)@0x10000 0x26ffc0 RW_FWID_B@0x27ffc0 0x40 } - RW_MISC@0x17d0000 0x30000 { + RW_MISC@0x1798000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 @@ -34,7 +33,7 @@ FLASH@0xfe000000 0x2000000 { RW_VPD(PRESERVE)@0x28000 0x2000 RW_NVRAM(PRESERVE)@0x2a000 0x6000 } - WP_RO@0x1800000 0x400000 { + WP_RO@0x17c8000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x3f0000 { diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c index 20eee7f34b..03bc17f185 100644 --- a/src/mainboard/google/drallion/romstage.c +++ b/src/mainboard/google/drallion/romstage.c @@ -16,6 +16,9 @@ #include #include #include +#include + +void __weak variant_mainboard_post_init_params(FSPM_UPD *mupd) {} static const struct cnl_mb_cfg memcfg = { /* Access memory info through SMBUS. */ @@ -55,9 +58,18 @@ static const struct cnl_mb_cfg memcfg = { .vref_ca_config = 2, }; +const struct cnl_mb_cfg * __weak get_variant_memory_cfg(struct cnl_mb_cfg *mem_cfg) +{ + return &memcfg; +} + void mainboard_memory_init_params(FSPM_UPD *memupd) { + struct cnl_mb_cfg board_memcfg; + + variant_mainboard_post_init_params(memupd); + wilco_ec_romstage_init(); - cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); + cannonlake_memcfg_init(&memupd->FspmConfig, get_variant_memory_cfg(&board_memcfg)); } diff --git a/src/mainboard/google/drallion/smihandler.c b/src/mainboard/google/drallion/smihandler.c index 0efcaa9ef1..18dbfbc154 100644 --- a/src/mainboard/google/drallion/smihandler.c +++ b/src/mainboard/google/drallion/smihandler.c @@ -15,7 +15,7 @@ #include #include -#include +#include #include void mainboard_smi_espi_handler(void) diff --git a/src/mainboard/google/drallion/spd/Makefile.inc b/src/mainboard/google/drallion/spd/Makefile.inc new file mode 100644 index 0000000000..e35544bc7d --- /dev/null +++ b/src/mainboard/google/drallion/spd/Makefile.inc @@ -0,0 +1,34 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +ifeq ($(SPD_SOURCES),) + SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this) +else + SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) +endif + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/drallion/spd/empty_ddr4.spd.hex b/src/mainboard/google/drallion/spd/empty_ddr4.spd.hex new file mode 100644 index 0000000000..67b46cd239 --- /dev/null +++ b/src/mainboard/google/drallion/spd/empty_ddr4.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 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00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/drallion/spd/hynix_dimm_H5AN8G6NCJR-VKC.spd.hex b/src/mainboard/google/drallion/spd/hynix_dimm_H5AN8G6NCJR-VKC.spd.hex new file mode 100644 index 0000000000..50506476fb --- /dev/null +++ b/src/mainboard/google/drallion/spd/hynix_dimm_H5AN8G6NCJR-VKC.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 87 2E +0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 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00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/drallion/spd/hynix_dimm_H5ANAG6NCMR-VKC.spd.hex b/src/mainboard/google/drallion/spd/hynix_dimm_H5ANAG6NCMR-VKC.spd.hex new file mode 100644 index 0000000000..bd226e1839 --- /dev/null +++ b/src/mainboard/google/drallion/spd/hynix_dimm_H5ANAG6NCMR-VKC.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 91 08 00 60 00 03 01 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04 +16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 43 CE +0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 EF 55 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 AD 01 00 00 00 00 00 00 48 4D 41 41 31 47 53 +36 43 4D 52 38 4E 2D 56 4B 20 20 20 20 00 80 AD +FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KNR-075E.spd.hex b/src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KNR-075E.spd.hex new file mode 100644 index 0000000000..334ec9aed4 --- /dev/null +++ b/src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KNR-075E.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 00 08 00 60 00 03 01 03 00 00 +00 00 06 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 60 8D +0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 7D 21 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 2C 00 00 00 00 00 00 00 34 41 54 53 31 47 36 +34 48 5A 2D 32 47 36 45 31 20 20 20 20 31 80 2C +45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/drallion/spd/micron_dimm_MT40A512M16LY-075E.spd.hex b/src/mainboard/google/drallion/spd/micron_dimm_MT40A512M16LY-075E.spd.hex new file mode 100644 index 0000000000..410cac071e --- /dev/null +++ b/src/mainboard/google/drallion/spd/micron_dimm_MT40A512M16LY-075E.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 06 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 60 5B +0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 2C 00 00 00 00 00 00 00 34 41 54 46 35 31 32 +36 34 48 5A 2D 32 47 36 45 31 20 20 20 31 80 2C +45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/drallion/spd/micron_dimm_MT40A512M16TB-062EJ.spd.hex b/src/mainboard/google/drallion/spd/micron_dimm_MT40A512M16TB-062EJ.spd.hex new file mode 100644 index 0000000000..dd6806c2db --- /dev/null +++ b/src/mainboard/google/drallion/spd/micron_dimm_MT40A512M16TB-062EJ.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 30 53 +0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 2C 00 00 00 00 00 00 00 34 41 54 46 35 31 32 +36 34 48 5A 2D 33 47 32 4A 31 20 20 20 31 80 2C +4A 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/drallion/spd/samsung_dimm_K4A8G165WC-BCTD.spd.hex b/src/mainboard/google/drallion/spd/samsung_dimm_K4A8G165WC-BCTD.spd.hex new file mode 100644 index 0000000000..8620d536a7 --- /dev/null +++ b/src/mainboard/google/drallion/spd/samsung_dimm_K4A8G165WC-BCTD.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 87 2E +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 35 32 +34 34 43 42 30 2D 43 54 44 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/drallion/spd/samsung_dimm_K4AAG165WB-MCTD.spd.hex b/src/mainboard/google/drallion/spd/samsung_dimm_K4AAG165WB-MCTD.spd.hex new file mode 100644 index 0000000000..da1e1981a4 --- /dev/null +++ b/src/mainboard/google/drallion/spd/samsung_dimm_K4AAG165WB-MCTD.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 00 08 00 60 00 03 01 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04 +16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 D0 4E +0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 EF 55 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 31 4B +34 33 42 42 31 2D 43 54 44 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc b/src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc new file mode 100644 index 0000000000..b979be187e --- /dev/null +++ b/src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2018 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +## GPP_F12-F16 indicates mem_id to match specific spd file +SPD_SOURCES = empty_ddr4 # 0b00000 + +bootblock-y += gpio.c +ramstage-y += gpio.c +romstage-y += gpio.c +verstage-y += gpio.c + +ramstage-y += sku.c diff --git a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb new file mode 100644 index 0000000000..5f396fe353 --- /dev/null +++ b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb @@ -0,0 +1,395 @@ +chip soc/intel/cannonlake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "PMC_GPP_A" + register "gpe0_dw1" = "PMC_GPP_C" + register "gpe0_dw2" = "PMC_GPP_D" + + # EC host command ranges + register "gen1_dec" = "0x00040931" # 0x930-0x937 + register "gen2_dec" = "0x00040941" # 0x940-0x947 + register "gen3_dec" = "0x000c0951" # 0x950-0x95f + + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "HeciEnabled" = "0" + register "SataSalpSupport" = "1" + register "SataMode" = "Sata_AHCI" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[2]" = "1" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "4" # 4s + register "PchPmSlpSusMinAssert" = "4" # 4s + register "PchPmSlpAMinAssert" = "4" # 2s + register "PchUnlockGpioPads" = "1" + + register "speed_shift_enable" = "1" + register "psys_pmax" = "140" + register "s0ix_enable" = "1" + register "dptf_enable" = "1" + register "satapwroptimize" = "1" + register "tdp_pl1_override" = "25" + register "tdp_pl2_override" = "51" + register "Device4Enable" = "1" + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRateForIa" = "2" + register "SlowSlewRateForGt" = "2" + register "SlowSlewRateForSa" = "0" + register "SlowSlewRateForFivr" = "2" + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + # Enable DDC for DDI port B + register "DdiPortBDdc" = "1" + + # Disable iDisplay codec enumeration + register "PchHdaIDispCodecDisconnect" = "1" + register "PchHdaAudioLinkHda" = "1" + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 6A | 70A | 31A | 31A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | + #| DcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | + #+----------------+-------+-------+-------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(6), + .voltage_limit = 1520, + .ac_loadline = 1030, + .dc_loadline = 1030, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(70), + .voltage_limit = 1520, + .ac_loadline = 180, + .dc_loadline = 180, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + # Intel Common SoC Config + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port + register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Left Type-A Port + register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port + register "usb2_ports[3]" = "USB2_PORT_EMPTY" + register "usb2_ports[4]" = "USB2_PORT_EMPTY" + register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera + register "usb2_ports[6]" = "{ + .enable = 1, \ + .ocpin = OC_SKIP, \ + .tx_bias = USB2_BIAS_0MV, \ + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_28P15MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ + }" # WWAN + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Left Type-A Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN + register "usb3_ports[4]" = "USB3_PORT_EMPTY" + register "usb3_ports[5]" = "USB3_PORT_EMPTY" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| I2C0 | Touchscreen | + #| I2C1 | Touchpad | + #| I2C4 | H1 TPM | + #+-------------------+---------------------------+ + + register "tcc_offset" = "1" + + # PCH Thermal Trip Temperature in deg C + register "common_soc_config.pch_thermal_trip" = "77" + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 52, + .fall_time_ns = 110, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 52, + .fall_time_ns = 110, + .data_hold_time_ns = 330, + }, + .i2c[4] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 36, + .fall_time_ns = 99, + }, + }" + + # PCIe port 10 for M.2 2230 WLAN + register "PcieRpEnable[9]" = "1" + register "PcieClkSrcUsage[2]" = "9" + register "PcieClkSrcClkReq[2]" = "2" + + # PCIe port 11 for card reader + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + register "PcieClkSrcUsage[1]" = "10" + register "PcieClkSrcClkReq[1]" = "1" + + # PCIe port 13 for M.2 2280 SSD + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + register "PcieClkSrcUsage[4]" = "12" + register "PcieClkSrcClkReq[4]" = "4" + + # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 13.0 on # Integrated Sensor Hub + chip drivers/intel/ish + register "firmware_name" = ""arcada_ish.bin"" + device generic 0 on end + end + end + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""USH"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.7 on end + end + chip drivers/usb/acpi + register "desc" = ""Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.8 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H15)" + device usb 2.9 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.3 on end + end + end + end + end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + chip drivers/intel/wifi + register "wake" = "PME_B0_EN_BIT" + device pci 14.3 on end # CNVi wifi + end + device pci 14.5 off end # SDCard + device pci 15.0 on + chip drivers/i2c/hid + register "generic.hid" = ""WCOM48E2"" + register "generic.desc" = ""Wacom Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "generic.reset_delay_ms" = "120" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "generic.enable_delay_ms" = "55" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 0A on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "probed" = "1" + device i2c 2c on end + end + end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)" + device i2c 50 on end + end + end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off end # PCI Express Port 1 (USB) + device pci 1c.1 off end # PCI Express Port 2 (USB) + device pci 1c.2 off end # PCI Express Port 3 (USB) + device pci 1c.3 off end # PCI Express Port 4 (USB) + device pci 1c.4 off end # PCI Express Port 5 (USB) + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" + end # PCI Express Port 9 + device pci 1d.1 on end # PCI Express Port 10 + device pci 1d.2 on end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 on + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" + end # PCI Express Port 13 (x4) + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on + chip ec/google/wilco + device pnp 0c09.0 on end + end + end # LPC/eSPI + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/google/drallion/variants/arcada_cml/gpio.c b/src/mainboard/google/drallion/variants/arcada_cml/gpio.c new file mode 100644 index 0000000000..ff0240c991 --- /dev/null +++ b/src/mainboard/google/drallion/variants/arcada_cml/gpio.c @@ -0,0 +1,279 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { +/* RCIN# */ PAD_NC(GPP_A0, NONE), +/* ESPI_IO0 */ +/* ESPI_IO1 */ +/* ESPI_IO2 */ +/* ESPI_IO3 */ +/* ESPI_CS# */ +/* SERIRQ */ +/* PIRQA# */ PAD_NC(GPP_A7, NONE), +/* CLKRUN# */ PAD_NC(GPP_A8, NONE), +/* ESPI_CLK */ +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), +/* PME# */ PAD_NC(GPP_A11, NONE), + /* ISH_LID_CL#_TAB */ +/* ISH_GP6 */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF2), +/* SUSWARN# */ PAD_NC(GPP_A13, NONE), +/* ESPI_RESET# */ +/* SUSACK# */ PAD_NC(GPP_A15, NONE), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), + /* ISH_ACC1_INT# */ +/* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* ISH_ACC2_INT# */ +/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), + /* ISH_NB_MODE */ +/* ISH_GP4 */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), + /* ISH_LID_CL#_NB */ +/* ISH_GP5 */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + +/* CORE_VID0 */ +/* CORE_VID1 */ +/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ +/* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ + /* LAN_CLKREQ_CPU_N */ +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + /* CARD_CLKREQ_CPU_N */ +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* WLAN_CLKREQ_CPU_N */ +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* WWAN_CLKREQ_CPU_N */ +/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* SSD_CKLREQ_CPU_N */ +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* TBT_CLKREQ_CPU_N (nostuff) */ +/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */ +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), /* PRIM_CORE_OPT_DIS (nostuff) */ +/* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, DEEP), /* ONE_DIMM# */ +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* RTC_DET# */ +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */ +/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), +/* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K), + +/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* MEM_SMBCLK */ +/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* MEM_SMBDATA */ +/* SMBALERT# */ PAD_NC(GPP_C2, DN_20K), +/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_SMBCLK */ +/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_SMBDATA */ +/* SML0ALERT# */ PAD_NC(GPP_C5, DN_20K), +/* SM1CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1_SMBCLK */ +/* SM1DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_SMBDATA */ +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), /* PCH_TBT_PERST# (nostuff) */ +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */ +/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */ +/* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP, + EDGE_SINGLE), /* SIO_EXT_WAKE# */ +/* UART1_TXD */ PAD_NC(GPP_C13, NONE), +/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* LCD_CBL_DET# */ +/* UART1_CTS# */ PAD_NC(GPP_C15, NONE), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TS_I2C_SDA */ +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TS_I2C_SCL */ +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA_TP */ +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCK_TP */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ +/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), +/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, + LEVEL, NONE), /* TS_INT# */ + +/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */ +/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), +/* SPI1_MISO */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), /* ISH_LAN# */ +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* TBT_FORCE_PWR (nostuff) */ + /* ISH_I2C0_ACC_SDA */ +/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* ISH_I2C0_ACC_SCL */ +/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CS# */ PAD_CFG_GPI(GPP_D9, NONE, DEEP), /* IR_CAM_DET# */ +/* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE), +/* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */ +/* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE), + /* ISH_CPU_UART0_RX */ +/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, UP_20K, DEEP, NF1), + /* ISH_CPU_UART0_TX */ +/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), +/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */ +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */ +/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ +/* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE), +/* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE), +/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 1, DEEP), /* WWAN_BB_RST# */ +/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* WWAN_GPIO_PERST# */ +/* I2S_MCLK */ PAD_CFG_GPI_SCI_LOW(GPP_D23, NONE, DEEP, + EDGE_SINGLE), /* WWAN_GPIO_WAKE# */ + +/* SATAXPCIE0 */ PAD_NC(GPP_E0, NONE), + /* M3042_PCIE#_SATA */ +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* M2880_PCIE_SATA# */ +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), +/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */ +/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */ +/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */ +/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ +/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */ +/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */ +/* USB2_OC2# */ PAD_NC(GPP_E11, NONE), +/* USB2_OC3# */ PAD_NC(GPP_E12, NONE), +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DP_HPD_CPU */ +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP2_HPD_CPU */ +/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ +/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */ +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_SCL_CPU */ +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_SDA_CPU */ +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), +/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), + +/* CNV_PA_BLANKING */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_COEX3 */ +/* GPP_F1 */ PAD_NC(GPP_F1, NONE), +/* GPP_F2 */ PAD_NC(GPP_F2, NONE), +/* GPP_F3 */ PAD_NC(GPP_F3, NONE), +/* CNV_BRI_DT */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), +/* CNV_BRI_RSP */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), +/* CNV_RGI_DT */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), +/* CNV_RGI_RSP */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), +/* CNV_MFUART2_RXD */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* CNV_COEX2 */ +/* CNV_MFUART2_TXD */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* CNV_COEX1 */ +/* GPP_F10 */ PAD_NC(GPP_F10, NONE), +/* EMMC_CMD */ PAD_NC(GPP_F11, NONE), +/* EMMC_DATA0 */ PAD_NC(GPP_F12, NONE), +/* EMMC_DATA1 */ PAD_NC(GPP_F13, NONE), +/* EMMC_DATA2 */ PAD_NC(GPP_F14, NONE), +/* EMMC_DATA3 */ PAD_NC(GPP_F15, NONE), +/* EMMC_DATA4 */ PAD_NC(GPP_F16, NONE), +/* EMMC_DATA5 */ PAD_NC(GPP_F17, NONE), +/* EMMC_DATA6 */ PAD_NC(GPP_F18, NONE), +/* EMMC_DATA7 */ PAD_NC(GPP_F19, NONE), +/* EMMC_RCLK */ PAD_NC(GPP_F20, NONE), +/* EMMC_CLK */ PAD_NC(GPP_F21, NONE), +/* EMMC_RESET# */ PAD_NC(GPP_F22, NONE), +/* A4WP_PRESENT */ PAD_NC(GPP_F23, NONE), + +/* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */ +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), /* ANT_CONFIG (nostuff) */ +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), /* TBT_CIO_PLUG_EVT# (nostuff) */ +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */ +/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */ +/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */ +/* SD_WP */ PAD_CFG_GPI(GPP_G7, NONE, DEEP), /* SPK_DET# */ + +/* I2S2_SCLK */ PAD_NC(GPP_H0, NONE), +/* I2S2_SFRM */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# */ +/* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* CLKREQ_CNV# */ +/* I2S2_RXD */ PAD_NC(GPP_H3, NONE), +/* I2C2_SDA */ PAD_NC(GPP_H4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_H5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_H6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_H7, NONE), +/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ +/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ +/* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* ISH_I2C2_SDA */ +/* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* ISH_I2C2_SCL */ +/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), +/* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */ +/* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE), +/* DPPF_CTRLDATA */ PAD_NC(GPP_H17, NONE), +/* CPU_C10_GATE# */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* C10_GATE# */ +/* TIMESYNC0 */ PAD_NC(GPP_H19, NONE), +/* IMGCLKOUT1 */ PAD_NC(GPP_H20, NONE), +/* GPP_H21 */ PAD_NC(GPP_H21, NONE), +/* GPP_H22 */ PAD_NC(GPP_H22, NONE), /* RTD3_CIO_PWR_EN (nostuff) */ +/* GPP_H23 */ PAD_NC(GPP_H23, NONE), + +/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */ +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* AC_PRESENT */ +/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* LAN_WAKE# */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* SIO_PWRBTN# */ +/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */ +/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */ +/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */ +/* GPD7 */ PAD_NC(GPD7, NONE), /* TBT_RTD3_WAKE# (nostuff) */ +/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUSCLK */ +/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* SIO_SLP_WLAN# */ +/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* SIO_SLP_S5# */ +/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), /* PM_LANPHY_EN */ +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { +/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ +/* SSD RESET pin will stay low first */ +/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ +/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ +/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ +/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ +/* RESET# need to stay low before FULL_CARD_POWER_OFF assert */ +/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */ +/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ +/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ +/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ +/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */ +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/acpi/dptf.asl b/src/mainboard/google/drallion/variants/arcada_cml/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..73e1decc1b --- /dev/null +++ b/src/mainboard/google/drallion/variants/arcada_cml/include/variant/acpi/dptf.asl @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 98 +#define DPTF_CPU_CRITICAL 108 + +/* Skin Sensor for CPU VR temperature monitor */ +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "Skin" +#define DPTF_TSR0_PASSIVE 55 +#define DPTF_TSR0_CRITICAL 100 + +/* Memory Sensor for DDR temperature monitor */ +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "DDR" +#define DPTF_TSR1_PASSIVE 53 +#define DPTF_TSR1_CRITICAL 100 + +/* M.2 Sensor for Ambient temperature monitor */ +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "Ambient" +#define DPTF_TSR2_PASSIVE 38 +#define DPTF_TSR2_CRITICAL 93 + +#undef DPTF_ENABLE_FAN_CONTROL +#undef DPTF_ENABLE_CHARGER + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 500, 100, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Skin (TSR0) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 400, 40, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on DDR (TSR1) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 300, 50, 2, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR2) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 1000, 100, 1, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 21000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 51000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + } +}) diff --git a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/acpi/mainboard.asl b/src/mainboard/google/drallion/variants/arcada_cml/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000000..41121d28fe --- /dev/null +++ b/src/mainboard/google/drallion/variants/arcada_cml/include/variant/acpi/mainboard.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define CAM_EN GPP_B11 /* Active low */ +#define TS_PD GPP_E7 + +/* Method called from LPIT prior to enter s0ix state */ +Method (MS0X, 1) +{ + If (Arg0) { + /* Turn off camera power */ + \_SB.PCI0.STXS (CAM_EN) + } Else { + /* Turn on camera power */ + \_SB.PCI0.CTXS (CAM_EN) + } +} + +/* Method called from _PTS prior to enter sleep state */ +Method (MPTS, 1) +{ + \_SB.PCI0.LPCB.EC0.PTS (Arg0) + + /* Clear touch screen pd pin to avoid leakage */ + \_SB.PCI0.CTXS (TS_PD) +} + +/* Method called from _WAK prior to wakeup */ +Method (MWAK, 1) +{ + \_SB.PCI0.LPCB.EC0.WAK (Arg0) +} diff --git a/src/cpu/intel/model_206ax/tsc_freq.c b/src/mainboard/google/drallion/variants/arcada_cml/include/variant/ec.h similarity index 60% rename from src/cpu/intel/model_206ax/tsc_freq.c rename to src/mainboard/google/drallion/variants/arcada_cml/include/variant/ec.h index 545ca5f106..01a17b5f99 100644 --- a/src/cpu/intel/model_206ax/tsc_freq.c +++ b/src/mainboard/google/drallion/variants/arcada_cml/include/variant/ec.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. + * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,15 +13,22 @@ * GNU General Public License for more details. */ -#include -#include -#include -#include "model_206ax.h" +#ifndef VARIANT_EC_H +#define VARIANT_EC_H -unsigned long tsc_freq_mhz(void) -{ - msr_t platform_info; +#include +#include - platform_info = rdmsr(MSR_PLATFORM_INFO); - return SANDYBRIDGE_BCLK * ((platform_info.lo >> 8) & 0xff); -} +/* EC wake pin */ +#define EC_WAKE_PIN GPE0_DW1_12 + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* Enable PS/2 keyboard */ +#define SIO_EC_ENABLE_PS2K + +/* Enable DPTF */ +#define EC_ENABLE_DPTF + +#endif diff --git a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/gpio.h b/src/mainboard/google/drallion/variants/arcada_cml/include/variant/gpio.h new file mode 100644 index 0000000000..f7e0403e59 --- /dev/null +++ b/src/mainboard/google/drallion/variants/arcada_cml/include/variant/gpio.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include +#include + +/* Flash Write Protect */ +#define GPIO_PCH_WP GPP_E15 + +/* Recovery mode */ +#define GPIO_REC_MODE GPP_E8 + +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); + +struct cros_gpio; +const struct cros_gpio *variant_cros_gpios(size_t *num); + +#endif diff --git a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/hda_verb.h b/src/mainboard/google/drallion/variants/arcada_cml/include/variant/hda_verb.h new file mode 100644 index 0000000000..10fbaf13f5 --- /dev/null +++ b/src/mainboard/google/drallion/variants/arcada_cml/include/variant/hda_verb.h @@ -0,0 +1,209 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_HDA_VERB_H +#define MAINBOARD_HDA_VERB_H + +#include + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0295, // Codec Vendor / Device ID: Realtek ALC3204 + 0xffffffff, // Subsystem ID + 0x0000002b, // Number of jacks (NID entries) + + /* Rest Codec First */ + AZALIA_RESET(0x1), + /* NID 0x01, HDA Codec Subsystem ID Verb Table */ + AZALIA_SUBVENDOR(0x0, 0x102808b6), + + /* Pin Widget Verb Table */ + AZALIA_PIN_CFG(0x0, 0x12, 0xb7a60130), + AZALIA_PIN_CFG(0x0, 0x13, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0x0, 0x16, 0x40000000), + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x19, 0x04a11030), + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1d, 0x40c00001), + AZALIA_PIN_CFG(0x0, 0x1e, 0x421212f2), + AZALIA_PIN_CFG(0x0, 0x21, 0x04211020), + + /* D reset */ + 0x0205003C, + 0x0204F254, + 0x0205003C, + 0x0204F214, + /* JD1 - 2port JD mode */ + 0x02050009, + 0x0204E003, + 0x0205000A, + 0x02047770, + /* Set TRS type-1 */ + 0x02050045, + 0x02045289, + 0x02050049, + 0x02040049, + /* Set TRS type-2 + Set UAJ Line2 vref(ALC3254) */ + 0x0205004A, + 0x0204A830, + 0x02050063, + 0x0204CF00, + /* NID 0x20 set class-D to 2W@4ohm (+12dB gain) + * + Set sine tone gain(0x34) */ + 0x02050038, + 0x02043909, + 0x05C50000, + 0x05C43482, + /* AGC-1 Disable + (Front Gain=0dB ) */ + 0x05D50006, + 0x05D44C50, + 0x05D50002, + 0x05D44004, + /* AGC-2 (Backt Boost Gain= -0.375dB ,Limiter = -3dB) */ + 0x05D50003, + 0x05D45E5E, + 0x05D50001, + 0x05D4D788, + /* AGC-3 + AGC Enable */ + 0x05D50009, + 0x05D451FF, + 0x05D50006, + 0x05D44E50, + /* HP-JD Enable +Nokia type */ + 0x0205004A, + 0x02042010, + 0x02050008, + 0x02046A0C, + /* EAPD set to verb-control + I2C Un-use+ DVDD3.3V */ + 0x02050010, + 0x02040020, + 0x02050034, + 0x0204A23D, + /* Class D silent detection Enable -84dB threshold */ + 0x02050030, + 0x02049000, + 0x02050037, + 0x0204FE15, + /* Disable EQ + set 250Hz 3rd High Pass filter */ + 0x05350000, + 0x0534203A, + 0x05350000, + 0x0534203A, + /* Left Channel-1 */ + 0x0535001d, + 0x05340800, + 0x0535001e, + 0x05340800, + /* Left Channel-2 */ + 0x05350003, + 0x05341EF8, + 0x05350004, + 0x05340000, + /* Left Channel-3 */ + 0x05350005, + 0x053403EE, + 0x05350006, + 0x0534FA60, + /* Left Channel-4 */ + 0x05350007, + 0x05341E10, + 0x05350008, + 0x05347B86, + /* Left Channel-5 */ + 0x05350009, + 0x053401F7, + 0x0535000A, + 0x05349FB6, + /* Left Channel-6 */ + 0x0535000B, + 0x05341C00, + 0x0535000C, + 0x05340000, + /* Left Channel-7 */ + 0x0535000D, + 0x05340200, + 0x0535000E, + 0x05340000, + /* Right Channel-1 */ + 0x05450000, + 0x05442000, + 0x0545001d, + 0x05440800, + /* Right Channel-2 */ + 0x0545001e, + 0x05440800, + 0x05450003, + 0x05441EF8, + /* Right Channel-3 */ + 0x05450004, + 0x05440000, + 0x05450005, + 0x054403EE, + /* Right Channel-4 */ + 0x05450006, + 0x0544FA60, + 0x05450007, + 0x05441E10, + /* Right Channel-5 */ + 0x05450008, + 0x05447B86, + 0x05450009, + 0x054401F7, + /* Right Channel-6 */ + 0x0545000A, + 0x05449FB6, + 0x0545000B, + 0x05441C00, + /* Right Channel-7 */ + 0x0545000C, + 0x05440000, + 0x0545000D, + 0x05440200, + /* Right Channel-8 + EQ Update & Enable */ + 0x0545000E, + 0x05440000, + 0x05350000, + 0x0534E03A, + /* Enable all Microphone */ + 0x0205000D, + 0x0204A023, + 0x0205000D, + 0x0204A023, + /* Enable Internal Speaker (NID14) */ + 0x0205000F, + 0x02040000, + 0x0205000F, + 0x02040000, +}; + +const u32 pc_beep_verbs[] = { + /* PCBeep pass through to NID14 for ePSA test-1 */ + 0x02050036, + 0x020477D7, + 0x0143B000, + 0x01470740, + /* PCBeep pass through to NID14 for ePSA test-2 */ + 0x01470C02, + 0x01470C02, + 0x01470C02, + 0x01470C02, +}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/variant.h b/src/mainboard/google/drallion/variants/arcada_cml/include/variant/variant.h new file mode 100644 index 0000000000..da1189e14c --- /dev/null +++ b/src/mainboard/google/drallion/variants/arcada_cml/include/variant/variant.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* Arcada is SKU ID 2 and 4 */ +#define VARIANT_SKU_ID 2 +#define VARIANT_SKU_NAME "sku2" +#define VARIANT_SKU_ID_SIGNED_EC 4 +#define VARIANT_SKU_NAME_SIGNED_EC "sku4" + +#endif diff --git a/src/mainboard/google/drallion/sku.c b/src/mainboard/google/drallion/variants/arcada_cml/sku.c similarity index 100% rename from src/mainboard/google/drallion/sku.c rename to src/mainboard/google/drallion/variants/arcada_cml/sku.c diff --git a/src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000000..eb1d9aec48 --- /dev/null +++ b/src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef BASEBOARD_VARIANTS_H +#define BASEBOARD_VARIANTS_H + +#include +#include + +void variant_mainboard_post_init_params(FSPM_UPD *mupd); + +/* Return board specific memory configuration */ +const struct cnl_mb_cfg *get_variant_memory_cfg(struct cnl_mb_cfg *mem_cfg); + +#endif /* BASEBOARD_VARIANTS_H */ diff --git a/src/mainboard/google/drallion/variants/drallion/Makefile.inc b/src/mainboard/google/drallion/variants/drallion/Makefile.inc index 2bf028eb1f..ef3d54d185 100644 --- a/src/mainboard/google/drallion/variants/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/variants/drallion/Makefile.inc @@ -13,7 +13,21 @@ ## GNU General Public License for more details. ## +## GPP_F12-F16 indicates mem_id to match specific spd file +SPD_SOURCES = empty_ddr4 # 0b00000 +SPD_SOURCES += micron_dimm_MT40A512M16LY-075E # 0b10100 +SPD_SOURCES += micron_dimm_MT40A512M16TB-062EJ # 0b11100 +SPD_SOURCES += micron_dimm_MT40A1G16KNR-075E # 0b10010 +SPD_SOURCES += hynix_dimm_H5AN8G6NCJR-VKC # 0b10001 +SPD_SOURCES += hynix_dimm_H5ANAG6NCMR-VKC # 0b11001 +SPD_SOURCES += samsung_dimm_K4A8G165WC-BCTD # 0b10011 +SPD_SOURCES += samsung_dimm_K4AAG165WB-MCTD # 0b11011 + bootblock-y += gpio.c ramstage-y += gpio.c romstage-y += gpio.c verstage-y += gpio.c + +romstage-y += memory.c + +ramstage-y += sku.c diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 575b61014b..d824a552d0 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -32,7 +32,6 @@ chip soc/intel/cannonlake register "psys_pmax" = "140" register "s0ix_enable" = "1" register "dptf_enable" = "1" - register "dmipwroptimize" = "1" register "satapwroptimize" = "1" register "tdp_pl1_override" = "25" register "tdp_pl2_override" = "51" @@ -50,6 +49,10 @@ chip soc/intel/cannonlake # Enable DDC for DDI port B register "DdiPortBDdc" = "1" + # Disable iDisplay codec enumeration + register "PchHdaIDispCodecDisconnect" = "1" + register "PchHdaAudioLinkHda" = "1" + # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | @@ -127,29 +130,22 @@ chip soc/intel/cannonlake }" # Intel Common SoC Config - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port - register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Left Type-A Port - register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port - register "usb2_ports[3]" = "USB2_PORT_EMPTY" - register "usb2_ports[4]" = "USB2_PORT_EMPTY" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port 2 + register "usb2_ports[2]" = "USB2_PORT_LONG(OC0)" # Right Type-A Port 1 + register "usb2_ports[3]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port 2 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WWAN register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera - register "usb2_ports[6]" = "{ - .enable = 1, \ - .ocpin = OC_SKIP, \ - .tx_bias = USB2_BIAS_0MV, \ - .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \ - .pre_emp_bias = USB2_BIAS_28P15MV, \ - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ - }" # WWAN - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[6]" = "USB2_PORT_EMPTY" + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Left Type-A Port - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN - register "usb3_ports[4]" = "USB3_PORT_EMPTY" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port 2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Right Type-A Port 1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port 2 + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Intel Common SoC Config @@ -185,22 +181,27 @@ chip soc/intel/cannonlake }, }" + # PCIe port 9 for Card Reader + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[4]" = "8" + register "PcieClkSrcClkReq[4]" = "4" + # PCIe port 10 for M.2 2230 WLAN register "PcieRpEnable[9]" = "1" - register "PcieClkSrcUsage[2]" = "9" - register "PcieClkSrcClkReq[2]" = "2" - - # PCIe port 11 for card reader - register "PcieRpEnable[10]" = "1" - register "PcieRpLtrEnable[10]" = "1" - register "PcieClkSrcUsage[1]" = "10" + register "PcieClkSrcUsage[1]" = "9" register "PcieClkSrcClkReq[1]" = "1" + # PCIe port 12 for M.2 3042 WWAN + register "PcieRpEnable[11]" = "1" + register "PcieClkSrcUsage[0]" = "11" + register "PcieClkSrcClkReq[0]" = "0" + # PCIe port 13 for M.2 2280 SSD register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" - register "PcieClkSrcUsage[4]" = "12" - register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcUsage[2]" = "12" + register "PcieClkSrcClkReq[2]" = "2" # GPIO PM programming register "gpio_override_pm" = "1" @@ -244,8 +245,8 @@ chip soc/intel/cannonlake device usb 2.0 on end end chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" - register "type" = "UPC_TYPE_A" + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(1, 2)" device usb 2.1 on end end @@ -256,24 +257,20 @@ chip soc/intel/cannonlake device usb 2.2 on end end chip drivers/usb/acpi - register "desc" = ""Camera"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.5 on end + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.3 on end end chip drivers/usb/acpi register "desc" = ""WWAN"" register "type" = "UPC_TYPE_INTERNAL" - device usb 2.6 on end + device usb 2.4 on end end chip drivers/usb/acpi - register "desc" = ""USH"" + register "desc" = ""Camera"" register "type" = "UPC_TYPE_INTERNAL" - device usb 2.7 on end - end - chip drivers/usb/acpi - register "desc" = ""Fingerprint"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.8 on end + device usb 2.5 on end end chip drivers/usb/acpi register "desc" = ""Bluetooth"" @@ -288,21 +285,27 @@ chip soc/intel/cannonlake device usb 3.0 on end end chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" + register "desc" = ""Right Type-A Port"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" + register "group" = "ACPI_PLD_GROUP(2, 1)" device usb 3.1 on end end chip drivers/usb/acpi register "desc" = ""Right Type-A Port"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(2, 1)" + register "group" = "ACPI_PLD_GROUP(2, 2)" device usb 3.2 on end end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.3 on end + end chip drivers/usb/acpi register "desc" = ""WWAN"" register "type" = "UPC_TYPE_INTERNAL" - device usb 3.3 on end + device usb 3.4 on end end end end @@ -328,6 +331,37 @@ chip soc/intel/cannonlake register "hid_desc_reg_offset" = "0x1" device i2c 0A on end end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN900C"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "generic.reset_delay_ms" = "10" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "generic.enable_delay_ms" = "55" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + register "generic.device_present_gpio" = "GPP_B4" + register "generic.device_present_gpio_invert" = "1" + device i2c 10 on end + end + chip drivers/i2c/generic + register "hid" = ""MLFS0000"" + register "desc" = ""Melfas Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "reset_delay_ms" = "10" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "enable_delay_ms" = "55" + register "has_power_resource" = "1" + register "device_present_gpio" = "GPP_B4" + register "device_present_gpio_invert" = "1" + device i2c 34 on end + end end # I2C #0 device pci 15.1 on chip drivers/i2c/generic @@ -369,8 +403,8 @@ chip soc/intel/cannonlake smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" end # PCI Express Port 9 device pci 1d.1 on end # PCI Express Port 10 - device pci 1d.2 on end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 on end # PCI Express Port 12 device pci 1d.4 on smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" end # PCI Express Port 13 (x4) diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index ff0240c991..5fba04b0b2 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -15,6 +15,9 @@ #include #include +#include +#include +#include /* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { @@ -24,33 +27,33 @@ static const struct pad_config gpio_table[] = { /* ESPI_IO2 */ /* ESPI_IO3 */ /* ESPI_CS# */ -/* SERIRQ */ -/* PIRQA# */ PAD_NC(GPP_A7, NONE), +/* SERIRQ */ PAD_NC(GPP_A6, NONE), +/* TPM_PIRQ#_A7 */ PAD_NC(GPP_A7, NONE), /* CLKRUN# */ PAD_NC(GPP_A8, NONE), /* ESPI_CLK */ /* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* PME# */ PAD_NC(GPP_A11, NONE), /* ISH_LID_CL#_TAB */ /* ISH_GP6 */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF2), -/* SUSWARN# */ PAD_NC(GPP_A13, NONE), +/* SUSWARN# */ PAD_CFG_GPO(GPP_A13, 0, DEEP), /* ESPI_RESET# */ -/* SUSACK# */ PAD_NC(GPP_A15, NONE), -/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), -/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), +/* SUSACK# */ PAD_CFG_GPO(GPP_A15, 0, DEEP), +/* SD_1P8_SEL */ PAD_CFG_GPI(GPP_A16, NONE, PLTRST), /* 2.7MM_CAM_DET# */ +/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF2), /* ISH_ACC1_INT# */ /* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* ISH_ACC2_INT# */ /* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), -/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), -/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP2 */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), +/* ISH_GP3 */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), /* ISH_NB_MODE */ /* ISH_GP4 */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), /* ISH_LID_CL#_NB */ /* ISH_GP5 */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), -/* CORE_VID0 */ -/* CORE_VID1 */ -/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), +/* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), +/* VRALERT# */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), /* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ /* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ @@ -64,110 +67,103 @@ static const struct pad_config gpio_table[] = { /* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* SSD_CKLREQ_CPU_N */ /* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* TBT_CLKREQ_CPU_N (nostuff) */ -/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */ +/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), +/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, PLTRST), /* 3.3V_CAM_EN# */ /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), -/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), /* PRIM_CORE_OPT_DIS (nostuff) */ -/* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, DEEP), /* ONE_DIMM# */ +/* GSPI0_CS# */ PAD_CFG_GPO(GPP_B15, 0, PLTRST), /* PRIM_CORE_OPT_DIS */ +/* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, PLTRST), /* ONE_DIMM# */ /* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* RTC_DET# */ /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), /* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ -/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */ -/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, PLTRST), /* PCH_3.3V_TS_EN */ /* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), /* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K), /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* MEM_SMBCLK */ /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* MEM_SMBDATA */ /* SMBALERT# */ PAD_NC(GPP_C2, DN_20K), -/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_SMBCLK */ -/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_SMBDATA */ -/* SML0ALERT# */ PAD_NC(GPP_C5, DN_20K), -/* SM1CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1_SMBCLK */ -/* SM1DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_SMBDATA */ -/* UART0_RXD */ PAD_NC(GPP_C8, NONE), /* PCH_TBT_PERST# (nostuff) */ -/* UART0_TXD */ PAD_NC(GPP_C9, NONE), -/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */ -/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */ -/* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP, - EDGE_SINGLE), /* SIO_EXT_WAKE# */ +/* SML0CLK */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), +/* UART0_RTS# */ PAD_CFG_GPO(GPP_C10, 1, PLTRST), /* WWAN_FULL_PWR_EN */ +/* UART0_CTS# */ PAD_NC(GPP_C11, NONE), +/* UART1_RXD */ PAD_NC(GPP_C12, NONE), /* UART1_TXD */ PAD_NC(GPP_C13, NONE), -/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* LCD_CBL_DET# */ +/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, PLTRST), /* LCD_CBL_DET# */ /* UART1_CTS# */ PAD_NC(GPP_C15, NONE), /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TS_I2C_SDA */ /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TS_I2C_SCL */ /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA_TP */ /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCK_TP */ -/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ -/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ -/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), +/* UART2_RXD */ PAD_NC(GPP_C20, NONE), +/* UART2_TXD */ PAD_NC(GPP_C21, NONE), +/* UART2_RTS# */ PAD_CFG_GPI(GPP_C22, NONE, PLTRST), /* SPK_DETECT */ /* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, LEVEL, NONE), /* TS_INT# */ /* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST, EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */ -/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), -/* SPI1_MISO */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), /* ISH_LAN# */ -/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), -/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* TBT_FORCE_PWR (nostuff) */ +/* SPI1_CLK */ PAD_CFG_GPI(GPP_D1, NONE, DEEP), /* VPRO_DET# */ +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), +/* SPI1_MOSI */ PAD_CFG_GPI(GPP_D3, NONE, PLTRST), /* RTC_DET# */ +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* ISH_I2C0_ACC_SDA */ /* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* ISH_I2C0_ACC_SCL */ /* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), -/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), -/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), -/* ISH_SPI_CS# */ PAD_CFG_GPI(GPP_D9, NONE, DEEP), /* IR_CAM_DET# */ +/* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), +/* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), +/* ISH_SPI_CS# */ PAD_CFG_GPI(GPP_D9, NONE, PLTRST), /* IR_CAM_DET# */ /* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE), -/* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */ +/* ISH_SPI_MISO */ PAD_NC(GPP_D11, NONE), /* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE), /* ISH_CPU_UART0_RX */ /* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, UP_20K, DEEP, NF1), /* ISH_CPU_UART0_TX */ /* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), -/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */ -/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), -/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */ +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_CFG_GPI(GPP_D16, NONE, PLTRST), +/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, PLTRST), /* KB_DET# */ /* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ /* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE), /* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE), -/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 1, DEEP), /* WWAN_BB_RST# */ +/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */ /* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* WWAN_GPIO_PERST# */ /* I2S_MCLK */ PAD_CFG_GPI_SCI_LOW(GPP_D23, NONE, DEEP, EDGE_SINGLE), /* WWAN_GPIO_WAKE# */ -/* SATAXPCIE0 */ PAD_NC(GPP_E0, NONE), +/* SATAXPCIE0 */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF2), /* HDD_DET# */ /* M3042_PCIE#_SATA */ -/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2), /* M2880_PCIE_SATA# */ -/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), -/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2), +/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, PLTRST), /* MEM_INTERLEAVED */ /* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */ /* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */ -/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */ -/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ +/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 0, PLTRST), /* TOUCH_SCREEN_PD# */ +/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */ /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */ -/* USB2_OC2# */ PAD_NC(GPP_E11, NONE), -/* USB2_OC3# */ PAD_NC(GPP_E12, NONE), +/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DP_HPD_CPU */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP2_HPD_CPU */ -/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ -/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */ +/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ +/* DDPE_HPD3 */ PAD_CFG_GPO(GPP_E16, 1, PLTRST), /* HDMI_PD# */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_SCL_CPU */ -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_SDA_CPU */ -/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), -/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), /* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), /* CNV_PA_BLANKING */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_COEX3 */ -/* GPP_F1 */ PAD_NC(GPP_F1, NONE), -/* GPP_F2 */ PAD_NC(GPP_F2, NONE), /* GPP_F3 */ PAD_NC(GPP_F3, NONE), /* CNV_BRI_DT */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_BRI_RSP */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), @@ -177,38 +173,31 @@ static const struct pad_config gpio_table[] = { /* CNV_MFUART2_TXD */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* CNV_COEX1 */ /* GPP_F10 */ PAD_NC(GPP_F10, NONE), /* EMMC_CMD */ PAD_NC(GPP_F11, NONE), -/* EMMC_DATA0 */ PAD_NC(GPP_F12, NONE), -/* EMMC_DATA1 */ PAD_NC(GPP_F13, NONE), -/* EMMC_DATA2 */ PAD_NC(GPP_F14, NONE), -/* EMMC_DATA3 */ PAD_NC(GPP_F15, NONE), -/* EMMC_DATA4 */ PAD_NC(GPP_F16, NONE), /* EMMC_DATA5 */ PAD_NC(GPP_F17, NONE), /* EMMC_DATA6 */ PAD_NC(GPP_F18, NONE), /* EMMC_DATA7 */ PAD_NC(GPP_F19, NONE), /* EMMC_RCLK */ PAD_NC(GPP_F20, NONE), /* EMMC_CLK */ PAD_NC(GPP_F21, NONE), /* EMMC_RESET# */ PAD_NC(GPP_F22, NONE), -/* A4WP_PRESENT */ PAD_NC(GPP_F23, NONE), - -/* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */ +/* A4WP_PRESENT */ PAD_CFG_NF(GPP_F23, NONE, PLTRST, NF1), +/* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, PLTRST), /* CAM_MIC */ /* SD_DATA0 */ PAD_NC(GPP_G1, NONE), /* ANT_CONFIG (nostuff) */ -/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), /* TBT_CIO_PLUG_EVT# (nostuff) */ +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), /* SD_DATA2 */ PAD_NC(GPP_G3, NONE), -/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */ -/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */ -/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */ -/* SD_WP */ PAD_CFG_GPI(GPP_G7, NONE, DEEP), /* SPK_DET# */ +/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, PLTRST), /* CTLESS_DET# */ +/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, PLTRST), /* HOST_SD_WP# */ +/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* AUD_PWR_EN */ +/* SD_WP */ PAD_CFG_GPI(GPP_G7, NONE, PLTRST), /* SPK_DET# */ /* I2S2_SCLK */ PAD_NC(GPP_H0, NONE), /* I2S2_SFRM */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# */ /* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* CLKREQ_CNV# */ -/* I2S2_RXD */ PAD_NC(GPP_H3, NONE), +/* I2S2_RXD */ PAD_CFG_GPI(GPP_H3, NONE, DEEP), /* CNVI_EN# */ /* I2C2_SDA */ PAD_NC(GPP_H4, NONE), -/* I2C2_SCL */ PAD_NC(GPP_H5, NONE), /* I2C3_SDA */ PAD_NC(GPP_H6, NONE), /* I2C3_SCL */ PAD_NC(GPP_H7, NONE), -/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ -/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ +/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), +/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* ISH_I2C2_SDA */ /* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* ISH_I2C2_SCL */ /* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), @@ -219,7 +208,7 @@ static const struct pad_config gpio_table[] = { /* TIMESYNC0 */ PAD_NC(GPP_H19, NONE), /* IMGCLKOUT1 */ PAD_NC(GPP_H20, NONE), /* GPP_H21 */ PAD_NC(GPP_H21, NONE), -/* GPP_H22 */ PAD_NC(GPP_H22, NONE), /* RTD3_CIO_PWR_EN (nostuff) */ +/* GPP_H22 */ PAD_NC(GPP_H22, NONE), /* GPP_H23 */ PAD_NC(GPP_H23, NONE), /* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */ @@ -229,11 +218,11 @@ static const struct pad_config gpio_table[] = { /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */ /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */ /* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */ -/* GPD7 */ PAD_NC(GPD7, NONE), /* TBT_RTD3_WAKE# (nostuff) */ +/* GPD7 */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUSCLK */ /* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* SIO_SLP_WLAN# */ /* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* SIO_SLP_S5# */ -/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), /* PM_LANPHY_EN */ +/* LANPHYC */ PAD_NC(GPD11, NONE), /* PM_LANPHY_EN */ }; /* Early pad configuration in bootblock */ @@ -241,10 +230,10 @@ static const struct pad_config early_gpio_table[] = { /* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ /* SSD RESET pin will stay low first */ /* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ -/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ -/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ -/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ -/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* SERVOTX_UART */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* SERVORX_UART */ +/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* SDA_PCH_H1 */ +/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* SCL_PCH_H1 */ /* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ /* RESET# need to stay low before FULL_CARD_POWER_OFF assert */ @@ -253,6 +242,14 @@ static const struct pad_config early_gpio_table[] = { /* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ /* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */ +/* GPP_F1 */ PAD_CFG_GPI(GPP_F1, NONE, DEEP), /* DDR_CHA_EN_1P8 */ +/* GPP_F2 */ PAD_CFG_GPI(GPP_F2, NONE, DEEP), /* DDR_CHB_EN_1P8 */ +/* EMMC_DATA0 */ PAD_CFG_GPI(GPP_F12, NONE, DEEP), /* MEM_CONFIGO_1P8 */ +/* EMMC_DATA1 */ PAD_CFG_GPI(GPP_F13, NONE, DEEP), /* MEM_CONFIGO_1P8 */ +/* EMMC_DATA2 */ PAD_CFG_GPI(GPP_F14, NONE, DEEP), /* MEM_CONFIGO_1P8 */ +/* EMMC_DATA3 */ PAD_CFG_GPI(GPP_F15, NONE, DEEP), /* MEM_CONFIGO_1P8 */ +/* EMMC_DATA4 */ PAD_CFG_GPI(GPP_F16, NONE, DEEP), /* MEM_CONFIGO_1P8 */ +/* I2C2_SCL */ PAD_CFG_GPI(GPP_H5, NONE, PLTRST), /* 360_SENSOR_DET# */ }; const struct pad_config *variant_gpio_table(size_t *num) @@ -277,3 +274,16 @@ const struct cros_gpio *variant_cros_gpios(size_t *num) *num = ARRAY_SIZE(cros_gpios); return cros_gpios; } + +static int is_ish_device_enabled(void) +{ + gpio_input(SENSOR_DET_360); + return gpio_get(SENSOR_DET_360) == 0; +} + +void variant_mainboard_post_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *fsp_m_cfg = &mupd->FspmConfig; + if (fsp_m_cfg->PchIshEnable) + fsp_m_cfg->PchIshEnable = is_ish_device_enabled(); +} diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h index f7e0403e59..251b40e0d0 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h @@ -25,6 +25,16 @@ /* Recovery mode */ #define GPIO_REC_MODE GPP_E8 +/* Sensor detection pin */ +#define SENSOR_DET_360 GPP_H5 + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_F12 +#define GPIO_MEM_CONFIG_1 GPP_F13 +#define GPIO_MEM_CONFIG_2 GPP_F14 +#define GPIO_MEM_CONFIG_3 GPP_F15 +#define GPIO_MEM_CONFIG_4 GPP_F16 + const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h index d878623d59..508654faa5 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h @@ -17,9 +17,23 @@ #define VARIANT_H /* Need to update for Drallion with right SKU IDs*/ -#define VARIANT_SKU_ID 2 -#define VARIANT_SKU_NAME "sku2" -#define VARIANT_SKU_ID_SIGNED_EC 4 -#define VARIANT_SKU_NAME_SIGNED_EC "sku4" +typedef struct { + int id; + const char *name; +} sku_info; + +const static sku_info skus[] = { + // Drallion 360 + { .id = 1, .name = "sku1" }, + // Drallion + { .id = 2, .name = "sku2" }, + // Drallion 360 signed + { .id = 3, .name = "sku3" }, + // Drallion signed + { .id = 4, .name = "sku4" }, +}; + +/* Return memory SKU for the variant */ +int variant_memory_sku(void); #endif diff --git a/src/mainboard/google/drallion/variants/drallion/memory.c b/src/mainboard/google/drallion/variants/drallion/memory.c new file mode 100644 index 0000000000..10996a3e7b --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/memory.c @@ -0,0 +1,85 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +/* Use spd_index array to save mem_id */ +static const int spd_index[32] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 4, 3, 6, 1, 0, 0, 0, 0, + 5, 0, 7, 2, 0, 0, 0, 0 + }; + +const struct cnl_mb_cfg *get_variant_memory_cfg(struct cnl_mb_cfg *mem_cfg) +{ + int mem_sku; + struct cnl_mb_cfg baseboard_memcfg = { + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on ddr4 part + * the value = pin number on SoC + */ + .dqs_map[DDR_CH0] = { 0, 1, 4, 5, 2, 3, 6, 7 }, + .dqs_map[DDR_CH1] = { 0, 1, 4, 5, 2, 3, 6, 7 }, + + /* Baseboard uses 120, 81 and 100 rcomp resistors */ + .rcomp_resistor = { 120, 81, 100 }, + + /* Baseboard Rcomp target values */ + .rcomp_targets = { 100, 40, 20, 20, 26 }, + + /* Set CaVref config to 2 */ + .vref_ca_config = 2, + + /* Enable Early Command Training */ + .ect = 1, + }; + + mem_sku = variant_memory_sku(); + + memcpy(mem_cfg, &baseboard_memcfg, sizeof(baseboard_memcfg)); + + /* In Drallion dual channel is enabled by default. + * spd[0]-spd[3] map to CH0D0, CH0D1, CH1D0, Ch1D1 respectively. + * Dual-DIMM memory is not used in drallion family, so we only + * fill in spd info for CH0D0 and CH1D0 here. + */ + for (int i = 0; i < 3; i = i+2) { + mem_cfg->spd[i].read_type = READ_SPD_CBFS; + mem_cfg->spd[i].spd_spec.spd_index = mem_sku; + } + + return mem_cfg; +} + +int variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + GPIO_MEM_CONFIG_4, + }; + + return spd_index[gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios))]; +} diff --git a/src/mainboard/google/drallion/variants/drallion/sku.c b/src/mainboard/google/drallion/variants/drallion/sku.c new file mode 100644 index 0000000000..72776299b0 --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/sku.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +static const uint32_t get_sku_index(void) +{ + return (gpio_get(SENSOR_DET_360) | (wilco_ec_signed_fw() << 1)); +} + +uint32_t sku_id(void) +{ + return skus[get_sku_index()].id; +} + +const char *smbios_system_sku(void) +{ + return skus[get_sku_index()].name; +} diff --git a/src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc b/src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc new file mode 100644 index 0000000000..b979be187e --- /dev/null +++ b/src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2018 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +## GPP_F12-F16 indicates mem_id to match specific spd file +SPD_SOURCES = empty_ddr4 # 0b00000 + +bootblock-y += gpio.c +ramstage-y += gpio.c +romstage-y += gpio.c +verstage-y += gpio.c + +ramstage-y += sku.c diff --git a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb new file mode 100644 index 0000000000..f2367ffa1d --- /dev/null +++ b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb @@ -0,0 +1,422 @@ +chip soc/intel/cannonlake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "PMC_GPP_A" + register "gpe0_dw1" = "PMC_GPP_C" + register "gpe0_dw2" = "PMC_GPP_D" + + # EC host command ranges + register "gen1_dec" = "0x00040931" # 0x930-0x937 + register "gen2_dec" = "0x00040941" # 0x940-0x947 + register "gen3_dec" = "0x000c0951" # 0x950-0x95f + + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "HeciEnabled" = "0" + register "SataSalpSupport" = "1" + register "SataMode" = "Sata_AHCI" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[0]" = "1" + register "SataPortsDevSlp[1]" = "1" + register "SataPortsDevSlp[2]" = "1" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "4" # 4s + register "PchPmSlpSusMinAssert" = "4" # 4s + register "PchPmSlpAMinAssert" = "4" # 2s + + register "speed_shift_enable" = "1" + register "s0ix_enable" = "1" + register "dptf_enable" = "1" + register "satapwroptimize" = "1" + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRateForIa" = "2" + register "SlowSlewRateForGt" = "2" + register "SlowSlewRateForSa" = "2" + register "SlowSlewRateForFivr" = "2" + register "tdp_pl1_override" = "15" + register "tdp_pl2_override" = "51" + register "psys_pmax" = "136" + register "Device4Enable" = "1" + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + # Enable DDC for DDI port B + register "DdiPortBDdc" = "1" + + register "LanWakeFromDeepSx" = "0" + register "WolEnableOverride" = "0" + + # Disable iDisplay codec enumeration + register "PchHdaIDispCodecDisconnect" = "1" + register "PchHdaAudioLinkHda" = "1" + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 6A | 70A | 31A | 31A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | + #| DcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | + #+----------------+-------+-------+-------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(6), + .voltage_limit = 1520, + .ac_loadline = 1030, + .dc_loadline = 1030, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(70), + .voltage_limit = 1520, + .ac_loadline = 180, + .dc_loadline = 180, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + # Intel Common SoC Config + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port + register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Right Type-A Port 1 + register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Left Type-A Port + register "usb2_ports[3]" = "USB2_PORT_LONG(OC2)" # Right Type-A Port 2 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" + register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WWAN + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Right Type-A Port 1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Left Type-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Right Type-A Port 2 + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN + register "usb3_ports[5]" = "USB3_PORT_EMPTY" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| I2C0 | Touchscreen | + #| I2C1 | Touchpad | + #| I2C4 | H1 TPM | + #+-------------------+---------------------------+ + + register "tcc_offset" = "10" + + # PCH Thermal Trip Temperature in deg C + register "common_soc_config.pch_thermal_trip" = "77" + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 100, + .fall_time_ns = 80, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + .i2c[4] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 36, + .fall_time_ns = 99, + }, + }" + + # PCIe port 8 for Card Reader + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" + register "PcieClkSrcUsage[4]" = "7" + register "PcieClkSrcClkReq[4]" = "4" + + # PCIe port 9 for LAN + register "PcieRpEnable[8]" = "1" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN" + register "PcieClkSrcClkReq[3]" = "3" + + # PCIe port 10 for M.2 2230 WLAN + register "PcieRpEnable[9]" = "1" + register "PcieClkSrcUsage[1]" = "9" + register "PcieClkSrcClkReq[1]" = "1" + + # PCIe port 13 for M.2 2280 SSD + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + register "PcieClkSrcUsage[2]" = "12" + register "PcieClkSrcClkReq[2]" = "2" + + # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port 1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port 2"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""USH"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.7 on end + end + chip drivers/usb/acpi + register "desc" = ""Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.8 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H15)" + device usb 2.9 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port 1"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port 2"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.4 on end + end + end + end + end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + chip drivers/intel/wifi + register "wake" = "PME_B0_EN_BIT" + device pci 14.3 on end # CNVi wifi + end + device pci 14.5 off end # SDCard + device pci 15.0 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN900C"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "generic.reset_delay_ms" = "10" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "generic.enable_delay_ms" = "55" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + register "generic.device_present_gpio" = "GPP_B4" + register "generic.device_present_gpio_invert" = "1" + device i2c 10 on end + end + chip drivers/i2c/generic + register "hid" = ""MLFS0000"" + register "desc" = ""Melfas Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "reset_delay_ms" = "10" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "enable_delay_ms" = "55" + register "has_power_resource" = "1" + register "device_present_gpio" = "GPP_B4" + register "device_present_gpio_invert" = "1" + device i2c 34 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "probed" = "1" + device i2c 2c on end + end + end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)" + device i2c 50 on end + end + end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 on end # PCI Express Port 1 (USB) + device pci 1c.1 off end # PCI Express Port 2 (USB) + device pci 1c.2 off end # PCI Express Port 3 (USB) + device pci 1c.3 off end # PCI Express Port 4 (USB) + device pci 1c.4 off end # PCI Express Port 5 (USB) + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 on end # PCI Express Port 8 + device pci 1d.0 on + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" + end # PCI Express Port 9 + device pci 1d.1 on end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 on + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" + end # PCI Express Port 13 (x4) + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on + chip ec/google/wilco + device pnp 0c09.0 on end + end + end # LPC/eSPI + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/google/drallion/variants/sarien_cml/gpio.c b/src/mainboard/google/drallion/variants/sarien_cml/gpio.c new file mode 100644 index 0000000000..78db12e8a1 --- /dev/null +++ b/src/mainboard/google/drallion/variants/sarien_cml/gpio.c @@ -0,0 +1,267 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { +/* RCIN# */ PAD_NC(GPP_A0, NONE), +/* ESPI_IO0 */ +/* ESPI_IO1 */ +/* ESPI_IO2 */ +/* ESPI_IO3 */ +/* ESPI_CS# */ +/* SERIRQ */ +/* PIRQA# */ PAD_NC(GPP_A7, NONE), +/* CLKRUN# */ PAD_NC(GPP_A8, NONE), +/* ESPI_CLK */ +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), +/* PME# */ PAD_NC(GPP_A11, NONE), +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), + +/* ESPI_RESET# */ + +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), +/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), + +/* CORE_VID0 */ +/* CORE_VID1 */ +/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ +/* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLKREQ_PCIE#0 */ +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* CLKREQ_PCIE#1 */ +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* CLKREQ_PCIE#2 */ +/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* CLKREQ_PCIE#3 */ +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* CLKREQ_PCIE#4 */ +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */ +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE), +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */ +/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), +/* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K), + +/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* MEM_SMBCLK */ +/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* MEM_SMBDATA */ +/* SMBALERT# */ PAD_NC(GPP_C2, DN_20K), +/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_SMBCLK */ +/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_SMBDATA */ +/* SML0ALERT# */ PAD_NC(GPP_C5, DN_20K), +/* SM1CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1_SMBCLK */ +/* SM1DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_SMBDATA */ +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */ +/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */ +/* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP, + EDGE_SINGLE), /* SIO_EXT_WAKE# */ +/* UART1_TXD */ PAD_NC(GPP_C13, NONE), +/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* LCD_CBL_DET# */ +/* UART1_CTS# */ PAD_NC(GPP_C15, NONE), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TS_I2C_SDA */ +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TS_I2C_SCL */ +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA_TP */ +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCK_TP */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ +/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), +/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* TS_INT# */ + +/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */ +/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), +/* SPI1_MOSI */ PAD_CFG_GPI(GPP_D3, NONE, DEEP), /* RTC_DET# */ +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), +/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), +/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CS# */ PAD_CFG_GPI(GPP_D9, NONE, DEEP), /* IR_CAM_DET# */ +/* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE), +/* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */ +/* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */ +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */ +/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ +/* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE), +/* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE), +/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 1, DEEP), /* WWAN_BB_RST# */ +/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* WWAN_GPIO_PERST# */ +/* I2S_MCLK */ PAD_CFG_GPI_SCI_LOW(GPP_D23, NONE, DEEP, + EDGE_SINGLE), /* WWAN_GPIO_WAKE# */ + +/* SATAXPCIE0 */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* HDD_DET# */ + /* M3042_PCIE#_SATA */ +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* M2880_PCIE_SATA# */ +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), +/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ +/* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), /* HDD_DEVSLP */ +/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */ +/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */ +/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */ +/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ +/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */ +/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */ +/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB_OC2# */ +/* USB2_OC3# */ PAD_NC(GPP_E12, NONE), +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* HDMI_DP1_HPD */ +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* CPU_DP2_HPD */ +/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ +/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */ +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), +/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), + +/* CNV_PA_BLANKING */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_COEX3 */ +/* GPP_F1 */ PAD_NC(GPP_F1, NONE), /* T406 */ +/* GPP_F2 */ PAD_NC(GPP_F2, NONE), /* T407 */ +/* GPP_F3 */ PAD_NC(GPP_F3, NONE), +/* CNV_BRI_DT */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), +/* CNV_BRI_RSP */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), +/* CNV_RGI_DT */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), +/* CNV_RGI_RSP */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), +/* CNV_MFUART2_RXD */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* CNV_COEX2 */ +/* CNV_MFUART2_TXD */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* CNV_COEX1 */ +/* GPP_F10 */ PAD_NC(GPP_F10, NONE), +/* EMMC_CMD */ PAD_NC(GPP_F11, NONE), +/* EMMC_DATA0 */ PAD_NC(GPP_F12, NONE), +/* EMMC_DATA1 */ PAD_NC(GPP_F13, NONE), +/* EMMC_DATA2 */ PAD_NC(GPP_F14, NONE), +/* EMMC_DATA3 */ PAD_NC(GPP_F15, NONE), +/* EMMC_DATA4 */ PAD_NC(GPP_F16, NONE), +/* EMMC_DATA5 */ PAD_NC(GPP_F17, NONE), +/* EMMC_DATA6 */ PAD_NC(GPP_F18, NONE), +/* EMMC_DATA7 */ PAD_NC(GPP_F19, NONE), +/* EMMC_RCLK */ PAD_NC(GPP_F20, NONE), +/* EMMC_CLK */ PAD_NC(GPP_F21, NONE), +/* EMMC_RESET# */ PAD_NC(GPP_F22, NONE), +/* A4WP_PRESENT */ PAD_NC(GPP_F23, NONE), + +/* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */ +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), /* T383 */ +/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */ +/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */ +/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */ +/* SD_WP */ PAD_NC(GPP_G7, NONE), /* T384 */ + +/* I2S2_SCLK */ PAD_NC(GPP_H0, NONE), +/* I2S2_SFRM */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# */ +/* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* CLKREQ_CNV# */ +/* I2S2_RXD */ PAD_CFG_GPO(GPP_H3, 0, DEEP), /* CNVI_EN# */ +/* I2C2_SDA */ PAD_NC(GPP_H4, NONE), /* T388 */ +/* I2C2_SCL */ PAD_NC(GPP_H5, NONE), /* T389 */ +/* I2C3_SDA */ PAD_NC(GPP_H6, NONE), /* T378 */ +/* I2C3_SCL */ PAD_NC(GPP_H7, NONE), /* T379 */ +/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ +/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ +/* I2C5_SDA */ PAD_NC(GPP_H10, NONE), +/* I2C5_SCL */ PAD_NC(GPP_H11, NONE), +/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), +/* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */ +/* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE), +/* DPPF_CTRLDATA */ PAD_NC(GPP_H17, NONE), +/* CPU_C10_GATE# */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* C10_GATE# */ +/* TIMESYNC0 */ PAD_NC(GPP_H19, NONE), +/* IMGCLKOUT1 */ PAD_NC(GPP_H20, NONE), +/* GPP_H21 */ PAD_NC(GPP_H21, NONE), +/* GPP_H22 */ PAD_NC(GPP_H22, NONE), +/* GPP_H23 */ PAD_NC(GPP_H23, NONE), + +/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */ +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* AC_PRESENT */ +/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* LAN_WAKE# */ +/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */ +/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */ +/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */ +/* GPD7 */ PAD_NC(GPD7, NONE), +/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUSCLK */ +/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* SIO_SLP_WLAN# */ +/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* SIO_SLP_S5# */ +/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), /* PM_LANPHY_EN */ +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { +/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ +/* SUSWARN# */ PAD_CFG_GPO(GPP_A13, 0, DEEP), /* Card reader D3 cold */ +/* SUSACK# */ PAD_CFG_GPO(GPP_A15, 0, DEEP), /* Card reader D3 cold */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ +/* SSD RESET pin will stay low first */ +/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ +/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ +/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ +/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ +/* RESET# need to stay low before FULL_CARD_POWER_OFF assert */ +/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */ +/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ +/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ +/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* SIO_PWRBTN# */ +/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */ +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/acpi/dptf.asl b/src/mainboard/google/drallion/variants/sarien_cml/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..0cdbcd1400 --- /dev/null +++ b/src/mainboard/google/drallion/variants/sarien_cml/include/variant/acpi/dptf.asl @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 99 +#define DPTF_CPU_CRITICAL 105 + +/* Skin Sensor for CPU VR temperature monitor */ +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "Skin" +#define DPTF_TSR0_PASSIVE 71 +#define DPTF_TSR0_CRITICAL 100 + +/* Memory Sensor for DDR temperature monitor */ +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "DDR" +#define DPTF_TSR1_PASSIVE 55 +#define DPTF_TSR1_CRITICAL 100 + +/* M.2 Sensor for Ambient temperature monitor */ +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "Ambient" +#define DPTF_TSR2_PASSIVE 90 +#define DPTF_TSR2_CRITICAL 100 + +#undef DPTF_ENABLE_FAN_CONTROL +#undef DPTF_ENABLE_CHARGER + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 250, 10, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Skin (TSR0) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 250, 10, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on DDR (TSR1) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 250, 10, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR2) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 250, 10, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 5000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 10000, /* TimeWindowMinimum */ + 10000, /* TimeWindowMaximum */ + 100 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 5000, /* PowerLimitMinimum */ + 51000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + } +}) diff --git a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/acpi/mainboard.asl b/src/mainboard/google/drallion/variants/sarien_cml/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000000..41121d28fe --- /dev/null +++ b/src/mainboard/google/drallion/variants/sarien_cml/include/variant/acpi/mainboard.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define CAM_EN GPP_B11 /* Active low */ +#define TS_PD GPP_E7 + +/* Method called from LPIT prior to enter s0ix state */ +Method (MS0X, 1) +{ + If (Arg0) { + /* Turn off camera power */ + \_SB.PCI0.STXS (CAM_EN) + } Else { + /* Turn on camera power */ + \_SB.PCI0.CTXS (CAM_EN) + } +} + +/* Method called from _PTS prior to enter sleep state */ +Method (MPTS, 1) +{ + \_SB.PCI0.LPCB.EC0.PTS (Arg0) + + /* Clear touch screen pd pin to avoid leakage */ + \_SB.PCI0.CTXS (TS_PD) +} + +/* Method called from _WAK prior to wakeup */ +Method (MWAK, 1) +{ + \_SB.PCI0.LPCB.EC0.WAK (Arg0) +} diff --git a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/ec.h b/src/mainboard/google/drallion/variants/sarien_cml/include/variant/ec.h new file mode 100644 index 0000000000..01a17b5f99 --- /dev/null +++ b/src/mainboard/google/drallion/variants/sarien_cml/include/variant/ec.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include +#include + +/* EC wake pin */ +#define EC_WAKE_PIN GPE0_DW1_12 + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* Enable PS/2 keyboard */ +#define SIO_EC_ENABLE_PS2K + +/* Enable DPTF */ +#define EC_ENABLE_DPTF + +#endif diff --git a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/gpio.h b/src/mainboard/google/drallion/variants/sarien_cml/include/variant/gpio.h new file mode 100644 index 0000000000..f7e0403e59 --- /dev/null +++ b/src/mainboard/google/drallion/variants/sarien_cml/include/variant/gpio.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include +#include + +/* Flash Write Protect */ +#define GPIO_PCH_WP GPP_E15 + +/* Recovery mode */ +#define GPIO_REC_MODE GPP_E8 + +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); + +struct cros_gpio; +const struct cros_gpio *variant_cros_gpios(size_t *num); + +#endif diff --git a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/hda_verb.h b/src/mainboard/google/drallion/variants/sarien_cml/include/variant/hda_verb.h new file mode 100644 index 0000000000..6eb6d14f6b --- /dev/null +++ b/src/mainboard/google/drallion/variants/sarien_cml/include/variant/hda_verb.h @@ -0,0 +1,152 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_HDA_VERB_H +#define MAINBOARD_HDA_VERB_H + +#include + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0236, // Codec Vendor / Device ID: Realtek ALC3204 + 0xffffffff, // Subsystem ID + 0x0000001e, // Number of jacks (NID entries) + + /* Rest Codec First */ + AZALIA_RESET(0x1), + /* NID 0x01, HDA Codec Subsystem ID Verb Table */ + AZALIA_SUBVENDOR(0x0, 0x102808b8), + + /* Pin Widget Verb Table */ + AZALIA_PIN_CFG(0x0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0x0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x19, 0x04a11030), + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1d, 0x40700001), + AZALIA_PIN_CFG(0x0, 0x1e, 0x421212f2), + AZALIA_PIN_CFG(0x0, 0x21, 0x04211020), + + /* ALC3204 default-1 */ + 0x02050040, + 0x02049800, + 0x02050034, + 0x0204023C, + /* ALC3204 default-2 */ + 0x0205003C, + 0x02040354, + 0x0205003C, + 0x02040314, + /* ALC3204 Speaker output power - 4 ohm 2W (+12dB gain) + * + Combo Jack TRS setting */ + 0x02050038, + 0x02043901, + 0x02050045, + 0x02045089, + /* H/W AGC setting-1 */ + 0x02050016, + 0x02040C50, + 0x02050012, + 0x0204EBC2, + /* H/W AGC setting-2 */ + 0x02050013, + 0x0204401D, + 0x02050016, + 0x02044E50, + /* Zero data + EAPD to verb-control */ + 0x02050037, + 0x0204FE15, + 0x02050010, + 0x02040020, + /* Zero data */ + 0x02050030, + 0x02048000, + 0x02050030, + 0x02048000, + /* ALC3204 default-3 */ + 0x05750003, + 0x05740DA3, + 0x02050046, + 0x02040004, + /* ALC3204 default-4 */ + 0x0205001B, + 0x02040A4B, + 0x02050008, + 0x02046A6C, + /* JD1 */ + 0x02050009, + 0x0204E003, + 0x0205000A, + 0x02047770, + /* Microphone + Array MIC security Disable +ADC clock Enable */ + 0x0205000D, + 0x0204A020, + 0x02050005, + 0x02040700, + /* Speaker Enable */ + 0x0205000C, + 0x020401EF, + 0x0205000C, + 0x020401EF, + /* EQ Bypass + EQ HPF cutoff 250Hz */ + 0x05350000, + 0x0534201A, + 0x0535001d, + 0x05340800, + /* EQ-2 */ + 0x0535001e, + 0x05340800, + 0x05350003, + 0x05341EF8, + /* EQ-3 */ + 0x05350004, + 0x05340000, + 0x05450000, + 0x05442000, + /* EQ-4 */ + 0x0545001d, + 0x05440800, + 0x0545001e, + 0x05440800, + /* EQ-5 */ + 0x05450003, + 0x05441EF8, + 0x05450004, + 0x05440000, + /* EQ Update */ + 0x05350000, + 0x0534E01A, + 0x05350000, + 0x0534E01A, +}; + +const u32 pc_beep_verbs[] = { +/* PCBeep pass through to NID14 for ePSA test-1 */ + 0x02050036, + 0x02047717, + 0x02050036, + 0x02047717, +/* PCBeep pass through to NID14 for ePSA test-2 */ + 0x01470740, + 0x0143B000, + 0x01470C02, + 0x01470C02, +}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/variant.h b/src/mainboard/google/drallion/variants/sarien_cml/include/variant/variant.h new file mode 100644 index 0000000000..bbb3e9e68d --- /dev/null +++ b/src/mainboard/google/drallion/variants/sarien_cml/include/variant/variant.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* Sarien is SKU ID 1 and 3 */ +#define VARIANT_SKU_ID 1 +#define VARIANT_SKU_NAME "sku1" +#define VARIANT_SKU_ID_SIGNED_EC 3 +#define VARIANT_SKU_NAME_SIGNED_EC "sku3" + +#endif diff --git a/src/mainboard/google/drallion/variants/sarien_cml/sku.c b/src/mainboard/google/drallion/variants/sarien_cml/sku.c new file mode 100644 index 0000000000..d0b48f0572 --- /dev/null +++ b/src/mainboard/google/drallion/variants/sarien_cml/sku.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +uint32_t sku_id(void) +{ + if (wilco_ec_signed_fw()) + return VARIANT_SKU_ID_SIGNED_EC; + else + return VARIANT_SKU_ID; +} + +const char *smbios_system_sku(void) +{ + if (wilco_ec_signed_fw()) + return VARIANT_SKU_NAME_SIGNED_EC; + else + return VARIANT_SKU_NAME; +} diff --git a/src/mainboard/google/eve/romstage.c b/src/mainboard/google/eve/romstage.c index 975eea5819..7114715fbc 100644 --- a/src/mainboard/google/eve/romstage.c +++ b/src/mainboard/google/eve/romstage.c @@ -40,8 +40,10 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) /* Rcomp target */ const u16 rcomp_target[] = { 100, 40, 40, 23, 40 }; - memcpy(&mem_cfg->DqByteMapCh0, dq_map, sizeof(dq_map)); - memcpy(&mem_cfg->DqsMapCpu2DramCh0, dqs_map, sizeof(dqs_map)); + memcpy(&mem_cfg->DqByteMapCh0, dq_map[0], sizeof(dq_map[0])); + memcpy(&mem_cfg->DqByteMapCh1, dq_map[1], sizeof(dq_map[1])); + memcpy(&mem_cfg->DqsMapCpu2DramCh0, dqs_map[0], sizeof(dqs_map[0])); + memcpy(&mem_cfg->DqsMapCpu2DramCh1, dqs_map[1], sizeof(dqs_map[1])); memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor)); memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target)); diff --git a/src/mainboard/google/eve/smihandler.c b/src/mainboard/google/eve/smihandler.c index 7b97446271..5bca488d7c 100644 --- a/src/mainboard/google/eve/smihandler.c +++ b/src/mainboard/google/eve/smihandler.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include "ec.h" #include "gpio.h" diff --git a/src/mainboard/google/fizz/smihandler.c b/src/mainboard/google/fizz/smihandler.c index 2b7367ad34..d20780c709 100644 --- a/src/mainboard/google/fizz/smihandler.c +++ b/src/mainboard/google/fizz/smihandler.c @@ -15,7 +15,7 @@ #include #include -#include +#include #include #include diff --git a/src/mainboard/google/glados/smihandler.c b/src/mainboard/google/glados/smihandler.c index a4a1ccadaa..c10ae0e4d7 100644 --- a/src/mainboard/google/glados/smihandler.c +++ b/src/mainboard/google/glados/smihandler.c @@ -18,13 +18,12 @@ #include #include #include -#include #include #include #include #include #include -#include +#include #include "ec.h" #include diff --git a/src/mainboard/google/glados/variants/asuka/variant.c b/src/mainboard/google/glados/variants/asuka/variant.c index 4c778970fe..fdef81c5cd 100644 --- a/src/mainboard/google/glados/variants/asuka/variant.c +++ b/src/mainboard/google/glados/variants/asuka/variant.c @@ -39,10 +39,14 @@ void variant_memory_init_params( /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->DqByteMapCh0, dq_map[0], + sizeof(memory_params->DqByteMapCh0)); + memcpy(memory_params->DqByteMapCh1, dq_map[1], + sizeof(memory_params->DqByteMapCh1)); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0], + sizeof(memory_params->DqsMapCpu2DramCh0)); + memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1], + sizeof(memory_params->DqsMapCpu2DramCh1)); memcpy(memory_params->RcompResistor, RcompResistor, sizeof(memory_params->RcompResistor)); memcpy(memory_params->RcompTarget, RcompTarget, diff --git a/src/mainboard/google/glados/variants/caroline/variant.c b/src/mainboard/google/glados/variants/caroline/variant.c index d61a538d56..ab6bd2c1bd 100644 --- a/src/mainboard/google/glados/variants/caroline/variant.c +++ b/src/mainboard/google/glados/variants/caroline/variant.c @@ -41,10 +41,14 @@ void variant_memory_init_params( /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->DqByteMapCh0, dq_map[0], + sizeof(memory_params->DqByteMapCh0)); + memcpy(memory_params->DqByteMapCh1, dq_map[1], + sizeof(memory_params->DqByteMapCh1)); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0], + sizeof(memory_params->DqsMapCpu2DramCh0)); + memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1], + sizeof(memory_params->DqsMapCpu2DramCh1)); memcpy(memory_params->RcompResistor, RcompResistor, sizeof(memory_params->RcompResistor)); memcpy(memory_params->RcompTarget, RcompTarget, diff --git a/src/mainboard/google/glados/variants/cave/variant.c b/src/mainboard/google/glados/variants/cave/variant.c index fc27fb4b61..d63a298df7 100644 --- a/src/mainboard/google/glados/variants/cave/variant.c +++ b/src/mainboard/google/glados/variants/cave/variant.c @@ -41,10 +41,14 @@ void variant_memory_init_params( /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->DqByteMapCh0, dq_map[0], + sizeof(memory_params->DqByteMapCh0)); + memcpy(memory_params->DqByteMapCh1, dq_map[1], + sizeof(memory_params->DqByteMapCh1)); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0], + sizeof(memory_params->DqsMapCpu2DramCh0)); + memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1], + sizeof(memory_params->DqsMapCpu2DramCh1)); memcpy(memory_params->RcompResistor, RcompResistor, sizeof(memory_params->RcompResistor)); memcpy(memory_params->RcompTarget, RcompTarget, diff --git a/src/mainboard/google/glados/variants/chell/variant.c b/src/mainboard/google/glados/variants/chell/variant.c index 2d1b363cab..3e8503fe9e 100644 --- a/src/mainboard/google/glados/variants/chell/variant.c +++ b/src/mainboard/google/glados/variants/chell/variant.c @@ -41,10 +41,14 @@ void variant_memory_init_params( /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->DqByteMapCh0, dq_map[0], + sizeof(memory_params->DqByteMapCh0)); + memcpy(memory_params->DqByteMapCh1, dq_map[1], + sizeof(memory_params->DqByteMapCh1)); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0], + sizeof(memory_params->DqsMapCpu2DramCh0)); + memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1], + sizeof(memory_params->DqsMapCpu2DramCh1)); memcpy(memory_params->RcompResistor, RcompResistor, sizeof(memory_params->RcompResistor)); memcpy(memory_params->RcompTarget, RcompTarget, diff --git a/src/mainboard/google/glados/variants/glados/variant.c b/src/mainboard/google/glados/variants/glados/variant.c index fc27fb4b61..d63a298df7 100644 --- a/src/mainboard/google/glados/variants/glados/variant.c +++ b/src/mainboard/google/glados/variants/glados/variant.c @@ -41,10 +41,14 @@ void variant_memory_init_params( /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->DqByteMapCh0, dq_map[0], + sizeof(memory_params->DqByteMapCh0)); + memcpy(memory_params->DqByteMapCh1, dq_map[1], + sizeof(memory_params->DqByteMapCh1)); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0], + sizeof(memory_params->DqsMapCpu2DramCh0)); + memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1], + sizeof(memory_params->DqsMapCpu2DramCh1)); memcpy(memory_params->RcompResistor, RcompResistor, sizeof(memory_params->RcompResistor)); memcpy(memory_params->RcompTarget, RcompTarget, diff --git a/src/mainboard/google/glados/variants/lars/variant.c b/src/mainboard/google/glados/variants/lars/variant.c index cff0096291..37860c3738 100644 --- a/src/mainboard/google/glados/variants/lars/variant.c +++ b/src/mainboard/google/glados/variants/lars/variant.c @@ -58,10 +58,14 @@ void variant_memory_init_params( if (spd_index == K4E6E304EB_MEM_ID) targeted_rcomp = StrengthendRcompTarget; - memcpy(params->DqByteMapCh0, dq_map, - sizeof(params->DqByteMapCh0) * 2); - memcpy(params->DqsMapCpu2DramCh0, dqs_map, - sizeof(params->DqsMapCpu2DramCh0) * 2); + memcpy(params->DqByteMapCh0, dq_map[0], + sizeof(params->DqByteMapCh0)); + memcpy(params->DqByteMapCh1, dq_map[1], + sizeof(params->DqByteMapCh1)); + memcpy(params->DqsMapCpu2DramCh0, dqs_map[0], + sizeof(params->DqsMapCpu2DramCh0)); + memcpy(params->DqsMapCpu2DramCh1, dqs_map[1], + sizeof(params->DqsMapCpu2DramCh1)); memcpy(params->RcompResistor, RcompResistor, sizeof(params->RcompResistor)); memcpy(params->RcompTarget, targeted_rcomp, diff --git a/src/mainboard/google/glados/variants/sentry/variant.c b/src/mainboard/google/glados/variants/sentry/variant.c index 4c7fa23f08..101be2a0fb 100644 --- a/src/mainboard/google/glados/variants/sentry/variant.c +++ b/src/mainboard/google/glados/variants/sentry/variant.c @@ -51,10 +51,14 @@ void variant_memory_init_params( if (spd_index == K4E6E304EE_MEM_ID) targeted_rcomp = StrengthendRcompTarget; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->DqByteMapCh0, dq_map[0], + sizeof(memory_params->DqByteMapCh0)); + memcpy(memory_params->DqByteMapCh1, dq_map[1], + sizeof(memory_params->DqByteMapCh1)); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0], + sizeof(memory_params->DqsMapCpu2DramCh0)); + memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1], + sizeof(memory_params->DqsMapCpu2DramCh1)); memcpy(memory_params->RcompResistor, RcompResistor, sizeof(memory_params->RcompResistor)); memcpy(memory_params->RcompTarget, targeted_rcomp, diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 19f4ecca55..4ebe143dea 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -15,6 +15,7 @@ */ #include +#include #include #include #include @@ -23,7 +24,6 @@ #include #include #include -#include #include #include #include @@ -35,6 +35,8 @@ #include "board.h" +#include + /* * We have to drive the stronger pull-up within 1 second of powering up the * touchpad to prevent its firmware from falling into recovery. Not on @@ -71,9 +73,9 @@ static void configure_emmc(void) static void register_apio_suspend(void) { - static struct bl31_apio_param param_apio = { + static struct bl_aux_param_rk_apio param_apio = { .h = { - .type = PARAM_SUSPEND_APIO, + .type = BL_AUX_PARAM_RK_SUSPEND_APIO, }, .apio = { .apio1 = 1, @@ -83,7 +85,7 @@ static void register_apio_suspend(void) .apio5 = 1, }, }; - register_bl31_param(¶m_apio.h); + register_bl31_aux_param(¶m_apio.h); } static void register_gpio_suspend(void) @@ -98,34 +100,34 @@ static void register_gpio_suspend(void) * so we skip them. */ if (!CONFIG(GRU_BASEBOARD_SCARLET)) { - static struct bl31_gpio_param param_p15_en = { - .h = { .type = PARAM_SUSPEND_GPIO }, - .gpio = { .polarity = BL31_GPIO_LEVEL_LOW }, + static struct bl_aux_param_gpio param_p15_en = { + .h = { .type = BL_AUX_PARAM_RK_SUSPEND_GPIO }, + .gpio = { .polarity = ARM_TF_GPIO_LEVEL_LOW }, }; param_p15_en.gpio.index = GPIO_P15V_EN.raw; - register_bl31_param(¶m_p15_en.h); + register_bl31_aux_param(¶m_p15_en.h); - static struct bl31_gpio_param param_p18_audio_en = { - .h = { .type = PARAM_SUSPEND_GPIO }, - .gpio = { .polarity = BL31_GPIO_LEVEL_LOW }, + static struct bl_aux_param_gpio param_p18_audio_en = { + .h = { .type = BL_AUX_PARAM_RK_SUSPEND_GPIO }, + .gpio = { .polarity = ARM_TF_GPIO_LEVEL_LOW }, }; param_p18_audio_en.gpio.index = GPIO_P18V_AUDIO_PWREN.raw; - register_bl31_param(¶m_p18_audio_en.h); + register_bl31_aux_param(¶m_p18_audio_en.h); } - static struct bl31_gpio_param param_p30_en = { - .h = { .type = PARAM_SUSPEND_GPIO }, - .gpio = { .polarity = BL31_GPIO_LEVEL_LOW }, + static struct bl_aux_param_gpio param_p30_en = { + .h = { .type = BL_AUX_PARAM_RK_SUSPEND_GPIO }, + .gpio = { .polarity = ARM_TF_GPIO_LEVEL_LOW }, }; param_p30_en.gpio.index = GPIO_P30V_EN.raw; - register_bl31_param(¶m_p30_en.h); + register_bl31_aux_param(¶m_p30_en.h); } static void register_reset_to_bl31(void) { - static struct bl31_gpio_param param_reset = { + static struct bl_aux_param_gpio param_reset = { .h = { - .type = PARAM_RESET, + .type = BL_AUX_PARAM_RK_RESET_GPIO, }, .gpio = { .polarity = 1, @@ -135,14 +137,14 @@ static void register_reset_to_bl31(void) /* gru/kevin reset pin: gpio0b3 */ param_reset.gpio.index = GPIO_RESET.raw, - register_bl31_param(¶m_reset.h); + register_bl31_aux_param(¶m_reset.h); } static void register_poweroff_to_bl31(void) { - static struct bl31_gpio_param param_poweroff = { + static struct bl_aux_param_gpio param_poweroff = { .h = { - .type = PARAM_POWEROFF, + .type = BL_AUX_PARAM_RK_POWEROFF_GPIO, }, .gpio = { .polarity = 1, @@ -156,7 +158,7 @@ static void register_poweroff_to_bl31(void) */ param_poweroff.gpio.index = GPIO_POWEROFF.raw, - register_bl31_param(¶m_poweroff.h); + register_bl31_aux_param(¶m_poweroff.h); } static void configure_sdmmc(void) diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 5991b93e31..d4cf83dfe9 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -20,6 +20,7 @@ config BOARD_GOOGLE_BASEBOARD_HATCH select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE + select SOC_INTEL_COMETLAKE select SYSTEM_TYPE_LAPTOP if BOARD_GOOGLE_BASEBOARD_HATCH @@ -71,6 +72,8 @@ config FMDFILE config GBB_HWID string depends on CHROMEOS + default "AKEMI TEST 4326" if BOARD_GOOGLE_AKEMI + default "DRATINI TEST 4583" if BOARD_GOOGLE_DRATINI default "HATCH TEST 1823" if BOARD_GOOGLE_HATCH default "HELIOS TEST 0878" if BOARD_GOOGLE_HELIOS default "KINDRED TEST 2636" if BOARD_GOOGLE_KINDRED @@ -86,6 +89,8 @@ config MAINBOARD_FAMILY config MAINBOARD_PART_NUMBER string + default "Akemi" if BOARD_GOOGLE_AKEMI + default "Dratini" if BOARD_GOOGLE_DRATINI default "Hatch" if BOARD_GOOGLE_HATCH default "Helios" if BOARD_GOOGLE_HELIOS default "Kindred" if BOARD_GOOGLE_KINDRED @@ -109,6 +114,8 @@ config TPM_TIS_ACPI_INTERRUPT config VARIANT_DIR string + default "akemi" if BOARD_GOOGLE_AKEMI + default "dratini" if BOARD_GOOGLE_DRATINI default "hatch" if BOARD_GOOGLE_HATCH default "helios" if BOARD_GOOGLE_HELIOS default "kindred" if BOARD_GOOGLE_KINDRED diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 3b5d3f2910..fbc4c15894 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -1,25 +1,32 @@ comment "Hatch" +config BOARD_GOOGLE_AKEMI + bool "-> Akemi" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_16384 + +config BOARD_GOOGLE_DRATINI + bool "-> Dratini" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_16384 + config BOARD_GOOGLE_HATCH bool "-> Hatch" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_32768 - select SOC_INTEL_COMETLAKE config BOARD_GOOGLE_KOHAKU bool "-> Kohaku" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 - select SOC_INTEL_COMETLAKE config BOARD_GOOGLE_KINDRED bool "-> Kindred" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 - select SOC_INTEL_COMETLAKE + select SOC_INTEL_COMMON_MMC_OVERRIDE config BOARD_GOOGLE_HELIOS bool "-> Helios" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 - select SOC_INTEL_COMETLAKE diff --git a/src/mainboard/google/hatch/mainboard.c b/src/mainboard/google/hatch/mainboard.c index 4d5e8ed5f8..5761b085dd 100644 --- a/src/mainboard/google/hatch/mainboard.c +++ b/src/mainboard/google/hatch/mainboard.c @@ -52,3 +52,22 @@ const char *smbios_system_sku(void) return sku_str; } + +const char *smbios_mainboard_manufacturer(void) +{ + static char oem_name[32]; + static const char *manuf; + + if (manuf) + return manuf; + + if (google_chromeec_cbi_get_oem_name(&oem_name[0], + ARRAY_SIZE(oem_name)) < 0) { + printk(BIOS_INFO, "Couldn't obtain OEM name from CBI\n"); + manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; + } else { + manuf = &oem_name[0]; + } + + return manuf; +} diff --git a/src/mainboard/google/hatch/smihandler.c b/src/mainboard/google/hatch/smihandler.c index 68d562dd0f..c7833e3900 100644 --- a/src/mainboard/google/hatch/smihandler.c +++ b/src/mainboard/google/hatch/smihandler.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include void mainboard_smi_espi_handler(void) diff --git a/src/mainboard/google/hatch/spd/16G_3200.spd.hex b/src/mainboard/google/hatch/spd/16G_3200.spd.hex new file mode 100644 index 0000000000..09e1206ec8 --- /dev/null +++ b/src/mainboard/google/hatch/spd/16G_3200.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 40 36 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/hatch/variants/akemi/Makefile.inc b/src/mainboard/google/hatch/variants/akemi/Makefile.inc new file mode 100644 index 0000000000..c9627c449f --- /dev/null +++ b/src/mainboard/google/hatch/variants/akemi/Makefile.inc @@ -0,0 +1,25 @@ +## This file is part of the coreboot project. +## +## Copyright 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = 4G_2400 # 0b000 +SPD_SOURCES += empty_ddr4 # 0b001 +SPD_SOURCES += 8G_2400 # 0b010 +SPD_SOURCES += 8G_2666 # 0b011 +SPD_SOURCES += 16G_2400 # 0b100 +SPD_SOURCES += 16G_2666 # 0b101 +SPD_SOURCES += 8G_3200 # 0b110 + +bootblock-y += gpio.c +ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c new file mode 100644 index 0000000000..1ba9d3523d --- /dev/null +++ b/src/mainboard/google/hatch/variants/akemi/gpio.c @@ -0,0 +1,214 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +static const struct pad_config ssd_sku_gpio_table[] = { + /* A0 : NC */ + PAD_NC(GPP_A0, NONE), + /* A6 : NC */ + PAD_NC(GPP_A6, NONE), + /* A8 : NC */ + PAD_NC(GPP_A8, NONE), + /* A10 : NC */ + PAD_NC(GPP_A10, NONE), + /* A11 : NC */ + PAD_NC(GPP_A11, NONE), + /* A12 : NC */ + PAD_NC(GPP_A12, NONE), + /* A18 : NC */ + PAD_NC(GPP_A18, NONE), + /* A19 : NC */ + PAD_NC(GPP_A19, NONE), + /* A22 : NC */ + PAD_NC(GPP_A22, NONE), + /* A23 : NC */ + PAD_NC(GPP_A23, NONE), + /* B20 : NC */ + PAD_NC(GPP_B20, NONE), + /* B21 : NC */ + PAD_NC(GPP_B21, NONE), + /* B22 : NC */ + PAD_NC(GPP_B22, NONE), + /* C11 : NC */ + PAD_NC(GPP_C11, NONE), + /* C15 : NC */ + PAD_NC(GPP_C15, NONE), + /* F1 : NC */ + PAD_NC(GPP_F1, NONE), + /* F3 : MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_F3, NONE, PLTRST), + /* F10 : MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + /* F11 : NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : NC */ + PAD_NC(GPP_F12, NONE), + /* F13 : NC */ + PAD_NC(GPP_F13, NONE), + /* F14 : NC */ + PAD_NC(GPP_F14, NONE), + /* F15 : NC */ + PAD_NC(GPP_F15, NONE), + /* F16 : NC */ + PAD_NC(GPP_F16, NONE), + /* F17 : NC */ + PAD_NC(GPP_F17, NONE), + /* F18 : NC */ + PAD_NC(GPP_F18, NONE), + /* F19 : NC */ + PAD_NC(GPP_F19, NONE), + /* F20 : NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : NC */ + PAD_NC(GPP_F21, NONE), + /* F22 : NC */ + PAD_NC(GPP_F22, NONE), + /* H6 : NC */ + PAD_NC(GPP_H6, NONE), + /* H7 : NC */ + PAD_NC(GPP_H7, NONE), + /* H19 : MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_H19, NONE, PLTRST), + /* H22 : MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_H22, NONE, PLTRST), +}; + +static const struct pad_config gpio_table[] = { + /* A0 : NC */ + PAD_NC(GPP_A0, NONE), + /* A6 : NC */ + PAD_NC(GPP_A6, NONE), + /* A8 : NC */ + PAD_NC(GPP_A8, NONE), + /* A10 : NC */ + PAD_NC(GPP_A10, NONE), + /* A11 : NC */ + PAD_NC(GPP_A11, NONE), + /* A12 : NC */ + PAD_NC(GPP_A12, NONE), + /* A18 : NC */ + PAD_NC(GPP_A18, NONE), + /* A19 : NC */ + PAD_NC(GPP_A19, NONE), + /* A22 : NC */ + PAD_NC(GPP_A22, NONE), + /* A23 : NC */ + PAD_NC(GPP_A23, NONE), + /* B20 : NC */ + PAD_NC(GPP_B20, NONE), + /* B21 : NC */ + PAD_NC(GPP_B21, NONE), + /* B22 : NC */ + PAD_NC(GPP_B22, NONE), + /* C11 : NC */ + PAD_NC(GPP_C11, NONE), + /* C15 : NC */ + PAD_NC(GPP_C15, NONE), + /* F1 : NC */ + PAD_NC(GPP_F1, NONE), + /* F3 : MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_F3, NONE, PLTRST), + /* F10 : MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + /* F11 : EMMC_CMD ==> EMMC_CMD */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_DATA0 ==> EMMC_DAT0 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA1 ==> EMMC_DAT1 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA2 ==> EMMC_DAT2 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA3 ==> EMMC_DAT3 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA4 ==> EMMC_DAT4 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA5 ==> EMMC_DAT5 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA6 ==> EMMC_DAT6 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA7 ==> EMMC_DAT7 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_RCLK ==> EMMC_RCLK */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_CLK ==> EMMC_CLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_RESET# ==> EMMC_RST_L */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* H6 : NC */ + PAD_NC(GPP_H6, NONE), + /* H7 : NC */ + PAD_NC(GPP_H7, NONE), + /* H19 : MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_H19, NONE, PLTRST), + /* H22 : MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_H22, NONE, PLTRST), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + uint32_t sku_id = get_board_sku(); + /* For SSD SKU */ + if (sku_id == 2) { + *num = ARRAY_SIZE(ssd_sku_gpio_table); + return ssd_sku_gpio_table; + } + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* + * GPIOs configured before ramstage + * Note: the Hatch platform's romstage will configure + * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins + * as inputs before it reads them, so they are not + * needed in this table. + */ +static const struct pad_config early_gpio_table[] = { + /* A12 : NC */ + PAD_NC(GPP_A12, NONE), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..31f72b3f03 --- /dev/null +++ b/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/soc/mediatek/mt8173/bl31_plat_params.c b/src/mainboard/google/hatch/variants/akemi/include/variant/ec.h similarity index 79% rename from src/soc/mediatek/mt8173/bl31_plat_params.c rename to src/mainboard/google/hatch/variants/akemi/include/variant/ec.h index 245866a104..768987d225 100644 --- a/src/soc/mediatek/mt8173/bl31_plat_params.c +++ b/src/mainboard/google/hatch/variants/akemi/include/variant/ec.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. + * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -12,9 +12,10 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include -void *soc_get_bl31_plat_params(bl31_params_t *bl31_params) -{ - return NULL; -} +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/akemi/include/variant/gpio.h b/src/mainboard/google/hatch/variants/akemi/include/variant/gpio.h new file mode 100644 index 0000000000..b257589a0e --- /dev/null +++ b/src/mainboard/google/hatch/variants/akemi/include/variant/gpio.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_H19 +#define GPIO_MEM_CONFIG_1 GPP_H22 +#define GPIO_MEM_CONFIG_2 GPP_F10 +#define GPIO_MEM_CONFIG_3 GPP_F3 + +#endif diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb new file mode 100644 index 0000000000..5ba8531ba3 --- /dev/null +++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb @@ -0,0 +1,181 @@ +chip soc/intel/cannonlake + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | FP MCU | + #| I2C0 | Touchpad | + #| I2C1 | Touch screen | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 25, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 150, + .fall_time_ns = 150, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 120, + .fall_time_ns = 120, + }, + }" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + # Enable eMMC HS400 + register "ScsEmmcHs400Enabled" = "1" + + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "wake" = "GPE0_DW0_21" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "generic.wake" = "GPE0_DW0_21" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "100" + register "reset_off_delay_ms" = "5" + register "has_power_resource" = "1" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "stop_off_delay_ms" = "5" + device i2c 10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "10" + register "generic.reset_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" + register "key.wake" = "GPE0_DW0_08" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 on + chip drivers/i2c/sx9310 + register "desc" = ""SAR Proximity Sensor"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A0)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "reg_prox_ctrl0" = "0x10" + register "reg_prox_ctrl1" = "0x00" + register "reg_prox_ctrl2" = "0x84" + register "reg_prox_ctrl3" = "0x0e" + register "reg_prox_ctrl4" = "0x07" + register "reg_prox_ctrl5" = "0xc6" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" + register "reg_prox_ctrl9" = "0x43" + register "reg_prox_ctrl10" = "0x1f" + register "reg_prox_ctrl11" = "0x00" + register "reg_prox_ctrl12" = "0x00" + register "reg_prox_ctrl13" = "0x00" + register "reg_prox_ctrl14" = "0x00" + register "reg_prox_ctrl15" = "0x00" + register "reg_prox_ctrl16" = "0x00" + register "reg_prox_ctrl17" = "0x00" + register "reg_prox_ctrl18" = "0x00" + register "reg_prox_ctrl19" = "0x00" + register "reg_sar_ctrl0" = "0x50" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" + device i2c 28 on end + end + end # I2C #3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1a.0 on end # eMMC + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" + device spi 1 on end + end # FPMCU + end # GSPI #1 + end + +end diff --git a/src/mainboard/google/hatch/variants/akemi/variant.c b/src/mainboard/google/hatch/variants/akemi/variant.c new file mode 100644 index 0000000000..0717e810ce --- /dev/null +++ b/src/mainboard/google/hatch/variants/akemi/variant.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +void variant_devtree_update(void) +{ + uint32_t sku_id; + struct device *emmc_host; + struct device *ssd_host; + config_t *cfg = config_of_path(SA_DEVFN_ROOT); + emmc_host = pcidev_path_on_root(PCH_DEVFN_EMMC); + ssd_host = pcidev_path_on_root(PCH_DEVFN_SATA); + + /* SKU ID 2 doesn't have a eMMC device, hence disable it. */ + sku_id = get_board_sku(); + if (sku_id == 2) { + if (emmc_host == NULL) + return; + emmc_host->enabled = 0; + cfg->ScsEmmcHs400Enabled = 0; + } + + /* SKU ID 1 doesn't have a SSD device, hence disable it. */ + if (sku_id == 1) { + if (ssd_host == NULL) + return; + ssd_host->enabled = 0; + cfg->SataSalpSupport = 0; + cfg->SataMode = 0; + cfg->SataPortsEnable[1] = 0; + cfg->SataPortsDevSlp[1] = 0; + cfg->satapwroptimize = 0; + } +} diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 00198a5a81..7382209264 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -24,6 +24,8 @@ chip soc/intel/cannonlake register "SataMode" = "Sata_AHCI" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" + # Configure devslp pad reset to PLT_RST + register "SataPortsDevSlpResetConfig[1]" = "SataDevSlpPlatformReset" register "satapwroptimize" = "1" # Enable System Agent dynamic frequency register "SaGv" = "SaGv_Enabled" @@ -46,6 +48,8 @@ chip soc/intel/cannonlake register "tcc_offset" = "10" # TCC of 90C # Unlock GPIO pads register "PchUnlockGpioPads" = "1" + # SD card WP pin confguration + register "ScsSdCardWpPinEnabled" = "0" # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of @@ -168,11 +172,12 @@ chip soc/intel/cannonlake register "PcieClkSrcUsage[3]" = "13" register "PcieClkSrcClkReq[3]" = "3" - #Enable I2S Audio, SSP0, SSP1 and DMIC0 + #Enable I2S Audio, SSP0, SSP1 and DMIC0, default DMIC1 N/A (by variants override) register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkSsp0" = "1" register "PchHdaAudioLinkSsp1" = "1" register "PchHdaAudioLinkDmic0" = "1" + register "PchHdaAudioLinkDmic1" = "0" # GPIO PM programming register "gpio_override_pm" = "1" diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index fcb1a614cc..240bb5d23b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -31,7 +31,7 @@ static const struct pad_config gpio_table[] = { /* A7 : PP3300_SOC_A */ PAD_NC(GPP_A7, NONE), /* A8 : PEN_GARAGE_DET_L (wake) */ - PAD_CFG_GPI_GPIO_DRIVER_SCI(GPP_A8, NONE, DEEP, LEVEL, NONE), + PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), /* A9 : ESPI_CLK */ /* A10 : FPMCU_PCH_BOOT1 */ PAD_CFG_GPO(GPP_A10, 0, DEEP), diff --git a/src/mainboard/google/hatch/variants/dratini/Makefile.inc b/src/mainboard/google/hatch/variants/dratini/Makefile.inc new file mode 100644 index 0000000000..d82d7979e5 --- /dev/null +++ b/src/mainboard/google/hatch/variants/dratini/Makefile.inc @@ -0,0 +1,25 @@ +## This file is part of the coreboot project. +## +## Copyright 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = 4G_2400 # 0b000 +SPD_SOURCES += empty_ddr4 # 0b001 +SPD_SOURCES += 8G_2400 # 0b010 +SPD_SOURCES += 8G_2666 # 0b011 +SPD_SOURCES += 16G_2400 # 0b100 +SPD_SOURCES += 16G_2666 # 0b101 +SPD_SOURCES += 8G_3200 # 0b110 +SPD_SOURCES += 16G_3200 # 0b111 + +bootblock-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c new file mode 100644 index 0000000000..003b7d129e --- /dev/null +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -0,0 +1,138 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +static const struct pad_config gpio_table[] = { + /* A0 : NC */ + PAD_NC(GPP_A0, NONE), + /* A6 : NC */ + PAD_NC(GPP_A6, NONE), + /* A8 : NC */ + PAD_NC(GPP_A8, NONE), + /* A10 : NC */ + PAD_NC(GPP_A10, NONE), + /* A18 : NC */ + PAD_NC(GPP_A18, NONE), + /* A19 : NC */ + PAD_NC(GPP_A19, NONE), + /* C15 : NC */ + PAD_NC(GPP_C15, NONE), + /* F1 : NC */ + PAD_NC(GPP_F1, NONE), + /* F3 : MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_F3, NONE, PLTRST), + /* F10 : MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + /* F11 : EMMC_CMD ==> EMMC_CMD */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_DATA0 ==> EMMC_DAT0 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA1 ==> EMMC_DAT1 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA2 ==> EMMC_DAT2 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA3 ==> EMMC_DAT3 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA4 ==> EMMC_DAT4 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA5 ==> EMMC_DAT5 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA6 ==> EMMC_DAT6 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA7 ==> EMMC_DAT7 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_RCLK ==> EMMC_RCLK */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_CLK ==> EMMC_CLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_RESET# ==> EMMC_RST_L */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* H19 : MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_H19, NONE, PLTRST), + /* H22 : MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_H22, NONE, PLTRST), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* + * GPIOs configured before ramstage + * Note: the Hatch platform's romstage will configure + * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins + * as inputs before it reads them, so they are not + * needed in this table. + */ +static const struct pad_config early_gpio_table[] = { + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), + /* F11 : EMMC_CMD ==> EMMC_CMD */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_DATA0 ==> EMMC_DAT0 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA1 ==> EMMC_DAT1 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA2 ==> EMMC_DAT2 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA3 ==> EMMC_DAT3 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA4 ==> EMMC_DAT4 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA5 ==> EMMC_DAT5 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA6 ==> EMMC_DAT6 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA7 ==> EMMC_DAT7 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_RCLK ==> EMMC_RCLK */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_CLK ==> EMMC_CLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_RESET# ==> EMMC_RST_L */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..31f72b3f03 --- /dev/null +++ b/src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/mainboard/google/hatch/variants/dratini/include/variant/ec.h b/src/mainboard/google/hatch/variants/dratini/include/variant/ec.h new file mode 100644 index 0000000000..768987d225 --- /dev/null +++ b/src/mainboard/google/hatch/variants/dratini/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h b/src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h new file mode 100644 index 0000000000..92f9d412fd --- /dev/null +++ b/src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_H19 +#define GPIO_MEM_CONFIG_1 GPP_H22 +#define GPIO_MEM_CONFIG_2 GPP_F10 +#define GPIO_MEM_CONFIG_3 GPP_F3 + +#endif diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb new file mode 100644 index 0000000000..65649d1d45 --- /dev/null +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -0,0 +1,149 @@ +chip soc/intel/cannonlake + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | FP MCU | + #| I2C0 | Touchpad | + #| I2C1 | Touch screen | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + # Enable eMMC HS400 + register "ScsEmmcHs400Enabled" = "1" + + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "wake" = "GPE0_DW0_21" + register "probed" = "1" + device i2c 15 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "100" + register "reset_off_delay_ms" = "5" + register "has_power_resource" = "1" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "stop_off_delay_ms" = "5" + device i2c 10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "10" + register "generic.reset_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" + register "key.wake" = "GPE0_DW0_08" + register "key.wakeup_event_action" = "EV_ACT_ASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1a.0 on end # eMMC + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" + device spi 1 on end + end # FPMCU + end # GSPI #1 + end + +end diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index e40a566482..df2cc381e9 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -15,6 +15,15 @@ chip soc/intel/cannonlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # VR Slew rate setting + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRateForIa" = "2" + register "SlowSlewRateForGt" = "2" + register "SlowSlewRateForSa" = "2" + register "FastPkgCRampDisableIa" = "1" + register "FastPkgCRampDisableGt" = "1" + register "FastPkgCRampDisableSa" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -89,7 +98,7 @@ chip soc/intel/cannonlake register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "10" + register "generic.reset_delay_ms" = "500" register "generic.reset_off_delay_ms" = "3" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" register "generic.enable_delay_ms" = "12" diff --git a/src/mainboard/google/hatch/variants/helios/gpio.c b/src/mainboard/google/hatch/variants/helios/gpio.c index 0ad3967ee9..bebcf32662 100644 --- a/src/mainboard/google/hatch/variants/helios/gpio.c +++ b/src/mainboard/google/hatch/variants/helios/gpio.c @@ -125,6 +125,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C11 : GPP_C11 ==> EN_FP_RAILS */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl index f1f09438fa..e3159c8d59 100644 --- a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl @@ -13,4 +13,134 @@ * GNU General Public License for more details. */ -#include +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 105 +#define DPTF_CPU_ACTIVE_AC0 87 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 83 +#define DPTF_CPU_ACTIVE_AC3 80 +#define DPTF_CPU_ACTIVE_AC4 75 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Battery Charger" +#define DPTF_TSR0_PASSIVE 65 +#define DPTF_TSR0_CRITICAL 75 +#define DPTF_TSR0_ACTIVE_AC0 50 +#define DPTF_TSR0_ACTIVE_AC1 47 +#define DPTF_TSR0_ACTIVE_AC2 45 +#define DPTF_TSR0_ACTIVE_AC3 42 +#define DPTF_TSR0_ACTIVE_AC4 40 +#define DPTF_TSR0_ACTIVE_AC5 38 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "5V Regulator" +#define DPTF_TSR1_PASSIVE 45 +#define DPTF_TSR1_CRITICAL 65 +#define DPTF_TSR1_ACTIVE_AC0 50 +#define DPTF_TSR1_ACTIVE_AC1 47 +#define DPTF_TSR1_ACTIVE_AC2 45 +#define DPTF_TSR1_ACTIVE_AC3 42 +#define DPTF_TSR1_ACTIVE_AC4 40 +#define DPTF_TSR1_ACTIVE_AC5 38 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Ambient" +#define DPTF_TSR2_PASSIVE 50 +#define DPTF_TSR2_CRITICAL 65 +#define DPTF_TSR2_ACTIVE_AC0 50 +#define DPTF_TSR2_ACTIVE_AC1 47 +#define DPTF_TSR2_ACTIVE_AC2 45 +#define DPTF_TSR2_ACTIVE_AC3 42 +#define DPTF_TSR2_ACTIVE_AC4 40 +#define DPTF_TSR2_ACTIVE_AC5 38 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 100, 80, 60, 55, 40, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 30, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 30, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 90, 69, 56, 46, 36, 30, 0, + 0, 0, 0 + } +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 60, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on TSR0 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on TSR1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on TSR2 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 8000, /* PowerLimitMinimum */ + 13000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 64000, /* PowerLimitMinimum */ + 64000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index f97f120e7b..8ca878d43c 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -1,4 +1,7 @@ chip soc/intel/cannonlake + register "tdp_pl1_override" = "13" + register "tdp_pl2_override" = "64" + register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -100,7 +103,7 @@ chip soc/intel/cannonlake register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "10" + register "generic.reset_delay_ms" = "500" register "generic.reset_off_delay_ms" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" diff --git a/src/mainboard/google/hatch/variants/kindred/Makefile.inc b/src/mainboard/google/hatch/variants/kindred/Makefile.inc index 78f3812252..8b7e3d1014 100644 --- a/src/mainboard/google/hatch/variants/kindred/Makefile.inc +++ b/src/mainboard/google/hatch/variants/kindred/Makefile.inc @@ -18,6 +18,8 @@ SPD_SOURCES += 8G_2400 # 0b010 SPD_SOURCES += 8G_2666 # 0b011 SPD_SOURCES += 16G_2400 # 0b100 SPD_SOURCES += 16G_2666 # 0b101 +SPD_SOURCES += 8G_3200 # 0b110 +SPD_SOURCES += 16G_3200 # 0b111 bootblock-y += gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/kindred/gpio.c b/src/mainboard/google/hatch/variants/kindred/gpio.c index d6525e6564..827ee0b504 100644 --- a/src/mainboard/google/hatch/variants/kindred/gpio.c +++ b/src/mainboard/google/hatch/variants/kindred/gpio.c @@ -18,6 +18,82 @@ #include #include +static const struct pad_config ssd_sku_gpio_table[] = { + /* F3 : MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_F3, NONE, PLTRST), + /* F10 : MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + /* F11 : EMMC_CMD ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : EMMC_DATA0 ==> NC */ + PAD_NC(GPP_F12, NONE), + /* F13 : EMMC_DATA1 ==> NC */ + PAD_NC(GPP_F13, NONE), + /* F14 : EMMC_DATA2 ==> NC */ + PAD_NC(GPP_F14, NONE), + /* F15 : EMMC_DATA3 ==> NC */ + PAD_NC(GPP_F15, NONE), + /* F16 : EMMC_DATA4 ==> NC */ + PAD_NC(GPP_F16, NONE), + /* F17 : EMMC_DATA5 ==> NC */ + PAD_NC(GPP_F17, NONE), + /* F18 : EMMC_DATA6 ==> NC */ + PAD_NC(GPP_F18, NONE), + /* F19 : EMMC_DATA7 ==> NC */ + PAD_NC(GPP_F19, NONE), + /* F20 : EMMC_RCLK ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : EMMC_CLK ==> NC */ + PAD_NC(GPP_F21, NONE), + /* F22 : EMMC_RESET# ==> NC */ + PAD_NC(GPP_F22, NONE), + /* H19 : MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_H19, NONE, PLTRST), + /* H22 : MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_H22, NONE, PLTRST), +}; + +static const struct pad_config emmc_sku_gpio_table[] = { + /* E1 : M2_SSD_PEDET ==> NC */ + PAD_NC(GPP_E1, NONE), + /* E4 : M2_SSD_PE_WAKE_ODL ==> NC */ + PAD_NC(GPP_E4, NONE), + /* E5 : SATA_DEVSLP1 ==> NC */ + PAD_NC(GPP_E5, NONE), + /* F3 : MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_F3, NONE, PLTRST), + /* F10 : MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + /* F11 : EMMC_CMD ==> EMMC_CMD */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_DATA0 ==> EMMC_DAT0 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA1 ==> EMMC_DAT1 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA2 ==> EMMC_DAT2 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA3 ==> EMMC_DAT3 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA4 ==> EMMC_DAT4 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA5 ==> EMMC_DAT5 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA6 ==> EMMC_DAT6 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA7 ==> EMMC_DAT7 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_RCLK ==> EMMC_RCLK */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_CLK ==> EMMC_CLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_RESET# ==> EMMC_RST_L */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* H19 : MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_H19, NONE, PLTRST), + /* H22 : MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_H22, NONE, PLTRST), +}; + static const struct pad_config gpio_table[] = { /* F3 : MEM_STRAP_3 */ PAD_CFG_GPI(GPP_F3, NONE, PLTRST), @@ -55,6 +131,17 @@ static const struct pad_config gpio_table[] = { const struct pad_config *override_gpio_table(size_t *num) { + uint32_t sku_id = get_board_sku(); + /* For SSD SKU */ + if (sku_id == 1 || sku_id == 3 || sku_id == 23 || sku_id == 24) { + *num = ARRAY_SIZE(ssd_sku_gpio_table); + return ssd_sku_gpio_table; + } + /* For eMMC SKU */ + if (sku_id == 2 || sku_id == 4 || sku_id == 21 || sku_id == 22) { + *num = ARRAY_SIZE(emmc_sku_gpio_table); + return emmc_sku_gpio_table; + } *num = ARRAY_SIZE(gpio_table); return gpio_table; } diff --git a/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl index f1f09438fa..43c1b08508 100644 --- a/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl @@ -13,4 +13,121 @@ * GNU General Public License for more details. */ -#include +#define DPTF_CPU_PASSIVE 90 +#define DPTF_CPU_CRITICAL 105 +#define DPTF_CPU_ACTIVE_AC0 95 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor - Charger" +#define DPTF_TSR0_PASSIVE 65 +#define DPTF_TSR0_CRITICAL 75 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor - CPU" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 75 +#define DPTF_TSR1_ACTIVE_AC0 51 +#define DPTF_TSR1_ACTIVE_AC1 48 +#define DPTF_TSR1_ACTIVE_AC2 45 +#define DPTF_TSR1_ACTIVE_AC3 42 +#define DPTF_TSR1_ACTIVE_AC4 39 +#define DPTF_TSR1_ACTIVE_AC5 36 +#define DPTF_TSR1_ACTIVE_AC6 33 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Thermal Sensor - WIFI" +#define DPTF_TSR2_PASSIVE 65 +#define DPTF_TSR2_CRITICAL 75 +#define DPTF_TSR2_ACTIVE_AC0 55 +#define DPTF_TSR2_ACTIVE_AC1 50 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 80, 70, 60, 50, 40, 30, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 100, 80, 0, 0, 0, 0, 0, + 0, 0, 0 + } +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR0) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on CPU (TSR1) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on WIFI (TSR2) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 51000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index becfc49cae..272cbfb6ea 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -1,4 +1,6 @@ chip soc/intel/cannonlake + register "tdp_pl1_override" = "15" + register "tdp_pl2_override" = "51" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -23,7 +25,6 @@ chip soc/intel/cannonlake #| | required to set up a BAR | #| | for TPM communication | #| | before memory is up | - #| GSPI1 | FP MCU | #| I2C0 | Touchpad | #| I2C1 | Touch screen | #| I2C4 | Audio | @@ -50,6 +51,51 @@ chip soc/intel/cannonlake # Enable eMMC HS400 register "ScsEmmcHs400Enabled" = "1" + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-14.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-14.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x0F10" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-14.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2F2D2D" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-14.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C121936" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-14.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1182D" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-14.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1414" + device domain 0 on device pci 15.0 on chip drivers/i2c/generic @@ -79,9 +125,10 @@ chip soc/intel/cannonlake register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "reset_delay_ms" = "100" register "reset_off_delay_ms" = "5" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "enable_delay_ms" = "10" + register "enable_off_delay_ms" = "1" register "has_power_resource" = "1" - register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" - register "stop_off_delay_ms" = "5" device i2c 49 on end end chip drivers/i2c/generic @@ -92,22 +139,12 @@ chip soc/intel/cannonlake register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "reset_delay_ms" = "1" register "reset_off_delay_ms" = "2" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "enable_delay_ms" = "10" + register "enable_off_delay_ms" = "1" register "has_power_resource" = "1" device i2c 39 on end end - chip drivers/i2c/hid - register "generic.hid" = ""GDIX0000"" - register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "10" - register "generic.reset_off_delay_ms" = "1" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 5d on end - end chip drivers/generic/gpio_keys register "name" = ""PENH"" register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" @@ -120,39 +157,8 @@ chip soc/intel/cannonlake device generic 0 on end end end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 on - chip drivers/i2c/sx9310 - register "desc" = ""SAR Proximity Sensor"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A0)" - register "speed" = "I2C_SPEED_FAST" - register "uid" = "1" - register "reg_prox_ctrl0" = "0x10" - register "reg_prox_ctrl1" = "0x00" - register "reg_prox_ctrl2" = "0x84" - register "reg_prox_ctrl3" = "0x0e" - register "reg_prox_ctrl4" = "0x07" - register "reg_prox_ctrl5" = "0xc6" - register "reg_prox_ctrl6" = "0x20" - register "reg_prox_ctrl7" = "0x0d" - register "reg_prox_ctrl8" = "0x8d" - register "reg_prox_ctrl9" = "0x43" - register "reg_prox_ctrl10" = "0x1f" - register "reg_prox_ctrl11" = "0x00" - register "reg_prox_ctrl12" = "0x00" - register "reg_prox_ctrl13" = "0x00" - register "reg_prox_ctrl14" = "0x00" - register "reg_prox_ctrl15" = "0x00" - register "reg_prox_ctrl16" = "0x00" - register "reg_prox_ctrl17" = "0x00" - register "reg_prox_ctrl18" = "0x00" - register "reg_prox_ctrl19" = "0x00" - register "reg_sar_ctrl0" = "0x50" - register "reg_sar_ctrl1" = "0x8a" - register "reg_sar_ctrl2" = "0x3c" - device i2c 28 on end - end - end # I2C #3 + device pci 15.2 off end # I2C #2 unused + device pci 15.3 off end # I2C #3 unused device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -168,16 +174,7 @@ chip soc/intel/cannonlake end end #I2C #4 device pci 1a.0 on end # eMMC - device pci 1e.3 on - chip drivers/spi/acpi - register "name" = ""CRFP"" - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "uid" = "1" - register "compat_string" = ""google,cros-ec-spi"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" - device spi 1 on end - end # FPMCU - end # GSPI #1 + device pci 1e.3 off end # GSPI #1 unused end end diff --git a/src/mainboard/google/hatch/variants/kindred/variant.c b/src/mainboard/google/hatch/variants/kindred/variant.c index 14b26ed10c..6cd017bf60 100644 --- a/src/mainboard/google/hatch/variants/kindred/variant.c +++ b/src/mainboard/google/hatch/variants/kindred/variant.c @@ -14,6 +14,7 @@ */ #include +#include #include #include @@ -21,14 +22,28 @@ void variant_devtree_update(void) { uint32_t sku_id; struct device *emmc_host; - + struct device *ssd_host; + config_t *cfg = config_of_path(SA_DEVFN_ROOT); emmc_host = pcidev_path_on_root(PCH_DEVFN_EMMC); + ssd_host = pcidev_path_on_root(PCH_DEVFN_SATA); - if (emmc_host == NULL) - return; - - /* SKU ID 1, 3 doesn't have a eMMC device, hence disable it. */ + /* SKU ID 1/3/23/24 doesn't have a eMMC device, hence disable it. */ sku_id = get_board_sku(); - if (sku_id == 1 || sku_id == 3) + if (sku_id == 1 || sku_id == 3 || sku_id == 23 || sku_id == 24) { + if (emmc_host == NULL) + return; emmc_host->enabled = 0; + cfg->ScsEmmcHs400Enabled = 0; + } + /* SKU ID 2/4/21/22 doesn't have a SSD device, hence disable it. */ + if (sku_id == 2 || sku_id == 4 || sku_id == 21 || sku_id == 22) { + if (ssd_host == NULL) + return; + ssd_host->enabled = 0; + cfg->SataSalpSupport = 0; + cfg->SataMode = 0; + cfg->SataPortsEnable[1] = 0; + cfg->SataPortsDevSlp[1] = 0; + cfg->satapwroptimize = 0; + } } diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 53a58c9df7..9654388087 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -26,7 +26,7 @@ static const struct pad_config gpio_table[] = { /* A10 : PEN_RESET_ODL */ PAD_CFG_GPO(GPP_A10, 1, DEEP), /* A16 : EMR_GARAGE_DET (notification) */ - PAD_CFG_GPI_APIC(GPP_A16, NONE, PLTRST, LEVEL, NONE), + PAD_CFG_GPI_GPIO_DRIVER(GPP_A16, NONE, PLTRST), /* A17 : PIRQA# ==> NC */ PAD_NC(GPP_A17, NONE), /* A18 : ISH_GP0 ==> NC */ diff --git a/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl index 06df7b178f..13a501a29e 100644 --- a/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl @@ -13,18 +13,36 @@ * GNU General Public License for more details. */ -#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_PASSIVE 50 #define DPTF_CPU_CRITICAL 105 #define DPTF_TSR0_SENSOR_ID 0 -#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" -#define DPTF_TSR0_PASSIVE 49 -#define DPTF_TSR0_CRITICAL 75 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor - Charger" +#define DPTF_TSR0_PASSIVE 45 +#define DPTF_TSR0_CRITICAL 90 +#define DPTF_TSR0_TABLET_PASSIVE 32 +#define DPTF_TSR0_TABLET_CRITICAL 90 #define DPTF_TSR1_SENSOR_ID 1 -#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" -#define DPTF_TSR1_PASSIVE 65 -#define DPTF_TSR1_CRITICAL 75 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor - 5V" +#define DPTF_TSR1_PASSIVE 45 +#define DPTF_TSR1_CRITICAL 90 +#define DPTF_TSR1_TABLET_PASSIVE 32 +#define DPTF_TSR1_TABLET_CRITICAL 90 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Thermal Sensor - IA" +#define DPTF_TSR2_PASSIVE 45 +#define DPTF_TSR2_CRITICAL 90 +#define DPTF_TSR2_TABLET_PASSIVE 32 +#define DPTF_TSR2_TABLET_CRITICAL 90 + +#define DPTF_TSR3_SENSOR_ID 3 +#define DPTF_TSR3_SENSOR_NAME "Thermal Sensor - GT" +#define DPTF_TSR3_PASSIVE 45 +#define DPTF_TSR3_CRITICAL 90 +#define DPTF_TSR3_TABLET_PASSIVE 32 +#define DPTF_TSR3_TABLET_CRITICAL 90 #define DPTF_ENABLE_CHARGER @@ -38,13 +56,19 @@ Name (CHPS, Package () { Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 10, 0, 0, 0, 0 }, - /* CPU Throttle Effect on Ambient (TSR0) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 94, 0, 0, 0, 0 }, + /* CPU Throttle Effect on 5V (TSR1) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 10, 0, 0, 0, 0 }, - /* Charger Throttle Effect on Charger (TSR1) */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, + /* Charger Throttle Effect on Charger (TSR0) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 94, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on IA (TSR2) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 10, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on GT (TSR3) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR3, 100, 10, 0, 0, 0, 0 }, }) Name (MPPC, Package () @@ -52,8 +76,8 @@ Name (MPPC, Package () 0x2, /* Revision */ Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 8000, /* PowerLimitMinimum */ - 15000, /* PowerLimitMaximum */ + 7000, /* PowerLimitMinimum */ + 9000, /* PowerLimitMaximum */ 28000, /* TimeWindowMinimum */ 28000, /* TimeWindowMaximum */ 250 /* StepSize */ diff --git a/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h b/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h index 768987d225..84e050eacf 100644 --- a/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h @@ -18,4 +18,6 @@ #include +#define EC_ENABLE_MULTIPLE_DPTF_PROFILES + #endif diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 13025c83f7..8c7bb1ff9a 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -2,6 +2,8 @@ chip soc/intel/cannonlake register "tdp_pl1_override" = "8" register "tdp_pl2_override" = "51" + register "tcc_offset" = "35" # TCC of 65C + register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -20,6 +22,27 @@ chip soc/intel/cannonlake # No PCIe WiFi register "PcieRpEnable[13]" = "0" + # Enable DMIC1 + register "PchHdaAudioLinkDmic1" = "1" + + register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 0 + register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 + register "usb2_ports[2]" = "USB2_PORT_EMPTY" + register "usb2_ports[3]" = "USB2_PORT_LONG(OC_SKIP)" # SD CARD + register "usb2_ports[4]" = "USB2_PORT_EMPTY" + register "usb2_ports[5]" = "USB2_PORT_EMPTY" + register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # CnVi BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # World facing camera + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD CARD + register "usb3_ports[4]" = "USB3_PORT_EMPTY" + register "usb3_ports[5]" = "USB3_PORT_EMPTY" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -58,15 +81,78 @@ chip soc/intel/cannonlake device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.1 on end + end + chip drivers/usb/acpi + device usb 2.2 off end + end + chip drivers/usb/acpi + register "desc" = ""Micro SD Card"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.3 on end + end + chip drivers/usb/acpi + device usb 2.4 off end + end chip drivers/usb/acpi device usb 2.5 off end end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + device usb 2.7 off end + end + chip drivers/usb/acpi + device usb 2.8 off end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C14)" + device usb 2.9 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""WF Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Micro SD card"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.3 on end + end chip drivers/usb/acpi device usb 3.4 off end end end end end + device pci 14.5 off end # SDCard device pci 15.0 on @@ -83,9 +169,10 @@ chip soc/intel/cannonlake device pci 15.1 on chip drivers/i2c/generic - register "hid" = ""ATML0001"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""atmel,maxtouch"" register "desc" = ""Atmel Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "reset_delay_ms" = "91" # 90.5 ms register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C12)" diff --git a/src/mainboard/google/jecht/smihandler.c b/src/mainboard/google/jecht/smihandler.c index 9475361105..8e8c9d4b5d 100644 --- a/src/mainboard/google/jecht/smihandler.c +++ b/src/mainboard/google/jecht/smihandler.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index 886e14f265..8e5d8eb5b1 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -39,7 +39,7 @@ static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { PSO_END }; /* Liara-specific 2T memory configuration */ -static const PSO_ENTRY DDR4LiaraMemoryConfiguration[] = { +static const PSO_ENTRY DDR4_2T_MemoryConfiguration[] = { DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, DIMMS_PER_CHANNEL), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH), @@ -58,9 +58,9 @@ static const PSO_ENTRY DDR4LiaraMemoryConfiguration[] = { void OemPostParams(AMD_POST_PARAMS *PostParams) { - if (CONFIG(BOARD_GOOGLE_LIARA)) + if (CONFIG(BOARD_GOOGLE_LIARA) || CONFIG(BOARD_GOOGLE_TREEYA)) PostParams->MemConfig.PlatformMemoryConfiguration = - (PSO_ENTRY *)DDR4LiaraMemoryConfiguration; + (PSO_ENTRY *)DDR4_2T_MemoryConfiguration; else PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration; diff --git a/src/mainboard/google/kahlee/romstage.c b/src/mainboard/google/kahlee/romstage.c index 8bc766e112..ebe59ac77f 100644 --- a/src/mainboard/google/kahlee/romstage.c +++ b/src/mainboard/google/kahlee/romstage.c @@ -28,7 +28,7 @@ void __weak variant_romstage_entry(int s3_resume) /* By default, don't do anything */ } -void mainboard_romstage_entry(int s3_resume) +void mainboard_romstage_entry_s3(int s3_resume) { size_t num_gpios; const struct soc_amd_gpio *gpios; diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/empty.spd.hex b/src/mainboard/google/kahlee/spd/empty.spd.hex similarity index 100% rename from src/mainboard/google/kahlee/variants/baseboard/spd/empty.spd.hex rename to src/mainboard/google/kahlee/spd/empty.spd.hex diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5AN8G6NAFR-UH.spd.hex b/src/mainboard/google/kahlee/spd/hynix-H5AN8G6NAFR-UH.spd.hex similarity index 100% rename from src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5AN8G6NAFR-UH.spd.hex rename to src/mainboard/google/kahlee/spd/hynix-H5AN8G6NAFR-UH.spd.hex diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5AN8G6NCJR-VKC.spd.hex b/src/mainboard/google/kahlee/spd/hynix-H5AN8G6NCJR-VKC.spd.hex similarity index 100% rename from src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5AN8G6NCJR-VKC.spd.hex rename to src/mainboard/google/kahlee/spd/hynix-H5AN8G6NCJR-VKC.spd.hex diff --git a/src/mainboard/google/kahlee/spd/hynix-H5AN8G6NCJR-XNC.spd.hex b/src/mainboard/google/kahlee/spd/hynix-H5AN8G6NCJR-XNC.spd.hex new file mode 100644 index 0000000000..9993fa1dcf --- /dev/null +++ b/src/mainboard/google/kahlee/spd/hynix-H5AN8G6NCJR-XNC.spd.hex @@ -0,0 +1,33 @@ +# H5AN8G6NCJR-XNC +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B4 00 00 00 00 E7 00 75 20 +0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 AD 01 00 00 00 00 00 00 48 4D 41 38 35 31 53 +36 43 4A 52 36 4E 2D 58 4E 20 20 20 20 00 80 AD +FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 DD 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5ANAG6NAMR-UH.spd.hex b/src/mainboard/google/kahlee/spd/hynix-H5ANAG6NAMR-UH.spd.hex similarity index 100% rename from src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5ANAG6NAMR-UH.spd.hex rename to src/mainboard/google/kahlee/spd/hynix-H5ANAG6NAMR-UH.spd.hex diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5ANAG6NCMR-VKC.spd.hex b/src/mainboard/google/kahlee/spd/hynix-H5ANAG6NCMR-VKC.spd.hex similarity index 100% rename from src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5ANAG6NCMR-VKC.spd.hex rename to src/mainboard/google/kahlee/spd/hynix-H5ANAG6NCMR-VKC.spd.hex diff --git a/src/mainboard/google/kahlee/spd/hynix-H5ANAG6NCMR-XNC.spd.hex b/src/mainboard/google/kahlee/spd/hynix-H5ANAG6NCMR-XNC.spd.hex new file mode 100644 index 0000000000..b20c17ed62 --- /dev/null +++ b/src/mainboard/google/kahlee/spd/hynix-H5ANAG6NCMR-XNC.spd.hex @@ -0,0 +1,33 @@ +# Hynix H5ANAG6NCMR-XNC +23 11 0C 03 85 21 91 08 00 60 00 03 01 03 00 00 +00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 A8 14 28 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 C0 6E +0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 7D 21 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 AD 01 00 00 00 00 00 00 48 35 41 4E 41 47 36 +4E 43 4D 52 2D 58 4E 43 20 20 20 20 20 00 80 AD +FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 DD 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ No newline at end of file diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A1G16KNR-075-E.spd.hex b/src/mainboard/google/kahlee/spd/micron-MT40A1G16KNR-075-E.spd.hex similarity index 100% rename from src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A1G16KNR-075-E.spd.hex rename to src/mainboard/google/kahlee/spd/micron-MT40A1G16KNR-075-E.spd.hex diff --git a/src/mainboard/google/kahlee/spd/micron-MT40A1G16RC-062E-B.spd.hex b/src/mainboard/google/kahlee/spd/micron-MT40A1G16RC-062E-B.spd.hex new file mode 100644 index 0000000000..52a4a1bcdd --- /dev/null +++ b/src/mainboard/google/kahlee/spd/micron-MT40A1G16RC-062E-B.spd.hex @@ -0,0 +1,33 @@ +# MT40A1G16RC-062E:B +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 40 36 +0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 31 47 +31 36 52 43 2D 30 36 32 45 3A 42 20 20 31 80 2C +42 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16JY-083E-B.spd.hex b/src/mainboard/google/kahlee/spd/micron-MT40A512M16JY-083E-B.spd.hex similarity index 100% rename from src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16JY-083E-B.spd.hex rename to src/mainboard/google/kahlee/spd/micron-MT40A512M16JY-083E-B.spd.hex diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16LY-075-E.spd.hex b/src/mainboard/google/kahlee/spd/micron-MT40A512M16LY-075-E.spd.hex similarity index 100% rename from src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16LY-075-E.spd.hex rename to src/mainboard/google/kahlee/spd/micron-MT40A512M16LY-075-E.spd.hex diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16TB-062E-J.spd.hex b/src/mainboard/google/kahlee/spd/micron-MT40A512M16TB-062E-J.spd.hex similarity index 100% rename from src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16TB-062E-J.spd.hex rename to src/mainboard/google/kahlee/spd/micron-MT40A512M16TB-062E-J.spd.hex diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/samsung-K4A8G165WB-BCRC.spd.hex b/src/mainboard/google/kahlee/spd/samsung-K4A8G165WB-BCRC.spd.hex similarity index 100% rename from src/mainboard/google/kahlee/variants/baseboard/spd/samsung-K4A8G165WB-BCRC.spd.hex rename to src/mainboard/google/kahlee/spd/samsung-K4A8G165WB-BCRC.spd.hex diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/samsung-K4A8G165WC-BCTD.spd.hex b/src/mainboard/google/kahlee/spd/samsung-K4A8G165WC-BCTD.spd.hex similarity index 100% rename from src/mainboard/google/kahlee/variants/baseboard/spd/samsung-K4A8G165WC-BCTD.spd.hex rename to src/mainboard/google/kahlee/spd/samsung-K4A8G165WC-BCTD.spd.hex diff --git a/src/mainboard/google/kahlee/spd/samsung-K4A8G165WC-BCWE.spd.hex b/src/mainboard/google/kahlee/spd/samsung-K4A8G165WC-BCWE.spd.hex new file mode 100644 index 0000000000..4f148ce1ab --- /dev/null +++ b/src/mainboard/google/kahlee/spd/samsung-K4A8G165WC-BCWE.spd.hex @@ -0,0 +1,33 @@ +# Samsung-K4A8G165WC-BCWE +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 14 98 +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 35 32 +34 34 43 42 30 2D 43 57 45 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/kahlee/spd/samsung-K4AAG165WA-BCTD.spd.hex b/src/mainboard/google/kahlee/spd/samsung-K4AAG165WA-BCTD.spd.hex new file mode 100644 index 0000000000..f747f7c34e --- /dev/null +++ b/src/mainboard/google/kahlee/spd/samsung-K4AAG165WA-BCTD.spd.hex @@ -0,0 +1,33 @@ +# Samsung K4AAG165WA-BCTD +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 F7 4B +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4B 34 41 41 47 31 36 +35 57 41 2D 42 43 54 44 20 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/kahlee/spd/samsung-K4AAG165WA-BCWE.spd.hex b/src/mainboard/google/kahlee/spd/samsung-K4AAG165WA-BCWE.spd.hex new file mode 100644 index 0000000000..390e5a5417 --- /dev/null +++ b/src/mainboard/google/kahlee/spd/samsung-K4AAG165WA-BCWE.spd.hex @@ -0,0 +1,33 @@ +# Samsung K4AAG165WA-BCWE +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 E8 F5 +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4B 34 41 41 47 31 36 +35 57 41 2D 42 43 57 45 20 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/samsung-K4AAG165WB-MCRC.spd.hex b/src/mainboard/google/kahlee/spd/samsung-K4AAG165WB-MCRC.spd.hex similarity index 100% rename from src/mainboard/google/kahlee/variants/baseboard/spd/samsung-K4AAG165WB-MCRC.spd.hex rename to src/mainboard/google/kahlee/spd/samsung-K4AAG165WB-MCRC.spd.hex diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/samsung-K4AAG165WB-MCTD.spd.hex b/src/mainboard/google/kahlee/spd/samsung-K4AAG165WB-MCTD.spd.hex similarity index 100% rename from src/mainboard/google/kahlee/variants/baseboard/spd/samsung-K4AAG165WB-MCTD.spd.hex rename to src/mainboard/google/kahlee/spd/samsung-K4AAG165WB-MCTD.spd.hex diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c index 95274eb85d..30fcc8c2a2 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c +++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -24,7 +25,7 @@ #include #include -uint8_t variant_board_sku(void) +uint32_t sku_id(void) { static int sku = -1; @@ -34,6 +35,11 @@ uint8_t variant_board_sku(void) return sku; } +uint8_t variant_board_sku(void) +{ + return sku_id(); +} + void variant_mainboard_suspend_resume(void) { /* Enable backlight - GPIO 133 active low */ diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/Makefile.inc b/src/mainboard/google/kahlee/variants/baseboard/spd/Makefile.inc index 213fc051f8..b6a57b73ba 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/spd/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/baseboard/spd/Makefile.inc @@ -14,7 +14,7 @@ ## GNU General Public License for more details. ## -LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/baseboard/spd/$(f).spd.hex) +LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) SPD_SOURCES = hynix-H5AN8G6NAFR-UH # 0b0000 SPD_SOURCES += hynix-H5ANAG6NAMR-UH # 0b0001 diff --git a/src/mainboard/google/kahlee/variants/careena/Makefile.inc b/src/mainboard/google/kahlee/variants/careena/Makefile.inc index 0579e1899f..17ea78eee0 100644 --- a/src/mainboard/google/kahlee/variants/careena/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/careena/Makefile.inc @@ -13,7 +13,7 @@ # GNU General Public License for more details. # -subdirs-y += ../baseboard/spd +subdirs-y += ./spd romstage-y += ../baseboard/romstage.c diff --git a/src/mainboard/google/kahlee/variants/careena/spd/Makefile.inc b/src/mainboard/google/kahlee/variants/careena/spd/Makefile.inc new file mode 100644 index 0000000000..e764bafb27 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/careena/spd/Makefile.inc @@ -0,0 +1,34 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## Copyright (C) 2015 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +SPD_SOURCES = hynix-H5AN8G6NAFR-UH # 0b0000 +SPD_SOURCES += hynix-H5ANAG6NAMR-UH # 0b0001 +SPD_SOURCES += micron-MT40A512M16JY-083E-B # 0b0010 +SPD_SOURCES += micron-MT40A1G16KNR-075-E # 0b0011 +SPD_SOURCES += samsung-K4A8G165WB-BCRC # 0b0100 +SPD_SOURCES += samsung-K4AAG165WB-MCRC # 0b0101 +SPD_SOURCES += micron-MT40A512M16LY-075-E # 0b0110 +SPD_SOURCES += hynix-H5ANAG6NCMR-VKC # 0b0111 +SPD_SOURCES += hynix-H5AN8G6NCJR-VKC # 0b1000 +SPD_SOURCES += samsung-K4A8G165WC-BCTD # 0b1001 +SPD_SOURCES += samsung-K4AAG165WB-MCTD # 0b1010 +SPD_SOURCES += micron-MT40A512M16TB-062E-J # 0b1011 +SPD_SOURCES += samsung-K4AAG165WA-BCTD # 0b1100 +SPD_SOURCES += hynix-H5ANAG6NCMR-XNC # 0b1101 +SPD_SOURCES += micron-MT40A1G16RC-062E-B # 0b1110 +SPD_SOURCES += samsung-K4AAG165WA-BCWE # 0b1111 diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb index d73c47c6b8..a0a1876c3c 100644 --- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb @@ -146,7 +146,7 @@ chip soc/amd/stoneyridge register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" register "probed" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" diff --git a/src/mainboard/google/kahlee/variants/treeya/Makefile.inc b/src/mainboard/google/kahlee/variants/treeya/Makefile.inc index 0579e1899f..17ea78eee0 100644 --- a/src/mainboard/google/kahlee/variants/treeya/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/treeya/Makefile.inc @@ -13,7 +13,7 @@ # GNU General Public License for more details. # -subdirs-y += ../baseboard/spd +subdirs-y += ./spd romstage-y += ../baseboard/romstage.c diff --git a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb index d73c47c6b8..2e25340b6e 100644 --- a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb @@ -35,22 +35,22 @@ chip soc/amd/stoneyridge register "i2c[1]" = "{ .early_init = 1, .speed = I2C_SPEED_FAST, - .rise_time_ns = 62, + .rise_time_ns = 3, .fall_time_ns = 2, }" # Enable I2C2 for trackpad, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 170, - .fall_time_ns = 91, + .rise_time_ns = 3, + .fall_time_ns = 2, }" # Enable I2C3 for touchscreen at 400kHz register "i2c[3]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 84, - .fall_time_ns = 50, + .rise_time_ns = 16, + .fall_time_ns = 8, }" register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ @@ -138,15 +138,38 @@ chip soc/amd/stoneyridge register "desc" = ""ELAN Touchpad"" register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" register "wake" = "7" + register "probed" = "1" device i2c 15 on end end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_5)" + register "generic.wake" = "7" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end end device mmio 0xfedc5000 on + chip drivers/i2c/hid + register "generic.hid" = ""SYTS7817"" + register "generic.desc" = ""Synaptics Touchscreen"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "generic.reset_delay_ms" = "45" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 20 on end + end chip drivers/i2c/generic register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" register "probed" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h b/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h index 96388ae5e0..2d48018ee5 100644 --- a/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h @@ -1,4 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include -/* Enable EC backed Keyboard Backlight in ACPI */ -#define EC_ENABLE_KEYBOARD_BACKLIGHT +/* Enable Tablet switch */ +#define EC_ENABLE_TBMC_DEVICE + +/* + * Enable EC sync interrupt via GPIO controller, EC_SYNC_IRQ is defined in + * variant/gpio.h + */ +#define EC_ENABLE_SYNC_IRQ_GPIO diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/treeya/include/variant/gpio.h index 5a6b54044f..3ddabb1f27 100644 --- a/src/mainboard/google/kahlee/variants/treeya/include/variant/gpio.h +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/gpio.h @@ -14,3 +14,6 @@ */ #include + +/* EC sync irq is AGPIO 10 */ +#define EC_SYNC_IRQ 10 diff --git a/src/mainboard/google/kahlee/variants/treeya/spd/Makefile.inc b/src/mainboard/google/kahlee/variants/treeya/spd/Makefile.inc new file mode 100644 index 0000000000..a2d0d2fc9f --- /dev/null +++ b/src/mainboard/google/kahlee/variants/treeya/spd/Makefile.inc @@ -0,0 +1,34 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## Copyright (C) 2015 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +SPD_SOURCES = hynix-H5AN8G6NAFR-UH # 0b0000 +SPD_SOURCES += hynix-H5ANAG6NAMR-UH # 0b0001 +SPD_SOURCES += micron-MT40A512M16JY-083E-B # 0b0010 +SPD_SOURCES += micron-MT40A1G16KNR-075-E # 0b0011 +SPD_SOURCES += samsung-K4A8G165WB-BCRC # 0b0100 +SPD_SOURCES += samsung-K4AAG165WB-MCRC # 0b0101 +SPD_SOURCES += micron-MT40A512M16LY-075-E # 0b0110 +SPD_SOURCES += hynix-H5ANAG6NCMR-VKC # 0b0111 +SPD_SOURCES += hynix-H5AN8G6NCJR-VKC # 0b1000 +SPD_SOURCES += samsung-K4A8G165WC-BCTD # 0b1001 +SPD_SOURCES += samsung-K4AAG165WB-MCTD # 0b1010 +SPD_SOURCES += micron-MT40A512M16TB-062E-J # 0b1011 +SPD_SOURCES += samsung-K4A8G165WC-BCWE # 0b1100 +SPD_SOURCES += hynix-H5AN8G6NCJR-XNC # 0b1101 +SPD_SOURCES += empty # 0b1110 +SPD_SOURCES += empty # 0b1111 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 863f49ee23..282891846b 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -29,6 +29,7 @@ config BOARD_SPECIFIC_OPTIONS select SOC_MEDIATEK_MT8183 select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS + select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS select COMMON_CBFS_SPI_WRAPPER select SPI_FLASH select FATAL_ASSERTS @@ -41,6 +42,8 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER + select DRIVER_PARADE_PS8640 if BOARD_GOOGLE_JACUZZI + select MT8183_DRAM_EMCP if BOARD_GOOGLE_KRANE config MAINBOARD_DIR string @@ -53,6 +56,7 @@ config MAINBOARD_PART_NUMBER default "Kodama" if BOARD_GOOGLE_KODAMA default "Flapjack" if BOARD_GOOGLE_FLAPJACK default "Jacuzzi" if BOARD_GOOGLE_JACUZZI + default "Juniper" if BOARD_GOOGLE_JUNIPER config DRIVER_TPM_SPI_BUS hex @@ -74,4 +78,5 @@ config GBB_HWID default "KODAMA TEST 7122" if BOARD_GOOGLE_KODAMA default "FLAPJACK TEST 4147" if BOARD_GOOGLE_FLAPJACK default "JACUZZI TEST 6792" if BOARD_GOOGLE_JACUZZI + default "JUNIPER TEST 4819" if BOARD_GOOGLE_JUNIPER endif diff --git a/src/mainboard/google/kukui/Kconfig.name b/src/mainboard/google/kukui/Kconfig.name index 33049e38c2..c7772dd401 100644 --- a/src/mainboard/google/kukui/Kconfig.name +++ b/src/mainboard/google/kukui/Kconfig.name @@ -19,3 +19,7 @@ config BOARD_GOOGLE_FLAPJACK config BOARD_GOOGLE_JACUZZI bool "-> Jacuzzi" select BOARD_GOOGLE_KUKUI_COMMON + +config BOARD_GOOGLE_JUNIPER + bool "-> Juniper" + select BOARD_GOOGLE_KUKUI_COMMON diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index a0556c1a63..2e8a79ad82 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -1,4 +1,5 @@ subdirs-y += sdram_params/ +subdirs-y += panel_params/ bootblock-y += boardid.c bootblock-y += bootblock.c @@ -24,4 +25,9 @@ ramstage-y += boardid.c ramstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += memlayout.ld +ramstage-$(CONFIG_BOARD_GOOGLE_FLAPJACK) += panel_flapjack.c +ramstage-$(CONFIG_BOARD_GOOGLE_KODAMA) += panel_kodama.c +ramstage-$(CONFIG_BOARD_GOOGLE_KRANE) += panel_krane.c +ramstage-$(CONFIG_BOARD_GOOGLE_KUKUI) += panel_kukui.c +ramstage-$(CONFIG_DRIVER_PARADE_PS8640) += panel_ps8640.c ramstage-y += reset.c diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 40b8a49c61..7b00d94ba6 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -13,11 +13,28 @@ * GNU General Public License for more details. */ +#include +#include +#include +#include +#include +#include +#include #include +#include +#include +#include +#include #include #include #include #include +#include + +#include "gpio.h" +#include "panel.h" + +#include static void configure_emmc(void) { @@ -49,11 +66,143 @@ static void configure_audio(void) gpio_set_mode(GPIO(CAM_PDN0), PAD_CAM_PDN0_FUNC_I2S2_MCK); gpio_set_mode(GPIO(EINT3), PAD_EINT3_FUNC_I2S3_DO); } + +/* Default implementation for boards without panels defined yet. */ +struct panel_description __weak *get_panel_description(int panel_id) +{ + printk(BIOS_ERR, "%s: ERROR: No panels defined for board: %s.\n", + __func__, CONFIG_MAINBOARD_PART_NUMBER); + return NULL; +} + +/* Set up backlight control pins as output pin and power-off by default */ +static void configure_panel_backlight(void) +{ + gpio_output(GPIO(PERIPHERAL_EN13), 0); + gpio_output(GPIO(DISP_PWM), 0); +} + +static void power_on_panel(struct panel_description *panel) +{ + if (panel->power_on) { + panel->power_on(); + return; + } + + /* Default power sequence for most panels. */ + gpio_output(GPIO_LCM_RST_1V8, 0); + gpio_output(GPIO_PPVARP_LCD_EN, 1); + gpio_output(GPIO_PPVARN_LCD_EN, 1); + gpio_output(GPIO_PP1800_LCM_EN, 1); + gpio_output(GPIO_PP3300_LCM_EN, 1); + mdelay(6); + gpio_output(GPIO_LCM_RST_1V8, 1); + mdelay(6); +} + +struct panel_description *get_panel_from_cbfs(struct panel_description *desc) +{ + /* The CBFS name will be panel-{MANUFACTURER}-${PANEL_NAME}, + * where MANUFACTURER is 3 characters and PANEL_NAME is usually + * 13 characters. + */ + char cbfs_name[64]; + static union { + u8 raw[4 * 1024]; /* Most panels only need < 2K. */ + struct panel_serializable_data s; + } buffer; + + if (!desc->name) + return NULL; + + snprintf(cbfs_name, sizeof(cbfs_name), "panel-%s", desc->name); + if (cbfs_boot_load_file(cbfs_name, buffer.raw, sizeof(buffer), + CBFS_TYPE_STRUCT)) + desc->s = &buffer.s; + else + printk(BIOS_ERR, "Missing %s in CBFS.\n", cbfs_name); + + return desc->s ? desc : NULL; +} + +static struct panel_description *get_active_panel(void) +{ + /* TODO(hungte) Create a dedicated panel_id() in board_id.c */ + int panel_id = sku_id() >> 4; + + struct panel_description *panel = get_panel_description(panel_id); + if (!panel) { + printk(BIOS_ERR, "%s: Panel %d is not supported.\n", + __func__, panel_id); + return NULL; + } + assert(panel->s); + + const struct edid *edid = &panel->s->edid; + const char *name = edid->ascii_string; + if (name[0] == '\0') + name = "unknown name"; + printk(BIOS_INFO, "%s: Found ID %d: '%s %s' %dx%d@%dHz\n", __func__, + panel_id, edid->manufacturer_name, name, edid->mode.ha, + edid->mode.va, edid->mode.refresh); + return panel; +} + +static bool configure_display(void) +{ + struct panel_description *panel = get_active_panel(); + if (!panel) + return false; + + mtcmos_display_power_on(); + mtcmos_protect_display_bus(); + configure_panel_backlight(); + power_on_panel(panel); + + struct edid *edid = &panel->s->edid; + edid_set_framebuffer_bits_per_pixel(edid, 32, 0); + mtk_ddp_init(); + u32 mipi_dsi_flags = (MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM); + if (mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, edid, + panel->s->init) < 0) { + printk(BIOS_ERR, "%s: Failed in DSI init.\n", __func__); + return false; + } + mtk_ddp_mode_set(edid); + set_vbe_mode_info_valid(edid, 0); + set_vbe_framebuffer_orientation(panel->s->orientation); + return true; +} + +static void register_reset_to_bl31(void) +{ + static struct bl_aux_param_gpio param_reset = { + .h = { .type = BL_AUX_PARAM_MTK_RESET_GPIO }, + .gpio = { .polarity = ARM_TF_GPIO_LEVEL_HIGH }, + }; + + param_reset.gpio.index = GPIO_RESET.id; + register_bl31_aux_param(¶m_reset.h); +} + static void mainboard_init(struct device *dev) { + if (display_init_required()) { + printk(BIOS_INFO, "%s: Starting display init.\n", __func__); + if (!configure_display()) + printk(BIOS_ERR, "%s: Failed to init display.\n", + __func__); + } else { + printk(BIOS_INFO, "%s: Skipped display init.\n", __func__); + } + configure_emmc(); configure_usb(); configure_audio(); + + register_reset_to_bl31(); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/google/kukui/panel.h b/src/mainboard/google/kukui/panel.h new file mode 100644 index 0000000000..0156cd68bf --- /dev/null +++ b/src/mainboard/google/kukui/panel.h @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Huaqin Telecom Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_GOOGLE_KUKUI_PANEL_H__ +#define __MAINBOARD_GOOGLE_KUKUI_PANEL_H__ + +#include +#include + +/* + * The data that to be serialized and put into CBFS. + * Note some fields, for example edid.mode.name, were actually pointers and + * cannot be really serialized. + */ +struct panel_serializable_data { + struct edid edid; /* edid info of this panel */ + enum lb_fb_orientation orientation; /* Panel orientation */ + u8 init[]; /* A packed array of lcm_init_command */ +}; + +struct panel_description { + const char *name; /* Panel name for constructing CBFS file name */ + struct panel_serializable_data *s; + void (*power_on)(void); /* Callback to turn on panel */ +}; + +/* Returns the panel description from given ID. */ +struct panel_description *get_panel_description(int panel_id); + +/* Loads panel serializable data from CBFS. */ +struct panel_description *get_panel_from_cbfs(struct panel_description *desc); + +#define INIT_DCS_CMD(...) \ + LCM_DCS_CMD, \ + sizeof((u8[]){__VA_ARGS__}), \ + __VA_ARGS__ + +#define INIT_GENERIC_CMD(...) \ + LCM_GENERIC_CMD, \ + sizeof((u8[]){__VA_ARGS__}), \ + __VA_ARGS__ + +#define INIT_DELAY_CMD(delay) \ + LCM_DELAY_CMD, \ + delay + +#define INIT_END_CMD \ + LCM_END_CMD + +/* GPIO names */ +#define GPIO_LCM_RST_1V8 GPIO(LCM_RST) /* 45 */ +#define GPIO_MIPIBRDG_PWRDN_L_1V8 GPIO(LCM_RST) /* 45 */ +#define GPIO_MIPIBRDG_RST_L_1V8 GPIO(BPI_BUS3) /* 73 */ +#define GPIO_PP1200_MIPIBRDG_EN GPIO(BPI_OLAT1) /* 54 */ +#define GPIO_PP1800_LCM_EN GPIO(SIM2_SRST) /* 36 */ +#define GPIO_PP3300_LCM_EN GPIO(SIM2_SIO) /* 35 */ +#define GPIO_PPVARN_LCD_EN GPIO(PERIPHERAL_EN9) /* 166 */ +#define GPIO_PPVARP_LCD_EN GPIO(MISC_BSI_CK_3) /* 66 */ +#define GPIO_VDDIO_MIPIBRDG_EN GPIO(SIM2_SCLK) /* 37 */ + +#endif /* __MAINBOARD_GOOGLE_KUKUI_PANEL_H__ */ diff --git a/src/mainboard/google/kukui/panel_flapjack.c b/src/mainboard/google/kukui/panel_flapjack.c new file mode 100644 index 0000000000..b10cc709a7 --- /dev/null +++ b/src/mainboard/google/kukui/panel_flapjack.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "panel.h" + +static struct panel_description flapjack_panels[] = { + [0] = { .name = "BOE_TV101WUM_NG0", }, + [1] = { .name = "BOE_TV080WUM_NG0", }, + [2] = { .name = "INX_OTA7290D10P", }, + [3] = { .name = "AUO_NT51021D8P", }, +}; + +struct panel_description *get_panel_description(int panel_id) +{ + if (panel_id < 0 || panel_id >= ARRAY_SIZE(flapjack_panels)) + return NULL; + + return get_panel_from_cbfs(&flapjack_panels[panel_id]); +} diff --git a/src/mainboard/google/kukui/panel_kodama.c b/src/mainboard/google/kukui/panel_kodama.c new file mode 100644 index 0000000000..033e469964 --- /dev/null +++ b/src/mainboard/google/kukui/panel_kodama.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Bitland Tech Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "panel.h" + +static struct panel_description kodama_panels[] = { + [1] = { .name = "AUO_B101UAN08_3", }, + [2] = { .name = "BOE_TV101WUM_N53", }, +}; + +struct panel_description *get_panel_description(int panel_id) +{ + if (panel_id < 0 || panel_id >= ARRAY_SIZE(kodama_panels)) + return NULL; + + return get_panel_from_cbfs(&kodama_panels[panel_id]); +} diff --git a/src/mainboard/google/kukui/panel_krane.c b/src/mainboard/google/kukui/panel_krane.c new file mode 100644 index 0000000000..4694e49485 --- /dev/null +++ b/src/mainboard/google/kukui/panel_krane.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Huaqin Telecom Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "panel.h" + +static struct panel_description krane_panels[] = { + [0] = { .name = "AUO_KD101N80_45NA", }, + [1] = { .name = "BOE_TV101WUM_NL6", }, /* Only Rev3, can be reused. */ + [11] = { .name = "BOE_TV101WUM_NL6", }, +}; + +struct panel_description *get_panel_description(int panel_id) +{ + if (panel_id < 0 || panel_id >= ARRAY_SIZE(krane_panels)) + return NULL; + + return get_panel_from_cbfs(&krane_panels[panel_id]); +} diff --git a/src/mainboard/google/kukui/panel_kukui.c b/src/mainboard/google/kukui/panel_kukui.c new file mode 100644 index 0000000000..bca5c6ef26 --- /dev/null +++ b/src/mainboard/google/kukui/panel_kukui.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Huaqin Telecom Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#include "panel.h" + +static void power_on_ssd2858(void) +{ + gpio_output(GPIO_MIPIBRDG_PWRDN_L_1V8, 0); + gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 0); + gpio_output(GPIO_PPVARP_LCD_EN, 1); + gpio_output(GPIO_PPVARN_LCD_EN, 1); + gpio_output(GPIO_PP1800_LCM_EN, 1); + gpio_output(GPIO_PP3300_LCM_EN, 1); + gpio_output(GPIO_PP1200_MIPIBRDG_EN, 1); + gpio_output(GPIO_VDDIO_MIPIBRDG_EN, 1); + mdelay(20); + gpio_output(GPIO_MIPIBRDG_PWRDN_L_1V8, 1); + mdelay(20); + gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 1); + mdelay(20); +} + +static struct panel_description kukui_panel = { + .name = "CMN_P097PFG_SSD2858", + .power_on = power_on_ssd2858, +}; + +struct panel_description *get_panel_description(int panel_id) +{ + /* The Innolux panel before Rev2 is no longer supported. */ + if (board_id() < 2) + return NULL; + + /* Only one panel no matter what panel_id was provided. */ + return get_panel_from_cbfs(&kukui_panel); +} diff --git a/src/mainboard/google/kukui/panel_params/Makefile.inc b/src/mainboard/google/kukui/panel_params/Makefile.inc new file mode 100644 index 0000000000..016dad05ef --- /dev/null +++ b/src/mainboard/google/kukui/panel_params/Makefile.inc @@ -0,0 +1,17 @@ +panel-params-y := +panel-params-$(CONFIG_BOARD_GOOGLE_KRANE) += panel-AUO_KD101N80_45NA +panel-params-$(CONFIG_BOARD_GOOGLE_KRANE) += panel-BOE_TV101WUM_NL6 +panel-params-$(CONFIG_BOARD_GOOGLE_KODAMA) += panel-AUO_B101UAN08_3 +panel-params-$(CONFIG_BOARD_GOOGLE_KODAMA) += panel-BOE_TV101WUM_N53 +panel-params-$(CONFIG_BOARD_GOOGLE_KUKUI) += panel-CMN_P097PFG_SSD2858 +panel-params-$(CONFIG_BOARD_GOOGLE_FLAPJACK) += panel-AUO_NT51021D8P +panel-params-$(CONFIG_BOARD_GOOGLE_FLAPJACK) += panel-BOE_TV080WUM_NG0 +panel-params-$(CONFIG_BOARD_GOOGLE_FLAPJACK) += panel-BOE_TV101WUM_NG0 +panel-params-$(CONFIG_BOARD_GOOGLE_FLAPJACK) += panel-INX_OTA7290D10P + +$(foreach params,$(panel-params-y), \ + $(eval cbfs-files-y += $(params)) \ + $(eval $(params)-file := $(params).c:struct) \ + $(eval $(params)-type := struct) \ + $(eval $(params)-compression := $(CBFS_COMPRESS_FLAG)) \ +) diff --git a/src/mainboard/google/kukui/panel_params/panel-AUO_B101UAN08_3.c b/src/mainboard/google/kukui/panel_params/panel-AUO_B101UAN08_3.c new file mode 100644 index 0000000000..a3da2a8876 --- /dev/null +++ b/src/mainboard/google/kukui/panel_params/panel-AUO_B101UAN08_3.c @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Bitland Tech Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../panel.h" + +struct panel_serializable_data AUO_B101UAN08_3 = { + .edid = { + .ascii_string = "B101UAN08.3", + .manufacturer_name = "AUO", + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .pixel_clock = 159192, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 144, .hso = 60, .hspw = 4, + .va = 1920, .vbl = 60, .vso = 34, .vspw = 2, + .phsync = '-', .pvsync = '-', + .x_mm = 135, .y_mm = 216, + }, + }, + .orientation = LB_FB_ORIENTATION_LEFT_UP, + .init = { + INIT_DELAY_CMD(24), + INIT_DCS_CMD(0xB0, 0x01), + INIT_DCS_CMD(0xC0, 0x48), + INIT_DCS_CMD(0xC1, 0x48), + INIT_DCS_CMD(0xC2, 0x47), + INIT_DCS_CMD(0xC3, 0x47), + INIT_DCS_CMD(0xC4, 0x46), + INIT_DCS_CMD(0xC5, 0x46), + INIT_DCS_CMD(0xC6, 0x45), + INIT_DCS_CMD(0xC7, 0x45), + INIT_DCS_CMD(0xC8, 0x64), + INIT_DCS_CMD(0xC9, 0x64), + INIT_DCS_CMD(0xCA, 0x4F), + INIT_DCS_CMD(0xCB, 0x4F), + INIT_DCS_CMD(0xCC, 0x40), + INIT_DCS_CMD(0xCD, 0x40), + INIT_DCS_CMD(0xCE, 0x66), + INIT_DCS_CMD(0xCF, 0x66), + INIT_DCS_CMD(0xD0, 0x4F), + INIT_DCS_CMD(0xD1, 0x4F), + INIT_DCS_CMD(0xD2, 0x41), + INIT_DCS_CMD(0xD3, 0x41), + INIT_DCS_CMD(0xD4, 0x48), + INIT_DCS_CMD(0xD5, 0x48), + INIT_DCS_CMD(0xD6, 0x47), + INIT_DCS_CMD(0xD7, 0x47), + INIT_DCS_CMD(0xD8, 0x46), + INIT_DCS_CMD(0xD9, 0x46), + INIT_DCS_CMD(0xDA, 0x45), + INIT_DCS_CMD(0xDB, 0x45), + INIT_DCS_CMD(0xDC, 0x64), + INIT_DCS_CMD(0xDD, 0x64), + INIT_DCS_CMD(0xDE, 0x4F), + INIT_DCS_CMD(0xDF, 0x4F), + INIT_DCS_CMD(0xE0, 0x40), + INIT_DCS_CMD(0xE1, 0x40), + INIT_DCS_CMD(0xE2, 0x66), + INIT_DCS_CMD(0xE3, 0x66), + INIT_DCS_CMD(0xE4, 0x4F), + INIT_DCS_CMD(0xE5, 0x4F), + INIT_DCS_CMD(0xE6, 0x41), + INIT_DCS_CMD(0xE7, 0x41), + INIT_DELAY_CMD(150), + INIT_END_CMD, + }, +}; diff --git a/src/mainboard/google/kukui/panel_params/panel-AUO_KD101N80_45NA.c b/src/mainboard/google/kukui/panel_params/panel-AUO_KD101N80_45NA.c new file mode 100644 index 0000000000..924b566fbd --- /dev/null +++ b/src/mainboard/google/kukui/panel_params/panel-AUO_KD101N80_45NA.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Huaqin Telecom Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../panel.h" + +struct panel_serializable_data AUO_KD101N80_45NA = { + .edid = { + .ascii_string = "KD101N80-45NA", + .manufacturer_name = "AUO", + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .pixel_clock = 157000, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 140, .hso = 80, .hspw = 24, + .va = 1920, .vbl = 36, .vso = 16, .vspw = 4, + .phsync = '-', .pvsync = '-', + .x_mm = 135, .y_mm = 216, + }, + }, + .orientation = LB_FB_ORIENTATION_LEFT_UP, + .init = { + INIT_DELAY_CMD(10), + INIT_DCS_CMD(0x11), + INIT_DELAY_CMD(120), + INIT_DCS_CMD(0x29), + INIT_DELAY_CMD(20), + INIT_END_CMD, + }, +}; diff --git a/src/mainboard/google/kukui/panel_params/panel-AUO_NT51021D8P.c b/src/mainboard/google/kukui/panel_params/panel-AUO_NT51021D8P.c new file mode 100644 index 0000000000..8fca7df162 --- /dev/null +++ b/src/mainboard/google/kukui/panel_params/panel-AUO_NT51021D8P.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Huaqin Telecom Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../panel.h" + +struct panel_serializable_data AUO_NT51021D8P = { + .edid = { + .ascii_string = "NT51021D8P", + .manufacturer_name = "AUO", + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .pixel_clock = 159420, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 141, .hso = 80, .hspw = 1, + .va = 1920, .vbl = 61, .vso = 35, .vspw = 1, + .phsync = '-', .pvsync = '-', + .x_mm = 107, .y_mm = 132, + }, + }, + .init = { + INIT_DCS_CMD(0x11), + INIT_DELAY_CMD(0x78), + INIT_DCS_CMD(0x29), + INIT_DELAY_CMD(0x14), + INIT_END_CMD, + }, +}; diff --git a/src/mainboard/google/kukui/panel_params/panel-BOE_TV080WUM_NG0.c b/src/mainboard/google/kukui/panel_params/panel-BOE_TV080WUM_NG0.c new file mode 100644 index 0000000000..5e56eb9ac0 --- /dev/null +++ b/src/mainboard/google/kukui/panel_params/panel-BOE_TV080WUM_NG0.c @@ -0,0 +1,350 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Huaqin Telecom Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../panel.h" + +struct panel_serializable_data BOE_TV080WUM_NG0 = { + .edid = { + .ascii_string = "TV080WUM-NG0", + .manufacturer_name = "BOE", + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .pixel_clock = 159420, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 164, .hso = 80, .hspw = 24, + .va = 1920, .vbl = 28, .vso = 10, .vspw = 4, + .phsync = '-', .pvsync = '-', + .x_mm = 107, .y_mm = 132, + }, + }, + .init = { + INIT_DCS_CMD(0x10), + INIT_DELAY_CMD(0x22), + INIT_DCS_CMD(0xB0, 0x05), + INIT_DCS_CMD(0xB1, 0xE5), + INIT_DCS_CMD(0xB3, 0x52), + INIT_DCS_CMD(0xB0, 0x00), + INIT_DCS_CMD(0xB3, 0x88), + INIT_DCS_CMD(0xB0, 0x04), + INIT_DCS_CMD(0xB8, 0x00), + INIT_DCS_CMD(0xB0, 0x00), + INIT_DCS_CMD(0xB2, 0x50), + INIT_DCS_CMD(0xB6, 0x03), + INIT_DCS_CMD(0xBA, 0x8B), + INIT_DCS_CMD(0xBF, 0x15), + INIT_DCS_CMD(0xC0, 0x0F), + INIT_DCS_CMD(0xC2, 0x0C), + INIT_DCS_CMD(0xC3, 0x02), + INIT_DCS_CMD(0xC4, 0x0C), + INIT_DCS_CMD(0xC5, 0x02), + INIT_DCS_CMD(0xB0, 0x01), + INIT_DCS_CMD(0xE0, 0x26), + INIT_DCS_CMD(0xE1, 0x26), + INIT_DCS_CMD(0xDC, 0x00), + INIT_DCS_CMD(0xDD, 0x00), + INIT_DCS_CMD(0xCC, 0x26), + INIT_DCS_CMD(0xCD, 0x26), + INIT_DCS_CMD(0xC8, 0x00), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xD2, 0x04), + INIT_DCS_CMD(0xD3, 0x04), + INIT_DCS_CMD(0xE6, 0x03), + INIT_DCS_CMD(0xE7, 0x03), + INIT_DCS_CMD(0xC4, 0x08), + INIT_DCS_CMD(0xC5, 0x08), + INIT_DCS_CMD(0xD8, 0x07), + INIT_DCS_CMD(0xD9, 0x07), + INIT_DCS_CMD(0xC2, 0x06), + INIT_DCS_CMD(0xC3, 0x06), + INIT_DCS_CMD(0xD6, 0x05), + INIT_DCS_CMD(0xD7, 0x05), + INIT_DCS_CMD(0xC0, 0x0C), + INIT_DCS_CMD(0xC1, 0x0C), + INIT_DCS_CMD(0xD4, 0x0B), + INIT_DCS_CMD(0xD5, 0x0B), + INIT_DCS_CMD(0xCA, 0x0A), + INIT_DCS_CMD(0xCB, 0x0A), + INIT_DCS_CMD(0xDE, 0x09), + INIT_DCS_CMD(0xDF, 0x09), + INIT_DCS_CMD(0xC6, 0x26), + INIT_DCS_CMD(0xC7, 0x26), + INIT_DCS_CMD(0xCE, 0x00), + INIT_DCS_CMD(0xCF, 0x00), + INIT_DCS_CMD(0xDA, 0x26), + INIT_DCS_CMD(0xDB, 0x26), + INIT_DCS_CMD(0xE2, 0x00), + INIT_DCS_CMD(0xE3, 0x00), + INIT_DCS_CMD(0xB0, 0x02), + INIT_DCS_CMD(0xC0, 0x00), + INIT_DCS_CMD(0xC1, 0x07), + INIT_DCS_CMD(0xC2, 0x0D), + INIT_DCS_CMD(0xC3, 0x18), + INIT_DCS_CMD(0xC4, 0x27), + INIT_DCS_CMD(0xC5, 0x28), + INIT_DCS_CMD(0xC6, 0x30), + INIT_DCS_CMD(0xC7, 0x2E), + INIT_DCS_CMD(0xC8, 0x2F), + INIT_DCS_CMD(0xC9, 0x1A), + INIT_DCS_CMD(0xCA, 0x20), + INIT_DCS_CMD(0xCB, 0x29), + INIT_DCS_CMD(0xCC, 0x26), + INIT_DCS_CMD(0xCD, 0x32), + INIT_DCS_CMD(0xCE, 0x33), + INIT_DCS_CMD(0xCF, 0x31), + INIT_DCS_CMD(0xD0, 0x06), + INIT_DCS_CMD(0xD2, 0x00), + INIT_DCS_CMD(0xD3, 0x07), + INIT_DCS_CMD(0xD4, 0x12), + INIT_DCS_CMD(0xD5, 0x26), + INIT_DCS_CMD(0xD6, 0x3D), + INIT_DCS_CMD(0xD7, 0x3F), + INIT_DCS_CMD(0xD8, 0x3F), + INIT_DCS_CMD(0xD9, 0x3F), + INIT_DCS_CMD(0xDA, 0x3F), + INIT_DCS_CMD(0xDB, 0x3F), + INIT_DCS_CMD(0xDC, 0x3F), + INIT_DCS_CMD(0xDD, 0x3F), + INIT_DCS_CMD(0xDE, 0x3F), + INIT_DCS_CMD(0xDF, 0x3A), + INIT_DCS_CMD(0xE0, 0x37), + INIT_DCS_CMD(0xE1, 0x35), + INIT_DCS_CMD(0xE2, 0x07), + INIT_DCS_CMD(0xB0, 0x03), + INIT_DCS_CMD(0xC8, 0x0B), + INIT_DCS_CMD(0xC9, 0x07), + INIT_DCS_CMD(0xC3, 0x00), + INIT_DCS_CMD(0xE7, 0x00), + INIT_DCS_CMD(0xC5, 0x2A), + INIT_DCS_CMD(0xDE, 0x2A), + INIT_DCS_CMD(0xCA, 0x43), + INIT_DCS_CMD(0xC9, 0x07), + INIT_DCS_CMD(0xE4, 0xC0), + INIT_DCS_CMD(0xE5, 0x0D), + INIT_DCS_CMD(0xCB, 0x00), + INIT_DCS_CMD(0xB0, 0x06), + INIT_DCS_CMD(0xB8, 0xA5), + INIT_DCS_CMD(0xC0, 0xA5), + INIT_DCS_CMD(0xC7, 0x0F), + INIT_DCS_CMD(0xD5, 0x32), + INIT_DCS_CMD(0xB8, 0x00), + INIT_DCS_CMD(0xC0, 0x00), + INIT_DCS_CMD(0xBC, 0x00), + INIT_DCS_CMD(0xB0, 0x07), + INIT_DCS_CMD(0xB1, 0x00), + INIT_DCS_CMD(0xB2, 0x09), + INIT_DCS_CMD(0xB3, 0x19), + INIT_DCS_CMD(0xB4, 0x2F), + INIT_DCS_CMD(0xB5, 0x44), + INIT_DCS_CMD(0xB6, 0x52), + INIT_DCS_CMD(0xB7, 0x6A), + INIT_DCS_CMD(0xB8, 0x8A), + INIT_DCS_CMD(0xB9, 0xCA), + INIT_DCS_CMD(0xBA, 0x0C), + INIT_DCS_CMD(0xBB, 0x87), + INIT_DELAY_CMD(0x05), + INIT_DCS_CMD(0xBC, 0x06), + INIT_DCS_CMD(0xBD, 0x0A), + INIT_DCS_CMD(0xBE, 0x9B), + INIT_DCS_CMD(0xBF, 0x0C), + INIT_DCS_CMD(0xC0, 0x3D), + INIT_DCS_CMD(0xC1, 0x71), + INIT_DCS_CMD(0xC2, 0x90), + INIT_DCS_CMD(0xC3, 0xA0), + INIT_DCS_CMD(0xC4, 0xA8), + INIT_DCS_CMD(0xC5, 0xB1), + INIT_DCS_CMD(0xC6, 0xBB), + INIT_DCS_CMD(0xC7, 0xC0), + INIT_DCS_CMD(0xC8, 0xC4), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x08), + INIT_DCS_CMD(0xB1, 0x04), + INIT_DCS_CMD(0xB2, 0x08), + INIT_DCS_CMD(0xB3, 0x19), + INIT_DCS_CMD(0xB4, 0x31), + INIT_DCS_CMD(0xB5, 0x46), + INIT_DCS_CMD(0xB6, 0x55), + INIT_DCS_CMD(0xB7, 0x6E), + INIT_DCS_CMD(0xB8, 0x92), + INIT_DCS_CMD(0xB9, 0xD4), + INIT_DCS_CMD(0xBA, 0x1B), + INIT_DCS_CMD(0xBB, 0x9B), + INIT_DELAY_CMD(0x05), + INIT_DCS_CMD(0xBC, 0x28), + INIT_DCS_CMD(0xBD, 0x2D), + INIT_DCS_CMD(0xBE, 0xC3), + INIT_DCS_CMD(0xBF, 0x2F), + INIT_DCS_CMD(0xC0, 0x62), + INIT_DCS_CMD(0xC1, 0x99), + INIT_DCS_CMD(0xC2, 0xAB), + INIT_DCS_CMD(0xC3, 0xBF), + INIT_DCS_CMD(0xC4, 0xCF), + INIT_DCS_CMD(0xC5, 0xDF), + INIT_DCS_CMD(0xC6, 0xF0), + INIT_DCS_CMD(0xC7, 0xF9), + INIT_DCS_CMD(0xC8, 0xFC), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x09), + INIT_DCS_CMD(0xB1, 0x04), + INIT_DCS_CMD(0xB2, 0x05), + INIT_DCS_CMD(0xB3, 0x17), + INIT_DCS_CMD(0xB4, 0x2E), + INIT_DCS_CMD(0xB5, 0x42), + INIT_DCS_CMD(0xB6, 0x51), + INIT_DCS_CMD(0xB7, 0x69), + INIT_DCS_CMD(0xB8, 0x88), + INIT_DCS_CMD(0xB9, 0xC9), + INIT_DCS_CMD(0xBA, 0x0C), + INIT_DCS_CMD(0xBB, 0x86), + INIT_DELAY_CMD(0x05), + INIT_DCS_CMD(0xBC, 0x03), + INIT_DCS_CMD(0xBD, 0x08), + INIT_DCS_CMD(0xBE, 0x95), + INIT_DCS_CMD(0xBF, 0x05), + INIT_DCS_CMD(0xC0, 0x35), + INIT_DCS_CMD(0xC1, 0x62), + INIT_DCS_CMD(0xC2, 0x81), + INIT_DCS_CMD(0xC3, 0x96), + INIT_DCS_CMD(0xC4, 0x9E), + INIT_DCS_CMD(0xC5, 0xA5), + INIT_DCS_CMD(0xC6, 0xAD), + INIT_DCS_CMD(0xC7, 0xB1), + INIT_DCS_CMD(0xC8, 0xB4), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x0A), + INIT_DCS_CMD(0xB1, 0x00), + INIT_DCS_CMD(0xB2, 0x09), + INIT_DCS_CMD(0xB3, 0x19), + INIT_DCS_CMD(0xB4, 0x2F), + INIT_DCS_CMD(0xB5, 0x44), + INIT_DCS_CMD(0xB6, 0x52), + INIT_DCS_CMD(0xB7, 0x6A), + INIT_DCS_CMD(0xB8, 0x8A), + INIT_DCS_CMD(0xB9, 0xCA), + INIT_DCS_CMD(0xBA, 0x0C), + INIT_DCS_CMD(0xBB, 0x87), + INIT_DELAY_CMD(0x05), + INIT_DCS_CMD(0xBC, 0x06), + INIT_DCS_CMD(0xBD, 0x0A), + INIT_DCS_CMD(0xBE, 0x9B), + INIT_DCS_CMD(0xBF, 0x0C), + INIT_DCS_CMD(0xC0, 0x3D), + INIT_DCS_CMD(0xC1, 0x71), + INIT_DCS_CMD(0xC2, 0x90), + INIT_DCS_CMD(0xC3, 0xA0), + INIT_DCS_CMD(0xC4, 0xA8), + INIT_DCS_CMD(0xC5, 0xB1), + INIT_DCS_CMD(0xC6, 0xBB), + INIT_DCS_CMD(0xC7, 0xC0), + INIT_DCS_CMD(0xC8, 0xC4), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x0B), + INIT_DCS_CMD(0xB1, 0x04), + INIT_DCS_CMD(0xB2, 0x08), + INIT_DCS_CMD(0xB3, 0x19), + INIT_DCS_CMD(0xB4, 0x31), + INIT_DCS_CMD(0xB5, 0x46), + INIT_DCS_CMD(0xB6, 0x55), + INIT_DCS_CMD(0xB7, 0x6E), + INIT_DCS_CMD(0xB8, 0x92), + INIT_DCS_CMD(0xB9, 0xD4), + INIT_DCS_CMD(0xBA, 0x1B), + INIT_DCS_CMD(0xBB, 0x9B), + INIT_DELAY_CMD(0x05), + INIT_DCS_CMD(0xBC, 0x28), + INIT_DCS_CMD(0xBD, 0x2D), + INIT_DCS_CMD(0xBE, 0xC3), + INIT_DCS_CMD(0xBF, 0x2F), + INIT_DCS_CMD(0xC0, 0x62), + INIT_DCS_CMD(0xC1, 0x99), + INIT_DCS_CMD(0xC2, 0xAB), + INIT_DCS_CMD(0xC3, 0xBF), + INIT_DCS_CMD(0xC4, 0xCF), + INIT_DCS_CMD(0xC5, 0xDF), + INIT_DCS_CMD(0xC6, 0xF0), + INIT_DCS_CMD(0xC7, 0xF9), + INIT_DCS_CMD(0xC8, 0xFC), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x0C), + INIT_DCS_CMD(0xB1, 0x04), + INIT_DCS_CMD(0xB2, 0x05), + INIT_DCS_CMD(0xB3, 0x17), + INIT_DCS_CMD(0xB4, 0x2E), + INIT_DCS_CMD(0xB5, 0x42), + INIT_DCS_CMD(0xB6, 0x51), + INIT_DCS_CMD(0xB7, 0x69), + INIT_DCS_CMD(0xB8, 0x88), + INIT_DCS_CMD(0xB9, 0xC9), + INIT_DCS_CMD(0xBA, 0x0C), + INIT_DCS_CMD(0xBB, 0x86), + INIT_DELAY_CMD(0x05), + INIT_DCS_CMD(0xBC, 0x03), + INIT_DCS_CMD(0xBD, 0x08), + INIT_DCS_CMD(0xBE, 0x95), + INIT_DCS_CMD(0xBF, 0x05), + INIT_DCS_CMD(0xC0, 0x35), + INIT_DCS_CMD(0xC1, 0x62), + INIT_DCS_CMD(0xC2, 0x81), + INIT_DCS_CMD(0xC3, 0x96), + INIT_DCS_CMD(0xC4, 0x9E), + INIT_DCS_CMD(0xC5, 0xA5), + INIT_DCS_CMD(0xC6, 0xAD), + INIT_DCS_CMD(0xC7, 0xB1), + INIT_DCS_CMD(0xC8, 0xB4), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DELAY_CMD(0x64), + INIT_DCS_CMD(0xB0, 0x00), + INIT_DCS_CMD(0xB3, 0x08), + INIT_DCS_CMD(0xB0, 0x04), + INIT_DCS_CMD(0xB8, 0x68), + INIT_DELAY_CMD(0x0A), + INIT_DCS_CMD(0x11), + INIT_DELAY_CMD(0x78), + INIT_DCS_CMD(0x29), + INIT_DELAY_CMD(0x14), + INIT_END_CMD, + }, +}; diff --git a/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_N53.c b/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_N53.c new file mode 100644 index 0000000000..dc5a2ac911 --- /dev/null +++ b/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_N53.c @@ -0,0 +1,330 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Bitland Tech Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../panel.h" + +struct panel_serializable_data BOE_TV101WUM_N53 = { + .edid = { + .ascii_string = "TV101WUM-N53", + .manufacturer_name = "BOE", + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .pixel_clock = 159834, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 164, .hso = 114, .hspw = 10, + .va = 1920, .vbl = 33, .vso = 19, .vspw = 4, + .phsync = '-', .pvsync = '-', + .x_mm = 135, .y_mm = 216, + }, + }, + .orientation = LB_FB_ORIENTATION_LEFT_UP, + .init = { + INIT_DELAY_CMD(24), + INIT_DCS_CMD(0xB0, 0x05), + INIT_DCS_CMD(0xB1, 0xE5), + INIT_DCS_CMD(0xB3, 0x52), + INIT_DCS_CMD(0xB0, 0x00), + INIT_DCS_CMD(0xB3, 0x88), + INIT_DCS_CMD(0xB0, 0x04), + INIT_DCS_CMD(0xB8, 0x00), + INIT_DCS_CMD(0xB0, 0x00), + INIT_DCS_CMD(0xB6, 0x03), + INIT_DCS_CMD(0xBA, 0x8B), + INIT_DCS_CMD(0xBF, 0x1A), + INIT_DCS_CMD(0xC0, 0x0F), + INIT_DCS_CMD(0xC2, 0x0C), + INIT_DCS_CMD(0xC3, 0x02), + INIT_DCS_CMD(0xC4, 0x0C), + INIT_DCS_CMD(0xC5, 0x02), + INIT_DCS_CMD(0xB0, 0x01), + INIT_DCS_CMD(0xE0, 0x26), + INIT_DCS_CMD(0xE1, 0x26), + INIT_DCS_CMD(0xDC, 0x00), + INIT_DCS_CMD(0xDD, 0x00), + INIT_DCS_CMD(0xCC, 0x26), + INIT_DCS_CMD(0xCD, 0x26), + INIT_DCS_CMD(0xC8, 0x00), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xD2, 0x03), + INIT_DCS_CMD(0xD3, 0x03), + INIT_DCS_CMD(0xE6, 0x04), + INIT_DCS_CMD(0xE7, 0x04), + INIT_DCS_CMD(0xC4, 0x09), + INIT_DCS_CMD(0xC5, 0x09), + INIT_DCS_CMD(0xD8, 0x0A), + INIT_DCS_CMD(0xD9, 0x0A), + INIT_DCS_CMD(0xC2, 0x0B), + INIT_DCS_CMD(0xC3, 0x0B), + INIT_DCS_CMD(0xD6, 0x0C), + INIT_DCS_CMD(0xD7, 0x0C), + INIT_DCS_CMD(0xC0, 0x05), + INIT_DCS_CMD(0xC1, 0x05), + INIT_DCS_CMD(0xD4, 0x06), + INIT_DCS_CMD(0xD5, 0x06), + INIT_DCS_CMD(0xCA, 0x07), + INIT_DCS_CMD(0xCB, 0x07), + INIT_DCS_CMD(0xDE, 0x08), + INIT_DCS_CMD(0xDF, 0x08), + INIT_DCS_CMD(0xB0, 0x02), + INIT_DCS_CMD(0xC0, 0x00), + INIT_DCS_CMD(0xC1, 0x0D), + INIT_DCS_CMD(0xC2, 0x17), + INIT_DCS_CMD(0xC3, 0x26), + INIT_DCS_CMD(0xC4, 0x31), + INIT_DCS_CMD(0xC5, 0x1C), + INIT_DCS_CMD(0xC6, 0x2C), + INIT_DCS_CMD(0xC7, 0x33), + INIT_DCS_CMD(0xC8, 0x31), + INIT_DCS_CMD(0xC9, 0x37), + INIT_DCS_CMD(0xCA, 0x37), + INIT_DCS_CMD(0xCB, 0x37), + INIT_DCS_CMD(0xCC, 0x39), + INIT_DCS_CMD(0xCD, 0x2E), + INIT_DCS_CMD(0xCE, 0x2F), + INIT_DCS_CMD(0xCF, 0x2F), + INIT_DCS_CMD(0xD0, 0x07), + INIT_DCS_CMD(0xD2, 0x00), + INIT_DCS_CMD(0xD3, 0x0D), + INIT_DCS_CMD(0xD4, 0x17), + INIT_DCS_CMD(0xD5, 0x26), + INIT_DCS_CMD(0xD6, 0x31), + INIT_DCS_CMD(0xD7, 0x3F), + INIT_DCS_CMD(0xD8, 0x3F), + INIT_DCS_CMD(0xD9, 0x3F), + INIT_DCS_CMD(0xDA, 0x3F), + INIT_DCS_CMD(0xDB, 0x37), + INIT_DCS_CMD(0xDC, 0x37), + INIT_DCS_CMD(0xDD, 0x37), + INIT_DCS_CMD(0xDE, 0x39), + INIT_DCS_CMD(0xDF, 0x2E), + INIT_DCS_CMD(0xE0, 0x2F), + INIT_DCS_CMD(0xE1, 0x2F), + INIT_DCS_CMD(0xE2, 0x07), + INIT_DCS_CMD(0xB0, 0x03), + INIT_DCS_CMD(0xC8, 0x0B), + INIT_DCS_CMD(0xC9, 0x07), + INIT_DCS_CMD(0xC3, 0x00), + INIT_DCS_CMD(0xE7, 0x00), + INIT_DCS_CMD(0xC5, 0x2A), + INIT_DCS_CMD(0xDE, 0x2A), + INIT_DCS_CMD(0xCA, 0x43), + INIT_DCS_CMD(0xC9, 0x07), + INIT_DCS_CMD(0xE4, 0xC0), + INIT_DCS_CMD(0xE5, 0x0D), + INIT_DCS_CMD(0xCB, 0x00), + INIT_DCS_CMD(0xB0, 0x06), + INIT_DCS_CMD(0xB8, 0xA5), + INIT_DCS_CMD(0xC0, 0xA5), + INIT_DCS_CMD(0xC7, 0x0F), + INIT_DCS_CMD(0xD5, 0x32), + INIT_DCS_CMD(0xB8, 0x00), + INIT_DCS_CMD(0xC0, 0x00), + INIT_DCS_CMD(0xBC, 0x00), + INIT_DCS_CMD(0xB0, 0x07), + INIT_DCS_CMD(0xB1, 0x00), + INIT_DCS_CMD(0xB2, 0x02), + INIT_DCS_CMD(0xB3, 0x0F), + INIT_DCS_CMD(0xB4, 0x25), + INIT_DCS_CMD(0xB5, 0x39), + INIT_DCS_CMD(0xB6, 0x4E), + INIT_DCS_CMD(0xB7, 0x72), + INIT_DCS_CMD(0xB8, 0x97), + INIT_DCS_CMD(0xB9, 0xDC), + INIT_DCS_CMD(0xBA, 0x22), + INIT_DCS_CMD(0xBB, 0xA4), + INIT_DCS_CMD(0xBC, 0x2B), + INIT_DCS_CMD(0xBD, 0x2F), + INIT_DCS_CMD(0xBE, 0xA9), + INIT_DCS_CMD(0xBF, 0x25), + INIT_DCS_CMD(0xC0, 0x61), + INIT_DCS_CMD(0xC1, 0x97), + INIT_DCS_CMD(0xC2, 0xB2), + INIT_DCS_CMD(0xC3, 0xCD), + INIT_DCS_CMD(0xC4, 0xD9), + INIT_DCS_CMD(0xC5, 0xE7), + INIT_DCS_CMD(0xC6, 0xF4), + INIT_DCS_CMD(0xC7, 0xFA), + INIT_DCS_CMD(0xC8, 0xFC), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x08), + INIT_DCS_CMD(0xB1, 0x04), + INIT_DCS_CMD(0xB2, 0x05), + INIT_DCS_CMD(0xB3, 0x11), + INIT_DCS_CMD(0xB4, 0x24), + INIT_DCS_CMD(0xB5, 0x39), + INIT_DCS_CMD(0xB6, 0x4F), + INIT_DCS_CMD(0xB7, 0x72), + INIT_DCS_CMD(0xB8, 0x98), + INIT_DCS_CMD(0xB9, 0xDC), + INIT_DCS_CMD(0xBA, 0x23), + INIT_DCS_CMD(0xBB, 0xA6), + INIT_DCS_CMD(0xBC, 0x2C), + INIT_DCS_CMD(0xBD, 0x30), + INIT_DCS_CMD(0xBE, 0xAA), + INIT_DCS_CMD(0xBF, 0x26), + INIT_DCS_CMD(0xC0, 0x62), + INIT_DCS_CMD(0xC1, 0x9B), + INIT_DCS_CMD(0xC2, 0xB5), + INIT_DCS_CMD(0xC3, 0xCF), + INIT_DCS_CMD(0xC4, 0xDB), + INIT_DCS_CMD(0xC5, 0xE8), + INIT_DCS_CMD(0xC6, 0xF5), + INIT_DCS_CMD(0xC7, 0xFA), + INIT_DCS_CMD(0xC8, 0xFC), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x09), + INIT_DCS_CMD(0xB1, 0x04), + INIT_DCS_CMD(0xB2, 0x02), + INIT_DCS_CMD(0xB3, 0x16), + INIT_DCS_CMD(0xB4, 0x24), + INIT_DCS_CMD(0xB5, 0x3B), + INIT_DCS_CMD(0xB6, 0x4F), + INIT_DCS_CMD(0xB7, 0x73), + INIT_DCS_CMD(0xB8, 0x99), + INIT_DCS_CMD(0xB9, 0xE0), + INIT_DCS_CMD(0xBA, 0x26), + INIT_DCS_CMD(0xBB, 0xAD), + INIT_DCS_CMD(0xBC, 0x36), + INIT_DCS_CMD(0xBD, 0x3A), + INIT_DCS_CMD(0xBE, 0xAE), + INIT_DCS_CMD(0xBF, 0x2A), + INIT_DCS_CMD(0xC0, 0x66), + INIT_DCS_CMD(0xC1, 0x9E), + INIT_DCS_CMD(0xC2, 0xB8), + INIT_DCS_CMD(0xC3, 0xD1), + INIT_DCS_CMD(0xC4, 0xDD), + INIT_DCS_CMD(0xC5, 0xE9), + INIT_DCS_CMD(0xC6, 0xF6), + INIT_DCS_CMD(0xC7, 0xFA), + INIT_DCS_CMD(0xC8, 0xFC), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x0A), + INIT_DCS_CMD(0xB1, 0x00), + INIT_DCS_CMD(0xB2, 0x02), + INIT_DCS_CMD(0xB3, 0x0F), + INIT_DCS_CMD(0xB4, 0x25), + INIT_DCS_CMD(0xB5, 0x39), + INIT_DCS_CMD(0xB6, 0x4E), + INIT_DCS_CMD(0xB7, 0x72), + INIT_DCS_CMD(0xB8, 0x97), + INIT_DCS_CMD(0xB9, 0xDC), + INIT_DCS_CMD(0xBA, 0x22), + INIT_DCS_CMD(0xBB, 0xA4), + INIT_DCS_CMD(0xBC, 0x2B), + INIT_DCS_CMD(0xBD, 0x2F), + INIT_DCS_CMD(0xBE, 0xA9), + INIT_DCS_CMD(0xBF, 0x25), + INIT_DCS_CMD(0xC0, 0x61), + INIT_DCS_CMD(0xC1, 0x97), + INIT_DCS_CMD(0xC2, 0xB2), + INIT_DCS_CMD(0xC3, 0xCD), + INIT_DCS_CMD(0xC4, 0xD9), + INIT_DCS_CMD(0xC5, 0xE7), + INIT_DCS_CMD(0xC6, 0xF4), + INIT_DCS_CMD(0xC7, 0xFA), + INIT_DCS_CMD(0xC8, 0xFC), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x0B), + INIT_DCS_CMD(0xB1, 0x04), + INIT_DCS_CMD(0xB2, 0x05), + INIT_DCS_CMD(0xB3, 0x11), + INIT_DCS_CMD(0xB4, 0x24), + INIT_DCS_CMD(0xB5, 0x39), + INIT_DCS_CMD(0xB6, 0x4F), + INIT_DCS_CMD(0xB7, 0x72), + INIT_DCS_CMD(0xB8, 0x98), + INIT_DCS_CMD(0xB9, 0xDC), + INIT_DCS_CMD(0xBA, 0x23), + INIT_DCS_CMD(0xBB, 0xA6), + INIT_DCS_CMD(0xBC, 0x2C), + INIT_DCS_CMD(0xBD, 0x30), + INIT_DCS_CMD(0xBE, 0xAA), + INIT_DCS_CMD(0xBF, 0x26), + INIT_DCS_CMD(0xC0, 0x62), + INIT_DCS_CMD(0xC1, 0x9B), + INIT_DCS_CMD(0xC2, 0xB5), + INIT_DCS_CMD(0xC3, 0xCF), + INIT_DCS_CMD(0xC4, 0xDB), + INIT_DCS_CMD(0xC5, 0xE8), + INIT_DCS_CMD(0xC6, 0xF5), + INIT_DCS_CMD(0xC7, 0xFA), + INIT_DCS_CMD(0xC8, 0xFC), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x0C), + INIT_DCS_CMD(0xB1, 0x04), + INIT_DCS_CMD(0xB2, 0x02), + INIT_DCS_CMD(0xB3, 0x16), + INIT_DCS_CMD(0xB4, 0x24), + INIT_DCS_CMD(0xB5, 0x3B), + INIT_DCS_CMD(0xB6, 0x4F), + INIT_DCS_CMD(0xB7, 0x73), + INIT_DCS_CMD(0xB8, 0x99), + INIT_DCS_CMD(0xB9, 0xE0), + INIT_DCS_CMD(0xBA, 0x26), + INIT_DCS_CMD(0xBB, 0xAD), + INIT_DCS_CMD(0xBC, 0x36), + INIT_DCS_CMD(0xBD, 0x3A), + INIT_DCS_CMD(0xBE, 0xAE), + INIT_DCS_CMD(0xBF, 0x2A), + INIT_DCS_CMD(0xC0, 0x66), + INIT_DCS_CMD(0xC1, 0x9E), + INIT_DCS_CMD(0xC2, 0xB8), + INIT_DCS_CMD(0xC3, 0xD1), + INIT_DCS_CMD(0xC4, 0xDD), + INIT_DCS_CMD(0xC5, 0xE9), + INIT_DCS_CMD(0xC6, 0xF6), + INIT_DCS_CMD(0xC7, 0xFA), + INIT_DCS_CMD(0xC8, 0xFC), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x00), + INIT_DCS_CMD(0xB3, 0x08), + INIT_DCS_CMD(0xB0, 0x04), + INIT_DCS_CMD(0xB8, 0x68), + INIT_DELAY_CMD(150), + INIT_END_CMD, + }, +}; diff --git a/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_NG0.c b/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_NG0.c new file mode 100644 index 0000000000..bb4452ed90 --- /dev/null +++ b/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_NG0.c @@ -0,0 +1,350 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Huaqin Telecom Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../panel.h" + +struct panel_serializable_data BOE_TV101WUM_NG0 = { + .edid = { + .ascii_string = "TV101WUM-NG0", + .manufacturer_name = "BOE", + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .pixel_clock = 159420, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 164, .hso = 80, .hspw = 24, + .va = 1920, .vbl = 28, .vso = 10, .vspw = 4, + .phsync = '-', .pvsync = '-', + .x_mm = 135, .y_mm = 216, + }, + }, + .init = { + INIT_DCS_CMD(0x10), + INIT_DELAY_CMD(0x22), + INIT_DCS_CMD(0xB0, 0x05), + INIT_DCS_CMD(0xB1, 0xE5), + INIT_DCS_CMD(0xB3, 0x52), + INIT_DCS_CMD(0xB0, 0x00), + INIT_DCS_CMD(0xB3, 0x88), + INIT_DCS_CMD(0xB0, 0x04), + INIT_DCS_CMD(0xB8, 0x00), + INIT_DCS_CMD(0xB0, 0x00), + INIT_DCS_CMD(0xB2, 0x50), + INIT_DCS_CMD(0xB6, 0x03), + INIT_DCS_CMD(0xBA, 0x8B), + INIT_DCS_CMD(0xBF, 0x15), + INIT_DCS_CMD(0xC0, 0x0F), + INIT_DCS_CMD(0xC2, 0x0C), + INIT_DCS_CMD(0xC3, 0x02), + INIT_DCS_CMD(0xC4, 0x0C), + INIT_DCS_CMD(0xC5, 0x02), + INIT_DCS_CMD(0xB0, 0x01), + INIT_DCS_CMD(0xE0, 0x26), + INIT_DCS_CMD(0xE1, 0x26), + INIT_DCS_CMD(0xDC, 0x00), + INIT_DCS_CMD(0xDD, 0x00), + INIT_DCS_CMD(0xCC, 0x26), + INIT_DCS_CMD(0xCD, 0x26), + INIT_DCS_CMD(0xC8, 0x00), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xD2, 0x04), + INIT_DCS_CMD(0xD3, 0x04), + INIT_DCS_CMD(0xE6, 0x03), + INIT_DCS_CMD(0xE7, 0x03), + INIT_DCS_CMD(0xC4, 0x08), + INIT_DCS_CMD(0xC5, 0x08), + INIT_DCS_CMD(0xD8, 0x07), + INIT_DCS_CMD(0xD9, 0x07), + INIT_DCS_CMD(0xC2, 0x06), + INIT_DCS_CMD(0xC3, 0x06), + INIT_DCS_CMD(0xD6, 0x05), + INIT_DCS_CMD(0xD7, 0x05), + INIT_DCS_CMD(0xC0, 0x0C), + INIT_DCS_CMD(0xC1, 0x0C), + INIT_DCS_CMD(0xD4, 0x0B), + INIT_DCS_CMD(0xD5, 0x0B), + INIT_DCS_CMD(0xCA, 0x0A), + INIT_DCS_CMD(0xCB, 0x0A), + INIT_DCS_CMD(0xDE, 0x09), + INIT_DCS_CMD(0xDF, 0x09), + INIT_DCS_CMD(0xC6, 0x26), + INIT_DCS_CMD(0xC7, 0x26), + INIT_DCS_CMD(0xCE, 0x00), + INIT_DCS_CMD(0xCF, 0x00), + INIT_DCS_CMD(0xDA, 0x26), + INIT_DCS_CMD(0xDB, 0x26), + INIT_DCS_CMD(0xE2, 0x00), + INIT_DCS_CMD(0xE3, 0x00), + INIT_DCS_CMD(0xB0, 0x02), + INIT_DCS_CMD(0xC0, 0x00), + INIT_DCS_CMD(0xC1, 0x07), + INIT_DCS_CMD(0xC2, 0x0D), + INIT_DCS_CMD(0xC3, 0x18), + INIT_DCS_CMD(0xC4, 0x27), + INIT_DCS_CMD(0xC5, 0x28), + INIT_DCS_CMD(0xC6, 0x30), + INIT_DCS_CMD(0xC7, 0x2E), + INIT_DCS_CMD(0xC8, 0x2F), + INIT_DCS_CMD(0xC9, 0x1A), + INIT_DCS_CMD(0xCA, 0x20), + INIT_DCS_CMD(0xCB, 0x29), + INIT_DCS_CMD(0xCC, 0x26), + INIT_DCS_CMD(0xCD, 0x32), + INIT_DCS_CMD(0xCE, 0x33), + INIT_DCS_CMD(0xCF, 0x31), + INIT_DCS_CMD(0xD0, 0x06), + INIT_DCS_CMD(0xD2, 0x00), + INIT_DCS_CMD(0xD3, 0x07), + INIT_DCS_CMD(0xD4, 0x12), + INIT_DCS_CMD(0xD5, 0x26), + INIT_DCS_CMD(0xD6, 0x3D), + INIT_DCS_CMD(0xD7, 0x3F), + INIT_DCS_CMD(0xD8, 0x3F), + INIT_DCS_CMD(0xD9, 0x3F), + INIT_DCS_CMD(0xDA, 0x3F), + INIT_DCS_CMD(0xDB, 0x3F), + INIT_DCS_CMD(0xDC, 0x3F), + INIT_DCS_CMD(0xDD, 0x3F), + INIT_DCS_CMD(0xDE, 0x3F), + INIT_DCS_CMD(0xDF, 0x3A), + INIT_DCS_CMD(0xE0, 0x37), + INIT_DCS_CMD(0xE1, 0x35), + INIT_DCS_CMD(0xE2, 0x07), + INIT_DCS_CMD(0xB0, 0x03), + INIT_DCS_CMD(0xC8, 0x0B), + INIT_DCS_CMD(0xC9, 0x07), + INIT_DCS_CMD(0xC3, 0x00), + INIT_DCS_CMD(0xE7, 0x00), + INIT_DCS_CMD(0xC5, 0x2A), + INIT_DCS_CMD(0xDE, 0x2A), + INIT_DCS_CMD(0xCA, 0x43), + INIT_DCS_CMD(0xC9, 0x07), + INIT_DCS_CMD(0xE4, 0xC0), + INIT_DCS_CMD(0xE5, 0x0D), + INIT_DCS_CMD(0xCB, 0x00), + INIT_DCS_CMD(0xB0, 0x06), + INIT_DCS_CMD(0xB8, 0xA5), + INIT_DCS_CMD(0xC0, 0xA5), + INIT_DCS_CMD(0xC7, 0x0F), + INIT_DCS_CMD(0xD5, 0x32), + INIT_DCS_CMD(0xB8, 0x00), + INIT_DCS_CMD(0xC0, 0x00), + INIT_DCS_CMD(0xBC, 0x00), + INIT_DCS_CMD(0xB0, 0x07), + INIT_DCS_CMD(0xB1, 0x00), + INIT_DCS_CMD(0xB2, 0x09), + INIT_DCS_CMD(0xB3, 0x19), + INIT_DCS_CMD(0xB4, 0x2F), + INIT_DCS_CMD(0xB5, 0x44), + INIT_DCS_CMD(0xB6, 0x52), + INIT_DCS_CMD(0xB7, 0x6A), + INIT_DCS_CMD(0xB8, 0x8A), + INIT_DCS_CMD(0xB9, 0xCA), + INIT_DCS_CMD(0xBA, 0x0C), + INIT_DCS_CMD(0xBB, 0x87), + INIT_DELAY_CMD(0x05), + INIT_DCS_CMD(0xBC, 0x06), + INIT_DCS_CMD(0xBD, 0x0A), + INIT_DCS_CMD(0xBE, 0x9B), + INIT_DCS_CMD(0xBF, 0x0C), + INIT_DCS_CMD(0xC0, 0x3D), + INIT_DCS_CMD(0xC1, 0x71), + INIT_DCS_CMD(0xC2, 0x90), + INIT_DCS_CMD(0xC3, 0xA0), + INIT_DCS_CMD(0xC4, 0xA8), + INIT_DCS_CMD(0xC5, 0xB1), + INIT_DCS_CMD(0xC6, 0xBB), + INIT_DCS_CMD(0xC7, 0xC0), + INIT_DCS_CMD(0xC8, 0xC4), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x08), + INIT_DCS_CMD(0xB1, 0x04), + INIT_DCS_CMD(0xB2, 0x08), + INIT_DCS_CMD(0xB3, 0x19), + INIT_DCS_CMD(0xB4, 0x31), + INIT_DCS_CMD(0xB5, 0x46), + INIT_DCS_CMD(0xB6, 0x55), + INIT_DCS_CMD(0xB7, 0x6E), + INIT_DCS_CMD(0xB8, 0x92), + INIT_DCS_CMD(0xB9, 0xD4), + INIT_DCS_CMD(0xBA, 0x1B), + INIT_DCS_CMD(0xBB, 0x9B), + INIT_DELAY_CMD(0x05), + INIT_DCS_CMD(0xBC, 0x28), + INIT_DCS_CMD(0xBD, 0x2D), + INIT_DCS_CMD(0xBE, 0xC3), + INIT_DCS_CMD(0xBF, 0x2F), + INIT_DCS_CMD(0xC0, 0x62), + INIT_DCS_CMD(0xC1, 0x99), + INIT_DCS_CMD(0xC2, 0xAB), + INIT_DCS_CMD(0xC3, 0xBF), + INIT_DCS_CMD(0xC4, 0xCF), + INIT_DCS_CMD(0xC5, 0xDF), + INIT_DCS_CMD(0xC6, 0xF0), + INIT_DCS_CMD(0xC7, 0xF9), + INIT_DCS_CMD(0xC8, 0xFC), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x09), + INIT_DCS_CMD(0xB1, 0x04), + INIT_DCS_CMD(0xB2, 0x05), + INIT_DCS_CMD(0xB3, 0x17), + INIT_DCS_CMD(0xB4, 0x2E), + INIT_DCS_CMD(0xB5, 0x42), + INIT_DCS_CMD(0xB6, 0x51), + INIT_DCS_CMD(0xB7, 0x69), + INIT_DCS_CMD(0xB8, 0x88), + INIT_DCS_CMD(0xB9, 0xC9), + INIT_DCS_CMD(0xBA, 0x0C), + INIT_DCS_CMD(0xBB, 0x86), + INIT_DELAY_CMD(0x05), + INIT_DCS_CMD(0xBC, 0x03), + INIT_DCS_CMD(0xBD, 0x08), + INIT_DCS_CMD(0xBE, 0x95), + INIT_DCS_CMD(0xBF, 0x05), + INIT_DCS_CMD(0xC0, 0x35), + INIT_DCS_CMD(0xC1, 0x62), + INIT_DCS_CMD(0xC2, 0x81), + INIT_DCS_CMD(0xC3, 0x96), + INIT_DCS_CMD(0xC4, 0x9E), + INIT_DCS_CMD(0xC5, 0xA5), + INIT_DCS_CMD(0xC6, 0xAD), + INIT_DCS_CMD(0xC7, 0xB1), + INIT_DCS_CMD(0xC8, 0xB4), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x0A), + INIT_DCS_CMD(0xB1, 0x00), + INIT_DCS_CMD(0xB2, 0x09), + INIT_DCS_CMD(0xB3, 0x19), + INIT_DCS_CMD(0xB4, 0x2F), + INIT_DCS_CMD(0xB5, 0x44), + INIT_DCS_CMD(0xB6, 0x52), + INIT_DCS_CMD(0xB7, 0x6A), + INIT_DCS_CMD(0xB8, 0x8A), + INIT_DCS_CMD(0xB9, 0xCA), + INIT_DCS_CMD(0xBA, 0x0C), + INIT_DCS_CMD(0xBB, 0x87), + INIT_DELAY_CMD(0x05), + INIT_DCS_CMD(0xBC, 0x06), + INIT_DCS_CMD(0xBD, 0x0A), + INIT_DCS_CMD(0xBE, 0x9B), + INIT_DCS_CMD(0xBF, 0x0C), + INIT_DCS_CMD(0xC0, 0x3D), + INIT_DCS_CMD(0xC1, 0x71), + INIT_DCS_CMD(0xC2, 0x90), + INIT_DCS_CMD(0xC3, 0xA0), + INIT_DCS_CMD(0xC4, 0xA8), + INIT_DCS_CMD(0xC5, 0xB1), + INIT_DCS_CMD(0xC6, 0xBB), + INIT_DCS_CMD(0xC7, 0xC0), + INIT_DCS_CMD(0xC8, 0xC4), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x0B), + INIT_DCS_CMD(0xB1, 0x04), + INIT_DCS_CMD(0xB2, 0x08), + INIT_DCS_CMD(0xB3, 0x19), + INIT_DCS_CMD(0xB4, 0x31), + INIT_DCS_CMD(0xB5, 0x46), + INIT_DCS_CMD(0xB6, 0x55), + INIT_DCS_CMD(0xB7, 0x6E), + INIT_DCS_CMD(0xB8, 0x92), + INIT_DCS_CMD(0xB9, 0xD4), + INIT_DCS_CMD(0xBA, 0x1B), + INIT_DCS_CMD(0xBB, 0x9B), + INIT_DELAY_CMD(0x05), + INIT_DCS_CMD(0xBC, 0x28), + INIT_DCS_CMD(0xBD, 0x2D), + INIT_DCS_CMD(0xBE, 0xC3), + INIT_DCS_CMD(0xBF, 0x2F), + INIT_DCS_CMD(0xC0, 0x62), + INIT_DCS_CMD(0xC1, 0x99), + INIT_DCS_CMD(0xC2, 0xAB), + INIT_DCS_CMD(0xC3, 0xBF), + INIT_DCS_CMD(0xC4, 0xCF), + INIT_DCS_CMD(0xC5, 0xDF), + INIT_DCS_CMD(0xC6, 0xF0), + INIT_DCS_CMD(0xC7, 0xF9), + INIT_DCS_CMD(0xC8, 0xFC), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x0C), + INIT_DCS_CMD(0xB1, 0x04), + INIT_DCS_CMD(0xB2, 0x05), + INIT_DCS_CMD(0xB3, 0x17), + INIT_DCS_CMD(0xB4, 0x2E), + INIT_DCS_CMD(0xB5, 0x42), + INIT_DCS_CMD(0xB6, 0x51), + INIT_DCS_CMD(0xB7, 0x69), + INIT_DCS_CMD(0xB8, 0x88), + INIT_DCS_CMD(0xB9, 0xC9), + INIT_DCS_CMD(0xBA, 0x0C), + INIT_DCS_CMD(0xBB, 0x86), + INIT_DELAY_CMD(0x05), + INIT_DCS_CMD(0xBC, 0x03), + INIT_DCS_CMD(0xBD, 0x08), + INIT_DCS_CMD(0xBE, 0x95), + INIT_DCS_CMD(0xBF, 0x05), + INIT_DCS_CMD(0xC0, 0x35), + INIT_DCS_CMD(0xC1, 0x62), + INIT_DCS_CMD(0xC2, 0x81), + INIT_DCS_CMD(0xC3, 0x96), + INIT_DCS_CMD(0xC4, 0x9E), + INIT_DCS_CMD(0xC5, 0xA5), + INIT_DCS_CMD(0xC6, 0xAD), + INIT_DCS_CMD(0xC7, 0xB1), + INIT_DCS_CMD(0xC8, 0xB4), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DELAY_CMD(0x64), + INIT_DCS_CMD(0xB0, 0x00), + INIT_DCS_CMD(0xB3, 0x08), + INIT_DCS_CMD(0xB0, 0x04), + INIT_DCS_CMD(0xB8, 0x68), + INIT_DELAY_CMD(0x0A), + INIT_DCS_CMD(0x11), + INIT_DELAY_CMD(0x78), + INIT_DCS_CMD(0x29), + INIT_DELAY_CMD(0x14), + INIT_END_CMD, + }, +}; diff --git a/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_NL6.c b/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_NL6.c new file mode 100644 index 0000000000..928f7fecb9 --- /dev/null +++ b/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_NL6.c @@ -0,0 +1,330 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Huaqin Telecom Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../panel.h" + +struct panel_serializable_data BOE_TV101WUM_NL6 = { + .edid = { + .ascii_string = "TV101WUM-NL6", + .manufacturer_name = "BOE", + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .pixel_clock = 159425, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 164, .hso = 100, .hspw = 24, + .va = 1920, .vbl = 28, .vso = 10, .vspw = 4, + .phsync = '-', .pvsync = '-', + .x_mm = 135, .y_mm = 216, + }, + }, + .orientation = LB_FB_ORIENTATION_LEFT_UP, + .init = { + INIT_DELAY_CMD(24), + INIT_DCS_CMD(0xB0, 0x05), + INIT_DCS_CMD(0xB1, 0xE5), + INIT_DCS_CMD(0xB3, 0x52), + INIT_DCS_CMD(0xB0, 0x00), + INIT_DCS_CMD(0xB3, 0x88), + INIT_DCS_CMD(0xB0, 0x04), + INIT_DCS_CMD(0xB8, 0x00), + INIT_DCS_CMD(0xB0, 0x00), + INIT_DCS_CMD(0xB6, 0x03), + INIT_DCS_CMD(0xBA, 0x8B), + INIT_DCS_CMD(0xBF, 0x1A), + INIT_DCS_CMD(0xC0, 0x0F), + INIT_DCS_CMD(0xC2, 0x0C), + INIT_DCS_CMD(0xC3, 0x02), + INIT_DCS_CMD(0xC4, 0x0C), + INIT_DCS_CMD(0xC5, 0x02), + INIT_DCS_CMD(0xB0, 0x01), + INIT_DCS_CMD(0xE0, 0x26), + INIT_DCS_CMD(0xE1, 0x26), + INIT_DCS_CMD(0xDC, 0x00), + INIT_DCS_CMD(0xDD, 0x00), + INIT_DCS_CMD(0xCC, 0x26), + INIT_DCS_CMD(0xCD, 0x26), + INIT_DCS_CMD(0xC8, 0x00), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xD2, 0x03), + INIT_DCS_CMD(0xD3, 0x03), + INIT_DCS_CMD(0xE6, 0x04), + INIT_DCS_CMD(0xE7, 0x04), + INIT_DCS_CMD(0xC4, 0x09), + INIT_DCS_CMD(0xC5, 0x09), + INIT_DCS_CMD(0xD8, 0x0A), + INIT_DCS_CMD(0xD9, 0x0A), + INIT_DCS_CMD(0xC2, 0x0B), + INIT_DCS_CMD(0xC3, 0x0B), + INIT_DCS_CMD(0xD6, 0x0C), + INIT_DCS_CMD(0xD7, 0x0C), + INIT_DCS_CMD(0xC0, 0x05), + INIT_DCS_CMD(0xC1, 0x05), + INIT_DCS_CMD(0xD4, 0x06), + INIT_DCS_CMD(0xD5, 0x06), + INIT_DCS_CMD(0xCA, 0x07), + INIT_DCS_CMD(0xCB, 0x07), + INIT_DCS_CMD(0xDE, 0x08), + INIT_DCS_CMD(0xDF, 0x08), + INIT_DCS_CMD(0xB0, 0x02), + INIT_DCS_CMD(0xC0, 0x00), + INIT_DCS_CMD(0xC1, 0x0D), + INIT_DCS_CMD(0xC2, 0x17), + INIT_DCS_CMD(0xC3, 0x26), + INIT_DCS_CMD(0xC4, 0x31), + INIT_DCS_CMD(0xC5, 0x1C), + INIT_DCS_CMD(0xC6, 0x2C), + INIT_DCS_CMD(0xC7, 0x33), + INIT_DCS_CMD(0xC8, 0x31), + INIT_DCS_CMD(0xC9, 0x37), + INIT_DCS_CMD(0xCA, 0x37), + INIT_DCS_CMD(0xCB, 0x37), + INIT_DCS_CMD(0xCC, 0x39), + INIT_DCS_CMD(0xCD, 0x2E), + INIT_DCS_CMD(0xCE, 0x2F), + INIT_DCS_CMD(0xCF, 0x2F), + INIT_DCS_CMD(0xD0, 0x07), + INIT_DCS_CMD(0xD2, 0x00), + INIT_DCS_CMD(0xD3, 0x0D), + INIT_DCS_CMD(0xD4, 0x17), + INIT_DCS_CMD(0xD5, 0x26), + INIT_DCS_CMD(0xD6, 0x31), + INIT_DCS_CMD(0xD7, 0x3F), + INIT_DCS_CMD(0xD8, 0x3F), + INIT_DCS_CMD(0xD9, 0x3F), + INIT_DCS_CMD(0xDA, 0x3F), + INIT_DCS_CMD(0xDB, 0x37), + INIT_DCS_CMD(0xDC, 0x37), + INIT_DCS_CMD(0xDD, 0x37), + INIT_DCS_CMD(0xDE, 0x39), + INIT_DCS_CMD(0xDF, 0x2E), + INIT_DCS_CMD(0xE0, 0x2F), + INIT_DCS_CMD(0xE1, 0x2F), + INIT_DCS_CMD(0xE2, 0x07), + INIT_DCS_CMD(0xB0, 0x03), + INIT_DCS_CMD(0xC8, 0x0B), + INIT_DCS_CMD(0xC9, 0x07), + INIT_DCS_CMD(0xC3, 0x00), + INIT_DCS_CMD(0xE7, 0x00), + INIT_DCS_CMD(0xC5, 0x2A), + INIT_DCS_CMD(0xDE, 0x2A), + INIT_DCS_CMD(0xCA, 0x43), + INIT_DCS_CMD(0xC9, 0x07), + INIT_DCS_CMD(0xE4, 0xC0), + INIT_DCS_CMD(0xE5, 0x0D), + INIT_DCS_CMD(0xCB, 0x00), + INIT_DCS_CMD(0xB0, 0x06), + INIT_DCS_CMD(0xB8, 0xA5), + INIT_DCS_CMD(0xC0, 0xA5), + INIT_DCS_CMD(0xC7, 0x0F), + INIT_DCS_CMD(0xD5, 0x32), + INIT_DCS_CMD(0xB8, 0x00), + INIT_DCS_CMD(0xC0, 0x00), + INIT_DCS_CMD(0xBC, 0x00), + INIT_DCS_CMD(0xB0, 0x07), + INIT_DCS_CMD(0xB1, 0x00), + INIT_DCS_CMD(0xB2, 0x02), + INIT_DCS_CMD(0xB3, 0x0F), + INIT_DCS_CMD(0xB4, 0x25), + INIT_DCS_CMD(0xB5, 0x39), + INIT_DCS_CMD(0xB6, 0x4E), + INIT_DCS_CMD(0xB7, 0x72), + INIT_DCS_CMD(0xB8, 0x97), + INIT_DCS_CMD(0xB9, 0xDC), + INIT_DCS_CMD(0xBA, 0x22), + INIT_DCS_CMD(0xBB, 0xA4), + INIT_DCS_CMD(0xBC, 0x2B), + INIT_DCS_CMD(0xBD, 0x2F), + INIT_DCS_CMD(0xBE, 0xA9), + INIT_DCS_CMD(0xBF, 0x25), + INIT_DCS_CMD(0xC0, 0x61), + INIT_DCS_CMD(0xC1, 0x97), + INIT_DCS_CMD(0xC2, 0xB2), + INIT_DCS_CMD(0xC3, 0xCD), + INIT_DCS_CMD(0xC4, 0xD9), + INIT_DCS_CMD(0xC5, 0xE7), + INIT_DCS_CMD(0xC6, 0xF4), + INIT_DCS_CMD(0xC7, 0xFA), + INIT_DCS_CMD(0xC8, 0xFC), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x08), + INIT_DCS_CMD(0xB1, 0x04), + INIT_DCS_CMD(0xB2, 0x05), + INIT_DCS_CMD(0xB3, 0x11), + INIT_DCS_CMD(0xB4, 0x24), + INIT_DCS_CMD(0xB5, 0x39), + INIT_DCS_CMD(0xB6, 0x4F), + INIT_DCS_CMD(0xB7, 0x72), + INIT_DCS_CMD(0xB8, 0x98), + INIT_DCS_CMD(0xB9, 0xDC), + INIT_DCS_CMD(0xBA, 0x23), + INIT_DCS_CMD(0xBB, 0xA6), + INIT_DCS_CMD(0xBC, 0x2C), + INIT_DCS_CMD(0xBD, 0x30), + INIT_DCS_CMD(0xBE, 0xAA), + INIT_DCS_CMD(0xBF, 0x26), + INIT_DCS_CMD(0xC0, 0x62), + INIT_DCS_CMD(0xC1, 0x9B), + INIT_DCS_CMD(0xC2, 0xB5), + INIT_DCS_CMD(0xC3, 0xCF), + INIT_DCS_CMD(0xC4, 0xDB), + INIT_DCS_CMD(0xC5, 0xE8), + INIT_DCS_CMD(0xC6, 0xF5), + INIT_DCS_CMD(0xC7, 0xFA), + INIT_DCS_CMD(0xC8, 0xFC), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x09), + INIT_DCS_CMD(0xB1, 0x04), + INIT_DCS_CMD(0xB2, 0x02), + INIT_DCS_CMD(0xB3, 0x16), + INIT_DCS_CMD(0xB4, 0x24), + INIT_DCS_CMD(0xB5, 0x3B), + INIT_DCS_CMD(0xB6, 0x4F), + INIT_DCS_CMD(0xB7, 0x73), + INIT_DCS_CMD(0xB8, 0x99), + INIT_DCS_CMD(0xB9, 0xE0), + INIT_DCS_CMD(0xBA, 0x26), + INIT_DCS_CMD(0xBB, 0xAD), + INIT_DCS_CMD(0xBC, 0x36), + INIT_DCS_CMD(0xBD, 0x3A), + INIT_DCS_CMD(0xBE, 0xAE), + INIT_DCS_CMD(0xBF, 0x2A), + INIT_DCS_CMD(0xC0, 0x66), + INIT_DCS_CMD(0xC1, 0x9E), + INIT_DCS_CMD(0xC2, 0xB8), + INIT_DCS_CMD(0xC3, 0xD1), + INIT_DCS_CMD(0xC4, 0xDD), + INIT_DCS_CMD(0xC5, 0xE9), + INIT_DCS_CMD(0xC6, 0xF6), + INIT_DCS_CMD(0xC7, 0xFA), + INIT_DCS_CMD(0xC8, 0xFC), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x0A), + INIT_DCS_CMD(0xB1, 0x00), + INIT_DCS_CMD(0xB2, 0x02), + INIT_DCS_CMD(0xB3, 0x0F), + INIT_DCS_CMD(0xB4, 0x25), + INIT_DCS_CMD(0xB5, 0x39), + INIT_DCS_CMD(0xB6, 0x4E), + INIT_DCS_CMD(0xB7, 0x72), + INIT_DCS_CMD(0xB8, 0x97), + INIT_DCS_CMD(0xB9, 0xDC), + INIT_DCS_CMD(0xBA, 0x22), + INIT_DCS_CMD(0xBB, 0xA4), + INIT_DCS_CMD(0xBC, 0x2B), + INIT_DCS_CMD(0xBD, 0x2F), + INIT_DCS_CMD(0xBE, 0xA9), + INIT_DCS_CMD(0xBF, 0x25), + INIT_DCS_CMD(0xC0, 0x61), + INIT_DCS_CMD(0xC1, 0x97), + INIT_DCS_CMD(0xC2, 0xB2), + INIT_DCS_CMD(0xC3, 0xCD), + INIT_DCS_CMD(0xC4, 0xD9), + INIT_DCS_CMD(0xC5, 0xE7), + INIT_DCS_CMD(0xC6, 0xF4), + INIT_DCS_CMD(0xC7, 0xFA), + INIT_DCS_CMD(0xC8, 0xFC), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x0B), + INIT_DCS_CMD(0xB1, 0x04), + INIT_DCS_CMD(0xB2, 0x05), + INIT_DCS_CMD(0xB3, 0x11), + INIT_DCS_CMD(0xB4, 0x24), + INIT_DCS_CMD(0xB5, 0x39), + INIT_DCS_CMD(0xB6, 0x4F), + INIT_DCS_CMD(0xB7, 0x72), + INIT_DCS_CMD(0xB8, 0x98), + INIT_DCS_CMD(0xB9, 0xDC), + INIT_DCS_CMD(0xBA, 0x23), + INIT_DCS_CMD(0xBB, 0xA6), + INIT_DCS_CMD(0xBC, 0x2C), + INIT_DCS_CMD(0xBD, 0x30), + INIT_DCS_CMD(0xBE, 0xAA), + INIT_DCS_CMD(0xBF, 0x26), + INIT_DCS_CMD(0xC0, 0x62), + INIT_DCS_CMD(0xC1, 0x9B), + INIT_DCS_CMD(0xC2, 0xB5), + INIT_DCS_CMD(0xC3, 0xCF), + INIT_DCS_CMD(0xC4, 0xDB), + INIT_DCS_CMD(0xC5, 0xE8), + INIT_DCS_CMD(0xC6, 0xF5), + INIT_DCS_CMD(0xC7, 0xFA), + INIT_DCS_CMD(0xC8, 0xFC), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x0C), + INIT_DCS_CMD(0xB1, 0x04), + INIT_DCS_CMD(0xB2, 0x02), + INIT_DCS_CMD(0xB3, 0x16), + INIT_DCS_CMD(0xB4, 0x24), + INIT_DCS_CMD(0xB5, 0x3B), + INIT_DCS_CMD(0xB6, 0x4F), + INIT_DCS_CMD(0xB7, 0x73), + INIT_DCS_CMD(0xB8, 0x99), + INIT_DCS_CMD(0xB9, 0xE0), + INIT_DCS_CMD(0xBA, 0x26), + INIT_DCS_CMD(0xBB, 0xAD), + INIT_DCS_CMD(0xBC, 0x36), + INIT_DCS_CMD(0xBD, 0x3A), + INIT_DCS_CMD(0xBE, 0xAE), + INIT_DCS_CMD(0xBF, 0x2A), + INIT_DCS_CMD(0xC0, 0x66), + INIT_DCS_CMD(0xC1, 0x9E), + INIT_DCS_CMD(0xC2, 0xB8), + INIT_DCS_CMD(0xC3, 0xD1), + INIT_DCS_CMD(0xC4, 0xDD), + INIT_DCS_CMD(0xC5, 0xE9), + INIT_DCS_CMD(0xC6, 0xF6), + INIT_DCS_CMD(0xC7, 0xFA), + INIT_DCS_CMD(0xC8, 0xFC), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x00), + INIT_DCS_CMD(0xB3, 0x08), + INIT_DCS_CMD(0xB0, 0x04), + INIT_DCS_CMD(0xB8, 0x68), + INIT_DELAY_CMD(150), + INIT_END_CMD, + }, +}; diff --git a/src/mainboard/google/kukui/panel_params/panel-CMN_P097PFG_SSD2858.c b/src/mainboard/google/kukui/panel_params/panel-CMN_P097PFG_SSD2858.c new file mode 100644 index 0000000000..f9523358f7 --- /dev/null +++ b/src/mainboard/google/kukui/panel_params/panel-CMN_P097PFG_SSD2858.c @@ -0,0 +1,85 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Huaqin Telecom Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../panel.h" + +struct panel_serializable_data P097PFG_SSD2858 = { + .edid = { + .ascii_string = "P097PFG", + .manufacturer_name = "CMN", + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .pixel_clock = 211660, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1536, .hbl = 160, .hso = 140, .hspw = 10, + .va = 2048, .vbl = 32, .vso = 20, .vspw = 2, + .phsync = '-', .pvsync = '-', + .x_mm = 147, .y_mm = 196, + }, + }, + .orientation = LB_FB_ORIENTATION_NORMAL, + .init = { + INIT_GENERIC_CMD(0xff, 0x00), + /* LOCKCNT=0x1f4, MRX=0, POSTDIV=1 (/2} }, MULT=0x49 + * 27 Mhz => 985.5 Mhz */ + INIT_GENERIC_CMD(0x00, 0x08, 0x01, 0xf4, 0x01, 0x49), + /* MTXDIV=1, SYSDIV=3 (=> 4) */ + INIT_GENERIC_CMD(0x00, 0x0c, 0x00, 0x00, 0x00, 0x03), + /* MTXVPF=24bpp, MRXLS=4 lanes, MRXVB=bypass, MRXECC=1, + * MRXEOT=1, MRXEE=1 */ + INIT_GENERIC_CMD(0x00, 0x14, 0x0c, 0x3d, 0x80, 0x0f), + INIT_GENERIC_CMD(0x00, 0x20, 0x15, 0x92, 0x56, 0x7d), + INIT_GENERIC_CMD(0x00, 0x24, 0x00, 0x00, 0x30, 0x00), + + INIT_GENERIC_CMD(0x10, 0x08, 0x01, 0x20, 0x08, 0x45), + INIT_GENERIC_CMD(0x10, 0x1c, 0x00, 0x00, 0x00, 0x00), + INIT_GENERIC_CMD(0x20, 0x0c, 0x00, 0x00, 0x00, 0x04), + /* Pixel clock 985.5 Mhz * 0x49/0x4b = 959 Mhz */ + INIT_GENERIC_CMD(0x20, 0x10, 0x00, 0x4b, 0x00, 0x49), + INIT_GENERIC_CMD(0x20, 0xa0, 0x00, 0x00, 0x00, 0x00), + /* EOT=1, LPE = 0, LSOUT=4 lanes, LPD=25 */ + INIT_GENERIC_CMD(0x60, 0x08, 0x00, 0xd9, 0x00, 0x08), + INIT_GENERIC_CMD(0x60, 0x14, 0x01, 0x00, 0x01, 0x06), + /* DSI0 enable (default: probably not needed) */ + INIT_GENERIC_CMD(0x60, 0x80, 0x00, 0x00, 0x00, 0x0f), + /* DSI1 enable */ + INIT_GENERIC_CMD(0x60, 0xa0, 0x00, 0x00, 0x00, 0x0f), + + /* HSA=0x18, VSA=0x02, HBP=0x50, VBP=0x0c */ + INIT_GENERIC_CMD(0x60, 0x0c, 0x0c, 0x50, 0x02, 0x18), + /* VACT= 0x800 (2048} }, VFP= 0x14, HFP=0x50 */ + INIT_GENERIC_CMD(0x60, 0x10, 0x08, 0x00, 0x14, 0x50), + /* HACT=0x300 (768) */ + INIT_GENERIC_CMD(0x60, 0x84, 0x00, 0x00, 0x03, 0x00), + INIT_GENERIC_CMD(0x60, 0xa4, 0x00, 0x00, 0x03, 0x00), + + /* Take panel out of sleep. */ + INIT_GENERIC_CMD(0xff, 0x01), + INIT_DCS_CMD(0x11), + INIT_DELAY_CMD(120), + INIT_DCS_CMD(0x29), + INIT_DELAY_CMD(20), + INIT_GENERIC_CMD(0xff, 0x00), + + INIT_DELAY_CMD(120), + INIT_DCS_CMD(0x11), + INIT_DELAY_CMD(120), + INIT_DCS_CMD(0x29), + INIT_DELAY_CMD(20), + INIT_END_CMD, + }, +}; diff --git a/src/mainboard/google/kukui/panel_params/panel-INX_OTA7290D10P.c b/src/mainboard/google/kukui/panel_params/panel-INX_OTA7290D10P.c new file mode 100644 index 0000000000..069fb639e5 --- /dev/null +++ b/src/mainboard/google/kukui/panel_params/panel-INX_OTA7290D10P.c @@ -0,0 +1,294 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Huaqin Telecom Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../panel.h" + +struct panel_serializable_data INX_OTA7290D10P = { + .edid = { + .ascii_string = "OTA7290D10P", + .manufacturer_name = "INX", + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .pixel_clock = 159420, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 141, .hso = 80, .hspw = 1, + .va = 1920, .vbl = 61, .vso = 35, .vspw = 1, + .phsync = '-', .pvsync = '-', + .x_mm = 135, .y_mm = 216, + }, + }, + .init = { + INIT_DCS_CMD(0xB0, 0x5A), + INIT_DCS_CMD(0xB1, 0x00), + INIT_DCS_CMD(0x89, 0x01), + INIT_DCS_CMD(0x91, 0x17), + INIT_DCS_CMD(0xB1, 0x03), + INIT_DCS_CMD(0x2C, 0x28), + INIT_DCS_CMD(0x00, 0xF1), + INIT_DCS_CMD(0x01, 0x78), + INIT_DCS_CMD(0x02, 0x3C), + INIT_DCS_CMD(0x03, 0x1E), + INIT_DCS_CMD(0x04, 0x8F), + INIT_DCS_CMD(0x05, 0x01), + INIT_DCS_CMD(0x06, 0x00), + INIT_DCS_CMD(0x07, 0x00), + INIT_DCS_CMD(0x08, 0x00), + INIT_DCS_CMD(0x09, 0x00), + INIT_DCS_CMD(0x0A, 0x01), + INIT_DCS_CMD(0x0B, 0x3C), + INIT_DCS_CMD(0x0C, 0x00), + INIT_DCS_CMD(0x0D, 0x00), + INIT_DCS_CMD(0x0E, 0x24), + INIT_DCS_CMD(0x0F, 0x1C), + INIT_DCS_CMD(0x10, 0xC8), + INIT_DCS_CMD(0x11, 0x60), + INIT_DCS_CMD(0x12, 0x70), + INIT_DCS_CMD(0x13, 0x01), + INIT_DCS_CMD(0x14, 0xE3), + INIT_DCS_CMD(0x15, 0xFF), + INIT_DCS_CMD(0x16, 0x3D), + INIT_DCS_CMD(0x17, 0x0E), + INIT_DCS_CMD(0x18, 0x01), + INIT_DCS_CMD(0x19, 0x00), + INIT_DCS_CMD(0x1A, 0x00), + INIT_DCS_CMD(0x1B, 0xFC), + INIT_DCS_CMD(0x1C, 0x0B), + INIT_DCS_CMD(0x1D, 0xA0), + INIT_DCS_CMD(0x1E, 0x03), + INIT_DCS_CMD(0x1F, 0x04), + INIT_DCS_CMD(0x20, 0x0C), + INIT_DCS_CMD(0x21, 0x00), + INIT_DCS_CMD(0x22, 0x04), + INIT_DCS_CMD(0x23, 0x81), + INIT_DCS_CMD(0x24, 0x1F), + INIT_DCS_CMD(0x25, 0x10), + INIT_DCS_CMD(0x26, 0x9B), + INIT_DCS_CMD(0x2D, 0x01), + INIT_DCS_CMD(0x2E, 0x84), + INIT_DCS_CMD(0x2F, 0x00), + INIT_DCS_CMD(0x30, 0x02), + INIT_DCS_CMD(0x31, 0x08), + INIT_DCS_CMD(0x32, 0x01), + INIT_DCS_CMD(0x33, 0x1C), + INIT_DCS_CMD(0x34, 0x70), + INIT_DCS_CMD(0x35, 0xFF), + INIT_DCS_CMD(0x36, 0xFF), + INIT_DCS_CMD(0x37, 0xFF), + INIT_DCS_CMD(0x38, 0xFF), + INIT_DCS_CMD(0x39, 0xFF), + INIT_DCS_CMD(0x3A, 0x05), + INIT_DCS_CMD(0x3B, 0x00), + INIT_DCS_CMD(0x3C, 0x00), + INIT_DCS_CMD(0x3D, 0x00), + INIT_DCS_CMD(0x3E, 0x0F), + INIT_DCS_CMD(0x3F, 0xA4), + INIT_DCS_CMD(0x40, 0x28), + INIT_DCS_CMD(0x41, 0xFC), + INIT_DCS_CMD(0x42, 0x01), + INIT_DCS_CMD(0x43, 0x08), + INIT_DCS_CMD(0x44, 0x05), + INIT_DCS_CMD(0x45, 0xF0), + INIT_DCS_CMD(0x46, 0x01), + INIT_DCS_CMD(0x47, 0x02), + INIT_DCS_CMD(0x48, 0x00), + INIT_DCS_CMD(0x49, 0x58), + INIT_DCS_CMD(0x4A, 0x00), + INIT_DCS_CMD(0x4B, 0x05), + INIT_DCS_CMD(0x4C, 0x03), + INIT_DCS_CMD(0x4D, 0xD0), + INIT_DCS_CMD(0x4E, 0x13), + INIT_DCS_CMD(0x4F, 0xFF), + INIT_DCS_CMD(0x50, 0x0A), + INIT_DCS_CMD(0x51, 0x53), + INIT_DCS_CMD(0x52, 0x26), + INIT_DCS_CMD(0x53, 0x22), + INIT_DCS_CMD(0x54, 0x09), + INIT_DCS_CMD(0x55, 0x22), + INIT_DCS_CMD(0x56, 0x00), + INIT_DCS_CMD(0x57, 0x1C), + INIT_DCS_CMD(0x58, 0x03), + INIT_DCS_CMD(0x59, 0x3F), + INIT_DCS_CMD(0x5A, 0x28), + INIT_DCS_CMD(0x5B, 0x01), + INIT_DCS_CMD(0x5C, 0xCC), + INIT_DCS_CMD(0x5D, 0x21), + INIT_DCS_CMD(0x5E, 0x04), + INIT_DCS_CMD(0x5F, 0x13), + INIT_DCS_CMD(0x60, 0x42), + INIT_DCS_CMD(0x61, 0x08), + INIT_DCS_CMD(0x62, 0x64), + INIT_DCS_CMD(0x63, 0xEB), + INIT_DCS_CMD(0x64, 0x10), + INIT_DCS_CMD(0x65, 0xA8), + INIT_DCS_CMD(0x66, 0x84), + INIT_DCS_CMD(0x67, 0x8E), + INIT_DCS_CMD(0x68, 0x29), + INIT_DCS_CMD(0x69, 0x11), + INIT_DCS_CMD(0x6A, 0x42), + INIT_DCS_CMD(0x6B, 0x38), + INIT_DCS_CMD(0x6C, 0x21), + INIT_DCS_CMD(0x6D, 0x84), + INIT_DCS_CMD(0x6E, 0x50), + INIT_DCS_CMD(0x6F, 0xB6), + INIT_DCS_CMD(0x70, 0x0E), + INIT_DCS_CMD(0x71, 0xA1), + INIT_DCS_CMD(0x72, 0xCE), + INIT_DCS_CMD(0x73, 0xF8), + INIT_DCS_CMD(0x74, 0xDA), + INIT_DCS_CMD(0x75, 0x1A), + INIT_DCS_CMD(0x76, 0x00), + INIT_DCS_CMD(0x77, 0x00), + INIT_DCS_CMD(0x78, 0x5F), + INIT_DCS_CMD(0x79, 0xE0), + INIT_DCS_CMD(0x7A, 0x01), + INIT_DCS_CMD(0x7B, 0xFF), + INIT_DCS_CMD(0x7C, 0xFF), + INIT_DCS_CMD(0x7D, 0xFF), + INIT_DCS_CMD(0x7E, 0xFF), + INIT_DCS_CMD(0x7F, 0xFE), + INIT_DCS_CMD(0xB1, 0x02), + INIT_DCS_CMD(0x00, 0xFF), + INIT_DCS_CMD(0x01, 0x01), + INIT_DCS_CMD(0x02, 0x00), + INIT_DCS_CMD(0x03, 0x00), + INIT_DCS_CMD(0x04, 0x00), + INIT_DCS_CMD(0x05, 0x00), + INIT_DCS_CMD(0x06, 0x00), + INIT_DCS_CMD(0x07, 0x00), + INIT_DCS_CMD(0x08, 0xC0), + INIT_DCS_CMD(0x09, 0x00), + INIT_DCS_CMD(0x0A, 0x00), + INIT_DCS_CMD(0x0B, 0x04), + INIT_DCS_CMD(0x0C, 0xE6), + INIT_DCS_CMD(0x0D, 0x0D), + INIT_DCS_CMD(0x0F, 0x08), + INIT_DCS_CMD(0x10, 0xE5), + INIT_DCS_CMD(0x11, 0xA8), + INIT_DCS_CMD(0x12, 0xEC), + INIT_DCS_CMD(0x13, 0x54), + INIT_DCS_CMD(0x14, 0x5A), + INIT_DCS_CMD(0x15, 0xD5), + INIT_DCS_CMD(0x16, 0x23), + INIT_DCS_CMD(0x17, 0x11), + INIT_DCS_CMD(0x18, 0x2F), + INIT_DCS_CMD(0x19, 0x93), + INIT_DCS_CMD(0x1A, 0xA6), + INIT_DCS_CMD(0x1B, 0x0F), + INIT_DCS_CMD(0x1C, 0xFF), + INIT_DCS_CMD(0x1D, 0xFF), + INIT_DCS_CMD(0x1E, 0xFF), + INIT_DCS_CMD(0x1F, 0xFF), + INIT_DCS_CMD(0x20, 0xFF), + INIT_DCS_CMD(0x21, 0xFF), + INIT_DCS_CMD(0x22, 0xFF), + INIT_DCS_CMD(0x23, 0xFF), + INIT_DCS_CMD(0x24, 0xFF), + INIT_DCS_CMD(0x25, 0xFF), + INIT_DCS_CMD(0x26, 0xFF), + INIT_DCS_CMD(0x27, 0x1F), + INIT_DCS_CMD(0x28, 0xC8), + INIT_DCS_CMD(0x29, 0xFF), + INIT_DCS_CMD(0x2A, 0xFF), + INIT_DCS_CMD(0x2B, 0xFF), + INIT_DCS_CMD(0x2C, 0x07), + INIT_DCS_CMD(0x2D, 0x03), + INIT_DCS_CMD(0x33, 0x09), + INIT_DCS_CMD(0x35, 0x7F), + INIT_DCS_CMD(0x36, 0x0C), + INIT_DCS_CMD(0x38, 0x7F), + INIT_DCS_CMD(0x3A, 0x80), + INIT_DCS_CMD(0x3B, 0x55), + INIT_DCS_CMD(0x3C, 0xE2), + INIT_DCS_CMD(0x3D, 0x32), + INIT_DCS_CMD(0x3E, 0x00), + INIT_DCS_CMD(0x3F, 0x58), + INIT_DCS_CMD(0x40, 0x06), + INIT_DCS_CMD(0x41, 0x80), + INIT_DCS_CMD(0x42, 0xCB), + INIT_DCS_CMD(0x43, 0x2C), + INIT_DCS_CMD(0x44, 0x61), + INIT_DCS_CMD(0x45, 0x39), + INIT_DCS_CMD(0x46, 0x00), + INIT_DCS_CMD(0x47, 0x00), + INIT_DCS_CMD(0x48, 0x8B), + INIT_DCS_CMD(0x49, 0xD2), + INIT_DCS_CMD(0x4A, 0x01), + INIT_DCS_CMD(0x4B, 0x00), + INIT_DCS_CMD(0x4C, 0x10), + INIT_DCS_CMD(0x4D, 0xC0), + INIT_DCS_CMD(0x4E, 0x0F), + INIT_DCS_CMD(0x4F, 0xF1), + INIT_DCS_CMD(0x50, 0x78), + INIT_DCS_CMD(0x51, 0x7A), + INIT_DCS_CMD(0x52, 0x34), + INIT_DCS_CMD(0x53, 0x99), + INIT_DCS_CMD(0x54, 0xA2), + INIT_DCS_CMD(0x55, 0x03), + INIT_DCS_CMD(0x56, 0x6C), + INIT_DCS_CMD(0x57, 0x1A), + INIT_DCS_CMD(0x58, 0x05), + INIT_DCS_CMD(0x59, 0x30), + INIT_DCS_CMD(0x5A, 0x1E), + INIT_DCS_CMD(0x5B, 0x8F), + INIT_DCS_CMD(0x5C, 0xC7), + INIT_DCS_CMD(0x5D, 0xE3), + INIT_DCS_CMD(0x5E, 0xF1), + INIT_DCS_CMD(0x5F, 0x78), + INIT_DCS_CMD(0x60, 0x3C), + INIT_DCS_CMD(0x61, 0x36), + INIT_DCS_CMD(0x62, 0x1E), + INIT_DCS_CMD(0x63, 0x1B), + INIT_DCS_CMD(0x64, 0x8F), + INIT_DCS_CMD(0x65, 0xC7), + INIT_DCS_CMD(0x66, 0xE3), + INIT_DCS_CMD(0x67, 0x31), + INIT_DCS_CMD(0x68, 0x14), + INIT_DCS_CMD(0x69, 0x89), + INIT_DCS_CMD(0x6A, 0x70), + INIT_DCS_CMD(0x6B, 0x8C), + INIT_DCS_CMD(0x6C, 0x8D), + INIT_DCS_CMD(0x6D, 0x8D), + INIT_DCS_CMD(0x6E, 0x8D), + INIT_DCS_CMD(0x6F, 0x8D), + INIT_DCS_CMD(0x70, 0xC7), + INIT_DCS_CMD(0x71, 0xE3), + INIT_DCS_CMD(0x72, 0xF1), + INIT_DCS_CMD(0x73, 0xD8), + INIT_DCS_CMD(0x74, 0xD8), + INIT_DCS_CMD(0x75, 0xD8), + INIT_DCS_CMD(0x76, 0x18), + INIT_DCS_CMD(0x77, 0x00), + INIT_DCS_CMD(0x78, 0x00), + INIT_DCS_CMD(0x79, 0x00), + INIT_DCS_CMD(0x7A, 0xC6), + INIT_DCS_CMD(0x7B, 0xC6), + INIT_DCS_CMD(0x7C, 0xC6), + INIT_DCS_CMD(0x7D, 0xC6), + INIT_DCS_CMD(0x7E, 0xC6), + INIT_DCS_CMD(0x7F, 0xE3), + INIT_DCS_CMD(0x0B, 0x04), + INIT_DCS_CMD(0xB1, 0x03), + INIT_DCS_CMD(0x2C, 0x2C), + INIT_DCS_CMD(0xB1, 0x00), + INIT_DCS_CMD(0x89, 0x03), + INIT_DCS_CMD(0x11), + INIT_DELAY_CMD(0x78), + INIT_DCS_CMD(0x29), + INIT_DELAY_CMD(0x14), + INIT_END_CMD, + }, +}; diff --git a/src/mainboard/google/kukui/panel_ps8640.c b/src/mainboard/google/kukui/panel_ps8640.c new file mode 100644 index 0000000000..83358d366a --- /dev/null +++ b/src/mainboard/google/kukui/panel_ps8640.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "panel.h" + + +static void power_on_ps8640(void) +{ + gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 0); + gpio_output(GPIO_PP1200_MIPIBRDG_EN, 1); + gpio_output(GPIO_VDDIO_MIPIBRDG_EN, 1); + mdelay(2); + gpio_output(GPIO_MIPIBRDG_PWRDN_L_1V8, 1); + mdelay(2); + gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 1); + gpio_output(GPIO_PP3300_LCM_EN, 1); +} + +static void dummy_power_on(void) +{ + /* The panel has been already powered on when getting panel information + * so we should do nothing here. + */ +} + +static struct panel_serializable_data ps8640_data = { + .orientation = LB_FB_ORIENTATION_NORMAL, + .init = { INIT_END_CMD }, +}; + +static struct panel_description ps8640_panel = { + .s = &ps8640_data, + .power_on = dummy_power_on, +}; + +struct panel_description *get_panel_description(int panel_id) +{ + /* To read panel EDID, we have to first power on PS8640. */ + power_on_ps8640(); + + u8 i2c_bus = 4, i2c_addr = 0x08; + mtk_i2c_bus_init(i2c_bus); + + ps8640_init(i2c_bus, i2c_addr); + struct edid *edid = &ps8640_data.edid; + if (ps8640_get_edid(i2c_bus, i2c_addr, edid)) { + printk(BIOS_ERR, "Can't get panel's edid\n"); + return NULL; + } + return &ps8640_panel; +} diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index 1465243f07..a86690b6fb 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -32,6 +32,7 @@ void platform_romstage_main(void) /* Adjust VSIM2 down to 2.7V because it is shared with IT6505. */ pmic_set_vsim2_cali(2700); mt_pll_raise_ca53_freq(1989 * MHz); + pmic_init_scp_voltage(); rtc_boot(); mt_mem_init(get_sdram_config()); mtk_mmu_after_dram(); diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c index d8b3cc4c2f..b6277eaebf 100644 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -26,6 +26,7 @@ static const char *const sdram_configs[] = { [5] = "sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB", [6] = "sdram-lpddr4x-KMDV6001DA-B620-4GB", [7] = "sdram-lpddr4x-SDADA4CR-128G-4GB", + [8] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB", }; static struct sdram_params params; diff --git a/src/mainboard/google/kukui/sdram_params/Makefile.inc b/src/mainboard/google/kukui/sdram_params/Makefile.inc index fbc505b588..4d91998e52 100644 --- a/src/mainboard/google/kukui/sdram_params/Makefile.inc +++ b/src/mainboard/google/kukui/sdram_params/Makefile.inc @@ -1,4 +1,5 @@ sdram-params := +sdram-params += sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB sdram-params += sdram-lpddr4x-H9HCNNNCPMALHR-4GB sdram-params += sdram-lpddr4x-MT53E1G32D4NQ-4GB sdram-params += sdram-lpddr4x-KMDH6001DA-B422-4GB diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c new file mode 100644 index 0000000000..8d855ff1ba --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +struct sdram_params params = { + .impedance = { + [ODT_OFF] = {0x9, 0x7, 0x0, 0xF}, + [ODT_ON] = {0xB, 0x9, 0x0, 0xE} + }, + .wr_level = { + [CHANNEL_A] = { {0x22, 0x1C}, {0x23, 0x1D} }, + [CHANNEL_B] = { {0x26, 0x23}, {0x26, 0x23} } + }, + .cbt_cs = { + [CHANNEL_A] = {0x6, 0x5}, + [CHANNEL_B] = {0x6, 0x6} + }, + .cbt_mr12 = { + [CHANNEL_A] = {0x56, 0x58}, + [CHANNEL_B] = {0x58, 0x56} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_NORMAL_MODE, + .delay_cell_unit = 868, +}; diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index ecd7592823..a5370beddb 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -15,13 +15,11 @@ #include #include +#include #include #include #include -#ifndef __PRE_RAM__ -#include - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -41,7 +39,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif int get_write_protect_state(void) { diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 2f3f07cdce..8e8d94335c 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -156,8 +156,12 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) }, }; *pei_data = pei_data_template; + /* LINK has 2 channels of memory down, so spd_data[0] and [2] + both need to be populated */ memcpy(pei_data->spd_data[0], locate_spd(), sizeof(pei_data->spd_data[0])); + memcpy(pei_data->spd_data[2], pei_data->spd_data[0], + sizeof(pei_data->spd_data[0])); } const struct southbridge_usb_port mainboard_usb_ports[] = { @@ -180,7 +184,10 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { void mainboard_get_spd(spd_raw_data *spd, bool id_only) { + /* LINK has 2 channels of memory down, so spd_data[0] and [2] + both need to be populated */ memcpy(&spd[0], locate_spd(), 128); + memcpy(&spd[2], &spd[0], 128); } void mainboard_early_init(int s3resume) diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index 807cec3f3f..3e9f9fad7b 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c index c8bb8136d4..9c4e943ae5 100644 --- a/src/mainboard/google/nyan_big/mainboard.c +++ b/src/mainboard/google/nyan_big/mainboard.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig index a5b174781e..1e91da9d9e 100644 --- a/src/mainboard/google/nyan_blaze/Kconfig +++ b/src/mainboard/google/nyan_blaze/Kconfig @@ -17,7 +17,6 @@ if BOARD_GOOGLE_NYAN_BLAZE config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_ARM select COMMON_CBFS_SPI_WRAPPER select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_SPI diff --git a/src/mainboard/google/nyan_blaze/mainboard.c b/src/mainboard/google/nyan_blaze/mainboard.c index 97d0576278..7f8abab119 100644 --- a/src/mainboard/google/nyan_blaze/mainboard.c +++ b/src/mainboard/google/nyan_blaze/mainboard.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index 0dce17d40d..916632e27b 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -22,8 +22,6 @@ #include #include #include - -#include #include #include #include @@ -234,7 +232,7 @@ static void display_startup(void) edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); mtk_ddp_init(); - ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, &edid); + ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, &edid, NULL); if (ret < 0) { printk(BIOS_ERR, "dsi init fail\n"); return; diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index b3145d10df..6f685227c4 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -361,8 +361,6 @@ static const struct pad_config sleep_gpio_table[] = { static const struct pad_config sleep_s5_gpio_table[] = { /* BT_DISABLE_L */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_109, 0, DEEP, NONE, Tx0RxDCRx1, SAME), - /* WLAN_DISABLE_L */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_116, 0, DEEP, NONE, Tx0RxDCRx1, SAME), }; const struct pad_config *__weak diff --git a/src/mainboard/google/octopus/variants/bloog/overridetree.cb b/src/mainboard/google/octopus/variants/bloog/overridetree.cb index 6c64ba78e0..0212bea46d 100644 --- a/src/mainboard/google/octopus/variants/bloog/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bloog/overridetree.cb @@ -138,6 +138,20 @@ chip soc/intel/apollolake register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end # - I2C 7 end diff --git a/src/mainboard/google/octopus/variants/bloog/variant.c b/src/mainboard/google/octopus/variants/bloog/variant.c index 58b3bc4cd2..6484080d41 100644 --- a/src/mainboard/google/octopus/variants/bloog/variant.c +++ b/src/mainboard/google/octopus/variants/bloog/variant.c @@ -29,6 +29,9 @@ const char *get_wifi_sar_cbfs_filename(void) if (sku_id == SKU_UNKNOWN) return NULL; + if (sku_id == 33 || sku_id == 34 || sku_id == 35 || sku_id == 36) + filename = "wifi_sar-bloog.hex"; + if (sku_id == 49 || sku_id == 50 || sku_id == 51 || sku_id == 52) filename = "wifi_sar-blooguard.hex"; diff --git a/src/mainboard/google/octopus/variants/garg/gpio.c b/src/mainboard/google/octopus/variants/garg/gpio.c index 36fde90631..bcabac5001 100644 --- a/src/mainboard/google/octopus/variants/garg/gpio.c +++ b/src/mainboard/google/octopus/variants/garg/gpio.c @@ -23,6 +23,8 @@ enum { SKU_1_2A2C = 1, SKU_9_HDMI = 9, SKU_17_LTE = 17, + SKU_18_LTE_TS = 18, + SKU_37_2A2C_360 = 37, }; static const struct pad_config default_override_table[] = { @@ -84,6 +86,7 @@ const struct pad_config *variant_override_gpio_table(size_t *num) *num = ARRAY_SIZE(hdmi_override_table); return hdmi_override_table; case SKU_17_LTE: + case SKU_18_LTE_TS: *num = ARRAY_SIZE(lte_override_table); return lte_override_table; default: diff --git a/src/mainboard/google/octopus/variants/garg/variant.c b/src/mainboard/google/octopus/variants/garg/variant.c index 2754e640f9..942ea5f3b4 100644 --- a/src/mainboard/google/octopus/variants/garg/variant.c +++ b/src/mainboard/google/octopus/variants/garg/variant.c @@ -25,6 +25,8 @@ enum { SKU_1_2A2C = 1, SKU_9_HDMI = 9, SKU_17_LTE = 17, + SKU_18_LTE_TS = 18, + SKU_37_2A2C_360 = 37, }; struct gpio_with_delay { @@ -78,6 +80,7 @@ void variant_smi_sleep(u8 slp_typ) switch (get_board_sku()) { case SKU_17_LTE: + case SKU_18_LTE_TS: power_off_lte_module(slp_typ); return; default: diff --git a/src/mainboard/google/octopus/variants/meep/include/variant/sku.h b/src/mainboard/google/octopus/variants/meep/include/variant/sku.h index 16a4eabecc..c12ba80302 100644 --- a/src/mainboard/google/octopus/variants/meep/include/variant/sku.h +++ b/src/mainboard/google/octopus/variants/meep/include/variant/sku.h @@ -17,14 +17,19 @@ #define __MAINBOARD_SKU_H__ enum { - SKU_4_VORTININJA = 4, /* Stylus + rear camera */ - SKU_5_VORTININJA = 5, /* Stylus + no rear camera */ - SKU_6_VORTININJA = 6, /* no Stylus + rear camera */ - SKU_7_VORTININJA = 7, /* no Stylus + no rear camera */ + SKU_1_MEEP = 1, /* Stylus + rear camera*/ + SKU_2_MEEP = 2, /* no Stylus + rear camera */ + SKU_3_MEEP = 3, /* no Stylus + no rear camera */ + SKU_4_MEEP = 4, /* Stylus + no rear camera */ SKU_33_DORP = 33, /* HDMI */ SKU_34_DORP = 34, /* HDMI+Kblight */ SKU_35_DORP = 35, /* HDMI+TS */ SKU_36_DORP = 36, /* HDMI+TS+KBlight */ + SKU_49_VORTININJA = 49, /* Stylus + rear camera */ + SKU_50_VORTININJA = 50, /* Stylus + no rear camera */ + SKU_51_VORTININJA = 51, /* no Stylus + rear camera */ + SKU_52_VORTININJA = 52, /* no Stylus + no rear camera */ + }; #endif /* __MAINBOARD_SKU_H__ */ diff --git a/src/mainboard/google/octopus/variants/meep/overridetree.cb b/src/mainboard/google/octopus/variants/meep/overridetree.cb index d7bdd2e936..8881c9d98f 100644 --- a/src/mainboard/google/octopus/variants/meep/overridetree.cb +++ b/src/mainboard/google/octopus/variants/meep/overridetree.cb @@ -219,6 +219,20 @@ chip soc/intel/apollolake register "hid_desc_reg_offset" = "0x20" device i2c 2c on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end # - I2C 7 end diff --git a/src/mainboard/google/octopus/variants/meep/variant.c b/src/mainboard/google/octopus/variants/meep/variant.c index ece8ff955a..ed76a29298 100644 --- a/src/mainboard/google/octopus/variants/meep/variant.c +++ b/src/mainboard/google/octopus/variants/meep/variant.c @@ -25,10 +25,16 @@ const char *get_wifi_sar_cbfs_filename(void) uint32_t sku_id = get_board_sku(); switch (sku_id) { - case SKU_4_VORTININJA: - case SKU_5_VORTININJA: - case SKU_6_VORTININJA: - case SKU_7_VORTININJA: + case SKU_1_MEEP: + case SKU_2_MEEP: + case SKU_3_MEEP: + case SKU_4_MEEP: + filename = "wifi_sar-meep.hex"; + break; + case SKU_49_VORTININJA: + case SKU_50_VORTININJA: + case SKU_51_VORTININJA: + case SKU_52_VORTININJA: filename = "wifi_sar-vortininja.hex"; break; } diff --git a/src/mainboard/google/parrot/gma-mainboard.ads b/src/mainboard/google/parrot/gma-mainboard.ads index d4a5d7d990..e45320f36e 100644 --- a/src/mainboard/google/parrot/gma-mainboard.ads +++ b/src/mainboard/google/parrot/gma-mainboard.ads @@ -28,7 +28,6 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal, - others => Disabled); + Internal); end GMA.Mainboard; diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 8c3ad6352e..5f6b09d7be 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -17,11 +17,9 @@ #include #include #include -#include #include #include #include -#include #include #include "onboard.h" #include "ec.h" diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index 84b0031654..23e575d8da 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -32,6 +32,9 @@ void fill_lb_gpios(struct lb_gpios *gpios) {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"}, +#ifdef EC_SYNC_GPIO + {EC_SYNC_GPIO, ACTIVE_LOW, gpio_get(EC_SYNC_GPIO), "EC sync gpio"}, +#endif }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } diff --git a/src/mainboard/google/poppy/smihandler.c b/src/mainboard/google/poppy/smihandler.c index 4f45687700..44ab10cdf1 100644 --- a/src/mainboard/google/poppy/smihandler.c +++ b/src/mainboard/google/poppy/smihandler.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c index d0f60741e3..42f84f57f4 100644 --- a/src/mainboard/google/poppy/variants/nami/gpio.c +++ b/src/mainboard/google/poppy/variants/nami/gpio.c @@ -466,12 +466,18 @@ const struct pad_config *variant_sku_gpio_table(size_t *num) case SKU_1_EKKO: case SKU_2_EKKO: case SKU_3_EKKO: + case SKU_4_EKKO: + case SKU_5_EKKO: + case SKU_6_EKKO: + case SKU_7_EKKO: case SKU_0_BARD: case SKU_1_BARD: case SKU_2_BARD: case SKU_3_BARD: case SKU_4_BARD: case SKU_5_BARD: + case SKU_6_BARD: + case SKU_7_BARD: *num = ARRAY_SIZE(fpmcu_gpio_table); board_gpio_tables = fpmcu_gpio_table; break; diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/sku.h b/src/mainboard/google/poppy/variants/nami/include/variant/sku.h index 63c8928bab..7ff3cc7551 100644 --- a/src/mainboard/google/poppy/variants/nami/include/variant/sku.h +++ b/src/mainboard/google/poppy/variants/nami/include/variant/sku.h @@ -40,15 +40,21 @@ #define SKU_5_SYNDRA 0X6BC62 #define SKU_6_SYNDRA 0X6BC61 #define SKU_7_SYNDRA 0X6BC60 -#define SKU_0_EKKO 0x10118E3 -#define SKU_1_EKKO 0x10018E3 -#define SKU_2_EKKO 0x10118E1 -#define SKU_3_EKKO 0X10018E1 -#define SKU_0_BARD 0x1019CE3 -#define SKU_1_BARD 0x1009CE3 -#define SKU_2_BARD 0x1019CE1 -#define SKU_3_BARD 0X1009CE1 -#define SKU_4_BARD 0X1009CE0 -#define SKU_5_BARD 0X1009CE2 +#define SKU_0_EKKO 0x10118E3 +#define SKU_1_EKKO 0x10018E3 +#define SKU_2_EKKO 0x10118E1 +#define SKU_3_EKKO 0X10018E1 +#define SKU_4_EKKO 0x10118E2 +#define SKU_5_EKKO 0x10018E2 +#define SKU_6_EKKO 0x10118E0 +#define SKU_7_EKKO 0x10018E0 +#define SKU_0_BARD 0x1019CE3 +#define SKU_1_BARD 0x1009CE3 +#define SKU_2_BARD 0x1019CE1 +#define SKU_3_BARD 0X1009CE1 +#define SKU_4_BARD 0X1009CE0 +#define SKU_5_BARD 0X1009CE2 +#define SKU_6_BARD 0x1019CE0 +#define SKU_7_BARD 0x1019CE2 #endif /* __MAINBOARD_SKU_H__ */ diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index f63c520013..e48a952022 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -214,6 +214,8 @@ const char *mainboard_vbt_filename(void) case SKU_3_BARD: case SKU_4_BARD: case SKU_5_BARD: + case SKU_6_BARD: + case SKU_7_BARD: return "vbt-bard.bin"; default: return "vbt.bin"; @@ -271,10 +273,16 @@ void variant_devtree_update(void) case SKU_3_BARD: case SKU_4_BARD: case SKU_5_BARD: + case SKU_6_BARD: + case SKU_7_BARD: case SKU_0_EKKO: case SKU_1_EKKO: case SKU_2_EKKO: case SKU_3_EKKO: + case SKU_4_EKKO: + case SKU_5_EKKO: + case SKU_6_EKKO: + case SKU_7_EKKO: pl2_id = PL2_ID_BARD_EKKO; cfg->usb2_ports[5].enable = 0; cfg->usb2_ports[7].enable = 0; diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c index c62317a04b..a4ea3c329b 100644 --- a/src/mainboard/google/poppy/variants/nocturne/gpio.c +++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c @@ -196,7 +196,7 @@ static const struct pad_config gpio_table[] = { /* D16 : ISH_UART0_CTS# ==> RCAM_RST_L */ PAD_CFG_GPO(GPP_D16, 0, DEEP), /* D17 : DMIC_CLK1 ==> EC_PCH_ARCORE_INT_L */ - PAD_CFG_GPI_APIC(GPP_D17, NONE, PLTRST), + PAD_CFG_GPI_APIC_INVERT(GPP_D17, NONE, PLTRST), /* D18 : DMIC_DATA1 ==> TP131 */ PAD_CFG_NC(GPP_D18), /* D19 : DMIC_CLK0 ==> PCH_DMIC_CLK_OUT */ diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h b/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h index fb7ad1abb4..45bb76b7b6 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h @@ -34,9 +34,12 @@ /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK -/* EC sync irq is GPP_D12 */ +/* EC sync irq is tied to GPP_D17 */ #define EC_SYNC_IRQ GPP_D17_IRQ +/* EC sync gpio */ +#define EC_SYNC_GPIO GPP_D17 + /* eSPI virtual wire reporting */ #define EC_SCI_GPI GPE0_ESPI diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index 7880154586..3472b1c4b4 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -14,15 +14,13 @@ */ #include +#include #include #include /* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */ #define WP_STATUS_PAD 36 -#ifndef __PRE_RAM__ -#include - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -33,7 +31,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif int get_write_protect_state(void) { @@ -44,9 +41,8 @@ int get_write_protect_state(void) * there is a 10K pullup. Disable the internal pull in romstage so that * there isn't any ambiguity in the reading. */ -#if defined(__PRE_RAM__) - ssus_disable_internal_pull(WP_STATUS_PAD); -#endif + if (ENV_ROMSTAGE) + ssus_disable_internal_pull(WP_STATUS_PAD); /* WP is enabled when the pin is reading high. */ return ssus_get_gpio(WP_STATUS_PAD); diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index d3f6164cd3..30be5f79ca 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #if CONFIG(VGA_ROM_RUN) #include diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index 5322267af9..f74d77d3f3 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -55,21 +55,13 @@ static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) return &spd_file_content[SPD_SIZE * ram_id]; } -void mainboard_romstage_entry(struct romstage_params *rp) +void mainboard_fill_mrc_params(struct mrc_params *mp) { void *spd_content; int dual_channel = 0; void *spd_file; size_t spd_fsize; - struct mrc_params mp = { - .mainboard = { - .dram_type = DRAM_DDR3L, - .dram_info_location = DRAM_INFO_SPD_MEM, - .weaker_odt_settings = 1, - }, - }; - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, &spd_fsize); if (!spd_file) @@ -77,10 +69,12 @@ void mainboard_romstage_entry(struct romstage_params *rp) spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE, &dual_channel); - mp.mainboard.dram_data[0] = spd_content; - if (dual_channel) - mp.mainboard.dram_data[1] = spd_content; - rp->mrc_params = ∓ - romstage_common(rp); + mp->mainboard.dram_type = DRAM_DDR3L; + mp->mainboard.dram_info_location = DRAM_INFO_SPD_MEM, + mp->mainboard.weaker_odt_settings = 1, + + mp->mainboard.dram_data[0] = spd_content; + if (dual_channel) + mp->mainboard.dram_data[1] = spd_content; } diff --git a/src/mainboard/google/rambi/variants/clapper/Makefile.inc b/src/mainboard/google/rambi/variants/clapper/Makefile.inc index a15bac54d0..0d13f0db02 100644 --- a/src/mainboard/google/rambi/variants/clapper/Makefile.inc +++ b/src/mainboard/google/rambi/variants/clapper/Makefile.inc @@ -17,18 +17,22 @@ SPD_BIN = $(obj)/spd.bin # Order matters for SPD sources. The following indices # define the SPD data to use. -# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz -# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz -# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz -# 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz -# 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz -# 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz +# 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz +# 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +# 0b111 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125 SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125 SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/rambi/variants/clapper/gpio.c b/src/mainboard/google/rambi/variants/clapper/gpio.c index 385b40627a..1e02783d68 100644 --- a/src/mainboard/google/rambi/variants/clapper/gpio.c +++ b/src/mainboard/google/rambi/variants/clapper/gpio.c @@ -28,7 +28,7 @@ static const struct soc_gpio_map gpncore_gpio_map[] = { GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ GPIO_NC, /* S0_NC08 - NC */ - GPIO_FUNC2, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ GPIO_NC, /* S0_NC12 - NC */ @@ -58,7 +58,7 @@ static const struct soc_gpio_map gpscore_gpio_map[] = { GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ - GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC007 - SD3_WP external pull (NC) */ GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ @@ -84,15 +84,15 @@ static const struct soc_gpio_map gpscore_gpio_map[] = { GPIO_NC, /* S0-SC030 - NC */ GPIO_NC, /* S0-SC031 - NC */ GPIO_NC, /* S0-SC032 - NC */ - GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ - GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_NC, /* S0-SC033 - SD3_CLK (NC) */ + GPIO_NC, /* S0-SC034 - SD3_D0 (NC) */ + GPIO_NC, /* S0-SC035 - SD3_D1 (NC) */ + GPIO_NC, /* S0-SC036 - SD3_D2 (NC) */ + GPIO_NC, /* S0-SC037 - SD3_D3 (NC) */ + GPIO_NC, /* S0-SC038 - SD3_CD# (NC) */ + GPIO_NC, /* S0-SC039 - SD3_CMD (NC) */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 (NC) */ + GPIO_NC, /* S0-SC041 - SDIO3_PWR_EN# (NC) */ GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ @@ -117,11 +117,11 @@ static const struct soc_gpio_map gpscore_gpio_map[] = { GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ - GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ - GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ - GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ - GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ - GPIO_INPUT, /* S0-SC070 - ALS_INT_L - INT */ + GPIO_NC, /* S0-SC066 - SIO_SPI_CS# (NC) */ + GPIO_NC, /* S0-SC067 - SIO_SPI_MISO (NC) */ + GPIO_NC, /* S0-SC068 - SIO_SPI_MOSI (NC) */ + GPIO_NC, /* S0-SC069 - SIO_SPI_CLK (NC) */ + GPIO_NC, /* S0-SC070 - ALS_INT_L - INT (NC) */ GPIO_NC, /* S0-SC071 - NC */ GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ GPIO_NC, /* S0-SC073 - NC */ @@ -137,8 +137,8 @@ static const struct soc_gpio_map gpscore_gpio_map[] = { GPIO_NC, /* S0-SC083 - NC */ GPIO_NC, /* S0-SC084 - NC */ GPIO_NC, /* S0-SC085 - NC */ - GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */ - GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */ + GPIO_NC, /* S0-SC086 - NC */ + GPIO_NC, /* S0-SC087 - NC */ GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */ GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */ GPIO_NC, /* S0-SC090 - NC */ @@ -158,16 +158,16 @@ static const struct soc_gpio_map gpscore_gpio_map[] = { /* SSUS GPIOs */ static const struct soc_gpio_map gpssus_gpio_map[] = { - GPIO_ACPI_SCI, /* S500 - PCH_WAKE# */ - GPIO_FUNC6, /* S501 - TRACKPAD_INT# - INT */ - GPIO_FUNC6, /* S502 - TOUCH_INT# - INT */ + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */ GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ GPIO_NC, /* S508 - NC */ - GPIO_NC, /* S509 - MUX_AUD_INT1# (NC) */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ GPIO_FUNC0, /* S511 - SUSPWRDNACK */ GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ @@ -195,9 +195,9 @@ static const struct soc_gpio_map gpssus_gpio_map[] = { GPIO_NC, /* S534 - NC */ GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ GPIO_NC, /* S536 - NC */ - GPIO_FUNC0, /* S537 - RAM_ID0 */ - GPIO_FUNC0, /* S538 - RAM_ID1 */ - GPIO_FUNC0, /* S539 - RAM_ID2 */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ GPIO_NC, /* S540 - NC */ GPIO_NC, /* S541 - NC */ GPIO_NC, /* S542 - NC */ diff --git a/src/mainboard/google/rambi/variants/clapper/include/variant/onboard.h b/src/mainboard/google/rambi/variants/clapper/include/variant/onboard.h index cd5052d5e0..3fbd77f5d1 100644 --- a/src/mainboard/google/rambi/variants/clapper/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/clapper/include/variant/onboard.h @@ -23,13 +23,13 @@ #define BOARD_TRACKPAD_NAME "trackpad" #define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) -#define BOARD_TRACKPAD_WAKE_GPIO 1 /* GPSSUS1 */ +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) #define BOARD_TRACKPAD_I2C_BUS 0 #define BOARD_TRACKPAD_I2C_ADDR 0x15 #define BOARD_TOUCHSCREEN_NAME "touchscreen" #define BOARD_TOUCHSCREEN_IRQ GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET) -#define BOARD_TOUCHSCREEN_WAKE_GPIO 2 /* GPSSUS2 */ +#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2) #define BOARD_TOUCHSCREEN_I2C_BUS 5 #define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a diff --git a/src/mainboard/google/rambi/variants/clapper/include/variant/variant.h b/src/mainboard/google/rambi/variants/clapper/include/variant/variant.h index 0210b07564..4e5ba4216e 100644 --- a/src/mainboard/google/rambi/variants/clapper/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/clapper/include/variant/variant.h @@ -18,16 +18,18 @@ /* * RAM_ID[2:0] are on GPIO_SSUS[39:37] - * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz - * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz - * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz - * 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz - * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz - * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz + * 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz + * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b111 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz */ static const uint32_t dual_channel_config = - (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); + (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6); #define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 diff --git a/src/mainboard/google/sarien/smihandler.c b/src/mainboard/google/sarien/smihandler.c index 0efcaa9ef1..18dbfbc154 100644 --- a/src/mainboard/google/sarien/smihandler.c +++ b/src/mainboard/google/sarien/smihandler.c @@ -15,7 +15,7 @@ #include #include -#include +#include #include void mainboard_smi_espi_handler(void) diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index ebcf140b4c..0f3023cace 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -32,7 +32,6 @@ chip soc/intel/cannonlake register "psys_pmax" = "140" register "s0ix_enable" = "1" register "dptf_enable" = "1" - register "dmipwroptimize" = "1" register "satapwroptimize" = "1" register "tdp_pl1_override" = "25" register "tdp_pl2_override" = "51" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index d3aab62a68..cd216e593b 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -34,7 +34,6 @@ chip soc/intel/cannonlake register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" - register "dmipwroptimize" = "1" register "satapwroptimize" = "1" register "AcousticNoiseMitigation" = "1" register "SlowSlewRateForIa" = "2" diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 242876da86..35fced0231 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -16,6 +16,7 @@ config BOARD_GOOGLE_BASEBOARD_SLIPPY select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT select INTEL_GMA_HAVE_VBT + select DRIVERS_I2C_RTD2132 if BOARD_GOOGLE_LEON if BOARD_GOOGLE_BASEBOARD_SLIPPY diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index f52bace271..772b5a874b 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -14,13 +14,11 @@ */ #include +#include #include #include #include -#ifndef __PRE_RAM__ -#include - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -31,7 +29,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif int get_write_protect_state(void) { diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index b98fc8a380..cf025d1740 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -18,11 +18,9 @@ #include #include #include -#include #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index ec5d5ea138..3a2d96f3a0 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -14,11 +14,11 @@ * GNU General Public License for more details. */ -#include +#include #include "variant.h" -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { - variant_romstage_entry(bist); + variant_romstage_entry(); } diff --git a/src/mainboard/google/slippy/variant.h b/src/mainboard/google/slippy/variant.h index eec024ed0e..87a228c89c 100644 --- a/src/mainboard/google/slippy/variant.h +++ b/src/mainboard/google/slippy/variant.h @@ -16,6 +16,6 @@ #ifndef VARIANT_H #define VARIANT_H -void variant_romstage_entry(unsigned long bist); +void variant_romstage_entry(void); #endif diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index 25f8d27ece..1903588816 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -105,7 +105,7 @@ static void copy_spd(struct pei_data *peid) } } -void variant_romstage_entry(unsigned long bist) +void variant_romstage_entry(void) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -167,7 +167,6 @@ void variant_romstage_entry(unsigned long bist) .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], - .bist = bist, .copy_spd = copy_spd, }; diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index b95c6e1187..3ef8eec5df 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -102,7 +102,7 @@ static void copy_spd(struct pei_data *peid) spd_file + (spd_index * spd_len), spd_len); } -void variant_romstage_entry(unsigned long bist) +void variant_romstage_entry(void) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -162,7 +162,6 @@ void variant_romstage_entry(unsigned long bist) .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], - .bist = bist, .copy_spd = copy_spd, }; diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index 37c7853347..71eafc2d7a 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -119,7 +119,7 @@ static void copy_spd(struct pei_data *peid) } } -void variant_romstage_entry(unsigned long bist) +void variant_romstage_entry(void) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -179,7 +179,6 @@ void variant_romstage_entry(unsigned long bist) .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], - .bist = bist, .copy_spd = copy_spd, }; diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 731b35748d..7fcf085455 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -106,7 +106,7 @@ static void copy_spd(struct pei_data *peid) } } -void variant_romstage_entry(unsigned long bist) +void variant_romstage_entry(void) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -166,7 +166,6 @@ void variant_romstage_entry(unsigned long bist) .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], - .bist = bist, .copy_spd = copy_spd, }; diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index ff247da471..09144507b8 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -71,10 +71,12 @@ int get_lid_switch(void) */ int get_recovery_mode_switch(void) { -#ifndef __PRE_RAM__ - static int ec_in_rec_mode = 0; - static int ec_rec_flag_good = 0; -#endif + MAYBE_STATIC_BSS int ec_in_rec_mode = 0; + MAYBE_STATIC_BSS int ec_rec_flag_good = 0; + + if (ec_rec_flag_good) + return ec_in_rec_mode; + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); u8 reg8 = pci_s_read_config8(dev, GEN_PMCON_3); @@ -83,17 +85,10 @@ int get_recovery_mode_switch(void) printk(BIOS_SPEW,"%s: EC status:%#x RTC_BAT: %x\n", __func__, ec_status, reg8 & RTC_BATTERY_DEAD); -#ifdef __PRE_RAM__ - return (((reg8 & RTC_BATTERY_DEAD) != 0) && - ((ec_status & 0x3) == EC_IN_RECOVERY_MODE)); -#else - if (!ec_rec_flag_good) { - ec_in_rec_mode = (((reg8 & RTC_BATTERY_DEAD) != 0) && - ((ec_status & 0x3) == EC_IN_RECOVERY_MODE)); - ec_rec_flag_good = 1; - } + ec_in_rec_mode = (((reg8 & RTC_BATTERY_DEAD) != 0) && + ((ec_status & 0x3) == EC_IN_RECOVERY_MODE)); + ec_rec_flag_good = 1; return ec_in_rec_mode; -#endif } static const struct cros_gpio cros_gpios[] = { diff --git a/src/mainboard/google/stout/gma-mainboard.ads b/src/mainboard/google/stout/gma-mainboard.ads index d4a5d7d990..e45320f36e 100644 --- a/src/mainboard/google/stout/gma-mainboard.ads +++ b/src/mainboard/google/stout/gma-mainboard.ads @@ -28,7 +28,6 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal, - others => Disabled); + Internal); end GMA.Mainboard; diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 05de8cb63d..ac356027f5 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/veyron/mainboard.c b/src/mainboard/google/veyron/mainboard.c index 5243dc9290..8aa20aa006 100644 --- a/src/mainboard/google/veyron/mainboard.c +++ b/src/mainboard/google/veyron/mainboard.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/veyron_mickey/mainboard.c b/src/mainboard/google/veyron_mickey/mainboard.c index 9024b6c66a..2de720ccf4 100644 --- a/src/mainboard/google/veyron_mickey/mainboard.c +++ b/src/mainboard/google/veyron_mickey/mainboard.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/veyron_rialto/mainboard.c b/src/mainboard/google/veyron_rialto/mainboard.c index 6259955669..52ecbf6bbc 100644 --- a/src/mainboard/google/veyron_rialto/mainboard.c +++ b/src/mainboard/google/veyron_rialto/mainboard.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/hp/8460p/gma-mainboard.ads b/src/mainboard/hp/8460p/gma-mainboard.ads index da495f6195..01ae99aaaf 100644 --- a/src/mainboard/hp/8460p/gma-mainboard.ads +++ b/src/mainboard/hp/8460p/gma-mainboard.ads @@ -28,7 +28,6 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal, - others => Disabled); + Internal); end GMA.Mainboard; diff --git a/src/mainboard/hp/8470p/gma-mainboard.ads b/src/mainboard/hp/8470p/gma-mainboard.ads index da495f6195..01ae99aaaf 100644 --- a/src/mainboard/hp/8470p/gma-mainboard.ads +++ b/src/mainboard/hp/8470p/gma-mainboard.ads @@ -28,7 +28,6 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal, - others => Disabled); + Internal); end GMA.Mainboard; diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 354bf125be..1b91e97ec7 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include "option_table.h" diff --git a/src/mainboard/hp/folio_9470m/gma-mainboard.ads b/src/mainboard/hp/folio_9470m/gma-mainboard.ads index d4a5d7d990..e45320f36e 100644 --- a/src/mainboard/hp/folio_9470m/gma-mainboard.ads +++ b/src/mainboard/hp/folio_9470m/gma-mainboard.ads @@ -28,7 +28,6 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal, - others => Disabled); + Internal); end GMA.Mainboard; diff --git a/src/mainboard/hp/revolve_810_g1/gma-mainboard.ads b/src/mainboard/hp/revolve_810_g1/gma-mainboard.ads index da495f6195..01ae99aaaf 100644 --- a/src/mainboard/hp/revolve_810_g1/gma-mainboard.ads +++ b/src/mainboard/hp/revolve_810_g1/gma-mainboard.ads @@ -28,7 +28,6 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal, - others => Disabled); + Internal); end GMA.Mainboard; diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index c98556c30f..82dbba5dc5 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -13,15 +13,12 @@ * GNU General Public License for more details. */ -// __PRE_RAM__ means: use "unsigned" for device, not a struct. - #include #include #include #include #include -#include -#include +#include #include #include #include @@ -199,12 +196,11 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0; - if (bist == 0) - enable_lapic(); + enable_lapic(); ich7_enable_lpc(); early_superio_config_w83627ehg(); @@ -212,9 +208,6 @@ void mainboard_romstage_entry(unsigned long bist) /* Set up the console */ console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); system_reset(); diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 6048620659..2d5919c06e 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index 49e66bff80..e0fa7eb714 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -17,11 +17,9 @@ #include #include #include -#include #include #include #include -#include #include #include #include diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index b43110bab1..1a10931431 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -16,7 +16,7 @@ #include #include -#include +#include #include #include #include @@ -63,7 +63,7 @@ const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -136,7 +136,6 @@ void mainboard_romstage_entry(unsigned long bist) .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], - .bist = bist, .copy_spd = NULL, }; diff --git a/src/mainboard/intel/bayleybay_fsp/mainboard.c b/src/mainboard/intel/bayleybay_fsp/mainboard.c index 16c1844ce5..2ffb137469 100644 --- a/src/mainboard/intel/bayleybay_fsp/mainboard.c +++ b/src/mainboard/intel/bayleybay_fsp/mainboard.c @@ -17,11 +17,9 @@ #include #include #include -#include #if CONFIG(VGA_ROM_RUN) #include #endif -#include #include /* diff --git a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c index ee9f36ed31..e497bdbdc9 100644 --- a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c +++ b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c @@ -17,11 +17,9 @@ #include #include #include -#include #if CONFIG(VGA_ROM_RUN) #include #endif -#include #include /* diff --git a/src/mainboard/intel/d510mo/mainboard.c b/src/mainboard/intel/d510mo/mainboard.c index d2751bc119..cac5064704 100644 --- a/src/mainboard/intel/d510mo/mainboard.c +++ b/src/mainboard/intel/d510mo/mainboard.c @@ -15,7 +15,6 @@ #include #include -#include #include #include diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 15a00cf19f..bad2b6d538 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -13,16 +13,13 @@ * GNU General Public License for more details. */ -// __PRE_RAM__ means: use "unsigned" for device, not a struct. - #include #include #include #include #include #include -#include -#include +#include #include #include #include @@ -119,12 +116,11 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0, boot_mode = 0; - if (bist == 0) - enable_lapic(); + enable_lapic(); ich7_enable_lpc(); /* Enable SuperIO PM */ @@ -134,9 +130,6 @@ void mainboard_romstage_entry(unsigned long bist) /* Set up the console */ console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected.\n"); boot_mode = 1; diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index 2d6e916d5a..74f86221eb 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -18,8 +18,7 @@ #include #include #include -#include -#include +#include #include #include #include @@ -75,7 +74,7 @@ static void ich7_enable_lpc(void) pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; @@ -89,7 +88,6 @@ void mainboard_romstage_entry(unsigned long bist) console_init(); - report_bist_failure(bist); enable_smbus(); x4x_early_init(); diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c index c7ef09d8db..8207638a5b 100644 --- a/src/mainboard/intel/dg43gt/romstage.c +++ b/src/mainboard/intel/dg43gt/romstage.c @@ -20,8 +20,7 @@ #include #include #include -#include -#include +#include #include #include #include @@ -68,7 +67,7 @@ static void ich10_enable_lpc(void) pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; u8 boot_path = 0; @@ -81,7 +80,6 @@ void mainboard_romstage_entry(unsigned long bist) console_init(); - report_bist_failure(bist); enable_smbus(); x4x_early_init(); diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 74fe20f548..4fb512a694 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index d07da832ca..5a64e07d99 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -17,10 +17,8 @@ #include #include #include -#include #include #include -#include #include #include #include diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index a28ae78f28..ee3cec1ebf 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index 0f49c7f29a..7e1742d0f9 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_TPM2 select PLATFORM_USES_FSP2_0 select UDK_2015_BINDING - select POSTCAR_STAGE config MAINBOARD_DIR @@ -95,12 +94,10 @@ config FSP_DEBUG_ALL # Enable display and verification for coreboot build tests select DISPLAY_HOBS select DISPLAY_MTRRS - select DISPLAY_SMM_MEMORY_MAP select DISPLAY_UPD_DATA select DISPLAY_ESRAM_LAYOUT select DISPLAY_FSP_CALLS_AND_STATUS select DISPLAY_FSP_HEADER - select POSTCAR_CONSOLE select VERIFY_HOBS help Turn on debug support to display HOBS, MTRRS, SMM_MEMORY_MAP, UPD_DATA diff --git a/src/mainboard/intel/glkrvp/boardid.c b/src/mainboard/intel/glkrvp/boardid.c index 0676eaca32..1a7b3e383f 100644 --- a/src/mainboard/intel/glkrvp/boardid.c +++ b/src/mainboard/intel/glkrvp/boardid.c @@ -25,7 +25,7 @@ uint32_t board_id(void) { - MAYBE_STATIC int id = -1; + MAYBE_STATIC_NONZERO int id = -1; if (id < 0) { if (CONFIG(EC_GOOGLE_CHROMEEC)) id = variant_board_id(); diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c index 69a0a9116a..89a736f1bf 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c @@ -19,7 +19,7 @@ int variant_board_id(void) { - MAYBE_STATIC uint32_t id = BOARD_ID_INIT; + MAYBE_STATIC_NONZERO uint32_t id = BOARD_ID_INIT; if (CONFIG(EC_GOOGLE_CHROMEEC)) { if (id == BOARD_ID_INIT) { diff --git a/src/mainboard/intel/icelake_rvp/board_id.c b/src/mainboard/intel/icelake_rvp/board_id.c index b56f047008..c0def22d38 100644 --- a/src/mainboard/intel/icelake_rvp/board_id.c +++ b/src/mainboard/intel/icelake_rvp/board_id.c @@ -31,7 +31,7 @@ static int get_board_id_via_ext_ec(void) /* Get Board ID via EC I/O port write/read */ int get_board_id(void) { - MAYBE_STATIC int id = -1; + MAYBE_STATIC_NONZERO int id = -1; if (id < 0) { if (CONFIG(EC_GOOGLE_CHROMEEC)) diff --git a/src/mainboard/intel/kblrvp/board_id.c b/src/mainboard/intel/kblrvp/board_id.c index a978e0ff86..dc5afcfbcf 100644 --- a/src/mainboard/intel/kblrvp/board_id.c +++ b/src/mainboard/intel/kblrvp/board_id.c @@ -22,7 +22,7 @@ */ int get_ec_boardinfo(void) { - MAYBE_STATIC int ec_info = -1; + MAYBE_STATIC_NONZERO int ec_info = -1; if (ec_info < 0) { uint8_t buffer[2]; uint8_t index; diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index 0385e29eac..1ae7d6e504 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -35,8 +35,10 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) printk(BIOS_INFO, "SPD index %d\n", spd_index); - mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); - mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, + &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, + &mem_cfg->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); diff --git a/src/mainboard/intel/kblrvp/smihandler.c b/src/mainboard/intel/kblrvp/smihandler.c index ba8458be15..e2fc7da6f0 100644 --- a/src/mainboard/intel/kblrvp/smihandler.c +++ b/src/mainboard/intel/kblrvp/smihandler.c @@ -16,12 +16,11 @@ #include #include -#include #include #include #include #include -#include +#include #include "ec.h" #include diff --git a/src/mainboard/intel/kblrvp/spd/spd.h b/src/mainboard/intel/kblrvp/spd/spd.h index c24baa07bf..316ff5eb40 100644 --- a/src/mainboard/intel/kblrvp/spd/spd.h +++ b/src/mainboard/intel/kblrvp/spd/spd.h @@ -22,8 +22,8 @@ #define RCOMP_TARGET_PARAMS 0x5 -void mainboard_fill_dq_map_data(void *dq_map_ptr); -void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1); +void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); #endif diff --git a/src/mainboard/intel/kblrvp/spd/spd_util.c b/src/mainboard/intel/kblrvp/spd/spd_util.c index 9318c3975d..4795435a9c 100644 --- a/src/mainboard/intel/kblrvp/spd/spd_util.c +++ b/src/mainboard/intel/kblrvp/spd/spd_util.c @@ -19,7 +19,7 @@ #include "../board_id.h" #include "spd.h" -void mainboard_fill_dq_map_data(void *dq_map_ptr) +void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -27,16 +27,18 @@ void mainboard_fill_dq_map_data(void *dq_map_ptr) 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); + memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); + memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); } -void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1) { /* DQS CPU<>DRAM map */ const u8 dqs_map[2][8] = { { 0, 1, 3, 2, 4, 5, 6, 7 }, { 1, 0, 4, 5, 2, 3, 6, 7 } }; - memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); + memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); + memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); } void mainboard_fill_rcomp_res_data(void *rcomp_ptr) diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c index f900ca319b..0312ad1987 100644 --- a/src/mainboard/intel/kunimitsu/romstage.c +++ b/src/mainboard/intel/kunimitsu/romstage.c @@ -24,8 +24,10 @@ void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params) { spd_memory_init_params(memory_params); - mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0); - mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0); + mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0, + &memory_params->DqByteMapCh1); + mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0, + &memory_params->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&memory_params->RcompResistor); mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget); memory_params->MemorySpdDataLen = SPD_LEN; diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage_fsp20.c index 536469339d..2a4474e15f 100644 --- a/src/mainboard/intel/kunimitsu/romstage_fsp20.c +++ b/src/mainboard/intel/kunimitsu/romstage_fsp20.c @@ -25,8 +25,10 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) FSP_M_CONFIG *mem_cfg; mem_cfg = &mupd->FspmConfig; - mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); - mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, + &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, + &mem_cfg->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); diff --git a/src/mainboard/intel/kunimitsu/smihandler.c b/src/mainboard/intel/kunimitsu/smihandler.c index df02601368..490812138b 100644 --- a/src/mainboard/intel/kunimitsu/smihandler.c +++ b/src/mainboard/intel/kunimitsu/smihandler.c @@ -17,12 +17,11 @@ #include #include #include -#include #include #include #include #include -#include +#include #include "ec.h" #include "gpio.h" diff --git a/src/mainboard/intel/kunimitsu/spd/spd.h b/src/mainboard/intel/kunimitsu/spd/spd.h index 22d371f4bc..8bc7336470 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.h +++ b/src/mainboard/intel/kunimitsu/spd/spd.h @@ -55,8 +55,8 @@ static inline int get_spd_index(void) { return (gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios))); } void spd_memory_init_params(MEMORY_INIT_UPD *memory_params); -void mainboard_fill_dq_map_data(void *dq_map_ptr); -void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1); +void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); uintptr_t mainboard_get_spd_data(void); diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c index 288ee1e7ee..05a0a86734 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd_util.c +++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c @@ -19,7 +19,7 @@ #include "boardid.h" #include "spd.h" -void mainboard_fill_dq_map_data(void *dq_map_ptr) +void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -27,16 +27,18 @@ void mainboard_fill_dq_map_data(void *dq_map_ptr) 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); + memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); + memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); } -void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1) { /* DQS CPU<>DRAM map */ const u8 dqs_map[2][8] = { { 0, 1, 3, 2, 6, 5, 4, 7 }, { 2, 3, 0, 1, 6, 7, 4, 5 } }; - memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); + memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); + memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); } void mainboard_fill_rcomp_res_data(void *rcomp_ptr) diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c index 45f39d46e2..46c2cdd6e0 100644 --- a/src/mainboard/intel/saddlebrook/romstage.c +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -49,8 +49,10 @@ void mainboard_memory_init_params( * should be set in the FSP flash image and should not need to be * changed. */ - mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0); - mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0); + mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0, + &memory_params->DqByteMapCh1); + mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0, + &memory_params->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&memory_params->RcompResistor); mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget); diff --git a/src/mainboard/intel/saddlebrook/spd/spd.h b/src/mainboard/intel/saddlebrook/spd/spd.h index a5f1af3a77..70a1f68ce8 100644 --- a/src/mainboard/intel/saddlebrook/spd/spd.h +++ b/src/mainboard/intel/saddlebrook/spd/spd.h @@ -19,8 +19,8 @@ #define RCOMP_TARGET_PARAMS 0x5 -void mainboard_fill_dq_map_data(void *dq_map_ptr); -void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1); +void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); diff --git a/src/mainboard/intel/saddlebrook/spd/spd_util.c b/src/mainboard/intel/saddlebrook/spd/spd_util.c index 5055d9a3af..a09cebcf4e 100644 --- a/src/mainboard/intel/saddlebrook/spd/spd_util.c +++ b/src/mainboard/intel/saddlebrook/spd/spd_util.c @@ -17,7 +17,7 @@ #include #include "spd.h" -void mainboard_fill_dq_map_data(void *dq_map_ptr) +void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -25,16 +25,18 @@ void mainboard_fill_dq_map_data(void *dq_map_ptr) 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); + memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); + memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); } -void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1) { /* DQS CPU<>DRAM map */ const u8 dqs_map[2][8] = { { 0, 1, 3, 2, 4, 5, 6, 7 }, { 1, 0, 4, 5, 2, 3, 6, 7 } }; - memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); + memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); + memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); } void mainboard_fill_rcomp_res_data(void *rcomp_ptr) diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 802221446d..556677acb6 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -22,9 +23,6 @@ /* Compile-time settings for recovery mode. */ #define REC_MODE_SETTING 0 -#ifndef __PRE_RAM__ -#include - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -35,7 +33,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif int get_recovery_mode_switch(void) { diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index 4bfd039117..0e9217daec 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -17,11 +17,9 @@ #include #include #include -#include #include #include #include -#include #include #include diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index 73d59974b9..85b704e3dd 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include /* Hardware Monitor */ diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index b51e4b44d0..bbaad83089 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -13,14 +13,11 @@ * GNU General Public License for more details. */ -/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ - #include #include #include #include -#include -#include +#include #include #include #include @@ -243,12 +240,11 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0; - if (bist == 0) - enable_lapic(); + enable_lapic(); /* Force PCIRST# */ pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); @@ -261,9 +257,6 @@ void mainboard_romstage_entry(unsigned long bist) /* Set up the console */ console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); system_reset(); diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index afedbfce83..675cb05003 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #if CONFIG(VGA_ROM_RUN) #include diff --git a/src/mainboard/lenovo/l520/gma-mainboard.ads b/src/mainboard/lenovo/l520/gma-mainboard.ads index d4a5d7d990..e45320f36e 100644 --- a/src/mainboard/lenovo/l520/gma-mainboard.ads +++ b/src/mainboard/lenovo/l520/gma-mainboard.ads @@ -28,7 +28,6 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal, - others => Disabled); + Internal); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/s230u/gma-mainboard.ads b/src/mainboard/lenovo/s230u/gma-mainboard.ads index d4a5d7d990..e45320f36e 100644 --- a/src/mainboard/lenovo/s230u/gma-mainboard.ads +++ b/src/mainboard/lenovo/s230u/gma-mainboard.ads @@ -28,7 +28,6 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal, - others => Disabled); + Internal); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 43d6088788..1b763188e8 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -// __PRE_RAM__ means: use "unsigned" for device, not a struct. - #include #include #include diff --git a/src/mainboard/lenovo/t420/gma-mainboard.ads b/src/mainboard/lenovo/t420/gma-mainboard.ads index e9471cb352..a19bf339fd 100644 --- a/src/mainboard/lenovo/t420/gma-mainboard.ads +++ b/src/mainboard/lenovo/t420/gma-mainboard.ads @@ -27,7 +27,6 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal, - others => Disabled); + Internal); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t420s/gma-mainboard.ads b/src/mainboard/lenovo/t420s/gma-mainboard.ads index d4a5d7d990..e45320f36e 100644 --- a/src/mainboard/lenovo/t420s/gma-mainboard.ads +++ b/src/mainboard/lenovo/t420s/gma-mainboard.ads @@ -28,7 +28,6 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal, - others => Disabled); + Internal); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t430/gma-mainboard.ads b/src/mainboard/lenovo/t430/gma-mainboard.ads index e9471cb352..a19bf339fd 100644 --- a/src/mainboard/lenovo/t430/gma-mainboard.ads +++ b/src/mainboard/lenovo/t430/gma-mainboard.ads @@ -27,7 +27,6 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal, - others => Disabled); + Internal); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index b0a22aafbf..0c7d0756ba 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS select GFX_GMA_INTERNAL_IS_LVDS if BOARD_LENOVO_T430S select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION + select DRIVERS_RICOH_RCE822 if BOARD_LENOVO_T431S # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t430s/gma-mainboard.ads b/src/mainboard/lenovo/t430s/gma-mainboard.ads index d635d88fb9..8cf5d2fe13 100644 --- a/src/mainboard/lenovo/t430s/gma-mainboard.ads +++ b/src/mainboard/lenovo/t430s/gma-mainboard.ads @@ -28,7 +28,6 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal, - others => Disabled); + Internal); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb index ff307027ec..ee949792a7 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb @@ -1,6 +1,11 @@ chip northbridge/intel/sandybridge device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + # Enable hotplug on Port 5 for Thunderbolt controller + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 1, 0, 0, 0 }" + device pci 1c.4 on + subsystemid 0x17aa 0x21fb + end # PCIe Port #5 Thunderbolt controller device pci 1f.0 on chip ec/lenovo/h8 register "has_bdc_detection" = "1" diff --git a/src/mainboard/lenovo/t520/gma-mainboard.ads b/src/mainboard/lenovo/t520/gma-mainboard.ads index d4a5d7d990..e45320f36e 100644 --- a/src/mainboard/lenovo/t520/gma-mainboard.ads +++ b/src/mainboard/lenovo/t520/gma-mainboard.ads @@ -28,7 +28,6 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal, - others => Disabled); + Internal); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 5fd9118e94..f63a12054f 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -21,6 +21,7 @@ config BOARD_LENOVO_BASEBOARD_T530 select GFX_GMA_INTERNAL_IS_LVDS select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION + select DRIVERS_RICOH_RCE822 if BOARD_LENOVO_W530 # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t530/gma-mainboard.ads b/src/mainboard/lenovo/t530/gma-mainboard.ads index d4a5d7d990..e45320f36e 100644 --- a/src/mainboard/lenovo/t530/gma-mainboard.ads +++ b/src/mainboard/lenovo/t530/gma-mainboard.ads @@ -28,7 +28,6 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal, - others => Disabled); + Internal); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index cfe2d237db..9e832208b5 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -15,8 +15,6 @@ * GNU General Public License for more details. */ -// __PRE_RAM__ means: use "unsigned" for device, not a struct. - #include #include #include @@ -26,8 +24,7 @@ #include #include #include -#include -#include +#include #include #include #include @@ -159,14 +156,13 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0; int dock_err; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 }; - if (bist == 0) - enable_lapic(); + enable_lapic(); ich7_enable_lpc(); @@ -190,9 +186,6 @@ void mainboard_romstage_entry(unsigned long bist) /* Setup the console */ console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); system_reset(); diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c index e41035166c..e4abab5770 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c @@ -20,8 +20,7 @@ #include #include #include -#include -#include +#include #include #include #include @@ -60,7 +59,7 @@ static void ich7_enable_lpc(void) pci_write_config32(LPC_DEV, GEN1_DEC, 0x00fc0a01); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; @@ -74,7 +73,6 @@ void mainboard_romstage_entry(unsigned long bist) console_init(); - report_bist_failure(bist); enable_smbus(); x4x_early_init(); diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index afaa9aafe1..4382bc084d 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -// __PRE_RAM__ means: use "unsigned" for device, not a struct. - #include #include #include diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 69e20385bf..905d81d682 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -31,10 +31,6 @@ config MAINBOARD_PART_NUMBER string default "ThinkPad X201" -config MMCONF_BASE_ADDRESS - hex - default 0xe0000000 - config USBDEBUG_HCD_INDEX int default 2 @@ -47,10 +43,6 @@ config MAX_CPUS int default 4 -config CPU_ADDR_BITS - int - default 36 - # Without the Intel ME's EFFS partition some PCIe devices (like the USB and SATA # controllers) don't work as expected config ME_CLEANER_ARGS diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 96033f88df..56c439bb58 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -35,23 +35,8 @@ static void fill_ssdt(struct device *device) static void mainboard_enable(struct device *dev) { - u16 pmbase; - dev->ops->acpi_fill_ssdt_generator = fill_ssdt; - pmbase = pci_read_config32(pcidev_on_root(0x1f, 0), - PMBASE) & 0xff80; - - printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); - - outl(0, pmbase + SMI_EN); - - enable_lapic(); - pci_write_config32(pcidev_on_root(0x1f, 0), GPIO_BASE, - DEFAULT_GPIOBASE | 1); - pci_write_config8(pcidev_on_root(0x1f, 0), GPIO_CNTL, - 0x10); - /* If we're resuming from suspend, blink suspend LED */ if (acpi_is_wakeup_s3()) ec_write(0x0c, 0xc7); diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index ae154e25b1..3a06a8cd93 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -16,8 +16,6 @@ * GNU General Public License for more details. */ -/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ - #include #include #include @@ -25,8 +23,7 @@ #include #include #include -#include -#include +#include #include #include #include @@ -169,14 +166,12 @@ static void set_fsb_frequency(void) smbus_block_write(0x69, 0, 5, block); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { u32 reg32; int s3resume = 0; const u8 spd_addrmap[4] = { 0x50, 0, 0x51, 0 }; - - if (bist == 0) - enable_lapic(); + enable_lapic(); nehalem_early_initialization(NEHALEM_MOBILE); @@ -199,9 +194,6 @@ void mainboard_romstage_entry(unsigned long bist) console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - /* Read PM1_CNT */ reg32 = inl(DEFAULT_PMBASE + 0x04); printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); diff --git a/src/mainboard/lenovo/x220/gma-mainboard.ads b/src/mainboard/lenovo/x220/gma-mainboard.ads index d4a5d7d990..e45320f36e 100644 --- a/src/mainboard/lenovo/x220/gma-mainboard.ads +++ b/src/mainboard/lenovo/x220/gma-mainboard.ads @@ -28,7 +28,6 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal, - others => Disabled); + Internal); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/x230/gma-mainboard.ads b/src/mainboard/lenovo/x230/gma-mainboard.ads index d4a5d7d990..e45320f36e 100644 --- a/src/mainboard/lenovo/x230/gma-mainboard.ads +++ b/src/mainboard/lenovo/x230/gma-mainboard.ads @@ -28,7 +28,6 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal, - others => Disabled); + Internal); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index fc0c678b77..5a8ab942bc 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -15,8 +15,6 @@ * GNU General Public License for more details. */ -// __PRE_RAM__ means: use "unsigned" for device, not a struct. - #include #include #include @@ -27,8 +25,7 @@ #include #include #include -#include -#include +#include #include #include #include @@ -159,13 +156,12 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 }; - if (bist == 0) - enable_lapic(); + enable_lapic(); /* Enable GPIOs */ pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); @@ -192,9 +188,6 @@ void mainboard_romstage_entry(unsigned long bist) else printk(BIOS_DEBUG, "Dock is not present\n"); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "Soft reset detected, rebooting properly.\n"); diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index c31301e4d1..7f12091ced 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -15,8 +15,6 @@ * GNU General Public License for more details. */ -// __PRE_RAM__ means: use "unsigned" for device, not a struct. - #include #include #include @@ -26,8 +24,7 @@ #include #include #include -#include -#include +#include #include #include #include @@ -159,14 +156,13 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0; int dock_err; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 }; - if (bist == 0) - enable_lapic(); + enable_lapic(); ich7_enable_lpc(); @@ -190,9 +186,6 @@ void mainboard_romstage_entry(unsigned long bist) /* Setup the console */ console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); system_reset(); diff --git a/src/mainboard/ocp/monolake/Kconfig b/src/mainboard/ocp/monolake/Kconfig index 13d7876cea..ad4e9c7208 100644 --- a/src/mainboard/ocp/monolake/Kconfig +++ b/src/mainboard/ocp/monolake/Kconfig @@ -12,6 +12,15 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_USES_IFD_GBE_REGION select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 + select IPMI_KCS + +config VBOOT + select VBOOT_VBNV_CMOS + select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP config INTEGRATED_UART def_bool n @@ -47,4 +56,7 @@ config FMDFILE string default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" +config IPMI_KCS_REGISTER_SPACING + default 4 + endif # BOARD_OCP_MONOLAKE diff --git a/src/mainboard/ocp/monolake/Makefile.inc b/src/mainboard/ocp/monolake/Makefile.inc index 1606476d80..b6a26b0147 100644 --- a/src/mainboard/ocp/monolake/Makefile.inc +++ b/src/mainboard/ocp/monolake/Makefile.inc @@ -14,3 +14,4 @@ ## ramstage-y += irqroute.c +ramstage-y += ipmi.c diff --git a/src/mainboard/ocp/monolake/cmos.layout b/src/mainboard/ocp/monolake/cmos.layout index 3c5bc3b03d..3aaa56b569 100644 --- a/src/mainboard/ocp/monolake/cmos.layout +++ b/src/mainboard/ocp/monolake/cmos.layout @@ -81,6 +81,7 @@ entries 408 1 e 1 nmi 409 2 e 7 power_on_after_fail #411 5 r 0 unused +416 128 r 0 vbnv # MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed diff --git a/src/mainboard/ocp/monolake/devicetree.cb b/src/mainboard/ocp/monolake/devicetree.cb index 2d91b73b02..26c95d5d67 100644 --- a/src/mainboard/ocp/monolake/devicetree.cb +++ b/src/mainboard/ocp/monolake/devicetree.cb @@ -4,6 +4,8 @@ chip soc/intel/fsp_broadwell_de end device domain 0 on device pci 00.0 on end # SoC router + device pci 02.2 off end # IOU0 port C, 10GbE + device pci 02.3 off end # IOU0 port D, 10GbE device pci 14.0 on end # xHCI Controller device pci 19.0 on end # Gigabit LAN Controller device pci 1d.0 on end # EHCI Controller @@ -11,8 +13,9 @@ chip soc/intel/fsp_broadwell_de chip drivers/pc80/tpm device pnp 0c31.0 on end end - chip drivers/generic/generic # BMC KCS + chip drivers/ipmi # BMC KCS device pnp ca2.0 on end + register "bmc_i2c_address" = "0x20" end end # LPC Bridge device pci 1f.2 on end # SATA Controller diff --git a/src/mainboard/ocp/monolake/dsdt.asl b/src/mainboard/ocp/monolake/dsdt.asl index 72b1c3c086..1248703266 100644 --- a/src/mainboard/ocp/monolake/dsdt.asl +++ b/src/mainboard/ocp/monolake/dsdt.asl @@ -27,9 +27,6 @@ DefinitionBlock( { #include "acpi/platform.asl" - Name (IDTP, 0x0CA2) - Name (ICDP, 0x0CA6) - Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) @@ -293,97 +290,5 @@ DefinitionBlock( } } - Scope (_SB.PCI0.LPC0) - { - Device (SPMI) - { - Name (_HID, EisaId ("IPI0001")) - Name (_STR, Unicode ("IPMI_KCS")) - Name (_UID, 0x00) - OperationRegion (IPST, SystemIO, ICDP, 0x01) - Field (IPST, ByteAcc, NoLock, Preserve) - { - STAS, 8 - } - Method (_STA, 0, NotSerialized) { - Return (0x0f) - } - Name (ICRS, ResourceTemplate () - { - IO (Decode16, - 0x0000, - 0x0000, - 0x00, - 0x00, - _Y01) - IO (Decode16, - 0x0000, - 0x0000, - 0x00, - 0x00, - _Y02) - - }) - Method (_CRS, 0, NotSerialized) - { - CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._MIN, IPDB) - CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._MAX, IPDH) - CreateByteField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._LEN, IPDL) - CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._MIN, IPCB) - CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._MAX, IPCH) - CreateByteField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._LEN, IPCL) - - IPDB = IDTP - IPDH = IDTP - IPDL = 0x01 - - IPCB = ICDP - IPCH = ICDP - IPCL = 0x01 - - Return (ICRS) - } - Method (_IFT, 0, NotSerialized) { - Return (0x01) - } - Method(_SRV, 0, NotSerialized) { - Return (0x0200) - } - } - - Device (SYSR) - { - Name (_HID, EisaId ("PNP0C02")) - - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings - { - IO (Decode16, - 0x0CA2, - 0x0CA2, - 0x01, - 0x01, - ) - IO (Decode16, - 0x0CA6, - 0x0CA6, - 0x01, - 0x01, - ) - IO (Decode16, - 0x0CA8, - 0x0CA8, - 0x01, - 0x01, - ) - IO (Decode16, - 0x0CAC, - 0x0CAC, - 0x01, - 0x01, - ) - }) - } - } - #include "acpi/mainboard.asl" } diff --git a/src/mainboard/ocp/monolake/ipmi.c b/src/mainboard/ocp/monolake/ipmi.c new file mode 100644 index 0000000000..37aacc842e --- /dev/null +++ b/src/mainboard/ocp/monolake/ipmi.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Wiwynn Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include "ipmi.h" + +#define BMC_KCS_BASE 0xca2 + +int is_ipmi_clear_cmos_set(ipmi_oem_rsp_t *rsp) +{ + int ret; + ipmi_oem_req_t req; + + if (rsp == NULL) { + printk(BIOS_ERR, "%s failed, null pointer parameter\n", + __func__); + return 0; + } + /* IPMI OEM get bios boot order command to check if the valid bit and + the CMOS clear bit are both set from the response BootMode byte. */ + ret = ipmi_kcs_message(BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, + IPMI_OEM_GET_BIOS_BOOT_ORDER, + (const unsigned char *) &req, sizeof(ipmi_oem_req_t), + (unsigned char *) rsp, sizeof(ipmi_oem_rsp_t)); + + if (ret < sizeof(struct ipmi_rsp) || rsp->CompletionCode) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp->CompletionCode); + return 0; + } + + if (GET_VALID_BIT(rsp->Data.BootMode) && GET_CMOS_BIT(rsp->Data.BootMode)) { + printk(BIOS_INFO, "IPMI CMOS clear requested\n"); + return 1; + } + + printk(BIOS_DEBUG, "IPMI CMOS clear is not set\n"); + return 0; +} + +void clear_ipmi_flags(ipmi_oem_rsp_t *rsp_get) +{ + int ret; + ipmi_oem_req_t req; + struct ipmi_rsp rsp; + + if (rsp_get == NULL) { + printk(BIOS_ERR, "%s failed, null pointer parameter\n", + __func__); + return; + } + + req = rsp_get->Data; + CLEAR_CMOS_AND_VALID_BIT(req.BootMode); + ret = ipmi_kcs_message(BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, + IPMI_OEM_SET_BIOS_BOOT_ORDER, + (const unsigned char *) &req, sizeof(ipmi_oem_req_t), + (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.completion_code); + return; + } + + printk(BIOS_INFO, "clear IPMI flags done\n"); +} diff --git a/src/mainboard/ocp/monolake/ipmi.h b/src/mainboard/ocp/monolake/ipmi.h new file mode 100644 index 0000000000..5863eb5082 --- /dev/null +++ b/src/mainboard/ocp/monolake/ipmi.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Wiwynn Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MONOLAKE_IPMI_H +#define MONOLAKE_IPMI_H +#include + +#define IPMI_NETFN_OEM 0x30 +#define IPMI_OEM_SET_BIOS_BOOT_ORDER 0x52 +#define IPMI_OEM_GET_BIOS_BOOT_ORDER 0x53 +#define GET_CMOS_BIT(x) ((x) & (1 << 1)) +#define GET_VALID_BIT(x) ((x) & (1 << 7)) +#define CLEAR_CMOS_AND_VALID_BIT(x) ((x) &= 0x7d) + +typedef struct { + u8 BootMode; /* Bit 1:CMOS clear, bit 7:valid bit. */ + u8 Boot0000; + u8 Boot0001; + u8 Boot0002; + u8 Boot0003; + u8 Boot0004; +} __packed ipmi_oem_req_t; + +typedef struct { + u16 KcsRsp; + u8 CompletionCode; + ipmi_oem_req_t Data; +} __packed ipmi_oem_rsp_t; + +/* + * IPMI get response to check if valid and CMOS clear bit + * are both set and store the IPMI response data to the parameter. + */ +int is_ipmi_clear_cmos_set(ipmi_oem_rsp_t *rsp); +/* + * Clear valid bit and CMOS clear bit from the parameter + * and set it back via IPMI. + */ +void clear_ipmi_flags(ipmi_oem_rsp_t *rsp); + +#endif diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c index bbfeeafb3b..010e064c35 100644 --- a/src/mainboard/ocp/monolake/mainboard.c +++ b/src/mainboard/ocp/monolake/mainboard.c @@ -15,34 +15,11 @@ */ #include +#include +#include #include -#if CONFIG(VGA_ROM_RUN) -#include -#endif - -#define BMC_KCS_BASE 0xca2 -#define INTERFACE_IS_IO 0x1 - -#if CONFIG(GENERATE_SMBIOS_TABLES) -static int mainboard_smbios_data(struct device *dev, int *handle, - unsigned long *current) -{ - int len = 0; - - // add IPMI Device Information - len += smbios_write_type38( - current, handle, - SMBIOS_BMC_INTERFACE_KCS, - 0x20, // IPMI Version - 0x20, // I2C address - 0xff, // no NV storage - BMC_KCS_BASE | INTERFACE_IS_IO, // IO port interface address - 0x40, - 0); // no IRQ - - return len; -} -#endif +#include +#include "ipmi.h" /* * mainboard_enable is executed as first thing after enumerate_buses(). @@ -50,18 +27,31 @@ static int mainboard_smbios_data(struct device *dev, int *handle, */ static void mainboard_enable(struct device *dev) { -#if CONFIG(GENERATE_SMBIOS_TABLES) - dev->ops->get_smbios_data = mainboard_smbios_data; -#endif + ipmi_oem_rsp_t rsp; - /* Enable access to the BMC IPMI via KCS */ - struct device *lpc_sio_dev = dev_find_slot_pnp(BMC_KCS_BASE, 0); - struct resource *res = new_resource(lpc_sio_dev, BMC_KCS_BASE); - res->base = BMC_KCS_BASE; - res->size = 1; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + if (is_ipmi_clear_cmos_set(&rsp)) { + /* TODO: Should also try to restore CMOS to cmos.default + * if USE_OPTION_TABLE is set */ + cmos_init(1); + clear_ipmi_flags(&rsp); + system_reset(); + } } struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; + +void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t) +{ + + char locator[64] = {0}; + + snprintf(locator, sizeof(locator), "DIMM_%c%u", 'A' + dimm->channel_num, + dimm->dimm_num); + t->device_locator = smbios_add_string(t->eos, locator); + + snprintf(locator, sizeof(locator), "_Node0_Channel%d_Dimm%d", dimm->channel_num, + dimm->dimm_num); + t->bank_locator = smbios_add_string(t->eos, locator); +} diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c index f3ec7e32b8..8625868428 100644 --- a/src/mainboard/ocp/monolake/romstage.c +++ b/src/mainboard/ocp/monolake/romstage.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -24,6 +25,9 @@ #include #include +/* Define the strings for UPD variables that could be customized */ +#define FSP_VAR_HYPERTHREADING "HyperThreading" + /** * /brief mainboard call for setup that needs to be done before fsp init * @@ -57,9 +61,26 @@ void late_mainboard_romstage_entry(void) 0x0c0ca1); } +/* + * This function sets up global variable to store VPD binary blob info, + * and use settings in the binary blob to configure UPD. + */ +static void board_configure_upd(UPD_DATA_REGION *UpdData) +{ + u8 val; + + if (vpd_get_bool(FSP_VAR_HYPERTHREADING, VPD_RW, &val)) + UpdData->HyperThreading = val; +} + /** - * /brief customize fsp parameters here if needed + * /brief customize fsp parameters, use data stored in VPD binary blob + * to configure FSP UPD variables. */ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) { + UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr; + + if (CONFIG(VPD)) + board_configure_upd(UpdData); } diff --git a/src/mainboard/ocp/monolake/vboot-ro.fmd b/src/mainboard/ocp/monolake/vboot-ro.fmd new file mode 100644 index 0000000000..44be3370ce --- /dev/null +++ b/src/mainboard/ocp/monolake/vboot-ro.fmd @@ -0,0 +1,22 @@ +FLASH 16M { + SI_ALL@0x0 0x800000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x7ff000 + } + SI_BIOS@0x800000 0x800000 { + MISC_RW@0x0 0x20000 { + RW_MRC_CACHE@0x0 0x10000 + RW_VPD(PRESERVE)@0x010000 0x4000 + } + WP_RO@0x020000 0x7e0000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x7dc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x4000 + COREBOOT(CBFS)@0x5000 0x7d7000 + } + } + } +} diff --git a/src/mainboard/packardbell/ms2290/Kconfig b/src/mainboard/packardbell/ms2290/Kconfig index 631559157f..a104fecd8c 100644 --- a/src/mainboard/packardbell/ms2290/Kconfig +++ b/src/mainboard/packardbell/ms2290/Kconfig @@ -30,10 +30,6 @@ config MAINBOARD_VENDOR string default "Packard Bell" -config MMCONF_BASE_ADDRESS - hex - default 0xe0000000 - config USBDEBUG_HCD_INDEX int default 2 @@ -46,8 +42,4 @@ config MAX_CPUS int default 4 -config CPU_ADDR_BITS - int - default 36 - endif diff --git a/src/mainboard/packardbell/ms2290/Makefile.inc b/src/mainboard/packardbell/ms2290/Makefile.inc index b23d2e5560..c35cde680f 100644 --- a/src/mainboard/packardbell/ms2290/Makefile.inc +++ b/src/mainboard/packardbell/ms2290/Makefile.inc @@ -14,5 +14,6 @@ ## smm-y += smihandler.c +romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/packardbell/ms2290/gma-mainboard.ads b/src/mainboard/packardbell/ms2290/gma-mainboard.ads index d4a5d7d990..e45320f36e 100644 --- a/src/mainboard/packardbell/ms2290/gma-mainboard.ads +++ b/src/mainboard/packardbell/ms2290/gma-mainboard.ads @@ -28,7 +28,6 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal, - others => Disabled); + Internal); end GMA.Mainboard; diff --git a/src/mainboard/packardbell/ms2290/gpio.c b/src/mainboard/packardbell/ms2290/gpio.c new file mode 100644 index 0000000000..3aed746af6 --- /dev/null +++ b/src/mainboard/packardbell/ms2290/gpio.c @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio12 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index 785e6e8103..809ccea597 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include #include @@ -33,8 +32,6 @@ static void mainboard_enable(struct device *dev) { - u16 pmbase; - int i; const u8 dmp[256] = { 0x00, 0x20, 0x00, 0x00, 0x00, 0x02, 0x89, 0xe4, 0x30, 0x00, 0x40, 0x14, 0x00, 0x00, 0x00, 0x11, @@ -58,19 +55,6 @@ static void mainboard_enable(struct device *dev) for (i = 0; i < 256; i++) ec_write (i, dmp[i]); - pmbase = pci_read_config32(pcidev_on_root(0x1f, 0), - PMBASE) & 0xff80; - - printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); - - outl(0, pmbase + SMI_EN); - - enable_lapic(); - pci_write_config32(pcidev_on_root(0x1f, 0), GPIO_BASE, - DEFAULT_GPIOBASE | 1); - pci_write_config8(pcidev_on_root(0x1f, 0), GPIO_CNTL, - 0x10); - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2); /* This sneaked in here, because EasyNote has no SuperIO chip. diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 0ab5544858..5a4a9f1e71 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -16,8 +16,6 @@ * GNU General Public License for more details. */ -/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ - #include #include #include @@ -25,12 +23,12 @@ #include #include #include -#include -#include +#include #include #include #include +#include #include #include @@ -161,7 +159,7 @@ static inline u16 read_acpi16(u32 addr) } #endif -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { u32 reg32; int s3resume = 0; @@ -171,8 +169,7 @@ void mainboard_romstage_entry(unsigned long bist) outb(4, 0x61); outb(0, 0x61); - if (bist == 0) - enable_lapic(); + enable_lapic(); nehalem_early_initialization(NEHALEM_MOBILE); @@ -181,15 +178,8 @@ void mainboard_romstage_entry(unsigned long bist) /* Enable GPIOs */ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - outl (0x796bd9c3, DEFAULT_GPIOBASE); - outl (0x86fec7c2, DEFAULT_GPIOBASE + 4); - outl (0xe4e8d7fe, DEFAULT_GPIOBASE + 0xc); - outl (0, DEFAULT_GPIOBASE + 0x18); - outl (0x00004182, DEFAULT_GPIOBASE + 0x2c); - outl (0x123360f8, DEFAULT_GPIOBASE + 0x30); - outl (0x1f47bfa8, DEFAULT_GPIOBASE + 0x34); - outl (0xfffe7fb6, DEFAULT_GPIOBASE + 0x38); + setup_pch_gpios(&mainboard_gpio_map); /* This should probably go away. Until now it is required * and mainboard specific @@ -198,9 +188,6 @@ void mainboard_romstage_entry(unsigned long bist) console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - /* Read PM1_CNT */ reg32 = inl(DEFAULT_PMBASE + 0x04); printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); diff --git a/src/mainboard/pcengines/apu1/BiosCallOuts.c b/src/mainboard/pcengines/apu1/BiosCallOuts.c index df5f03731b..caaa1f421f 100644 --- a/src/mainboard/pcengines/apu1/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu1/BiosCallOuts.c @@ -50,9 +50,11 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) { - AGESA_STATUS Status = AGESA_UNSUPPORTED; -#ifdef __PRE_RAM__ AGESA_READ_SPD_PARAMS *info = ConfigPtr; + + if (!ENV_ROMSTAGE) + return AGESA_UNSUPPORTED; + u8 index = get_spd_offset(); if (info->MemChannelId > 0) @@ -66,7 +68,5 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, index) < 0) die("No SPD data\n"); - Status = AGESA_SUCCESS; -#endif - return Status; + return AGESA_SUCCESS; } diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index edacb22bee..dff346e16a 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -130,9 +130,11 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) { - AGESA_STATUS Status = AGESA_UNSUPPORTED; -#ifdef __PRE_RAM__ AGESA_READ_SPD_PARAMS *info = ConfigPtr; + + if (!ENV_ROMSTAGE) + return AGESA_UNSUPPORTED; + u8 index = get_spd_offset(); if (info->MemChannelId > 0) @@ -146,7 +148,5 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, index) < 0) die("No SPD data\n"); - Status = AGESA_SUCCESS; -#endif - return Status; + return AGESA_SUCCESS; } diff --git a/src/mainboard/purism/librem_skl/romstage.c b/src/mainboard/purism/librem_skl/romstage.c index faf4090ae1..42003738c3 100644 --- a/src/mainboard/purism/librem_skl/romstage.c +++ b/src/mainboard/purism/librem_skl/romstage.c @@ -21,7 +21,7 @@ #include #include -static void mainboard_fill_dq_map_data(void *dq_map_ptr) +static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -29,16 +29,18 @@ static void mainboard_fill_dq_map_data(void *dq_map_ptr) 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); + memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); + memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); } -static void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1) { /* DQS CPU<>DRAM map */ const u8 dqs_map[2][8] = { { 0, 1, 3, 2, 4, 5, 6, 7 }, { 1, 0, 4, 5, 2, 3, 6, 7 } }; - memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); + memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); + memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); } static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) @@ -68,8 +70,10 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) dump_spd_info(&blk); assert(blk.spd_array[0][0] != 0); - mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); - mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, + &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, + &mem_cfg->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); diff --git a/src/mainboard/razer/Kconfig b/src/mainboard/razer/Kconfig new file mode 100644 index 0000000000..bae422eaaa --- /dev/null +++ b/src/mainboard/razer/Kconfig @@ -0,0 +1,17 @@ + +if VENDOR_RAZER + +choice + prompt "Mainboard model" + +source "src/mainboard/razer/*/Kconfig.name" + +endchoice + +source "src/mainboard/razer/*/Kconfig" + +config MAINBOARD_VENDOR + string "Mainboard Vendor" + default "RAZER" + +endif diff --git a/src/mainboard/razer/Kconfig.name b/src/mainboard/razer/Kconfig.name new file mode 100644 index 0000000000..8f67e02429 --- /dev/null +++ b/src/mainboard/razer/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_RAZER + bool "RAZER" diff --git a/src/mainboard/razer/blade_stealth_kbl/Kconfig b/src/mainboard/razer/blade_stealth_kbl/Kconfig new file mode 100644 index 0000000000..986a4df7bf --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/Kconfig @@ -0,0 +1,55 @@ +if BOARD_RAZER_BLADE_STEALTH_KBL + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SYSTEM_TYPE_LAPTOP + select BOARD_ROMSIZE_KB_8192 + select SUPERIO_ITE_IT8528E + select SOC_INTEL_KABYLAKE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select MAINBOARD_USES_FSP2_0 + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + select MAINBOARD_HAS_LIBGFXINIT + select GENERIC_SPD_BIN + select DRIVERS_I2C_HID + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select ADD_FSP_BINARIES + select FSP_USE_REPO + select NO_POST + + # For now no way to choose the correct the available RAM + config BOARD_RAZER_BLADE_STEALTH_KBL_16GB + bool "16GB RAM (4x MT52L1G32D4PG)" + default n + + config VGA_BIOS_ID + string + default "8086,5916" + + config IRQ_SLOT_COUNT + int + default 18 + + config MAINBOARD_FAMILY + string + default "BLADE_STEALTH" + + config MAINBOARD_PART_NUMBER + string + default "H2U" + + config MAINBOARD_VERSION + string + default "1.0" + + config MAINBOARD_DIR + string + default "razer/blade_stealth_kbl" + + config MAX_CPUS + int + default 4 + +endif diff --git a/src/mainboard/razer/blade_stealth_kbl/Kconfig.name b/src/mainboard/razer/blade_stealth_kbl/Kconfig.name new file mode 100644 index 0000000000..5193f4089c --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_RAZER_BLADE_STEALTH_KBL + bool "Razer Blade Stealth KabyLake (2016)" diff --git a/src/mainboard/razer/blade_stealth_kbl/Makefile.inc b/src/mainboard/razer/blade_stealth_kbl/Makefile.inc new file mode 100644 index 0000000000..e517484499 --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += spd + +ramstage-y += mainboard.c +ramstage-y += ramstage.c +ramstage-y += hda_verb.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi/ac.asl b/src/mainboard/razer/blade_stealth_kbl/acpi/ac.asl new file mode 100644 index 0000000000..813c008e68 --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/acpi/ac.asl @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Johanna Schander + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (AC) +{ + Name (_HID, "ACPI0003") + Name (_PCL, Package () { \_SB }) + + Method (_PSR) + { + Return (ACEX) + } + + Method (_STA) + { + Return (0x0F) + } +} diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl b/src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl new file mode 100644 index 0000000000..a89496d69e --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Johanna Schander + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (BAT) +{ + Name (_HID, EisaId ("PNP0C0A")) + Name (_UID, 1) + Name (_PCL, Package () { \_SB }) + + Name (BSTP, 0) + + Name (PBIF, Package () { + 0x00000001, /* 0x00: Power Unit: mAh */ + 0xFFFFFFFF, /* 0x01: Design Capacity */ + 0xFFFFFFFF, /* 0x02: Last Full Charge Capacity */ + 0x00000001, /* 0x03: Battery Technology: Rechargeable */ + 0xFFFFFFFF, /* 0x04: Design Voltage */ + 0x00000003, /* 0x05: Design Capacity of Warning */ + 0xFFFFFFFF, /* 0x06: Design Capacity of Low */ + 0x00000001, /* 0x07: Capacity Granularity 1 */ + 0x00000001, /* 0x08: Capacity Granularity 2 */ + "Razer Blade Stealth", + "SERIAL", + "LiIon", + "Razer" + }) + + + Name (PBST, Package () { + 0x00000000, /* 0x00: Battery State */ + 0xFFFFFFFF, /* 0x01: Battery Present Rate */ + 0xFFFFFFFF, /* 0x02: Battery Remaining Capacity */ + 0xFFFFFFFF, /* 0x03: Battery Present Voltage */ + }) + + Method (_STA, 0, Serialized) + { + Return (0x1F) + } + + Method (_BIF, 0, Serialized) + { + /* Last Full Charge Capacity */ + Store (BFCP, Index (PBIF, 2)) + + /* Design Voltage */ + Store (BDVT, Index (PBIF, 4)) + + /* Design Capacity */ + Store (BDCP, Index (PBIF, 1)) + + /* Design Capacity of Warning */ + Store (BDCP / 0x32, Index (PBIF, 5)) + + /* Design Capacity of Low */ + Store (BDCP / 0x64, Index (PBIF, 6)) + + Store (ToString (BSER, Ones), Index (PBIF, 0x0A)) + + Return (PBIF) + } + + Method (_BST, 0, Serialized) + { + /* + * 0: BATTERY STATE + * + * bit 0 = discharging + * bit 1 = charging + * bit 2 = critical level + */ + + /* Check if AC is present */ + If (ACEX) { + /* Read battery status from EC */ + Store (BCST, Local0) + } Else { + /* Always discharging when on battery power */ + Store (0x01, Local0) + } + + Store (Local0, Index (PBST, 0)) + + /* Notify if battery state has changed since last time */ + If (LNotEqual (Local0, BSTP)) { + Store (Local0, BSTP) + Notify (BAT, 0x80) + } + + /* + * 1: BATTERY PRESENT RATE + */ + Store (BCRT, Index (PBST, 1)) + + /* + * 2: BATTERY REMAINING CAPACITY + */ + Store (BRCP, Index (PBST, 2)) + + /* + * 3: BATTERY PRESENT VOLTAGE + */ + Store (BCVT, Index (PBST, 3)) + + Return (PBST) + } +} diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl b/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl new file mode 100644 index 0000000000..62a8622dc1 --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Johanna Schander + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (EC) +{ + Name (_HID, EisaId ("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 0x50) // Copied over + + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + }) + + Name (ACEX, 0) + + OperationRegion (ERAM, EmbeddedControl, 0x00, 0xFF) + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x1C), + ODP1, 8, + ODP2, 8, + Offset (0x56), + CPUT, 8, + CPU1, 8, + GPUT, 8, + ADPV, 16, + ADPC, 16, + FANC, 8, + Offset (0x60), + BSER, 256, // BAT Serial Number + Offset (0x90), + BIF0, 16, + BDCP, 16, // BAT Design Capacity + BFCP, 16, // BAT Full Capacity + BRCH, 16, // BAT Rechargable + BDVT, 16, // BAT Design Voltage + BIF5, 16, + BIF6, 16, + BIF7, 16, + BIF8, 16, + BCST, 16, // BAT Current State + BCRT, 16, // BAT Current Rate + BRCP, 16, // BAT Remaining Capacity + BCVT, 16, // BAT Current Voltage + PWRS, 8, // Power State (?) + ECN0, 8, + Offset (0xB0), + SRNM, 16, + MFDA, 16, + PHMR, 8, + BLDA, 8, + Offset (0xE2), + LIDS, 8 // Lid state + } + + Method (_REG, 2, NotSerialized) + { + /* Initialize AC power state */ + Store (PWRS - 0x82, ACEX) + + /* Initialize LID switch state */ + Store (LIDS, \LIDS) + } + + + // Close ? + Method (_Q14, 0, NotSerialized) + { + Store (LIDS, \LIDS) + Notify (LID0, 0x80) + } + + //Open + Method (_Q15, 0, NotSerialized) + { + Store (LIDS, \LIDS) + Notify (LID0, 0x80) + } + + + // AC plugged + Method (_Q13, 0, NotSerialized) + { + Store (PWRS - 0x82, ACEX) + Notify (BAT, 0x80) // Status Change + Notify (BAT, 0x81) // Information Change + Notify (AC, 0x80) // Status Change + } + + #include "ac.asl" + #include "battery.asl" +} diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi/mainboard.asl b/src/mainboard/razer/blade_stealth_kbl/acpi/mainboard.asl new file mode 100644 index 0000000000..6b8cb51380 --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/acpi/mainboard.asl @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB) +{ + Device (LID0) + { + Name (_HID, EisaId ("PNP0C0D")) + + Method (_LID) + { + if (\_SB.PCI0.LPCB.EC.LIDS > 1) + { + Return (One) + } + else + { + Return (Zero) + } + } + + Method (_STA) + { + Return (_LID) + } + } + + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + + Method (_STA) + { + Return (0xF) + } + + Name (_PRW, Package () { 27, 4 }) + } + +} diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi/superio.asl b/src/mainboard/razer/blade_stealth_kbl/acpi/superio.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi_tables.c b/src/mainboard/razer/blade_stealth_kbl/acpi_tables.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/razer/blade_stealth_kbl/board_info.txt b/src/mainboard/razer/blade_stealth_kbl/board_info.txt new file mode 100644 index 0000000000..414d880a12 --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: RAZER +Board name: Blade Stealth KabyLake (H2U) +Category: laptop +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2016 diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb new file mode 100644 index 0000000000..deb98690f8 --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -0,0 +1,277 @@ +chip soc/intel/skylake + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x000c0081" + register "gen2_dec" = "0x000c0681" + register "gen3_dec" = "0x000c1641" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "0" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "0" + register "SataPortsEnable[1]" = "0" + register "SataPortsEnable[2]" = "0" + register "EnableAzalia" = "1" + register "DspEnable" = "0" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "PttSwitch" = "0" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "1" + register "SaGv" = "SaGv_Enabled" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "0" + + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 6A | 64A | 31A | 31A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(6), + .voltage_limit = 1520, + .ac_loadline = 1030, + .dc_loadline = 1030, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(64), + .voltage_limit = 1520, + .ac_loadline = 240, + .dc_loadline = 240, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + # Enable Root Ports 3, 5 and 9 + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[8]" = "1" + + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[8]" = "1" + + register "PcieRpHotPlug[4]" = "1" + + # USB + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) + + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? + register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? + register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? + + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # Camera + register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # Keyboard + register "usb2_ports[8]" = "USB2_PORT_FLEX(OC2)" # Touchscreen + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) + + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # TODO Unknown. Maybe USBC? + + # PL1 override 25W + register "tdp_pl1_override" = "25" + + # PL2 override 44W + register "tdp_pl2_override" = "44" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # Thermal Subsystem + device pci 08.0 off end # Gaussian Mixture Model + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on end # I2C Controller #0 + device pci 15.1 on + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end # I2C Controller #1 + device pci 15.2 off end # I2C Controller #2 + device pci 15.3 off end # I2C Controller #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 off end # SATA + device pci 19.0 on end # I2C Controller #4 + device pci 19.1 off end # I2C Controller #5 + device pci 19.2 off end # UART #2 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 on end # Serial IO UART0 + device pci 1f.0 on # LPC + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip superio/ite/it8528e + device pnp 6e.1 off end + device pnp 6e.2 off end + device pnp 6e.3 off end + device pnp 6e.4 off end + device pnp 6e.5 off end + device pnp 6e.6 off end + device pnp 6e.a off end + device pnp 6e.f off end + device pnp 6e.10 off end + device pnp 6e.11 off end + device pnp 6e.12 off end + device pnp 6e.13 off end + device pnp 6e.14 off end + device pnp 6e.17 off end + device pnp 6e.18 off end + device pnp 6e.19 off end + end #superio/ite/it8528e + end # LPC Bridge + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/razer/blade_stealth_kbl/dsdt.asl b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl new file mode 100644 index 0000000000..e110067901 --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +){ + //Platform + #include + + // global NVS and variables + #include + + // CPU + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + } + + } + // Chipset specific sleep states + #include + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/razer/blade_stealth_kbl/gma-mainboard.ads b/src/mainboard/razer/blade_stealth_kbl/gma-mainboard.ads new file mode 100644 index 0000000000..4d55f2cbc8 --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/gma-mainboard.ads @@ -0,0 +1,30 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (Internal, + DP1, + DP2, + HDMI1, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/razer/blade_stealth_kbl/gpio.h b/src/mainboard/razer/blade_stealth_kbl/gpio.h new file mode 100644 index 0000000000..5bf1bc48df --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/gpio.h @@ -0,0 +1,182 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Johanna Schander + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include +#include + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { + /* RCIN# */ _PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x0), + /* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), + /* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), + /* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), + /* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), + /* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), + /* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_A7, 0x84000102, 0x0), + /* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000702, 0x0), + /* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), + /* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_A11, 0x40100102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_A12, 0x04000201, 0x0), + /* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), + /* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), + /* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x1000), + /* SD_1P8_SEL */ _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x0), + /* SD_PWR_EN# */ _PAD_CFG_STRUCT(GPP_A17, 0x44000700, 0x0), + /* ISH_GP0 */ _PAD_CFG_STRUCT(GPP_A18, 0x44000702, 0x0), + /* ISH_GP1 */ _PAD_CFG_STRUCT(GPP_A19, 0x44000702, 0x0), + /* ISH_GP2 */ _PAD_CFG_STRUCT(GPP_A20, 0x44000702, 0x0), + /* ISH_GP3 */ _PAD_CFG_STRUCT(GPP_A21, 0x44000702, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_A23, 0x40100102, 0x0), + /* CORE_VID0 */ _PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), + /* CORE_VID1 */ _PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), + /* VRALERT# */ _PAD_CFG_STRUCT(GPP_B2, 0x44000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B3, 0x80100100, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B4, 0x44000201, 0x0), + /* SRCCLKREQ0# */ _PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x0), + /* SRCCLKREQ1# */ _PAD_CFG_STRUCT(GPP_B6, 0x44000700, 0x0), + /* SRCCLKREQ2# */ _PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B8, 0x44000300, 0x0), + /* SRCCLKREQ4# */ _PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B10, 0x44000300, 0x0), + /* EXT_PWR_GATE# */ _PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), + /* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0), + /* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B15, 0x44000200, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B17, 0x42880100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B18, 0x80880102, 0x3000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x0), + /* GSPI1_CLK */ _PAD_CFG_STRUCT(GPP_B20, 0x44000700, 0x1000), + /* GSPI1_MISO */ _PAD_CFG_STRUCT(GPP_B21, 0x44000700, 0x1000), + /* GSPI1_MOSI */ _PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000), + /* SMBCLK */ _PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), + /* SMBDATA */ _PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), + /* SML0CLK */ _PAD_CFG_STRUCT(GPP_C3, 0x44000702, 0x0), + /* SML0DATA */ _PAD_CFG_STRUCT(GPP_C4, 0x44000702, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C5, 0x40900100, 0x1000), + /* RESERVED */ _PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), + /* RESERVED */ _PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), + /* UART0_RXD */ _PAD_CFG_STRUCT(GPP_C8, 0x44000702, 0x0), + /* UART0_TXD */ _PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0), + /* UART0_RTS# */ _PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0), + /* UART0_CTS# */ _PAD_CFG_STRUCT(GPP_C11, 0x44000700, 0x0), + /* UART1_RXD */ _PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0), + /* UART1_TXD */ _PAD_CFG_STRUCT(GPP_C13, 0x44000700, 0x0), + /* UART1_RTS# */ _PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0), + /* UART1_CTS# */ _PAD_CFG_STRUCT(GPP_C15, 0x44000702, 0x0), + /* I2C0_SDA */ _PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x0), + /* I2C0_SCL */ _PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x0), + /* I2C1_SDA */ _PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x0), + /* I2C1_SCL */ _PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x0), + /* UART2_RXD */ _PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0), + /* UART2_TXD */ _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), + /* UART2_RTS# */ _PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), + /* UART2_CTS# */ _PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0), + /* SPI1_CS# */ _PAD_CFG_STRUCT(GPP_D0, 0x44000700, 0x0), + /* SPI1_CLK */ _PAD_CFG_STRUCT(GPP_D1, 0x44000700, 0x0), + /* SPI1_MISO */ _PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0), + /* SPI1_MOSI */ _PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0), + /* FLASHTRIG */ _PAD_CFG_STRUCT(GPP_D4, 0x44000700, 0x0), + /* ISH_I2C0_SDA */ _PAD_CFG_STRUCT(GPP_D5, 0x44000700, 0x0), + /* ISH_I2C0_SCL */ _PAD_CFG_STRUCT(GPP_D6, 0x44000700, 0x0), + /* ISH_I2C1_SDA */ _PAD_CFG_STRUCT(GPP_D7, 0x44000700, 0x0), + /* ISH_I2C1_SCL */ _PAD_CFG_STRUCT(GPP_D8, 0x44000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D9, 0x40000100, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D10, 0x40000100, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D11, 0x40000100, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D12, 0x40000100, 0x0), + /* ISH_UART0_RXD */ _PAD_CFG_STRUCT(GPP_D13, 0x44000700, 0x0), + /* ISH_UART0_TXD */ _PAD_CFG_STRUCT(GPP_D14, 0x44000700, 0x0), + /* ISH_UART0_RTS# */ _PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0), + /* ISH_UART0_CTS# */ _PAD_CFG_STRUCT(GPP_D16, 0x44000700, 0x0), + /* DMIC_CLK1 */ _PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0), + /* DMIC_DATA1 */ _PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x0), + /* DMIC_CLK0 */ _PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), + /* DMIC_DATA0 */ _PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0), + /* SPI1_IO2 */ _PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0), + /* SPI1_IO3 */ _PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), + /* I2S_MCLK */ _PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E0, 0x42880100, 0x0), + /* SATAXPCIE1 */ _PAD_CFG_STRUCT(GPP_E1, 0x44000700, 0x0), + /* SATAXPCIE2 */ _PAD_CFG_STRUCT(GPP_E2, 0x44000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E3, 0x40000000, 0x0), + /* SATA_DEVSLP0 */ _PAD_CFG_STRUCT(GPP_E4, 0x04000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E5, 0x82880102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E6, 0x44000200, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E7, 0x80180102, 0x0), + /* SATALED# */ _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E9, 0x44000200, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E10, 0x44000201, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E11, 0x44000201, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E12, 0x44000300, 0x0), + /* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_E13, 0x44000702, 0x0), + /* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E15, 0x42840102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x0), + /* EDP_HPD */ _PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), + /* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x0), + /* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000), + /* DDPC_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x0), + /* DDPC_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E22, 0x40900100, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E23, 0x84000200, 0x1000), + /* I2S2_SCLK */ _PAD_CFG_STRUCT(GPP_F0, 0x44000700, 0x0), + /* I2S2_SFRM */ _PAD_CFG_STRUCT(GPP_F1, 0x44000700, 0x0), + /* I2S2_TXD */ _PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0), + /* I2S2_RXD */ _PAD_CFG_STRUCT(GPP_F3, 0x44000700, 0x0), + /* I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F4, 0x44000700, 0x2000000), + /* I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2000000), + /* I2C3_SDA */ _PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2000000), + /* I2C3_SCL */ _PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2000000), + /* I2C4_SDA */ _PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2000000), + /* I2C4_SCL */ _PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2000000), + /* ISH_I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2000000), + /* ISH_I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2000000), + /* EMMC_CMD */ _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_F13, 0x44000102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_F14, 0x44000102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_F15, 0x44000100, 0x0), + /* EMMC_DATA3 */ _PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x0), + /* EMMC_DATA4 */ _PAD_CFG_STRUCT(GPP_F17, 0x44000700, 0x0), + /* EMMC_DATA5 */ _PAD_CFG_STRUCT(GPP_F18, 0x44000700, 0x0), + /* EMMC_DATA6 */ _PAD_CFG_STRUCT(GPP_F19, 0x44000700, 0x0), + /* EMMC_DATA7 */ _PAD_CFG_STRUCT(GPP_F20, 0x44000700, 0x0), + /* EMMC_RCLK */ _PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0), + /* EMMC_CLK */ _PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0x40100100, 0x0), + /* SD_CMD */ _PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0), + /* SD_DATA0 */ _PAD_CFG_STRUCT(GPP_G1, 0x44000700, 0x0), + /* SD_DATA1 */ _PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0), + /* SD_DATA2 */ _PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0), + /* SD_DATA3 */ _PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0), + /* SD_CD# */ _PAD_CFG_STRUCT(GPP_G5, 0x44000700, 0x0), + /* SD_CLK */ _PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_G7, 0x44000100, 0x0), +}; + +#endif + +#endif diff --git a/src/mainboard/razer/blade_stealth_kbl/hda_verb.c b/src/mainboard/razer/blade_stealth_kbl/hda_verb.c new file mode 100644 index 0000000000..457d1d9447 --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/hda_verb.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * Copyright (C) 2019 Johanna Schander + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +const u32 cim_verb_data[] = { + + /* Realtek, ALC298 */ + 0x10ec0298, /* Vendor ID */ + 0x1a586752, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x1a586752), + AZALIA_PIN_CFG(0, 0x12, 0xb7a60140), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x03a11030), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4075a505), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x03211020), + + /* Intel, KabylakeHDMI */ + 0x8086280b, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/razer/blade_stealth_kbl/mainboard.c b/src/mainboard/razer/blade_stealth_kbl/mainboard.c new file mode 100644 index 0000000000..7f1f11416a --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/mainboard.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Purism SPC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#define MAX_SERIAL_LENGTH 0x100 + +const char *smbios_mainboard_serial_number(void) +{ + static char serial_number[MAX_SERIAL_LENGTH + 1] = {0}; + struct cbfsf file; + + if (serial_number[0] != 0) + return serial_number; + + if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) { + struct region_device cbfs_region; + size_t ser_len; + + cbfs_file_data(&cbfs_region, &file); + + ser_len = region_device_sz(&cbfs_region); + if (ser_len <= MAX_SERIAL_LENGTH) { + if (rdev_readat(&cbfs_region, serial_number, 0, ser_len) == ser_len) { + serial_number[ser_len] = 0; + return serial_number; + } + } + } + + strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER, MAX_SERIAL_LENGTH); + + return serial_number; +} diff --git a/src/mainboard/razer/blade_stealth_kbl/ramstage.c b/src/mainboard/razer/blade_stealth_kbl/ramstage.c new file mode 100644 index 0000000000..94f8071340 --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/ramstage.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/razer/blade_stealth_kbl/romstage.c b/src/mainboard/razer/blade_stealth_kbl/romstage.c new file mode 100644 index 0000000000..893d28a2ab --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/romstage.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2017 Purism SPC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include "spd/spd.h" +#include +#include +#include + +#define SPD_4X_2GB 0 +#define SPD_4X_4GB 1 + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + + +#if CONFIG(BOARD_RAZER_BLADE_STEALTH_KBL_16GB) + u8 spd_index = SPD_4X_4GB; +#else + u8 spd_index = SPD_4X_2GB; +#endif + + printk(BIOS_INFO, "SPD index %d\n", spd_index); + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + struct region_device spd_rdev; + + mem_cfg->DqPinsInterleaved = 0; + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found\n"); + mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); + /* Memory leak is ok since we have memory mapped boot media */ + // TODO evaluate google/eve way of loading + mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + + mupd->FspmTestConfig.DmiVc1 = 1; +} diff --git a/src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc b/src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc new file mode 100644 index 0000000000..3188dbf80e --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Johanna Schander +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd_util.c + +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES += micron_dimm_MT52L512M32D2PF-107 # 0b0000 8GB +SPD_SOURCES += micron_dimm_MT52L1G32D4PG-107 # 0b0001 16GB diff --git a/src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L1G32D4PG-107.spd.hex b/src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L1G32D4PG-107.spd.hex new file mode 100644 index 0000000000..8e6030b635 --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L1G32D4PG-107.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 1A 05 0A 03 11 01 08 09 00 00 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 B1 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 2B 1F +4D 54 35 32 4C 31 47 33 32 44 34 50 47 2D 31 30 +37 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L512M32D2PF-107.spd.hex b/src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L512M32D2PF-107.spd.hex new file mode 100644 index 0000000000..fb90339528 --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L512M32D2PF-107.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 0B 03 11 01 08 09 00 00 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 A1 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 3A 64 +4D 54 35 32 4C 35 31 32 4D 33 32 44 32 50 46 2D +31 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/razer/blade_stealth_kbl/spd/spd.h b/src/mainboard/razer/blade_stealth_kbl/spd/spd.h new file mode 100644 index 0000000000..233d368567 --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/spd/spd.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2019 Johanna Schander + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#include +#include "../gpio.h" + +#define RCOMP_TARGET_PARAMS 0x5 + +void mainboard_fill_dq_map_data(void *dq_map_ptr); +void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); +#endif diff --git a/src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c b/src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c new file mode 100644 index 0000000000..a6f31f0930 --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include "spd.h" + +void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + {0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00}, + {0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00}}; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = {{0, 1, 3, 2, 4, 5, 6, 7}, {1, 0, 4, 5, 2, 3, 6, 7}}; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = {200, 81, 162}; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = {100, 40, 40, 23, 40}; + + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} diff --git a/src/mainboard/roda/rk886ex/mainboard.c b/src/mainboard/roda/rk886ex/mainboard.c index 91c11d5830..922eba2d43 100644 --- a/src/mainboard/roda/rk886ex/mainboard.c +++ b/src/mainboard/roda/rk886ex/mainboard.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index efd739c52e..30ebf4431d 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ - #include #include #include @@ -26,8 +24,7 @@ #include #include #include -#include -#include +#include #include #include #include @@ -206,12 +203,11 @@ static void init_artec_dongle(void) outb(0xf4, 0x88); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0; - if (bist == 0) - enable_lapic(); + enable_lapic(); /* Force PCIRST# */ pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); @@ -224,9 +220,6 @@ void mainboard_romstage_entry(unsigned long bist) /* Set up the console */ console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); system_reset(); diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index eaddaf9a26..497828b58a 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ - #include #include #include diff --git a/src/mainboard/samsung/lumpy/gma-mainboard.ads b/src/mainboard/samsung/lumpy/gma-mainboard.ads index d4a5d7d990..e45320f36e 100644 --- a/src/mainboard/samsung/lumpy/gma-mainboard.ads +++ b/src/mainboard/samsung/lumpy/gma-mainboard.ads @@ -28,7 +28,6 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal, - others => Disabled); + Internal); end GMA.Mainboard; diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index 86642172dc..f793963fd4 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -18,10 +18,8 @@ #include #include #include -#include #include #include -#include #include #include #include "ec.h" diff --git a/src/mainboard/scaleway/tagada/bmcinfo.c b/src/mainboard/scaleway/tagada/bmcinfo.c index 237d551b59..93b45397ea 100644 --- a/src/mainboard/scaleway/tagada/bmcinfo.c +++ b/src/mainboard/scaleway/tagada/bmcinfo.c @@ -16,7 +16,6 @@ #include #include -#include #include #include @@ -52,15 +51,12 @@ enum biosBmcInfoValidFlag_e { BMCINFO_VALID_NEED_WARN, BMCINFO_VALID, }; - -static enum biosBmcInfoValidFlag_e CAR_GLOBAL biosBmcInfoValidFlag; - static bool bmcinfo_is_valid(size_t minsize) { + static enum biosBmcInfoValidFlag_e biosBmcInfoValidFlag; const biosBmcInfo_t *bmc_info = BMC_INFO; - int flag = car_get_var(biosBmcInfoValidFlag); - if (flag == BMCINFO_UNTESTED) { - flag = BMCINFO_INVALID; + if (biosBmcInfoValidFlag == BMCINFO_UNTESTED) { + biosBmcInfoValidFlag = BMCINFO_INVALID; if ((bmc_info->magic0 == BIOSBMCINFO_MAGIC0) && (bmc_info->magic1 == BIOSBMCINFO_MAGIC1) && (bmc_info->length >= offsetof(biosBmcInfo_t, hwRev)) @@ -73,20 +69,17 @@ static bool bmcinfo_is_valid(size_t minsize) if (bmc_info->chksum == chksum) { if (bmc_info->length >= offsetof(biosBmcInfo_t, endMarker)) - flag = BMCINFO_VALID; + biosBmcInfoValidFlag = BMCINFO_VALID; else - flag = BMCINFO_VALID_NEED_WARN; + biosBmcInfoValidFlag = BMCINFO_VALID_NEED_WARN; } } - car_set_var(biosBmcInfoValidFlag, flag); } -#if !defined(__PRE_RAM__) - if (flag == BMCINFO_INVALID) { + if (ENV_RAMSTAGE && biosBmcInfoValidFlag == BMCINFO_INVALID) { int length = offsetof(biosBmcInfo_t, endMarker); printk(BIOS_CRIT, "WARNING bmcInfo struct" "is not available please update your BMC.\n"); - flag = BMCINFO_INVALID_WARNED; - car_set_var(biosBmcInfoValidFlag, flag); + biosBmcInfoValidFlag = BMCINFO_INVALID_WARNED; printk(BIOS_CRIT, "bmcInfo magic = \"%x-%x\"\n", bmc_info->magic0, bmc_info->magic1); printk(BIOS_CRIT, "bmcInfo length = %d expected = %d\"\n", @@ -99,15 +92,13 @@ static bool bmcinfo_is_valid(size_t minsize) printk(BIOS_CRIT, "bmcInfo chksum = 0x%x expected = 0x%x\"\n", bmc_info->chksum, chksum); } - if (flag == BMCINFO_VALID_NEED_WARN) { + if (ENV_RAMSTAGE && biosBmcInfoValidFlag == BMCINFO_VALID_NEED_WARN) { printk(BIOS_CRIT, "WARNING bmcInfo struct" " is incomplete please update your BMC.\n"); - flag = BMCINFO_VALID; - car_set_var(biosBmcInfoValidFlag, flag); + biosBmcInfoValidFlag = BMCINFO_VALID; } -#endif - if (flag < BMCINFO_VALID_NEED_WARN) + if (biosBmcInfoValidFlag < BMCINFO_VALID_NEED_WARN) return false; return (bmc_info->length >= minsize); } diff --git a/src/mainboard/siemens/mc_apl1/Kconfig.name b/src/mainboard/siemens/mc_apl1/Kconfig.name index cae6ac16a1..70f314d985 100644 --- a/src/mainboard/siemens/mc_apl1/Kconfig.name +++ b/src/mainboard/siemens/mc_apl1/Kconfig.name @@ -12,10 +12,10 @@ config BOARD_SIEMENS_MC_APL3 bool "-> MC APL3" select BOARD_SIEMENS_BASEBOARD_MC_APL1 -config BOARD_SIEMENS_MC_APL5 - bool "-> MC APL5" - select BOARD_SIEMENS_BASEBOARD_MC_APL1 - config BOARD_SIEMENS_MC_APL4 bool "-> MC APL4" select BOARD_SIEMENS_BASEBOARD_MC_APL1 + +config BOARD_SIEMENS_MC_APL5 + bool "-> MC APL5" + select BOARD_SIEMENS_BASEBOARD_MC_APL1 diff --git a/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd b/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd new file mode 100644 index 0000000000..d1cbfcf7f7 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd @@ -0,0 +1,30 @@ +FLASH 16M { + WP_RO@0x0 0xe93000 { + SI_DESC@0x0 0x1000 + IFWI@0x1000 0x2ff000 + RO_VPD@0x300000 0x4000 + RO_SECTION@0x304000 0xb8f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + COREBOOT(CBFS)@0x1000 0xb4e000 + GBB@0xb4f000 0x40000 + } + } + MISC_RW@0xe93000 0x2c000 { + UNIFIED_MRC_CACHE@0x0 0x21000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 + } + RW_SHARED@0x21000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x25000 0x2000 + RW_NVRAM@0x27000 0x5000 + } + BIOS_UNUSABLE@0xebf000 0x40000 + DEVICE_EXTENSION@0xeff000 0x100000 + UNUSED_HOLE@0xfff000 0x1000 +} diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig index 4e4a9281bd..6adf4e9c41 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig @@ -10,4 +10,20 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LPC_TPM select TPM_ON_FAST_SPI +config CBFS_SIZE + default 0xb4e000 + +config VBOOT + select VBOOT_MEASURED_BOOT + select VBOOT_VBNV_FLASH + select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/mc_apl_vboot.fmd" + endif # BOARD_SIEMENS_MC_APL2 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig index 1ee72bb8d5..31317b9280 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig @@ -12,4 +12,20 @@ config BOARD_SPECIFIC_OPTIONS config UART_FOR_CONSOLE default 1 +config CBFS_SIZE + default 0xb4e000 + +config VBOOT + select VBOOT_MEASURED_BOOT + select VBOOT_VBNV_FLASH + select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/mc_apl_vboot.fmd" + endif # BOARD_SIEMENS_MC_APL4 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig index 4a4b6cc604..21d7ac7b78 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig @@ -12,4 +12,20 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LPC_TPM select TPM_ON_FAST_SPI +config CBFS_SIZE + default 0xb4e000 + +config VBOOT + select VBOOT_MEASURED_BOOT + select VBOOT_VBNV_FLASH + select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/mc_apl_vboot.fmd" + endif # BOARD_SIEMENS_MC_APL5 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c index f6fed97551..2cc7dd4532 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c @@ -16,9 +16,32 @@ #include #include #include +#include +#include #include #include +static void igd_disable(void) +{ + struct device *root_dev = pcidev_path_on_root(SA_DEVFN_ROOT); + uint8_t deven; + uint16_t ggc; + + /* GMCH Graphics Control Register */ + ggc = pci_read_config16(root_dev, 0x50); + /* Set size of Graphics Translation Table Memory (GGMS) [7:6] + * to 0 and select 0 MB for Graphics Memory (GMS) [15:8]. */ + ggc &= ~(0xffc0); + /* Disable IGD VGA (IVD). */ + ggc |= 0x2; + pci_write_config16(root_dev, 0x50, ggc); + /* Device Enable Register */ + deven = pci_read_config8(root_dev, 0x54); + /* Disable IGD device (D2F0EN). */ + deven &= ~(0x10); + pci_write_config8(root_dev, 0x54, deven); +} + /** * This function sets up the DP2LVDS-converter to be used with the appropriate * lcd panel. @@ -42,6 +65,8 @@ int ptn3460_init(const char *hwi_block) /* Get all needed information from hwinfo block. */ if (hwilib_get_field(Edid, edid_data, sizeof(edid_data)) != sizeof(edid_data)) { + /* Disable IGD to avoid panel failures. */ + igd_disable(); printk(BIOS_ERR, "LCD: No EDID data available in %s\n", hwi_block); return 1; diff --git a/src/mainboard/siemens/mc_bdx1/mainboard.c b/src/mainboard/siemens/mc_bdx1/mainboard.c index 2bb985285a..5cef53ce2a 100644 --- a/src/mainboard/siemens/mc_bdx1/mainboard.c +++ b/src/mainboard/siemens/mc_bdx1/mainboard.c @@ -27,7 +27,6 @@ #include #endif #include -#include #include #include #include diff --git a/src/mainboard/siemens/mc_tcu3/mainboard.c b/src/mainboard/siemens/mc_tcu3/mainboard.c index 169b04dd59..9e12aa588f 100644 --- a/src/mainboard/siemens/mc_tcu3/mainboard.c +++ b/src/mainboard/siemens/mc_tcu3/mainboard.c @@ -18,11 +18,9 @@ #include #include #include -#include #if CONFIG(VGA_ROM_RUN) #include #endif -#include #include #include #include diff --git a/src/mainboard/sifive/hifive-unleashed/Makefile.inc b/src/mainboard/sifive/hifive-unleashed/Makefile.inc index 207898e973..88ea145eef 100644 --- a/src/mainboard/sifive/hifive-unleashed/Makefile.inc +++ b/src/mainboard/sifive/hifive-unleashed/Makefile.inc @@ -12,16 +12,19 @@ # GNU General Public License for more details. bootblock-y += memlayout.ld +bootblock-y += media.c romstage-y += memlayout.ld romstage-y += romstage.c +romstage-y += media.c ramstage-y += memlayout.ld ramstage-y += fixup_fdt.c +ramstage-y += media.c DTB=$(obj)/hifive-unleashed.dtb -DTS=src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts +DTS=src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts $(DTB): $(DTS) dtc -I dts -O dtb -o $(DTB) $(DTS) diff --git a/src/mainboard/sifive/hifive-unleashed/fu540-c000.dtsi b/src/mainboard/sifive/hifive-unleashed/fu540-c000.dtsi new file mode 100644 index 0000000000..3dc27c33d6 --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/fu540-c000.dtsi @@ -0,0 +1,245 @@ +/* + * This file is part of the Linux kernel. + * + * Copyright (c) 2018-2019 SiFive, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540-c000", "sifive,fu540"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + cpu0: cpu@0 { + compatible = "sifive,e51", "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; + status = "disabled"; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <1>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu2: cpu@2 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <2>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu3: cpu@3 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <3>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu4: cpu@4 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <4>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu4_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus"; + ranges; + plic0: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + riscv,ndev = <53>; + interrupt-controller; + interrupts-extended = < + &cpu0_intc 0xffffffff + &cpu1_intc 0xffffffff &cpu1_intc 9 + &cpu2_intc 0xffffffff &cpu2_intc 9 + &cpu3_intc 0xffffffff &cpu3_intc 9 + &cpu4_intc 0xffffffff &cpu4_intc 9>; + }; + prci: clock-controller@10000000 { + compatible = "sifive,fu540-c000-prci"; + reg = <0x0 0x10000000 0x0 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; + }; + uart0: serial@10010000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + reg = <0x0 0x10010000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <4>; + clocks = <&prci 3>; + status = "disabled"; + }; + uart1: serial@10011000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + reg = <0x0 0x10011000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <5>; + clocks = <&prci 3>; + status = "disabled"; + }; + i2c0: i2c@10030000 { + compatible = "sifive,fu540-c000-i2c", "sifive,i2c0"; + reg = <0x0 0x10030000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <50>; + clocks = <&prci 3>; + reg-shift = <2>; + reg-io-width = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi0: spi@10040000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10040000 0x0 0x1000 + 0x0 0x20000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <51>; + clocks = <&prci 3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi1: spi@10041000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10041000 0x0 0x1000 + 0x0 0x30000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <52>; + clocks = <&prci 3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi2: spi@10050000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10050000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <6>; + clocks = <&prci 3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + eth0: ethernet@10090000 { + compatible = "sifive,fu540-c000-gem"; + interrupt-parent = <&plic0>; + interrupts = <53>; + reg = <0x0 0x10090000 0x0 0x2000 + 0x0 0x100a0000 0x0 0x1000>; + local-mac-address = [00 00 00 00 00 00]; + clock-names = "pclk", "hclk"; + clocks = <&prci 2>, <&prci 2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + }; +}; diff --git a/src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts b/src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts new file mode 100644 index 0000000000..454c3d807c --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts @@ -0,0 +1,97 @@ +/* + * This file is part of the Linux kernel. + * + * Copyright (c) 2018-2019 SiFive, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "fu540-c000.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "SiFive HiFive Unleashed A00"; + compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; + + chosen { + }; + + cpus { + /* Clock frequency (in Hz) of the PCB crystal for rtcclk */ + timebase-frequency = <1000000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; + + soc { + }; + + hfclk: hfclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333333>; + clock-output-names = "hfclk"; + }; + + rtcclk: rtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <1000000>; + clock-output-names = "rtcclk"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&qspi0 { + status = "okay"; + flash@0 { + compatible = "issi,is25wp256", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&qspi2 { + status = "okay"; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3300 3300>; + disable-wp; + }; +}; + +ð0 { + status = "okay"; + phy-mode = "gmii"; + phy-handle = <&phy0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; diff --git a/src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts b/src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts deleted file mode 100644 index 6b9bbaa399..0000000000 --- a/src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts +++ /dev/null @@ -1,640 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 SiFive, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -/dts-v1/; - -/ { - #address-cells = <2>; - #size-cells = <2>; - compatible = "sifive,fu540g", "sifive,fu500"; - model = "sifive,hifive-unleashed-a00"; - - aliases { - serial0 = &L28; - serial1 = &L29; - }; - - chosen { - }; -/* - firmware { - sifive,fsbl = "YYYY-MM-DD"; - }; -*/ - L3: cpus { - #address-cells = <1>; - #size-cells = <0>; - timebase-frequency = <1000000>; - L9: cpu@0 { - clock-frequency = <0>; - compatible = "sifive,rocket0", "riscv"; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <16384>; - next-level-cache = <&L24 &L0>; - reg = <0>; - riscv,isa = "rv64imac"; - sifive,dtim = <&L8>; - sifive,itim = <&L7>; - status = "okay"; - L10: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - L12: cpu@1 { - clock-frequency = <0>; - compatible = "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - next-level-cache = <&L24 &L0>; - reg = <1>; - riscv,isa = "rv64imafdc"; - sifive,itim = <&L11>; - status = "okay"; - tlb-split; - L13: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - L15: cpu@2 { - clock-frequency = <0>; - compatible = "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - next-level-cache = <&L24 &L0>; - reg = <2>; - riscv,isa = "rv64imafdc"; - sifive,itim = <&L14>; - status = "okay"; - tlb-split; - L16: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - L18: cpu@3 { - clock-frequency = <0>; - compatible = "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - next-level-cache = <&L24 &L0>; - reg = <3>; - riscv,isa = "rv64imafdc"; - sifive,itim = <&L17>; - status = "okay"; - tlb-split; - L19: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - L21: cpu@4 { - clock-frequency = <0>; - compatible = "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - next-level-cache = <&L24 &L0>; - reg = <4>; - riscv,isa = "rv64imafdc"; - sifive,itim = <&L20>; - status = "okay"; - tlb-split; - L22: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - }; - L36: memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x2 0x00000000>; - }; - L2: soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "SiFive,FU540G-soc", "fu500-soc", "sifive-soc", "simple-bus"; - ranges; - refclk: refclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <33333333>; - clock-output-names = "xtal"; - }; - prci: prci@10000000 { - /* compatible = "sifive,ux00prci0"; */ - compatible = "sifive,aloeprci0"; - reg = <0x0 0x10000000 0x0 0x1000>; - reg-names = "control"; - clocks = <&refclk>; - #clock-cells = <1>; - }; - tlclk: tlclk { - compatible = "fixed-factor-clock"; - clocks = <&prci 0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - L51: cadence-gemgxl-mgmt@100a0000 { - compatible = "sifive,cadencegemgxlmgmt0"; - reg = <0x0 0x100a0000 0x0 0x1000>; - reg-names = "control"; - #clock-cells = <0>; - }; - L35: bus-blocker@100b8000 { - compatible = "sifive,bus-blocker0"; - reg = <0x0 0x100b8000 0x0 0x1000>; - reg-names = "control"; - }; - L0: cache-controller@2010000 { - cache-block-size = <64>; - cache-level = <2>; - cache-sets = <2048>; - cache-size = <2097152>; - cache-unified; - compatible = "sifive,ccache0", "cache"; - interrupt-parent = <&L4>; - interrupts = <1 2 3>; - next-level-cache = <&L25 &L40 &L36>; - reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>; - reg-names = "control", "sideband"; - }; - L33: cadence-ddr-mgmt@100c0000 { - compatible = "sifive,cadenceddrmgmt0"; - reg = <0x0 0x100c0000 0x0 0x1000>; - reg-names = "control"; - }; - L40: chiplink@40000000 { - #address-cells = <2>; - #size-cells = <2>; - compatible = "sifive,chiplink", "simple-bus"; - ranges = <0x0 0x60000000 0x0 0x60000000 0x0 0x20000000 0x30 0x0 0x30 0x0 0x10 0x0 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000 0x20 0x0 0x20 0x0 0x10 0x0>; - }; - L5: clint@2000000 { - compatible = "riscv,clint0"; - interrupts-extended = <&L10 3 &L10 7 &L13 3 &L13 7 &L16 3 &L16 7 &L19 3 &L19 7 &L22 3 &L22 7>; - reg = <0x0 0x2000000 0x0 0x10000>; - reg-names = "control"; - }; - L6: debug-controller@0 { - compatible = "sifive,debug-013", "riscv,debug-013"; - interrupts-extended = <&L10 65535 &L13 65535 &L16 65535 &L19 65535 &L22 65535>; - reg = <0x0 0x0 0x0 0x1000>; - reg-names = "control"; - }; - L32: dma@3000000 { - #dma-cells = <1>; - compatible = "riscv,dma0"; - dma-channels = <4>; - dma-requests = <0>; - interrupt-parent = <&L4>; - interrupts = <23 24 25 26 27 28 29 30>; - reg = <0x0 0x3000000 0x0 0x100000>; - reg-names = "control"; - riscv,dma-pools = <1>; - }; - L8: dtim@1000000 { - compatible = "sifive,dtim0"; - reg = <0x0 0x1000000 0x0 0x2000>; - reg-names = "mem"; - }; - L44: ememoryotp@10070000 { - compatible = "sifive,ememoryotp0"; - reg = <0x0 0x10070000 0x0 0x1000>; - reg-names = "control"; - }; - L24: error-device@18000000 { - compatible = "sifive,error0"; - reg = <0x0 0x18000000 0x0 0x8000000>; - reg-names = "mem"; - }; - L52: ethernet@10090000 { - compatible = "cdns,macb"; - interrupt-parent = <&L4>; - interrupts = <53>; - reg = <0x0 0x10090000 0x0 0x2000>; - reg-names = "control"; - - local-mac-address = [00 00 00 00 00 00]; - phy-mode = "gmii"; - clock-names = "pclk", "hclk", "tx_clk"; - clocks = <&prci 1>, <&prci 1>, <&L51>; - - #address-cells = <1>; - #size-cells = <0>; - phy1: ethernet-phy@0 { - reg = <0>; - reset-gpios = <&L31 12 1>; - }; - }; - L31: gpio@10060000 { - compatible = "sifive,gpio0"; - interrupt-parent = <&L4>; - interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>; - reg = <0x0 0x10060000 0x0 0x1000>; - reg-names = "control"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - gpio-restart { - compatible = "gpio-restart"; - gpios = <&L31 10 1>; - }; - L47: i2c@10030000 { - compatible = "sifive,i2c0", "opencores,i2c-ocores"; - reg = <0x0 0x10030000 0x0 0x1000>; - reg-names = "control"; - clocks = <&tlclk>; - - reg-shift = <2>; - reg-io-width = <1>; - - #address-cells = <1>; - #size-cells = <0>; - - /* On pre-production boards only */ -/* - ina233-vdd_soc_core@40 { - compatible = "ti,pmbus"; - reg = <0x40>; - }; - ina233-vdd_ddr_soc@44 { - compatible = "ti,pmbus"; - reg = <0x44>; - }; - ina233-vdd_ddr_mem@45 { - compatible = "ti,pmbus"; - reg = <0x45>; - }; - ina233-vdd_corepll@47 { - compatible = "ti,pmbus"; - reg = <0x47>; - }; - ina233-vdd_otp@4a { - compatible = "ti,pmbus"; - reg = <0x4a>; - }; - ina233-vdd_io@4b { - compatible = "ti,pmbus"; - reg = <0x4b>; - }; - ina233-vdd_ddrpll@48 { - compatible = "ti,pmbus"; - reg = <0x48>; - }; - ina233-avdd_ddrpll@49 { - compatible = "ti,pmbus"; - reg = <0x49>; - }; - ina233-vdd_givdd@4c { - compatible = "ti,pmbus"; - reg = <0x4c>; - }; - ina233vdd_gemgxlpll@4d { - compatible = "ti,pmbus"; - reg = <0x4d>; - }; -*/ - /* On the tester board */ -/* - m24c02 { - compatible = "st,24c02"; - reg = <0x51>; - }; -*/ - }; - L4: interrupt-controller@c000000 { - #interrupt-cells = <1>; - compatible = "riscv,plic0"; - interrupt-controller; - interrupts-extended = <&L10 11 &L13 11 &L13 9 &L16 11 &L16 9 &L19 11 &L19 9 &L22 11 &L22 9>; - reg = <0x0 0xc000000 0x0 0x4000000>; - reg-names = "control"; - riscv,max-priority = <7>; - riscv,ndev = <53>; - }; - L7: itim@1800000 { - compatible = "sifive,itim0"; - reg = <0x0 0x1800000 0x0 0x4000>; - reg-names = "mem"; - }; - L11: itim@1808000 { - compatible = "sifive,itim0"; - reg = <0x0 0x1808000 0x0 0x8000>; - reg-names = "mem"; - }; - L14: itim@1810000 { - compatible = "sifive,itim0"; - reg = <0x0 0x1810000 0x0 0x8000>; - reg-names = "mem"; - }; - L17: itim@1818000 { - compatible = "sifive,itim0"; - reg = <0x0 0x1818000 0x0 0x8000>; - reg-names = "mem"; - }; - L20: itim@1820000 { - compatible = "sifive,itim0"; - reg = <0x0 0x1820000 0x0 0x8000>; - reg-names = "mem"; - }; - L37: memory-controller@100b0000 { - /* compatible = "sifive,ux00ddr0"; */ - compatible = "sifive,aloeddr0"; - interrupt-parent = <&L4>; - interrupts = <31>; - reg = <0x0 0x100b0000 0x0 0x4000>; - reg-names = "control"; - }; - pci@2000000000 { - #address-cells = <3>; - #interrupt-cells = <1>; - #size-cells = <2>; - compatible = "xlnx,axi-pcie-host-1.00.a"; - device_type = "pci"; - interrupt-map = <0 0 0 1 &xil_pcie_intc 1 0 0 0 2 &xil_pcie_intc 2 0 0 0 3 &xil_pcie_intc 3 0 0 0 4 &xil_pcie_intc 4>; - interrupt-map-mask = <0 0 0 7>; - interrupt-parent = <&L4>; - interrupts = <32>; - ranges = <0x2000000 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>; - reg = <0x020 0x0 0x0 0x4000000>; - reg-names = "control"; - xil_pcie_intc: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; -/* - pci@2030000000 { - #address-cells = <3>; - #interrupt-cells = <1>; - #size-cells = <2>; - compatible = "ms-pf,axi-pcie-host"; - device_type = "pci"; - bus-range = <0x01 0x7f>; - interrupt-map = <0 0 0 1 &ms_pcie_intc 1 0 0 0 2 &ms_pcie_intc 2 0 0 0 3 &ms_pcie_intc 3 0 0 0 4 &ms_pcie_intc 4>; - interrupt-map-mask = <0 0 0 7>; - interrupt-parent = <&L4>; - interrupts = <32>; - ranges = <0x2000000 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>; - reg = <0x20 0x30000000 0x0 0x4000000 0x20 0x0 0x0 0x100000>; - reg-names = "control", "apb"; - ms_pcie_intc: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; -*/ - L53: pinctrl@10080000 { - compatible = "sifive,pinctrl0"; - reg = <0x0 0x10080000 0x0 0x1000>; - reg-names = "control"; - }; - L45: pwm@10020000 { - compatible = "sifive,pwm0"; - interrupt-parent = <&L4>; - interrupts = <42 43 44 45>; - reg = <0x0 0x10020000 0x0 0x1000>; - reg-names = "control"; - clocks = <&tlclk>; - sifive,approx-period = <1000000>; - #pwm-cells = <2>; - }; - L46: pwm@10021000 { - compatible = "sifive,pwm0"; - interrupt-parent = <&L4>; - interrupts = <46 47 48 49>; - reg = <0x0 0x10021000 0x0 0x1000>; - reg-names = "control"; - clocks = <&tlclk>; - sifive,approx-period = <1000000>; - #pwm-cells = <2>; - }; - pwmleds { - compatible = "pwm-leds"; - heartbeat { - pwms = <&L45 0 0>; - max-brightness = <255>; - linux,default-trigger = "heartbeat"; - }; - mtd { - pwms = <&L45 1 0>; - max-brightness = <255>; - linux,default-trigger = "mtd"; - }; - netdev { - pwms = <&L45 2 0>; - max-brightness = <255>; - linux,default-trigger = "netdev"; - }; - panic { - pwms = <&L45 3 0>; - max-brightness = <255>; - linux,default-trigger = "panic"; - }; - /* These LEDs are on the tester board */ -/* - testled { - pwms = <&L46 0 0>; - max-brightness = <255>; - }; - green { - pwms = <&L46 1 0>; - max-brightness = <255>; - }; - red { - pwms = <&L46 2 0>; - max-brightness = <255>; - }; - blue { - pwms = <&L46 3 0>; - max-brightness = <255>; - }; -*/ - }; - L27: rom@1000 { - compatible = "sifive,modeselect0"; - reg = <0x0 0x1000 0x0 0x1000>; - reg-names = "mem"; - }; - L26: rom@10000 { - compatible = "sifive,maskrom0"; - reg = <0x0 0x10000 0x0 0x8000>; - reg-names = "mem"; - }; - L25: rom@a000000 { - compatible = "ucbbar,cacheable-zero0"; - reg = <0x0 0xa000000 0x0 0x2000000>; - reg-names = "mem"; - }; - L28: serial@10010000 { - compatible = "sifive,uart0"; - interrupt-parent = <&L4>; - interrupts = <4>; - reg = <0x0 0x10010000 0x0 0x1000>; - reg-names = "control"; - clocks = <&tlclk>; - }; - L29: serial@10011000 { - compatible = "sifive,uart0"; - interrupt-parent = <&L4>; - interrupts = <5>; - reg = <0x0 0x10011000 0x0 0x1000>; - reg-names = "control"; - clocks = <&tlclk>; - }; - L49: spi@10040000 { - compatible = "sifive,spi0"; - interrupt-parent = <&L4>; - interrupts = <51>; - reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>; - reg-names = "control", "mem"; - clocks = <&tlclk>; - - #address-cells = <1>; - #size-cells = <0>; - flash@0 { - compatible = "issi,is25wp256d", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - m25p,fast-read; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; - }; - L50: spi@10041000 { - compatible = "sifive,spi0"; - interrupt-parent = <&L4>; - interrupts = <52>; - reg = <0x0 0x10041000 0x0 0x1000 0x0 0x30000000 0x0 0x10000000>; - reg-names = "control", "mem"; - clocks = <&tlclk>; - - #address-cells = <1>; - #size-cells = <0>; - - /* These flash chips are on the tester board */ -/* - flash@0 { - compatible = "issi,is25wp032", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <25000000>; - m25p,fast-read; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; - flash@1 { - compatible = "issi,is25wp032", "jedec,spi-nor"; - reg = <1>; - spi-max-frequency = <25000000>; - m25p,fast-read; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; - flash@2 { - compatible = "issi,is25wp032", "jedec,spi-nor"; - reg = <2>; - spi-max-frequency = <25000000>; - m25p,fast-read; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; - flash@3 { - compatible = "issi,is25wp032", "jedec,spi-nor"; - reg = <3>; - spi-max-frequency = <25000000>; - m25p,fast-read; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; -*/ - }; - L30: spi@10050000 { - compatible = "sifive,spi0"; - interrupt-parent = <&L4>; - interrupts = <6>; - reg = <0x0 0x10050000 0x0 0x1000>; - reg-names = "control"; - clocks = <&tlclk>; - - #address-cells = <1>; - #size-cells = <0>; - mmc@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - spi-max-frequency = <20000000>; - voltage-ranges = <3300 3300>; - disable-wp; - gpios = <&L31 11 1>; - }; - }; - L23: teststatus@4000 { - compatible = "sifive,test0"; - reg = <0x0 0x4000 0x0 0x1000>; - reg-names = "control"; - }; - }; -}; diff --git a/src/soc/sifive/fu540/media.c b/src/mainboard/sifive/hifive-unleashed/media.c similarity index 62% rename from src/soc/sifive/fu540/media.c rename to src/mainboard/sifive/hifive-unleashed/media.c index 7b9ccb0e3c..b0198a7abe 100644 --- a/src/soc/sifive/fu540/media.c +++ b/src/mainboard/sifive/hifive-unleashed/media.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2018 Jonathan Neuschäfer + * Copyright (C) 2019 HardenedLinux * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,6 +15,7 @@ */ #include +#include /* At 0x20000000: A 256MiB long memory-mapped view of the flash at QSPI0 */ static struct mem_region_device mdev = @@ -23,3 +25,25 @@ const struct region_device *boot_device_ro(void) { return &mdev.rdev; } + +const static struct fu540_spi_mmap_config spi_mmap_config = { + .cmd_en = 1, + .addr_len = 4, + .pad_cnt = 6, + .cmd_proto = FU540_SPI_PROTO_S, + .addr_proto = FU540_SPI_PROTO_Q, + .data_proto = FU540_SPI_PROTO_Q, + .cmd_code = 0xec, + .pad_code = 0 +}; + +void boot_device_init(void) +{ + struct spi_slave slave; + + /* initialize spi controller */ + spi_setup_slave(0, 0, &slave); + + /* map flash to memory space */ + fu540_spi_mmap(&slave, &spi_mmap_config); +} diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index e43302af24..552ebd2113 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -16,7 +16,7 @@ */ #include -#include +#include #include #include #include @@ -38,7 +38,7 @@ static const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -92,7 +92,6 @@ void mainboard_romstage_entry(unsigned long bist) .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = rcba_config, - .bist = bist, }; romstage_common(&romstage_params); diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig new file mode 100644 index 0000000000..54be4e0104 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -0,0 +1,83 @@ +config BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES + def_bool n + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select SOC_INTEL_KABYLAKE + select SKYLAKE_SOC_PCH_H + select MAINBOARD_HAS_LPC_TPM + select DRIVERS_ASPEED_AST2050 + select SUPERIO_ASPEED_AST2400 + select GENERATE_SMBIOS_TABLES + select IPMI_KCS + +if BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES + +config MAINBOARD_FAMILY + string + default "Supermicro_X11_LGA1151_SERIES" + +config MAINBOARD_PART_NUMBER + string + default "X11SSH-TF" if BOARD_SUPERMICRO_X11SSH_TF + +config MAINBOARD_DIR + string + default "supermicro/x11-lga1151-series" + +config VARIANT_DIR + string + default "x11ssh-tf" if BOARD_SUPERMICRO_X11SSH_TF + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config VBOOT + select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-ro-rwab.fmd" if VBOOT_SLOTS_RW_AB + +config CBFS_SIZE + hex + default 0xb00000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 8 + +config SUBSYSTEM_VENDOR_ID + hex + default 0x8086 + +config CONSOLE_POST + bool + default y + +config POST_DEVICE + bool + default n + +config DIMM_SPD_SIZE + int + default 512 + +endif # BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name b/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name new file mode 100644 index 0000000000..ec01b135f8 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name @@ -0,0 +1,3 @@ +config BOARD_SUPERMICRO_X11SSH_TF + bool "X11SSH-TF" + select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES diff --git a/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc new file mode 100644 index 0000000000..a6d789e11c --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += bootblock.c + +ramstage-y += ramstage.c + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/supermicro/x11-lga1151-series/acpi/ec.asl b/src/mainboard/supermicro/x11-lga1151-series/acpi/ec.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/supermicro/x11-lga1151-series/acpi/mainboard.asl b/src/mainboard/supermicro/x11-lga1151-series/acpi/mainboard.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/supermicro/x11-lga1151-series/acpi/superio.asl b/src/mainboard/supermicro/x11-lga1151-series/acpi/superio.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/supermicro/x11-lga1151-series/acpi_tables.c b/src/mainboard/supermicro/x11-lga1151-series/acpi_tables.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/supermicro/x11-lga1151-series/board_info.txt b/src/mainboard/supermicro/x11-lga1151-series/board_info.txt new file mode 100644 index 0000000000..2fa11c95be --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/board_info.txt @@ -0,0 +1,2 @@ +Category: server +Vendor name: Supermicro diff --git a/src/mainboard/supermicro/x11-lga1151-series/bootblock.c b/src/mainboard/supermicro/x11-lga1151-series/bootblock.c new file mode 100644 index 0000000000..27653f5ae0 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/bootblock.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't do. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +static void early_config_superio(void) +{ + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1); + if (CONFIG(CONSOLE_SERIAL)) { + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + /* The serial output is garbeled before this timeout. + * FIXME: Find out why and remove delay. + */ + mdelay(1000); + } +} + +void bootblock_mainboard_early_init(void) +{ + early_config_gpio(); + early_config_superio(); +} diff --git a/src/mainboard/supermicro/x11-lga1151-series/cmos.layout b/src/mainboard/supermicro/x11-lga1151-series/cmos.layout new file mode 100644 index 0000000000..201ca3320c --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/cmos.layout @@ -0,0 +1,62 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name + +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level +448 128 r 0 vbnv + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb new file mode 100644 index 0000000000..a5ff0c5df0 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -0,0 +1,240 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # FSP Configuration + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "SaGv" = "SaGv_Disabled" + + # Disable SGX + register "sgx_enable" = "0" # SGX is broken in coreboot + register "PrmrrSize" = "128 * MiB" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # SATA configuration + register "SataMode" = "KBLFSP_SATA_MODE_AHCI" + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 1, \ + [5] = 1, \ + [6] = 1, \ + [7] = 1, \ + }" + + register "SataPortsDevSlp" = "{\ + [0] = 0, \ + [1] = 0, \ + [2] = 0, \ + [3] = 0, \ + [4] = 0, \ + [5] = 0, \ + [6] = 0, \ + [7] = 0, \ + }" + + # superspeed_inter-chip_supplement (SSIC) disabled + register "SsicPortEnable" = "0" + + # USB configuration + # USB2/3 + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + + # ? + register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" + + # USB4/5 + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" + + # USB0/1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + + # USB9/10 (USB3.0) + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" + + # USB6/7 (USB3.0) + register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" + + # USB8 (USB3.0) + register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" + + # IPMI USB HUB + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + + # LPC + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" + register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" + register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" + register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" + + # VR Settings Configuration for 4 Domains + # ICC_MAX = 0 (Auto) + # Voltage limit 1.52V (not used on KBL-S and KBL-DT) + # Disable PS4 powerstate in S0ix, thus no package C10 support + # psi threshold is using FSP default values + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, \ + .psi4enable = 0, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0, \ + .voltage_limit = 1520 \ + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, \ + .psi4enable = 0, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0, \ + .voltage_limit = 1520 \ + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, \ + .psi4enable = 0, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0 ,\ + .voltage_limit = 1520 \ + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, \ + .psi4enable = 0, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0, \ + .voltage_limit = 1520 \ + }" + + # No extra VR mailbox command + register "SendVrMbxCmd" = "0" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 01.0 off end # CPU PCIe Port 10 (x16) + device pci 01.1 off end # CPU PCIe Port 11 (x8) + device pci 01.2 off end # CPU PCIe Port 12 (x4) + device pci 02.0 off end # Integrated Graphics Device (IGD) + device pci 04.0 on end # SA thermal subsystem + device pci 05.0 off end # Imaging Unit + device pci 08.0 off end # Gaussion Mixture Model (GMM) + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 19.0 off end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # I2C #4 + device pci 1b.0 off end # PCH PCIe Port 17 + device pci 1b.1 off end # PCH PCIe Port 18 + device pci 1b.2 off end # PCH PCIe Port 19 + device pci 1b.3 off end # PCH PCIe Port 20 + device pci 1c.0 off end # PCH PCIe Port 1 + device pci 1c.1 off end # PCH PCIe Port 2 + device pci 1c.2 off end # PCH PCIe Port 3 + device pci 1c.3 off end # PCH PCIe Port 4 + device pci 1c.4 off end # PCH PCIe Port 5 + device pci 1c.5 off end # PCH PCIe Port 6 + device pci 1c.6 off end # PCH PCIe Port 7 + device pci 1c.7 off end # PCH PCIe Port 8 + device pci 1d.0 off end # PCH PCIe Port 9 + device pci 1d.1 off end # PCH PCIe Port 10 + device pci 1d.2 off end # PCH PCIe Port 11 + device pci 1d.3 off end # PCH PCIe Port 12 + device pci 1d.4 off end # PCH PCIe Port 13 + device pci 1d.5 off end # PCH PCIe Port 14 + device pci 1d.6 off end # PCH PCIe Port 15 + device pci 1d.7 off end # PCH PCIe Port 16 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # SPI #0 + device pci 1f.0 on # LPC Interface + chip superio/common + device pnp 2e.0 on end + end + chip drivers/pc80/tpm # TPM + device pnp 0c31.0 on end + end + end + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 off end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # SPI Controller + device pci 1f.6 off end # GbE + device pci 1f.7 off end # Intel Trace Hub + end +end diff --git a/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl new file mode 100644 index 0000000000..ac929a6bc4 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include + + // global NVS and variables + #include + + // CPU + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + } + } + + // Chipset specific sleep states + #include + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/supermicro/x11-lga1151-series/ramstage.c b/src/mainboard/supermicro/x11-lga1151-series/ramstage.c new file mode 100644 index 0000000000..694165aefc --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/ramstage.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + /* This must be one, otherwise FSP crashes ... */ + params->PchHdaVcType = 0x1; +} diff --git a/src/mainboard/supermicro/x11-lga1151-series/romstage.c b/src/mainboard/supermicro/x11-lga1151-series/romstage.c new file mode 100644 index 0000000000..cb1f1059f2 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/romstage.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + + struct spd_block blk = { + .addr_map = { 0x50, 0x51, 0x52, 0x53, }, + }; + + mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; + mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; + mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; + mem_cfg->UserBd = BOARD_TYPE_SERVER; + + mupd->FspmTestConfig.DmiVc1 = 1; +} diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/board_info.txt b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/board_info.txt new file mode 100644 index 0000000000..893ccf436c --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/board_info.txt @@ -0,0 +1,7 @@ +Category: server +Vendor name: Supermicro +Board name: X11SSH-TF +Board URL: https://www.supermicro.com/en/products/motherboard/X11SSH-TF +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h new file mode 100644 index 0000000000..a5eed6bd13 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h @@ -0,0 +1,248 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _GPIO_X11SSH_TF_H +#define _GPIO_X11SSH_TF_H + +#include +#include + +#ifndef __ACPI__ +static const struct pad_config gpio_table[] = { +/* RCIN# */ _PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x00000000), +/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000), +/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000), +/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000), +/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000), +/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000), +/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000), +/* PIRQA# */ _PAD_CFG_STRUCT(GPP_A7, 0x44000702, 0x00000000), +/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000), +/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000), +/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000), +/* PME# */ _PAD_CFG_STRUCT(GPP_A11, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A12, 0x80080201, 0x00000000), +/* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x00000000), +/* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x00000000), +/* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x00000000), +/* CLKOUT_48 */ _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A17, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A18, 0x84000100, 0x00000000), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffff00), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B0, 0x44000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B1, 0x44000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B5, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B6, 0x84000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B7, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B8, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B9, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B10, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B11, 0x44000200, 0x00000000), +/* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x00000000), +/* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x00000000), +/* SPKR */ _PAD_CFG_STRUCT(GPP_B14, 0x84000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B17, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B18, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B20, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B22, 0x44000300, 0x00000000), +/* PCHHOT# */ _PAD_CFG_STRUCT(GPP_B23, 0x40000b00, 0x00000000), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C0, 0xffffffff, 0xffffff00), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C1, 0xffffffff, 0xffffff00), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C2, 0x44000300, 0x00000000), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C3, 0xffffffff, 0xffffff00), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C4, 0xffffffff, 0xffffff00), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x00000000), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C8, 0x84000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C9, 0x84000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C10, 0x84000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C11, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C14, 0x84000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C16, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C17, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C22, 0x42040102, 0x00003000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C23, 0x84000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D0, 0x84000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D2, 0x42020102, 0x00003000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D4, 0x84000200, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D5, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D6, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D7, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D8, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D9, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D12, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D18, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D22, 0x04000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000000), +/* SATAXPCIE0 */ _PAD_CFG_STRUCT(GPP_E0, 0x44000502, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E1, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E6, 0x82020102, 0x00003000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x00000000), +/* SATA_LED# */ _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x00000000), +/* USB_OC0# */ _PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x00000000), +/* USB_OC1# */ _PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x00000000), +/* USB_OC2# */ _PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x00000000), +/* USB_OC3# */ _PAD_CFG_STRUCT(GPP_E12, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F5, 0x80100102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F6, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F7, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F8, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F9, 0x84000102, 0x00000000), +/* SATA_SCLOCK */ _PAD_CFG_STRUCT(GPP_F10, 0x44000700, 0x00000000), +/* SATA_SLOAD */ _PAD_CFG_STRUCT(GPP_F11, 0x44000700, 0x00000000), +/* SATA_SDATAOUT1 */ _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x00000000), +/* SATA_SDATAOUT2 */ _PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x00000000), +/* USB_OC4# */ _PAD_CFG_STRUCT(GPP_F15, 0x44000702, 0x00000000), +/* USB_OC5# */ _PAD_CFG_STRUCT(GPP_F16, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0x04000200, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G2, 0x44000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G3, 0x44000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G4, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G5, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G6, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G7, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G8, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G9, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G10, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G11, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G12, 0x84000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G13, 0x84000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G14, 0x84000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G15, 0x84000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G16, 0x84000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G17, 0x44000300, 0x00000000), +/* NMI# */ _PAD_CFG_STRUCT(GPP_G18, 0x44000700, 0x00000000), +/* SMI# */ _PAD_CFG_STRUCT(GPP_G19, 0x44000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G20, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G22, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G23, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H0, 0x44000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H1, 0x84000103, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H2, 0x44000201, 0x00000000), +/* SRCCLKREQ9# */ _PAD_CFG_STRUCT(GPP_H3, 0x44000602, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H4, 0x84000103, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H5, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H6, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H7, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H8, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H9, 0x84000201, 0x00000000), +/* SML2CLK */ _PAD_CFG_STRUCT(GPP_H10, 0x44000702, 0x00000000), +/* SML2DATA */ _PAD_CFG_STRUCT(GPP_H11, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H12, 0x44000300, 0x00000000), +/* SML3CLK */ _PAD_CFG_STRUCT(GPP_H13, 0x44000702, 0x00000000), +/* SML3DATA */ _PAD_CFG_STRUCT(GPP_H14, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H15, 0x44000300, 0x00000000), +/* SML4CLK */ _PAD_CFG_STRUCT(GPP_H16, 0x44000702, 0x00000000), +/* SML4DATA */ _PAD_CFG_STRUCT(GPP_H17, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H18, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H20, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H21, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H23, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD0, 0x04000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD1, 0x04000300, 0x00000000), +/* LAN_WAKE# */ _PAD_CFG_STRUCT(GPD2, 0x04000702, 0x00000000), +/* PWRBTN# */ _PAD_CFG_STRUCT(GPD3, 0x04000702, 0x00000000), +/* SLP_S3# */ _PAD_CFG_STRUCT(GPD4, 0x04000700, 0x00000000), +/* SLP_S4# */ _PAD_CFG_STRUCT(GPD5, 0x04000700, 0x00000000), +/* SLP_A# */ _PAD_CFG_STRUCT(GPD6, 0x04000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD7, 0x04000301, 0x00000000), +/* SUSCLK */ _PAD_CFG_STRUCT(GPD8, 0x04000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD9, 0x04000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD10, 0x04000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD11, 0x04000300, 0x00000000), +/* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_I0, 0x44000700, 0x00000000), +/* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_I1, 0x44000700, 0x00000000), +/* DDPD_HPD2 */ _PAD_CFG_STRUCT(GPP_I2, 0x44000700, 0x00000000), +/* DDPE_HPD3 */ _PAD_CFG_STRUCT(GPP_I3, 0x84000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_I4, 0x44000300, 0x00000000), +/* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I5, 0x44000700, 0x00000000), +/* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I6, 0x44000700, 0x00000000), +/* DDPC_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I7, 0x44000700, 0x00000000), +/* DDPC_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I8, 0x44000700, 0x00000000), +/* DDPD_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I9, 0x44000700, 0x00000000), +/* DDPD_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I10, 0x44000700, 0x00000000), +}; + + +/*** XXX TODO XXX */ +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { +/* LPC */ + +/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000), +/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000), +/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000), +/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000), +/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000), +/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000), +/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000), +/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000), +/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000), +}; + +#endif /* __ACPI__ */ +#endif /* _GPIO_X11SSH_TF_H */ diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb new file mode 100644 index 0000000000..1039f7a0ca --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -0,0 +1,103 @@ +chip soc/intel/skylake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x007c0a01" # Super IO SWC + register "gen2_dec" = "0x000c0ca1" # IPMI KCS + register "gen3_dec" = "0x000c03e1" # UART3 + register "gen4_dec" = "0x000c02e1" # UART4 + + # PCIe configuration + # Enable JPCIE1 + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "0" + + # Enable ASpeed PCI bridge + register "PcieRpEnable[2]" = "1" + register "PcieRpClkReqSupport[2]" = "0" + + # Enable X550T (10GbE) + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "0" + + # Enable M.2 + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "0" + + device domain 0 on + device pci 01.0 on end # unused + device pci 01.1 on # PCIE Slot (JPCIE1) + smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X" + end + device pci 1c.0 on # PCI Express Port 1 (Slot JPCIE1) + smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X" + end + device pci 1c.2 on # PCI Express Port 3 + device pci 00.0 on # Aspeed PCI Bridge + device pci 00.0 on end # Aspeed 2400 VGA + end + end + device pci 1c.4 on # PCI Express Port 5 + device pci 00.0 on end # 10GbE + device pci 00.1 on end # 10GbE + end + device pci 1d.0 on # PCI Express Port 9 + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" + end + device pci 1f.0 on # LPC Interface + chip drivers/ipmi + # On cold boot it takes a while for the BMC to start the IPMI service + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + device pnp ca2.0 on end # IPMI KCS + end + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # SUART2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 on # SWC + io 0x60 = 0xa00 + io 0x62 = 0xa10 + io 0x64 = 0xa20 + io 0x66 = 0xa30 + irq 0x70 = 0xb + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 0xc + end + device pnp 2e.7 on end # GPIO + device pnp 2e.b on # SUART3 + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.c on # SUART4 + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.d on end # iLPC2AHB + device pnp 2e.e on # Mailbox + io 0x60 = 0xa40 + irq 0x70 = 0x00 + end + end + end + end + end + end +end diff --git a/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd b/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd new file mode 100644 index 0000000000..a29568072e --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd @@ -0,0 +1,36 @@ +FLASH 16M { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x4ff000 + } + SI_BIOS@0x500000 0xb00000 { + RW_SECTION_A@0x0 0x33e000 { + VBLOCK_A@0x0 0x20000 + FW_MAIN_A(CBFS)@0x20000 0x31dfc0 + RW_FWID_A@0x33dfc0 0x40 + } + RW_SECTION_B@0x33e000 0x33e000 { + VBLOCK_B@0x0 0x20000 + FW_MAIN_B(CBFS)@0x20000 0x31dfc0 + RW_FWID_B@0x33dfc0 0x40 + } + MISC_RW@0x67d000 0x62000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x20000 0x2000 + SMMSTORE(PRESERVE)@0x22000 0x40000 + } + WP_RO@0x6df000 0x421000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x41d000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x32d000 + } + } + } +} diff --git a/src/mainboard/up/squared/gpio.h b/src/mainboard/up/squared/gpio.h index b4ac4e9b6d..eb3081bc54 100644 --- a/src/mainboard/up/squared/gpio.h +++ b/src/mainboard/up/squared/gpio.h @@ -342,10 +342,10 @@ static const struct pad_config gpio_table[] = { _PAD_CFG_STRUCT(GPIO_213, 0x44000201, 0x00003000), // GPIO - _PAD_CFG_STRUCT(GPIO_214, 0x44000102, 0x00000000), + _PAD_CFG_STRUCT(GPIO_214, 0x44000102, 0x00003300), // GPIO - _PAD_CFG_STRUCT(GPIO_215, 0x44000100, 0x00000000), + _PAD_CFG_STRUCT(GPIO_215, 0x44000100, 0x00003300), // *THERMTRIP_N _PAD_CFG_STRUCT(PMIC_THERMTRIP_B, 0x44000400, 0x00003000), diff --git a/src/mainboard/up/squared/romstage.c b/src/mainboard/up/squared/romstage.c index 2cfaa0064a..f9f0cfc424 100644 --- a/src/mainboard/up/squared/romstage.c +++ b/src/mainboard/up/squared/romstage.c @@ -15,11 +15,54 @@ #include #include +#include +#include #include #include #include +#include #include "gpio.h" +/* + * Offsets: + * - GPIO_214: 0xd8 + * - GPIO_215: 0xe0 + */ +static const uint8_t memory_skuid_pads[] = { GPIO_214, GPIO_215 }; + +static const struct lpddr4_sku skus[] = { + /* Samsung 280 K4F8E304HB-MGCJ 8Gb dual-ch */ + [0] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = 0, + .ch0_dual_rank = 0, + .ch1_dual_rank = 0, + .part_num = "K4F8E304HB-MGCJ", + }, + [1] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_dual_rank = 0, + .ch1_dual_rank = 0, + .part_num = "K4F8E304HB-MGCJ", + }, + [2] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_16Gb_DENSITY, + .ch1_rank_density = LP4_16Gb_DENSITY, + .ch0_dual_rank = 1, + .ch1_dual_rank = 1, + .part_num = "K4F6E304HB-MGCJ", + }, +}; + +static const struct lpddr4_cfg lp4cfg = { + .skus = skus, + .num_skus = ARRAY_SIZE(skus), +}; + static const uint8_t ch0_bit_swizzling[] = { 0x0D, 0x0A, 0x08, 0x0B, 0x0C, 0x0F, 0x0E, 0x09, 0x06, 0x00, 0x03, 0x04, 0x07, 0x01, 0x05, 0x02, @@ -48,49 +91,108 @@ static const uint8_t ch3_bit_swizzling[] = { 0x19, 0x1F, 0x1D, 0x1B, 0x1E, 0x18, 0x1C, 0x1A }; +/* + * GPIO215 GPIO214 Memory size + * 0 0 2 GiB + * 0 1 4 GiB + * 1 0 8 GiB + * 1 1 Reserved + */ +static uint8_t get_memory_skuid(void) +{ + uint8_t memory_skuid = 0; + + for (uint8_t i = 0; i < ARRAY_SIZE(memory_skuid_pads); i++) { + uint8_t rx_state = gpio_get(memory_skuid_pads[i]); + memory_skuid |= rx_state << i; + } + return memory_skuid; +} void mainboard_memory_init_params(FSPM_UPD *memupd) { printk(BIOS_DEBUG, "MAINBOARD: %s/%s called\n", __FILE__, __func__); + FSP_M_CONFIG *config = &memupd->FspmConfig; + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); - memupd->FspmConfig.Package = 0x1; // 0x0 - memupd->FspmConfig.Profile = 0xB; // 0x19 - memupd->FspmConfig.MemoryDown = 0x1; // 0x0 - memupd->FspmConfig.DDR3LPageSize = 0x0; // 0x1 - memupd->FspmConfig.DIMM0SPDAddress = 0x0; // 0xa0 - memupd->FspmConfig.DIMM1SPDAddress = 0x0; // 0xa4 - memupd->FspmConfig.RmtCheckRun = 0x3; // 0x0 - memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0xC8; // 0x0 - memupd->FspmConfig.EnhancePort8xhDecoding = 0x0; // 0x1 - memupd->FspmConfig.NpkEn = 0x0; // 0x3 - memupd->FspmConfig.PrimaryVideoAdaptor = 0x2; // 0x0 + uint8_t memory_skuid = get_memory_skuid(); + printk(BIOS_DEBUG, "MAINBOARD: Found memory SKU ID: 0x%02x\n", memory_skuid); - memupd->FspmConfig.Ch0_RankEnable = 0x1; // 0x0 - memupd->FspmConfig.Ch0_DeviceWidth = 0x1; // 0x0 - memupd->FspmConfig.Ch0_DramDensity = 0x2; // 0x0 - memupd->FspmConfig.Ch0_Option = 0x3; // 0x0 - memupd->FspmConfig.Ch1_RankEnable = 0x1; // 0x0 - memupd->FspmConfig.Ch1_DeviceWidth = 0x1; // 0x0 - memupd->FspmConfig.Ch1_DramDensity = 0x2; // 0x0 - memupd->FspmConfig.Ch1_Option = 0x3; // 0x0 - memupd->FspmConfig.Ch2_RankEnable = 0x1; // 0x0 - memupd->FspmConfig.Ch2_DeviceWidth = 0x1; // 0x0 - memupd->FspmConfig.Ch2_DramDensity = 0x2; // 0x0 - memupd->FspmConfig.Ch2_Option = 0x3; // 0x0 - memupd->FspmConfig.Ch3_RankEnable = 0x1; // 0x0 - memupd->FspmConfig.Ch3_DeviceWidth = 0x1; // 0x0 - memupd->FspmConfig.Ch3_DramDensity = 0x2; // 0x0 - memupd->FspmConfig.Ch3_Option = 0x3; // 0x0 - memupd->FspmConfig.StartTimerTickerOfPfetAssert = 0x4E20; // 0x0 + switch (memory_skuid) { + case 0: /* 2GB */ + config->DualRankSupportEnable = 0; + config->Ch0_RankEnable = 1; + config->Ch0_DramDensity = 2; + config->Ch1_RankEnable = 1; + config->Ch1_DramDensity = 2; + config->Ch2_RankEnable = 0; + config->Ch3_RankEnable = 0; + printk(BIOS_INFO, "MAINBOARD: Found supported memory: 2GB\n"); + break; + case 1: /* 4GB */ + config->DualRankSupportEnable = 1; + config->Ch0_RankEnable = 1; + config->Ch0_DramDensity = 2; + config->Ch1_RankEnable = 1; + config->Ch1_DramDensity = 2; + config->Ch2_RankEnable = 1; + config->Ch2_DramDensity = 2; + config->Ch3_RankEnable = 1; + config->Ch3_DramDensity = 2; + printk(BIOS_INFO, "MAINBOARD: Found supported memory: 4GB\n"); + break; + case 2: /* 8GB */ + config->DualRankSupportEnable = 1; + config->Ch0_RankEnable = 3; + config->Ch0_DramDensity = 2; + config->Ch1_RankEnable = 3; + config->Ch1_DramDensity = 2; + config->Ch2_RankEnable = 3; + config->Ch2_DramDensity = 2; + config->Ch3_RankEnable = 3; + config->Ch3_DramDensity = 2; + printk(BIOS_INFO, "MAINBOARD: Found supported memory: 8GB\n"); + break; + default: + printk(BIOS_INFO, "MAINBOARD: No supported memory found!\n"); + break; + } - memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &ch0_bit_swizzling, + config->Package = 0x1; // 0x0 + config->Profile = 0xB; // 0x19 + config->MemoryDown = 0x1; // 0x0 + config->DDR3LPageSize = 0x0; // 0x1 + config->DIMM0SPDAddress = 0x0; // 0xa0 + config->DIMM1SPDAddress = 0x0; // 0xa4 + config->RmtCheckRun = 0x3; // 0x0 + config->RmtMarginCheckScaleHighThreshold = 0xC8; // 0x0 + config->EnhancePort8xhDecoding = 0x0; // 0x1 + config->NpkEn = 0x0; // 0x3 + config->PrimaryVideoAdaptor = 0x2; // 0x0 + + config->Ch0_DeviceWidth = 0x1; // 0x0 + config->Ch0_Option = 0x3; // 0x0 + config->Ch1_DeviceWidth = 0x1; // 0x0 + config->Ch1_Option = 0x3; // 0x0 + config->Ch2_DeviceWidth = 0x1; // 0x0 + config->Ch2_Option = 0x3; // 0x0 + config->Ch3_DeviceWidth = 0x1; // 0x0 + config->Ch3_Option = 0x3; // 0x0 + config->StartTimerTickerOfPfetAssert = 0x4E20; // 0x0 + + memcpy(config->Ch0_Bit_swizzling, &ch0_bit_swizzling, sizeof(ch0_bit_swizzling)); - memcpy(memupd->FspmConfig.Ch1_Bit_swizzling, &ch1_bit_swizzling, + memcpy(config->Ch1_Bit_swizzling, &ch1_bit_swizzling, sizeof(ch1_bit_swizzling)); - memcpy(memupd->FspmConfig.Ch2_Bit_swizzling, &ch2_bit_swizzling, + memcpy(config->Ch2_Bit_swizzling, &ch2_bit_swizzling, sizeof(ch2_bit_swizzling)); - memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &ch3_bit_swizzling, + memcpy(config->Ch3_Bit_swizzling, &ch3_bit_swizzling, sizeof(ch3_bit_swizzling)); } + +void mainboard_save_dimm_info(void) +{ + save_lpddr4_dimm_info(&lp4cfg, get_memory_skuid()); +} diff --git a/src/mainboard/via/epia-m850/mainboard.c b/src/mainboard/via/epia-m850/mainboard.c index e7d65a0325..03699dba9f 100644 --- a/src/mainboard/via/epia-m850/mainboard.c +++ b/src/mainboard/via/epia-m850/mainboard.c @@ -16,7 +16,6 @@ #include #include -#include #include #if CONFIG(VGA_ROM_RUN) diff --git a/src/northbridge/amd/agesa/agesa_helper.h b/src/northbridge/amd/agesa/agesa_helper.h index 17819e9567..dcc336083f 100644 --- a/src/northbridge/amd/agesa/agesa_helper.h +++ b/src/northbridge/amd/agesa/agesa_helper.h @@ -17,7 +17,7 @@ #define _AGESA_HELPER_H_ #include -#include +#include enum { PICK_DMI, /* DMI Interface */ diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 290ab1647f..ab17d893bb 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -54,11 +54,7 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) { struct device *dev; struct dram_base_mask_t d; -#if defined(__PRE_RAM__) - dev = PCI_DEV(0, DEV_CDB, 1); -#else dev = __f1_dev[0]; -#endif // defined(__PRE_RAM__) u32 temp; temp = pci_read_config32(dev, 0x44); //[39:24] at [31:16] diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index a52f7ec1f0..83329a29cf 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -52,11 +52,7 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) { struct device *dev; struct dram_base_mask_t d; -#if defined(__PRE_RAM__) - dev = PCI_DEV(0, DEV_CDB, 1); -#else dev = __f1_dev[0]; -#endif // defined(__PRE_RAM__) u32 temp; temp = pci_read_config32(dev, 0x44); //[39:24] at [31:16] diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 0fbcea687c..96938b2c63 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -17,7 +17,7 @@ #ifndef AMDFAM10_H #define AMDFAM10_H -#include +#include #include #include "early_ht.h" @@ -922,13 +922,11 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #include "nums.h" -#ifdef __PRE_RAM__ #if NODE_NUMS == 64 #define NODE_PCI(x, fn) ((x < 32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) #else #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) #endif -#endif /* Include wrapper for MCT (works for DDR2 or DDR3) */ #include @@ -989,11 +987,8 @@ struct sys_info { struct DCTStatStruc DCTstatA[NODE_NUMS]; } __packed; -#ifndef __PRE_RAM__ struct device *get_node_pci(u32 nodeid, u32 fn); -#endif -#ifdef __PRE_RAM__ void showallroutes(int level, pci_devfn_t dev); void setup_resource_map_offset(const u32 *register_values, u32 max, u32 @@ -1017,8 +1012,6 @@ u32 get_sblk(void); u8 get_sbbusn(u8 sblk); void set_bios_reset(void); -#endif - #include "northbridge/amd/amdht/porting.h" BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, const u8 **List); diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c index 292049eff9..3e8c2fbeac 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_util.c +++ b/src/northbridge/amd/amdfam10/amdfam10_util.c @@ -14,15 +14,14 @@ * GNU General Public License for more details. */ -#include - #include +#include +#include +#include #include "raminit.h" #include -#ifndef __PRE_RAM__ -#include -#include +#ifndef __SIMPLE_DEVICE__ u32 Get_NB32(u32 dev, u32 reg) { return pci_read_config32(pcidev_path_on_root(PCI_DEV2DEVFN(dev)), reg); diff --git a/src/northbridge/amd/amdfam10/debug.h b/src/northbridge/amd/amdfam10/debug.h index 3710d15b77..01d87d96af 100644 --- a/src/northbridge/amd/amdfam10/debug.h +++ b/src/northbridge/amd/amdfam10/debug.h @@ -16,7 +16,7 @@ #ifndef AMDFAM10_DEBUG_H #define AMDFAM10_DEBUG_H -#include +#include #include "pci.h" void print_debug_addr(const char *str, void *val); diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c index d8784ac728..3f2b138533 100644 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ b/src/northbridge/amd/amdfam10/early_ht.c @@ -14,7 +14,7 @@ */ #include "early_ht.h" -#include +#include #include #include diff --git a/src/northbridge/amd/amdfam10/pci.h b/src/northbridge/amd/amdfam10/pci.h index 2893949135..21623c1168 100644 --- a/src/northbridge/amd/amdfam10/pci.h +++ b/src/northbridge/amd/amdfam10/pci.h @@ -16,7 +16,7 @@ #ifndef AMDFAM10_PCI_H #define AMDFAM10_PCI_H -#include +#include #include #include diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 440a02635b..a25a1510c8 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -15,7 +15,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c index 3e6a437934..735d72bbf7 100644 --- a/src/northbridge/amd/amdfam10/setup_resource_map.c +++ b/src/northbridge/amd/amdfam10/setup_resource_map.c @@ -15,7 +15,7 @@ */ #include -#include +#include #include #include #include diff --git a/src/northbridge/amd/amdfam10/util.c b/src/northbridge/amd/amdfam10/util.c index 39c2bfb4b2..ed5556ff70 100644 --- a/src/northbridge/amd/amdfam10/util.c +++ b/src/northbridge/amd/amdfam10/util.c @@ -21,11 +21,10 @@ * It can be called after RAM is set up by including amdfam10.h and enabling the * compilation of this file in src/northbridge/amd/amdfam10/Makefile.inc. */ -#ifndef __PRE_RAM__ #include #include #include -#endif + #include "amdfam10.h" /* Function 1 */ diff --git a/src/northbridge/amd/amdht/comlib.h b/src/northbridge/amd/amdht/comlib.h index dbc19f3cfa..98326b280f 100644 --- a/src/northbridge/amd/amdht/comlib.h +++ b/src/northbridge/amd/amdht/comlib.h @@ -17,7 +17,7 @@ #define COMLIB_H #include -#include +#include #include #include "porting.h" diff --git a/src/northbridge/amd/amdht/h3ncmn.h b/src/northbridge/amd/amdht/h3ncmn.h index c007089e03..db057c0f1c 100644 --- a/src/northbridge/amd/amdht/h3ncmn.h +++ b/src/northbridge/amd/amdht/h3ncmn.h @@ -17,7 +17,7 @@ #ifndef H3NCMN_H #define H3NCMN_H -#include +#include #include #include diff --git a/src/northbridge/amd/amdht/ht_wrapper.h b/src/northbridge/amd/amdht/ht_wrapper.h index 331c3df5f3..629e08f4fe 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.h +++ b/src/northbridge/amd/amdht/ht_wrapper.h @@ -18,7 +18,7 @@ #include #include -#include +#include #include "h3finit.h" void amd_ht_fixup(struct sys_info *sysinfo); diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index 14da928719..b985137987 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -22,7 +22,7 @@ #define DQS_TRAIN_DEBUG 0 -#include +#include #include #include diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h index 0b9a7d19f1..993aa21d74 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h @@ -16,7 +16,7 @@ #ifndef MCT_D_GCC_H #define MCT_D_GCC_H -#include +#include void _WRMSR(u32 addr, u32 lo, u32 hi); void _RDMSR(u32 addr, u32 *lo, u32 *hi); diff --git a/src/northbridge/amd/amdmct/mct/mctardk3.c b/src/northbridge/amd/amdmct/mct/mctardk3.c index 4eac790d5c..c36ba8ea7a 100644 --- a/src/northbridge/amd/amdmct/mct/mctardk3.c +++ b/src/northbridge/amd/amdmct/mct/mctardk3.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include "mct_d.h" static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, diff --git a/src/northbridge/amd/amdmct/mct/mctardk4.c b/src/northbridge/amd/amdmct/mct/mctardk4.c index 2e16a80002..c700593740 100644 --- a/src/northbridge/amd/amdmct/mct/mctardk4.c +++ b/src/northbridge/amd/amdmct/mct/mctardk4.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include "mct_d.h" static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 3cda13fd35..952a66f71a 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -22,7 +22,7 @@ #define DQS_TRAIN_DEBUG 0 -#include +#include #include /*=========================================================================== diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c index 82911c02d5..ccea732709 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c @@ -15,7 +15,7 @@ */ #include "mct_d_gcc.h" -#include +#include #include void _WRMSR(u32 addr, u32 lo, u32 hi) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h index f0d0f76d69..629e6e639b 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h @@ -17,7 +17,7 @@ #ifndef MCT_D_GCC_H #define MCT_D_GCC_H -#include +#include #include void _WRMSR(u32 addr, u32 lo, u32 hi); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c b/src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c index 2e5a5009d6..e8116340c4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c @@ -17,7 +17,7 @@ /* AM3/ASB2/C32/G34 DDR3 */ #include -#include +#include #include "mct_d.h" #include "mct_d_gcc.h" diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c index 55cf3a1eda..d458f3a48e 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include "mct_d.h" #include "mct_d_gcc.h" #include diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c index 716e419a5d..85e7930b24 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c @@ -20,7 +20,7 @@ * ;page size), and subtract 8. */ -#include +#include #include "mct_d.h" #include "mct_d_gcc.h" #include diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 6b31294586..d34b2dc2ba 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include @@ -1252,11 +1252,15 @@ void write_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, stop_dram_dqs_training_pattern_fam15(pMCTstat, pDCTstat, dct, Receiver); } +#define LANE_DIFF 1 + /* DQS Position Training * Algorithm detailed in the Fam15h BKDG Rev. 3.14 section 2.10.5.8.4 */ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t receiver_start, uint8_t receiver_end, uint8_t lane_start, uint8_t lane_end) + struct DCTStatStruc *pDCTstat, + uint8_t dct, uint8_t receiver_start, + uint8_t receiver_end, uint8_t lane_start) { uint8_t dimm; uint8_t lane; @@ -1276,7 +1280,8 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, uint16_t current_read_dqs_delay[MAX_BYTE_LANES]; uint16_t current_write_dqs_delay[MAX_BYTE_LANES]; uint8_t passing_dqs_delay_found[MAX_BYTE_LANES]; - uint8_t dqs_results_array[2][(lane_end - lane_start)][32][48]; /* [rank][lane][write step][read step + 16] */ + /* [rank][lane][write step][read step + 16] */ + uint8_t dqs_results_array[2][LANE_DIFF][32][48]; uint8_t last_pos = 0; uint8_t cur_count = 0; @@ -1286,6 +1291,8 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, uint32_t index_reg = 0x98; uint32_t dev = pDCTstat->dev_dct; + uint8_t lane_end = lane_start + LANE_DIFF; + uint8_t lane_count; lane_count = get_available_lane_count(pMCTstat, pDCTstat); @@ -1734,7 +1741,10 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, dct, 0); /* 2.10.5.8.3 (4 B) */ - dqs_results_array[current_phy_phase_delay[lane]] = TrainDQSRdWrPos_D_Fam15(pMCTstat, pDCTstat, dct, Receiver, Receiver + 2, lane, lane + 1); + dqs_results_array[current_phy_phase_delay[lane]] = + TrainDQSRdWrPos_D_Fam15(pMCTstat, pDCTstat, dct, + Receiver, Receiver + 2, + lane); if (dqs_results_array[current_phy_phase_delay[lane]]) lane_success_count++; @@ -1790,7 +1800,9 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, /* Update hardware registers with final values */ write_dqs_receiver_enable_control_registers(current_phy_phase_delay, dev, dct, dimm, index_reg); - TrainDQSRdWrPos_D_Fam15(pMCTstat, pDCTstat, dct, Receiver, Receiver + 2, lane, lane + 1); + TrainDQSRdWrPos_D_Fam15(pMCTstat, pDCTstat, dct, + Receiver, Receiver + 2, + lane); break; } prev = dqs_results_array[current_phy_phase_delay[lane]]; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 9aea1d79eb..4c33b9e4b6 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -15,7 +15,7 @@ */ #include -#include +#include #include #include diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c index 2038af9b6c..c821ec0628 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include +#include #include "mct_d.h" #include "mct_d_gcc.h" diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c index 57f0e96581..1ee10608b9 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c @@ -15,7 +15,7 @@ */ #include -#include +#include #include #include #include "mct_d.h" diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c index efe1e8f52a..73370e715b 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c index e878649d75..29949e02d4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include "mct_d.h" diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctprob.c b/src/northbridge/amd/amdmct/mct_ddr3/mctprob.c index 6918e9ca9d..3cb75675df 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctprob.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctprob.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include "mct_d.h" #include "mct_d_gcc.h" diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c index 8bed3b7d33..ddaaaab8d5 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include +#include #include "mct_d.h" #include "mct_d_gcc.h" diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctprod.c b/src/northbridge/amd/amdmct/mct_ddr3/mctprod.c index 76e0c5c029..b203942058 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctprod.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctprod.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include +#include #include "mct_d.h" #include "mct_d_gcc.h" diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c index d9ae58ec70..93cfb4bf1b 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c @@ -15,7 +15,7 @@ */ #include -#include +#include #include #include "mct_d.h" diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c index d75d1be036..f215695580 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c @@ -15,7 +15,7 @@ */ #include -#include +#include #include #include "mct_d.h" diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index 032152c39d..dbb989fe3d 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -20,7 +20,7 @@ ******************************************************************************/ #include -#include +#include #include #include #include diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c index 9f9fc80a76..98aadddc6c 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c @@ -15,7 +15,7 @@ */ #include -#include +#include #include "mct_d.h" #include "mct_d_gcc.h" diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c index ec9b8e4327..b6ab65e2f8 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c @@ -18,7 +18,7 @@ * Description: Max Read Latency Training feature for DDR 3 MCT */ -#include +#include #include #include #include diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c index 89edf6eee9..82523e01b8 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c @@ -15,7 +15,7 @@ */ #include -#include +#include #include #include "mct_d.h" diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c index 42f313ab92..353aa7a1cf 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -14,7 +14,8 @@ * GNU General Public License for more details. */ -#include +#include +#include #include #include @@ -31,6 +32,8 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 dimm, u8 targetAddr, uint8_t pass, uint8_t lane_count); void getWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 dimm, uint8_t pass, uint8_t nibble, uint8_t lane_count); +#define MAX_LANE_COUNT 9 + /*----------------------------------------------------------------------------- * uint8_t AgesaHwWlPhase1(SPDStruct *SPDData,MCTStruct *MCTData, DCTStruct *DCTData, * u8 Dimm, u8 Pass) @@ -185,8 +188,10 @@ uint8_t AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT lane_count = get_available_lane_count(pMCTstat, pDCTstat); + assert(lane_count <= MAX_LANE_COUNT); + if (is_fam15h()) { - int32_t gross_diff[lane_count]; + int32_t gross_diff[MAX_LANE_COUNT]; int32_t cgd = pDCTData->WLCriticalGrossDelayPrevPass; uint8_t index = (uint8_t)(lane_count * dimm); @@ -274,9 +279,11 @@ uint8_t AgesaHwWlPhase3(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT lane_count = get_available_lane_count(pMCTstat, pDCTstat); + assert(lane_count <= MAX_LANE_COUNT); + if (is_fam15h()) { uint32_t dword; - int32_t gross_diff[lane_count]; + int32_t gross_diff[MAX_LANE_COUNT]; int32_t cgd = pDCTData->WLCriticalGrossDelayPrevPass; uint8_t index = (uint8_t)(lane_count * dimm); @@ -1005,6 +1012,8 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui lane_count = get_available_lane_count(pMCTstat, pDCTstat); + assert(lane_count <= MAX_LANE_COUNT); + if (is_fam15h()) { /* MemClkFreq: 0x4: 333MHz; 0x6: 400MHz; 0xa: 533MHz; 0xe: 667MHz; 0x12: 800MHz; 0x16: 933MHz */ MemClkFreq = get_Bits(pDCTData, dct, pDCTData->NodeId, @@ -1168,8 +1177,8 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui /* From BKDG, Write Leveling Seed Value. */ if (is_fam15h()) { uint32_t RegisterDelay; - int32_t SeedTotal[lane_count]; - int32_t SeedTotalPreScaling[lane_count]; + int32_t SeedTotal[MAX_LANE_COUNT]; + int32_t SeedTotalPreScaling[MAX_LANE_COUNT]; uint32_t WrDqDqsEarly; uint8_t AddrCmdPrelaunch = 0; /* TODO: Fetch the correct value from RC2[0] */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/modtrd.c b/src/northbridge/amd/amdmct/mct_ddr3/modtrd.c index 2904cfb3ad..954dd6f2ef 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/modtrd.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/modtrd.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include "mct_d.h" #include "mct_d_gcc.h" diff --git a/src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c b/src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c index 5157a5ce8f..06bfdba84f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c @@ -16,7 +16,7 @@ /* This file contains functions for odt setting on registered DDR3 dimms */ -#include +#include #include #include "mct_d.h" diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c index ef99af8c5c..999cb94f24 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c @@ -14,7 +14,7 @@ */ #include -#include +#include #include "mct_d.h" #include "mct_d_gcc.h" diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c index 61a00562f4..0420b660b9 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c @@ -17,7 +17,7 @@ /* This file contains functions for common utility functions */ #include -#include +#include #include "mct_d.h" #include "mct_d_gcc.h" diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index d991002f5b..1fdbc169e4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include "mct_d.h" @@ -79,7 +79,7 @@ static uint32_t read_config32_dct(struct device *dev, uint8_t node, uint8_t dct, { if (is_fam15h()) { uint32_t dword; -#ifdef __PRE_RAM__ +#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); #else struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1); @@ -108,7 +108,7 @@ static void write_config32_dct(struct device *dev, uint8_t node, uint8_t dct, { if (is_fam15h()) { uint32_t dword; -#ifdef __PRE_RAM__ +#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); #else struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1); @@ -158,7 +158,7 @@ static uint32_t read_amd_dct_index_register_dct(struct device *dev, { if (is_fam15h()) { uint32_t dword; -#ifdef __PRE_RAM__ +#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); #else struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1); @@ -253,7 +253,6 @@ static struct amd_s3_persistent_data *map_s3nv_in_nvram(void) return persistent_data; } -#ifdef __PRE_RAM__ int8_t load_spd_hashes_from_nvram(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { struct amd_s3_persistent_data *persistent_data; @@ -269,14 +268,20 @@ int8_t load_spd_hashes_from_nvram(struct MCTStatStruc *pMCTstat, struct DCTStatS return 0; } -#endif -#ifdef __RAMSTAGE__ static uint64_t rdmsr_uint64_t(unsigned long index) { msr_t msr = rdmsr(index); return (((uint64_t)msr.hi) << 32) | ((uint64_t)msr.lo); } +static void wrmsr_uint64_t(unsigned long index, uint64_t value) +{ + msr_t msr; + msr.hi = (value & 0xffffffff00000000ULL) >> 32; + msr.lo = (value & 0xffffffff); + wrmsr(index, msr); +} + static uint32_t read_config32_dct_nbpstate(struct device *dev, uint8_t node, uint8_t dct, uint8_t nb_pstate, uint32_t reg) @@ -557,7 +562,7 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data *persistent_da } } } -#else + static void write_config32_dct_nbpstate(pci_devfn_t dev, uint8_t node, uint8_t dct, uint8_t nb_pstate, uint32_t reg, uint32_t value) @@ -615,15 +620,6 @@ static void write_amd_dct_index_register_dct(pci_devfn_t dev, uint8_t node, return write_amd_dct_index_register(dev, index_ctl_reg, index, value); } -#endif - -#ifdef __PRE_RAM__ -static void wrmsr_uint64_t(unsigned long index, uint64_t value) { - msr_t msr; - msr.hi = (value & 0xffffffff00000000ULL) >> 32; - msr.lo = (value & 0xffffffff); - wrmsr(index, msr); -} void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persistent_data, uint8_t training_only) { @@ -1130,9 +1126,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persiste } } } -#endif -#ifdef __RAMSTAGE__ int8_t save_mct_information_to_nvram(void) { uint8_t nvram; @@ -1206,7 +1200,6 @@ int8_t save_mct_information_to_nvram(void) return 0; } -#endif int8_t restore_mct_information_from_nvram(uint8_t training_only) { diff --git a/src/northbridge/amd/amdmct/wrappers/mcti.h b/src/northbridge/amd/amdmct/wrappers/mcti.h index 92dc0b853c..cc0e1b29b2 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti.h +++ b/src/northbridge/amd/amdmct/wrappers/mcti.h @@ -18,7 +18,7 @@ #ifndef MCTI_H #define MCTI_H -#include +#include #include #include diff --git a/src/northbridge/amd/pi/00730F01/iommu.c b/src/northbridge/amd/pi/00730F01/iommu.c index 1ff4cfbbc9..5ff631c405 100644 --- a/src/northbridge/amd/pi/00730F01/iommu.c +++ b/src/northbridge/amd/pi/00730F01/iommu.c @@ -16,7 +16,6 @@ #include #include #include -#include #include static void iommu_read_resources(struct device *dev) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 377d91eeae..ba17c614e5 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -491,11 +491,6 @@ static void add_ivrs_device_entries(struct device *parent, struct device *dev, unsigned int header_type; unsigned int is_pcie; - if (!root_level) { - root_level = malloc(sizeof(int8_t)); - *root_level = -1; - } - if (dev->path.type == DEVICE_PATH_PCI) { if ((dev->bus->secondary == 0x0) && @@ -536,8 +531,6 @@ static void add_ivrs_device_entries(struct device *parent, struct device *dev, sibling->sibling) add_ivrs_device_entries(dev, sibling, depth + 1, depth, root_level, current, length); - - free(root_level); } unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) @@ -643,7 +636,8 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) current += 8; /* Describe PCI devices */ - add_ivrs_device_entries(NULL, all_devices, 0, -1, NULL, ¤t, + int8_t root_level = -1; + add_ivrs_device_entries(NULL, all_devices, 0, -1, &root_level, ¤t, &ivrs->ivhd.length); /* Describe IOAPICs */ diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 1563216ba1..e3bfd90fd8 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -248,13 +248,15 @@ AGESA_STATUS agesawrapper_amdinitmid(void) return status; } -#ifndef __PRE_RAM__ AGESA_STATUS agesawrapper_amdinitlate(void) { AGESA_STATUS Status; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_LATE_PARAMS *AmdLateParams; + if (!ENV_RAMSTAGE) + return AGESA_UNSUPPORTED; + LibAmdMemFill (&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), @@ -289,7 +291,6 @@ AGESA_STATUS agesawrapper_amdinitlate(void) /* No AmdReleaseStruct(&AmdParamStruct), we need AmdLateParams later. */ return Status; } -#endif /* #ifndef __PRE_RAM__ */ const void *agesawrapper_locate_module (const CHAR8 name[8]) { diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig index a774c0e8f5..1b01653a28 100644 --- a/src/northbridge/intel/e7505/Kconfig +++ b/src/northbridge/intel/e7505/Kconfig @@ -22,6 +22,5 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP - select POSTCAR_STAGE endif diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index b954c6af74..11af6e334f 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -15,10 +15,9 @@ #define __SIMPLE_DEVICE__ #include -#include +#include #include #include -#include #include #include #include "e7505.h" @@ -43,17 +42,10 @@ void northbridge_write_smram(u8 smram) pci_write_config8(mch, SMRAMC, smram); } -/* platform_enter_postcar() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use, - * and continues execution in postcar stage. */ -void platform_enter_postcar(void) +void fill_postcar_frame(struct postcar_frame *pcf) { - struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - /* * Choose to NOT set ROM as WP cacheable here. * Timestamps indicate the CPU this northbridge code is @@ -61,15 +53,13 @@ void platform_enter_postcar(void) * operations when source is left as UC. */ + pcf->skip_common_mtrr = 1; + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); /* Cache CBMEM region as WB. */ top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, + postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); - - run_postcar_phase(&pcf); - - /* We do not return here. */ } diff --git a/src/northbridge/intel/fsp_rangeley/Makefile.inc b/src/northbridge/intel/fsp_rangeley/Makefile.inc index a2f80546d7..a167c2369e 100644 --- a/src/northbridge/intel/fsp_rangeley/Makefile.inc +++ b/src/northbridge/intel/fsp_rangeley/Makefile.inc @@ -27,8 +27,6 @@ romstage-y += memmap.c romstage-y += ../../../arch/x86/walkcbfs.S romstage-y += port_access.c -smm-y += udelay.c - CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR) CPPFLAGS_common += -I$(src)/northbridge/intel/fsp_rangeley/ diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index 04a696c2c2..43e71f4d3d 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -26,12 +26,6 @@ #include #include "../chip.h" -#ifdef __PRE_RAM__ -#include -#endif - -#ifdef __PRE_RAM__ - /* Copy the default UPD region and settings to a buffer for modification */ static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData) @@ -96,9 +90,9 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) if (config->MrcRmtCpgcNumBursts) { UpdData->PcdMrcRmtCpgcNumBursts = config->MrcRmtCpgcNumBursts; } -#if CONFIG(ENABLE_FSP_FAST_BOOT) - UpdData->PcdFastboot = UPD_ENABLE; -#endif + if (CONFIG(ENABLE_FSP_FAST_BOOT)) + UpdData->PcdFastboot = UPD_ENABLE; + /* * Loop through all the SOC devices in the devicetree * enabling and disabling them as requested. @@ -164,5 +158,3 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, return; } - -#endif /* __PRE_RAM__ */ diff --git a/src/northbridge/intel/fsp_rangeley/udelay.c b/src/northbridge/intel/fsp_rangeley/udelay.c deleted file mode 100644 index 08301a37f6..0000000000 --- a/src/northbridge/intel/fsp_rangeley/udelay.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#define MSR_PLATFORM_INFO 0xce - -/** - * Intel Rangeley CPUs always run the TSC at BCLK = 100MHz - */ - -/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. - * This code is used to prevent use of libgcc's umoddi3. - */ -static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) -{ - tsc->lo = (a & 0xffff) * (b & 0xffff); - tsc->hi = ((tsc->lo >> 16) - + ((a & 0xffff) * (b >> 16)) - + ((b & 0xffff) * (a >> 16))); - tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); - tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); -} - -void udelay(u32 us) -{ - u32 dword; - tsc_t tsc, tsc1, tscd; - msr_t msr; - u32 fsb = 100, divisor; - u32 d; /* ticks per us */ - - msr = rdmsr(MSR_PLATFORM_INFO); - divisor = (msr.lo >> 8) & 0xff; - - d = fsb * divisor; - multiply_to_tsc(&tscd, us, d); - - tsc1 = rdtsc(); - dword = tsc1.lo + tscd.lo; - if ((dword < tsc1.lo) || (dword < tscd.lo)) { - tsc1.hi++; - } - tsc1.lo = dword; - tsc1.hi += tscd.hi; - - do { - tsc = rdtsc(); - } while ((tsc.hi < tsc1.hi) - || ((tsc.hi == tsc1.hi) && (tsc.lo <= tsc1.lo))); -} diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 576ae475d1..3042741370 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -21,13 +21,10 @@ if NORTHBRIDGE_INTEL_GM45 config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y select HAVE_DEBUG_RAM_SETUP - select LAPIC_MONOTONIC_TIMER select VGA select INTEL_EDID select INTEL_GMA_ACPI select INTEL_GMA_SSC_ALTERNATE_REF - select POSTCAR_STAGE - select POSTCAR_CONSOLE select PARALLEL_MP config CBFS_SIZE diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc index 0ab1c94a27..3742cfcf7c 100644 --- a/src/northbridge/intel/gm45/Makefile.inc +++ b/src/northbridge/intel/gm45/Makefile.inc @@ -35,8 +35,6 @@ ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += gma.c -smm-y += ../../../cpu/x86/lapic/apic_timer.c - postcar-y += memmap.c endif diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c index decf712302..ef152db213 100644 --- a/src/northbridge/intel/gm45/acpi.c +++ b/src/northbridge/intel/gm45/acpi.c @@ -69,9 +69,14 @@ unsigned long acpi_fill_mcfg(unsigned long current) static unsigned long acpi_fill_dmar(unsigned long current) { - int me_active = (pcidev_on_root(3, 0) != NULL) && - (pci_read_config8(pcidev_on_root(3, 0), PCI_CLASS_REVISION) != - 0xff); + const struct device *dev; + + dev = pcidev_on_root(3, 0); + int me_active = dev && dev->enabled; + + dev = pcidev_on_root(2, 0); + int igd_active = dev && dev->enabled; + int stepping = pci_read_config8(pcidev_on_root(0, 0), PCI_CLASS_REVISION); @@ -80,7 +85,7 @@ static unsigned long acpi_fill_dmar(unsigned long current) current += acpi_create_dmar_ds_pci(current, 0, 0x1b, 0); acpi_dmar_drhd_fixup(tmp, current); - if (stepping != STEPPING_B2) { + if (stepping != STEPPING_B2 && igd_active) { tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE2); current += acpi_create_dmar_ds_pci(current, 0, 0x2, 0); diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index 6795f7a61f..7479a7834a 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -18,16 +18,15 @@ #define __SIMPLE_DEVICE__ #include -#include +#include #include #include #include -#include #include +#include #include #include -#include -#include +#include #include "gm45.h" /* @@ -85,7 +84,7 @@ u32 decode_tseg_size(u8 esmramc) } } -u32 northbridge_get_tseg_base(void) +static uintptr_t northbridge_get_tseg_base(void) { const pci_devfn_t dev = PCI_DEV(0, 0, 0); @@ -108,7 +107,7 @@ u32 northbridge_get_tseg_base(void) return tor; } -u32 northbridge_get_tseg_size(void) +static size_t northbridge_get_tseg_size(void) { const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); return decode_tseg_size(esmramc) << 10; @@ -124,43 +123,23 @@ void *cbmem_top(void) return (void *) top_of_ram; } -void stage_cache_external_region(void **base, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - /* The stage cache lives at the end of the TSEG region. - * The top of RAM is defined to be the TSEG base address. - */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)((uintptr_t)northbridge_get_tseg_base() - + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); + *start = northbridge_get_tseg_base(); + *size = northbridge_get_tseg_size(); } -/* platform_enter_postcar() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use, - * and continues execution in postcar stage. */ -void platform_enter_postcar(void) +void fill_postcar_frame(struct postcar_frame *pcf) { - struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - /* Cache 8 MiB region below the top of ram and 2 MiB above top of * ram to cover both cbmem as the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, + postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), + postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); - run_postcar_phase(&pcf); - - /* We do not return here. */ } diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index f011cce8d7..384d98a54e 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -23,7 +23,7 @@ #include #include #include -#include +#include #include "chip.h" #include "gm45.h" @@ -240,17 +240,11 @@ static struct device_operations pci_domain_ops = { .acpi_name = northbridge_acpi_name, }; - -static void cpu_bus_init(struct device *dev) -{ - bsp_init_and_start_aps(dev->link_list); -} - static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, - .init = cpu_bus_init, + .init = mp_cpu_bus_init, .scan_bus = 0, }; diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index b7ccdecdad..7a30b761c5 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1799,7 +1799,8 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) /* Perform ZQ calibration for DDR3. */ - ddr3_calibrate_zq(); + if (sysinfo->spd_type == DDR3) + ddr3_calibrate_zq(); /* Perform receive-enable calibration. */ raminit_receive_enable_calibration(timings, dimms); diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index 38f2d5f68f..c853a3a1f4 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -21,8 +21,7 @@ #include #include #include -#include -#include +#include #include #include #include @@ -47,7 +46,7 @@ void __weak mb_post_raminit_setup(void) /* Platform has no romstage entry point under mainboard directory, * so this one is named with prefix mainboard. */ -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { sysinfo_t sysinfo; int s3resume = 0; @@ -57,8 +56,7 @@ void mainboard_romstage_entry(unsigned long bist) /* basic northbridge setup, including MMCONF BAR */ gm45_early_init(); - if (bist == 0) - enable_lapic(); + enable_lapic(); /* First, run everything needed for console output. */ i82801ix_early_init(); @@ -69,7 +67,6 @@ void mainboard_romstage_entry(unsigned long bist) mb_setup_superio(); console_init(); - report_bist_failure(bist); reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3); pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16); diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index dbf91bf60d..aad2674241 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -19,8 +19,6 @@ config NORTHBRIDGE_INTEL_HASWELL select CACHE_MRC_SETTINGS select INTEL_DDI select INTEL_GMA_ACPI - select POSTCAR_STAGE - select POSTCAR_CONSOLE select C_ENVIRONMENT_BOOTBLOCK select BOOTBLOCK_CONSOLE diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index fdabc3fc9a..506aaa58e8 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -45,6 +45,4 @@ struct northbridge_intel_haswell_config { struct i915_gpu_controller_info gfx; }; -extern struct chip_operations northbridge_intel_haswell_ops; - #endif /* NORTHBRIDGE_INTEL_HASWELL_CHIP_H */ diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 6fef0da7c1..606c9c742d 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -20,7 +20,7 @@ #include #include #include -#include + #include "haswell.h" static bool peg_hidden[3]; diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index dc0e5db8e3..55c0b4b24b 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -208,12 +208,6 @@ #ifndef __ASSEMBLER__ static inline void barrier(void) { asm("" ::: "memory"); } -struct ied_header { - char signature[10]; - u32 size; - u8 reserved[34]; -} __packed; - #ifdef __SMM__ void intel_northbridge_haswell_finalize_smm(void); #else /* !__SMM__ */ diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index 3a63afcde6..b1eb770f90 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -16,9 +16,13 @@ // Use simple device model for this file even in ramstage #define __SIMPLE_DEVICE__ +#include +#include +#include +#include +#include #include #include -#include #include "haswell.h" static uintptr_t smm_region_start(void) @@ -36,15 +40,21 @@ void *cbmem_top(void) return (void *)smm_region_start(); } -/* Region of SMM space is reserved for multipurpose use. It falls below - * the IED region and above the SMM handler. */ -#define RESERVED_SMM_OFFSET \ - (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE) - -void stage_cache_external_region(void **base, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); + *start = smm_region_start(); + *size = CONFIG_SMM_TSEG_SIZE; +} + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + + /* Cache at least 8 MiB below the top of ram, and at most 8 MiB + * above top of the ram. This satisfies MTRR alignment requirement + * with different TSEG size configurations. + */ + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, + MTRR_TYPE_WRBACK); } diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 2fd5959ee0..c047c39ea7 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -525,16 +525,11 @@ static const struct pci_driver mc_driver_hsw __pci_driver = { .devices = mc_pci_device_ids, }; -static void cpu_bus_init(struct device *dev) -{ - bsp_init_and_start_aps(dev->link_list); -} - static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, - .init = cpu_bus_init, + .init = mp_cpu_bus_init, .scan_bus = 0, }; diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 0fdc2a3ce4..45cdd9c7f1 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -18,7 +18,6 @@ config NORTHBRIDGE_INTEL_I440BX select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select UDELAY_IO - select POSTCAR_STAGE config SDRAMPWR_4DIMM bool diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c index 495ca8682a..6c540a512a 100644 --- a/src/northbridge/intel/i440bx/memmap.c +++ b/src/northbridge/intel/i440bx/memmap.c @@ -15,12 +15,11 @@ #define __SIMPLE_DEVICE__ -#include +#include #include #include #include #include -#include #include #include #include "i440bx.h" @@ -68,27 +67,13 @@ void *cbmem_top(void) return (void *)tom; } -/* platform_enter_postcar() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use, - * and continues execution in postcar stage. */ -void platform_enter_postcar(void) +void fill_postcar_frame(struct postcar_frame *pcf) { - struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - /* Cache CBMEM region as WB. */ top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, + postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); - run_postcar_phase(&pcf); } diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 1a4d8875e9..0159bf2fde 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -21,14 +21,11 @@ if NORTHBRIDGE_INTEL_I945 config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y select HAVE_DEBUG_RAM_SETUP - select LAPIC_MONOTONIC_TIMER select VGA select INTEL_GMA_ACPI select INTEL_GMA_SSC_ALTERNATE_REF select INTEL_EDID select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT - select POSTCAR_STAGE - select POSTCAR_CONSOLE select PARALLEL_MP config NORTHBRIDGE_INTEL_SUBTYPE_I945GC diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index 47b4c5166b..af3c23580c 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -27,8 +27,6 @@ romstage-y += errata.c romstage-y += debug.c romstage-y += rcven.c -smm-y += udelay.c - postcar-y += memmap.c endif diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index ac1499e0fc..8207d06a55 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -17,16 +17,15 @@ #define __SIMPLE_DEVICE__ #include -#include +#include #include #include "i945.h" #include -#include #include +#include #include -#include +#include #include -#include /* Decodes TSEG region size to bytes. */ u32 decode_tseg_size(const u8 esmramc) @@ -46,7 +45,7 @@ u32 decode_tseg_size(const u8 esmramc) } } -u32 northbridge_get_tseg_base(void) +static uintptr_t northbridge_get_tseg_base(void) { uintptr_t tom; @@ -61,7 +60,7 @@ u32 northbridge_get_tseg_base(void) return tom; } -u32 northbridge_get_tseg_size(void) +static size_t northbridge_get_tseg_size(void) { const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); return decode_tseg_size(esmramc); @@ -90,43 +89,23 @@ u32 decode_igd_memory_size(const u32 gms) return ggc2uma[gms] << 10; } -void stage_cache_external_region(void **base, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - /* The stage cache lives at the end of the TSEG region. - * The top of RAM is defined to be the TSEG base address. - */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)((uintptr_t)northbridge_get_tseg_base() - + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); + *start = northbridge_get_tseg_base(); + *size = northbridge_get_tseg_size(); } -/* platform_enter_postcar() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use, - * and continues execution in postcar stage. */ -void platform_enter_postcar(void) +void fill_postcar_frame(struct postcar_frame *pcf) { - struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - /* Cache 8 MiB region below the top of ram and 2 MiB above top of * ram to cover both cbmem as the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, + postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), + postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); - run_postcar_phase(&pcf); - - /* We do not return here. */ } diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index e9867d988e..dde1b110f4 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -21,9 +21,8 @@ #include #include #include -#include #include -#include +#include #include "i945.h" static int get_pcie_bar(u32 *base) @@ -215,16 +214,11 @@ static const struct pci_driver mc_driver __pci_driver = { .devices = pci_device_ids, }; -static void cpu_bus_init(struct device *dev) -{ - bsp_init_and_start_aps(dev->link_list); -} - static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, - .init = cpu_bus_init, + .init = mp_cpu_bus_init, .scan_bus = 0, }; diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index dd9843300f..709677469f 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c deleted file mode 100644 index 8447453435..0000000000 --- a/src/northbridge/intel/i945/udelay.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -/** - * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock - */ - -void udelay(u32 us) -{ - u32 dword; - tsc_t tsc, tsc1, tscd; - msr_t msr; - u32 fsb = 0, divisor; - u32 d; /* ticks per us */ - - msr = rdmsr(MSR_FSB_FREQ); - switch (msr.lo & 0x07) { - case 5: - fsb = 400; - break; - case 1: - fsb = 533; - break; - case 3: - fsb = 667; - break; - case 2: - fsb = 800; - break; - case 0: - fsb = 1067; - break; - case 4: - fsb = 1333; - break; - case 6: - fsb = 1600; - break; - } - - msr = rdmsr(IA32_PERF_STATUS); - divisor = (msr.hi >> 8) & 0x1f; - - d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */ - - multiply_to_tsc(&tscd, us, d); - - tsc1 = rdtsc(); - dword = tsc1.lo + tscd.lo; - if ((dword < tsc1.lo) || (dword < tscd.lo)) - tsc1.hi++; - tsc1.lo = dword; - tsc1.hi += tscd.hi; - - do { - tsc = rdtsc(); - } while ((tsc.hi < tsc1.hi) - || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); -} diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 02b6e80832..3adf6987bf 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -20,12 +20,14 @@ config NORTHBRIDGE_INTEL_NEHALEM select INTEL_EDID select INTEL_GMA_ACPI select CACHE_MRC_SETTINGS - select POSTCAR_STAGE - select POSTCAR_CONSOLE select HAVE_DEBUG_RAM_SETUP if NORTHBRIDGE_INTEL_NEHALEM +config VBOOT + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_ROMSTAGE + config MMCONF_BUS_NUMBER int default 256 @@ -54,4 +56,8 @@ config MRC_CACHE_SIZE hex default 0x10000 +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + endif diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc index 52374acee8..ebb7b8be03 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/nehalem/Makefile.inc @@ -24,6 +24,7 @@ ramstage-y += acpi.c romstage-y += memmap.c romstage-y += raminit.c +romstage-y += raminit_tables.c romstage-y += early_init.c romstage-y += ../../../arch/x86/walkcbfs.S diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c index a5cac7b19a..5bdb5d5e0a 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/nehalem/early_init.c @@ -73,22 +73,7 @@ static void nehalem_setup_bars(void) pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(5), 0x33); pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(6), 0x33); -#if CONFIG(ELOG_BOOT_COUNT) - /* Increment Boot Counter for non-S3 resume */ - if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && - ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) - boot_count_increment(); -#endif - printk(BIOS_DEBUG, " done.\n"); - -#if CONFIG(ELOG_BOOT_COUNT) - /* Increment Boot Counter except when resuming from S3 */ - if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && - ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) - return; - boot_count_increment(); -#endif } static void early_cpu_init (void) @@ -134,6 +119,7 @@ void nehalem_early_initialization(int chipset_type) { u32 capid0_a; u8 reg8; + int s3_resume; /* Device ID Override Enable should be done very early */ capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); @@ -150,6 +136,11 @@ void nehalem_early_initialization(int chipset_type) /* Setup all BARs required for early PCIe and raminit */ nehalem_setup_bars(); + s3_resume = (inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && + (((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3); + + elog_boot_notify(s3_resume); + /* Device Enable */ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, DEVEN_IGD | DEVEN_PEG10 | DEVEN_HOST); @@ -161,7 +152,7 @@ void nehalem_early_initialization(int chipset_type) PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* Magic for S3 resume. Must be done early. */ - if (((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) { + if (s3_resume) { MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~1) | 6; MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~3) | 4; } diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/nehalem/finalize.c index 97f6011ba4..33892491b5 100644 --- a/src/northbridge/intel/nehalem/finalize.c +++ b/src/northbridge/intel/nehalem/finalize.c @@ -15,7 +15,6 @@ */ #include -#include #include "nehalem.h" #define PCI_DEV_SNB PCI_DEV(0, 0, 0) diff --git a/src/northbridge/intel/nehalem/memmap.c b/src/northbridge/intel/nehalem/memmap.c index ec036c9d7c..fd10542832 100644 --- a/src/northbridge/intel/nehalem/memmap.c +++ b/src/northbridge/intel/nehalem/memmap.c @@ -16,15 +16,14 @@ #define __SIMPLE_DEVICE__ -#include +#include #include #include #include -#include #include +#include #include -#include -#include +#include #include "nehalem.h" static uintptr_t smm_region_start(void) @@ -34,12 +33,12 @@ static uintptr_t smm_region_start(void) return tom; } -u32 northbridge_get_tseg_base(void) +static uintptr_t northbridge_get_tseg_base(void) { - return (u32)smm_region_start(); + return smm_region_start(); } -u32 northbridge_get_tseg_size(void) +static size_t northbridge_get_tseg_size(void) { return CONFIG_SMM_TSEG_SIZE; } @@ -49,41 +48,21 @@ void *cbmem_top(void) return (void *) smm_region_start(); } -void stage_cache_external_region(void **base, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - /* The stage cache lives at the end of TSEG region. - * The top of RAM is defined to be the TSEG base address. */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)((uintptr_t)northbridge_get_tseg_base() + - northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); + *start = northbridge_get_tseg_base(); + *size = northbridge_get_tseg_size(); } -/* platform_enter_postcar() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use, - * and continues execution in postcar stage. */ -void platform_enter_postcar(void) +void fill_postcar_frame(struct postcar_frame *pcf) { - struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); - - run_postcar_phase(&pcf); - - /* We do not return here. */ + postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); } diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index a058d3fa26..4ab89ad054 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -29,7 +29,7 @@ #include #include "chip.h" #include "nehalem.h" -#include +#include static int bridge_revision_id = -1; @@ -297,16 +297,11 @@ static const struct pci_driver mc_driver_44 __pci_driver = { .device = 0x0044, /* Nehalem */ }; -static void cpu_bus_init(struct device *dev) -{ - bsp_init_and_start_aps(dev->link_list); -} - static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, - .init = cpu_bus_init, + .init = mp_cpu_bus_init, .scan_bus = 0, }; diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index fadf0e0801..b9d407a58e 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -42,6 +42,7 @@ #include "chip.h" #include "nehalem.h" #include "raminit.h" +#include "raminit_tables.h" #define NORTHBRIDGE PCI_DEV(0, 0, 0) #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) @@ -357,8 +358,6 @@ const int cached_config = 0; #define RANK_SHIFT 28 #define CHANNEL_SHIFT 10 -#include "raminit_tables.c" - static void seq9(struct raminfo *info, int channel, int slot, int rank) { int i, lane; diff --git a/src/northbridge/intel/nehalem/raminit_tables.c b/src/northbridge/intel/nehalem/raminit_tables.c index 5c5d46f54a..1bd73305ea 100644 --- a/src/northbridge/intel/nehalem/raminit_tables.c +++ b/src/northbridge/intel/nehalem/raminit_tables.c @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +#include "raminit_tables.h" + /* [CHANNEL][EXT_REVISON][LANE][2*SLOT+RANK][CLOCK_SPEED] */ const u8 u8_FFFD1240[2][5][9][4][4] = { { @@ -617,46 +619,30 @@ const u16 u16_ffd1188[2][9][4] = { const u8 u8_FFFD1891[2][2][4][12] = { { { - {0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00}, - {0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00}, - {0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00}, - {0x08, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, - 0x00}, + {0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x08, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00}, }, { - {0x04, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, - 0x00}, - {0x05, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, - 0x00}, - {0x07, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, - 0x00}, - {0x08, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, - 0x00}, + {0x04, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x05, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x07, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x08, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00}, } }, { { - {0x06, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, - 0x00}, - {0x08, 0x00, 0x00, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00, 0x00, 0x00, - 0x00}, - {0x0a, 0x00, 0x00, 0x0c, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, - 0x00}, - {0x0c, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, - 0x00}, + {0x06, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x08, 0x00, 0x00, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x0a, 0x00, 0x00, 0x0c, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x0c, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00}, }, { - {0x06, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, - 0x00}, - {0x08, 0x00, 0x00, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00, 0x00, 0x00, - 0x00}, - {0x0a, 0x00, 0x00, 0x0c, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, - 0x00}, - {0x0c, 0x00, 0x00, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x74} + {0x06, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x08, 0x00, 0x00, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x0a, 0x00, 0x00, 0x0c, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x0c, 0x00, 0x00, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x74} } } }; diff --git a/src/northbridge/intel/nehalem/raminit_tables.h b/src/northbridge/intel/nehalem/raminit_tables.h new file mode 100644 index 0000000000..d912d6b18a --- /dev/null +++ b/src/northbridge/intel/nehalem/raminit_tables.h @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Vladimir Serbinenko. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef RAMINIT_TABLES_H +#define RAMINIT_TABLES_H + +#include + +/* [CHANNEL][EXT_REVISON][LANE][2*SLOT+RANK][CLOCK_SPEED] */ +extern const u8 u8_FFFD1240[2][5][9][4][4]; + +extern const u16 u16_FFFE0EB8[2][4]; + +/* [CARD][LANE][CLOCK_SPEED] */ +extern const u16 u16_ffd1188[2][9][4]; + +/* [REVISION][CHANNEL][CLOCK_INDEX][?] */ +extern const u8 u8_FFFD1891[2][2][4][12]; + +extern const u8 u8_FFFD17E0[2][5][4][4]; + +extern const u8 u8_FFFD0C78[2][5][4][2][2][4]; + +extern const u16 u16_fffd0c68[3]; + +extern const u16 u16_fffd0c70[2][2]; + +extern const u16 u16_fffd0c50[3][2][2]; + +/* [CLOCK_INDEX] */ +extern const u16 min_cycletime[4]; + +/* [CLOCK_INDEX] */ +extern const u16 min_cas_latency_time[4]; + +/* [CHANNEL][EXT_SILICON_REVISION][?][CLOCK_INDEX] */ +/* On other mobos may also depend on slot and rank. */ +extern const u8 u8_FFFD0EF8[2][5][4][4]; + +/* [CLOCK_SPEED] */ +extern const u8 u8_FFFD1218[4]; + +extern const u8 reg178_min[]; +extern const u8 reg178_max[]; +extern const u8 reg178_step[]; + +extern const u16 u16_ffd1178[2][4]; + +extern const u16 u16_fe0eb8[2][4]; + +extern const u8 lut16[4]; + +#endif // RAMINIT_TABLES_H diff --git a/src/northbridge/intel/nehalem/smi.c b/src/northbridge/intel/nehalem/smi.c index 5bfc934e04..8c19852043 100644 --- a/src/northbridge/intel/nehalem/smi.c +++ b/src/northbridge/intel/nehalem/smi.c @@ -19,7 +19,7 @@ #include #include "nehalem.h" -#include +#include void northbridge_write_smram(u8 smram) { diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 8acfaf8fec..d1d776b2a5 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -22,14 +22,11 @@ if NORTHBRIDGE_INTEL_PINEVIEW config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y select HAVE_DEBUG_RAM_SETUP - select LAPIC_MONOTONIC_TIMER select VGA select MAINBOARD_HAS_NATIVE_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_GMA_ACPI - select POSTCAR_STAGE - select POSTCAR_CONSOLE select PARALLEL_MP select C_ENVIRONMENT_BOOTBLOCK diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index 2f3ff6e921..b4fef6bc76 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -16,7 +16,7 @@ #define __SIMPLE_DEVICE__ -#include +#include #include #include #include @@ -24,10 +24,9 @@ #include #include #include -#include -#include +#include +#include #include -#include u8 decode_pciebar(u32 *const base, u32 *const len) { @@ -117,13 +116,13 @@ static u32 decode_tseg_size(const u32 esmramc) } } -u32 northbridge_get_tseg_size(void) +static size_t northbridge_get_tseg_size(void) { const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); return decode_tseg_size(esmramc); } -u32 northbridge_get_tseg_base(void) +static uintptr_t northbridge_get_tseg_base(void) { return pci_read_config32(PCI_DEV(0, 0, 0), TSEG); } @@ -140,43 +139,22 @@ void *cbmem_top(void) } -void stage_cache_external_region(void **base, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - /* The stage cache lives at the end of the TSEG region. - * The top of RAM is defined to be the TSEG base address. - */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)((uintptr_t)northbridge_get_tseg_base() - + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); + *start = northbridge_get_tseg_base(); + *size = northbridge_get_tseg_size(); } -/* platform_enter_postcar() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use, - * and continues execution in postcar stage. */ -void platform_enter_postcar(void) +void fill_postcar_frame(struct postcar_frame *pcf) { - struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - /* Cache 8 MiB region below the top of ram and 2 MiB above top of * ram to cover both cbmem as the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, + postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), + postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); - - run_postcar_phase(&pcf); - - /* We do not return here. */ } diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 4b67cfdefd..34cb583c49 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include /* Reserve everything between A segment and 1MB: * @@ -195,19 +195,13 @@ static struct device_operations pci_domain_ops = { .acpi_name = northbridge_acpi_name, }; -static void cpu_bus_init(struct device *dev) -{ - bsp_init_and_start_aps(dev->link_list); -} - static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, - .init = cpu_bus_init, + .init = mp_cpu_bus_init, }; - static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 8d7de45149..e60738ced5 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -26,8 +26,7 @@ #include #include #include -#include -#include +#include #include #include "raminit.h" #include "pineview.h" @@ -48,14 +47,13 @@ __weak void mb_pirq_setup(void) #define LPC_DEV PCI_DEV(0x0, 0x1f, 0x0) -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { u8 spd_addrmap[4] = {}; int boot_path, cbmem_was_initted; int s3resume = 0; - if (bist == 0) - enable_lapic(); + enable_lapic(); /* Enable GPIOs */ pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); @@ -63,9 +61,6 @@ void mainboard_romstage_entry(unsigned long bist) setup_pch_gpios(&mainboard_gpio_map); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - enable_smbus(); /* Perform some early chipset initialization required diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 53725cafb4..64ce4d82d9 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -20,8 +20,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE select CPU_INTEL_MODEL_206AX select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI - select POSTCAR_STAGE - select POSTCAR_CONSOLE if NORTHBRIDGE_INTEL_SANDYBRIDGE diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 7d5c173829..95bf4584ed 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -15,15 +15,14 @@ #define __SIMPLE_DEVICE__ -#include +#include #include #include #include -#include -#include +#include #include +#include #include -#include #include "sandybridge.h" static uintptr_t smm_region_start(void) @@ -38,57 +37,37 @@ void *cbmem_top(void) return (void *) smm_region_start(); } -u32 northbridge_get_tseg_base(void) +static uintptr_t northbridge_get_tseg_base(void) { return ALIGN_DOWN(smm_region_start(), 1*MiB); } -u32 northbridge_get_tseg_size(void) +static size_t northbridge_get_tseg_size(void) { return CONFIG_SMM_TSEG_SIZE; } -void stage_cache_external_region(void **base, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - /* The stage cache lives at the end of TSEG region. - * The top of RAM is defined to be the TSEG base address. */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)((uintptr_t)northbridge_get_tseg_base() + northbridge_get_tseg_size() - - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE); + *start = northbridge_get_tseg_base(); + *size = northbridge_get_tseg_size(); } -/* platform_enter_postcar() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use, - * and continues execution in postcar stage. */ -void platform_enter_postcar(void) +void fill_postcar_frame(struct postcar_frame *pcf) { - struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - top_of_ram = (uintptr_t)cbmem_top(); /* Cache 8MiB below the top of ram. On sandybridge systems the top of * ram under 4GiB is the start of the TSEG region. It is required to * be 8MiB aligned. Set this area as cacheable so it can be used later * for ramstage before setting up the entire RAM as cacheable. */ - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); /* Cache 8MiB at the top of ram. Top of ram on sandybridge systems * is where the TSEG region resides. However, it is not restricted * to SMM mode until SMM has been relocated. By setting the region * to cacheable it provides faster access when relocating the SMM * handler as well as using the TSEG region for other purposes. */ - postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); - - run_postcar_phase(&pcf); - - /* We do not return here. */ + postcar_frame_add_mtrr(pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); } diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 233384cd15..58f4a6812d 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -28,7 +28,7 @@ #include #include "chip.h" #include "sandybridge.h" -#include +#include static int bridge_revision_id = -1; @@ -493,16 +493,11 @@ static const struct pci_driver mc_driver_158 __pci_driver = { .device = 0x0158, /* Ivy bridge */ }; -static void cpu_bus_init(struct device *dev) -{ - bsp_init_and_start_aps(dev->link_list); -} - static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, - .init = cpu_bus_init, + .init = mp_cpu_bus_init, .scan_bus = 0, }; diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c index 344cd8027e..618ee52c7b 100644 --- a/src/northbridge/intel/sandybridge/pcie.c +++ b/src/northbridge/intel/sandybridge/pcie.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 2cef5f2605..55f2928213 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -22,8 +22,7 @@ #include #include #include "sandybridge.h" -#include -#include +#include #include #include #include @@ -44,15 +43,14 @@ static void early_pch_reset_pmcon(void) /* Platform has no romstage entry point under mainboard directory, * so this one is named with prefix mainboard. */ -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0; if (MCHBAR16(SSKPD) == 0xCAFE) system_reset(); - if (bist == 0) - enable_lapic(); + enable_lapic(); /* Init LPC, GPIO, BARs, disable watchdog ... */ early_pch_init(); @@ -68,9 +66,6 @@ void mainboard_romstage_entry(unsigned long bist) /* Initialize console device(s) */ console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - /* Perform some early chipset initialization required * before RAM initialization can work */ @@ -79,8 +74,7 @@ void mainboard_romstage_entry(unsigned long bist) s3resume = southbridge_detect_s3_resume(); - if (CONFIG(ELOG_BOOT_COUNT) && !s3resume) - boot_count_increment(); + elog_boot_notify(s3resume); post_code(0x38); diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index a819f57af2..8f002c6a8f 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -22,12 +22,9 @@ if NORTHBRIDGE_INTEL_X4X config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y select HAVE_DEBUG_RAM_SETUP - select LAPIC_MONOTONIC_TIMER select VGA select INTEL_GMA_ACPI select CACHE_MRC_SETTINGS - select POSTCAR_STAGE - select POSTCAR_CONSOLE select PARALLEL_MP config CBFS_SIZE diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index dda838760d..41e491200b 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -20,16 +20,15 @@ #include #include #include -#include +#include #include #include #include -#include #include +#include #include #include -#include -#include +#include /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ u32 decode_igd_memory_size(const u32 gms) @@ -113,13 +112,13 @@ u8 decode_pciebar(u32 *const base, u32 *const len) return 1; } -u32 northbridge_get_tseg_size(void) +static size_t northbridge_get_tseg_size(void) { const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); return decode_tseg_size(esmramc); } -u32 northbridge_get_tseg_base(void) +static uintptr_t northbridge_get_tseg_base(void) { return pci_read_config32(PCI_DEV(0, 0, 0), D0F0_TSEG); } @@ -135,43 +134,22 @@ void *cbmem_top(void) return (void *) top_of_ram; } -void stage_cache_external_region(void **base, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - /* The stage cache lives at the end of the TSEG region. - * The top of RAM is defined to be the TSEG base address. - */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)((uintptr_t)northbridge_get_tseg_base() - + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); + *start = northbridge_get_tseg_base(); + *size = northbridge_get_tseg_size(); } -/* platform_enter_postcar() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use, - * and continues execution in postcar stage. */ -void platform_enter_postcar(void) +void fill_postcar_frame(struct postcar_frame *pcf) { - struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - /* Cache 8 MiB region below the top of ram and 2 MiB above top of * ram to cover both cbmem as the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, + postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), + postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); - - run_postcar_phase(&pcf); - - /* We do not return here. */ } diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index b6616e1dd8..ee705277cb 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include static const int legacy_hole_base_k = 0xa0000 / 1024; @@ -191,20 +191,13 @@ static struct device_operations pci_domain_ops = { .acpi_name = northbridge_acpi_name, }; - -static void cpu_bus_init(struct device *dev) -{ - bsp_init_and_start_aps(dev->link_list); -} - static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, - .init = cpu_bus_init, + .init = mp_cpu_bus_init, }; - static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 1e40b9c511..efdcbb637a 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -2156,6 +2156,15 @@ void do_raminit(struct sysinfo *s, int fast_boot) MCHBAR32_OR(0x400*ch + 0x268, 0xc0000000); } + // Dummy reads + if (s->boot_path == BOOT_PATH_NORMAL) { + FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { + for (bank = 0; bank < 4; bank++) + read32((u32 *)(test_address(ch, r) | 0x800000 | (bank << 12))); + } + } + printk(BIOS_DEBUG, "Done dummy reads\n"); + // Receive enable sdram_program_receive_enable(s, fast_boot); printk(BIOS_DEBUG, "Done rcven\n"); @@ -2171,28 +2180,6 @@ void do_raminit(struct sysinfo *s, int fast_boot) MCHBAR8_AND(0x5dc, ~0x80); MCHBAR8_OR(0x5dc, 0x80); - // Dummy writes / reads - if (s->boot_path == BOOT_PATH_NORMAL) { - volatile u32 data; - FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { - for (bank = 0; bank < 4; bank++) { - reg32 = test_address(ch, r) | - (bank << 12); - write32((u32 *)reg32, 0xffffffff); - data = read32((u32 *)reg32); - printk(BIOS_DEBUG, "Wrote ones,"); - printk(BIOS_DEBUG, " Read: [0x%08x]=0x%08x\n", - reg32, data); - write32((u32 *)reg32, 0x00000000); - data = read32((u32 *)reg32); - printk(BIOS_DEBUG, "Wrote zeros,"); - printk(BIOS_DEBUG, " Read: [0x%08x]=0x%08x\n", - reg32, data); - } - } - } - printk(BIOS_DEBUG, "Done dummy reads\n"); - // XXX tRD if (!fast_boot) { diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index d865f388cd..260bd3de05 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -266,8 +266,15 @@ static void vx900_set_resources(struct device *dev) * to be always mapped to the top of 1M, but this can be overcome with * some smart positive/subtractive resource decoding */ ram_resource(dev, idx++, 768, (tolmk - 768)); - uma_memory_size = fbufk << 10; - uma_memory_base = tolmk << 10; + + uma_memory_size = (uint64_t)fbufk << 10; + uma_memory_base = (uint64_t)tolmk << 10; + + if (uma_memory_size > UINT32_MAX) + die("uma_memory_size %llu exceeds 32-bit address range\n", uma_memory_size); + + if (uma_memory_base > UINT32_MAX) + die("uma_memory_base %llu exceeds 32-bit address range\n", uma_memory_base); //uma_resource(dev, idx++, uma_memory_base>>10, uma_memory_size>>10); diff --git a/src/security/Kconfig b/src/security/Kconfig index 8a1531a08d..4e08bbd883 100644 --- a/src/security/Kconfig +++ b/src/security/Kconfig @@ -15,3 +15,4 @@ source "src/security/vboot/Kconfig" source "src/security/tpm/Kconfig" source "src/security/memory/Kconfig" +source "src/security/intel/Kconfig" diff --git a/src/security/Makefile.inc b/src/security/Makefile.inc index f62413e059..fd784385e6 100644 --- a/src/security/Makefile.inc +++ b/src/security/Makefile.inc @@ -1,3 +1,4 @@ subdirs-y += vboot subdirs-y += tpm subdirs-y += memory +subdirs-y += intel diff --git a/src/security/intel/Kconfig b/src/security/intel/Kconfig new file mode 100644 index 0000000000..333e3857ac --- /dev/null +++ b/src/security/intel/Kconfig @@ -0,0 +1,20 @@ +## This file is part of the coreboot project. +## +## Copyright (C) 2019 9elements Agency GmbH +## Copyright (C) 2019 Facebook Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +menu "Intel" + +source "src/security/intel/txt/Kconfig" + +endmenu # Intel diff --git a/src/security/intel/Makefile.inc b/src/security/intel/Makefile.inc new file mode 100644 index 0000000000..9388d3f798 --- /dev/null +++ b/src/security/intel/Makefile.inc @@ -0,0 +1 @@ +subdirs-y += txt diff --git a/src/security/intel/txt/Kconfig b/src/security/intel/txt/Kconfig new file mode 100644 index 0000000000..011a41cdc3 --- /dev/null +++ b/src/security/intel/txt/Kconfig @@ -0,0 +1,54 @@ +## This file is part of the coreboot project. +## +## Copyright (C) 2019 9elements Agency GmbH +## Copyright (C) 2019 Facebook Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config INTEL_TXT + bool "Intel TXT support" + default n + select MRC_SETTINGS_PROTECT if CACHE_MRC_SETTINGS + select ENABLE_VMX if CPU_INTEL_COMMON + select AP_IN_SIPI_WAIT + depends on (TPM1 || TPM2) + depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE + depends on PLATFORM_HAS_DRAM_CLEAR + depends on SOC_INTEL_FSP_BROADWELL_DE || SOC_INTEL_COMMON_BLOCK_SA + +if INTEL_TXT + +config INTEL_TXT_BIOSACM_FILE + string "BIOS ACM file" + default "3rdparty/blobs/soc/intel/fsp_broadwell_de/biosacm.bin" if SOC_INTEL_FSP_BROADWELL_DE + default "3rdparty/blobs/soc/intel/skylake/biosacm.bin" if SOC_INTEL_COMMON_SKYLAKE_BASE + help + Intel TXT BIOS ACM file. This file can be obtained by privileged + access to Intel resources. Or for some platforms found inside the + blob repository. + +config INTEL_TXT_SINITACM_FILE + string "SINIT ACM file" + default "3rdparty/blobs/soc/intel/fsp_broadwell_de/sinitacm.bin" if SOC_INTEL_FSP_BROADWELL_DE + default "3rdparty/blobs/soc/intel/skylake/sinitacm.bin" if SOC_INTEL_COMMON_SKYLAKE_BASE + help + Intel TXT SINIT ACM file. This file can be obtained by privileged + access to Intel resources. Or for some platforms found inside the + blob repository. + +config INTEL_TXT_BIOSACM_ALIGNMENT + hex + default 0x20000 # 128KB + help + Exceptions are Ivy- and Sandy Bridge with 64KB and Purely with 256KB + alignment size. Please overwrite it SoC specific. + +endif diff --git a/src/security/intel/txt/Makefile.inc b/src/security/intel/txt/Makefile.inc new file mode 100644 index 0000000000..d24026ae62 --- /dev/null +++ b/src/security/intel/txt/Makefile.inc @@ -0,0 +1,20 @@ +ifeq ($(CONFIG_INTEL_TXT),y) + +cbfs-files-y += txt_bios_acm.bin +txt_bios_acm.bin-file := $(CONFIG_INTEL_TXT_BIOSACM_FILE) +txt_bios_acm.bin-type := raw +txt_bios_acm.bin-align := $(CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT) + +ifneq ($(CONFIG_INTEL_TXT_SINITACM_FILE),"") +cbfs-files-y += txt_sinit_acm.bin +txt_sinit_acm.bin-file := $(CONFIG_INTEL_TXT_SINITACM_FILE) +txt_sinit_acm.bin-type := raw +txt_sinit_acm.bin-align := 0x10 +txt_sinit_acm.bin-compression := lzma +endif + +INTERMEDIATE+=add_acm_fit +add_acm_fit: $(obj)/coreboot.pre $(IFITTOOL) + $(IFITTOOL) -r COREBOOT -a -n txt_bios_acm.bin -t 2 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< + +endif diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c index 4019962a22..9986d9a7c5 100644 --- a/src/security/tpm/tspi/log.c +++ b/src/security/tpm/tspi/log.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -26,7 +25,7 @@ static struct tcpa_table *tcpa_cbmem_init(void) { - MAYBE_STATIC struct tcpa_table *tclt = NULL; + MAYBE_STATIC_BSS struct tcpa_table *tclt = NULL; if (tclt) return tclt; @@ -47,7 +46,7 @@ static struct tcpa_table *tcpa_cbmem_init(void) static struct tcpa_table *tcpa_log_init(void) { - MAYBE_STATIC struct tcpa_table *tclt = NULL; + MAYBE_STATIC_BSS struct tcpa_table *tclt = NULL; /* We are dealing here with pre CBMEM environment. * If cbmem isn't available use CAR or SRAM */ diff --git a/src/security/tpm/tss.h b/src/security/tpm/tss.h index 30e2a7b4b8..336935d911 100644 --- a/src/security/tpm/tss.h +++ b/src/security/tpm/tss.h @@ -79,6 +79,9 @@ uint32_t tlcl_get_capability(TPM_CAP capability, uint32_t property, */ void *tpm_process_command(TPM_CC command, void *command_body); +/* Return digest size of hash algorithm */ +uint16_t tlcl_get_hash_size_from_algo(TPMI_ALG_HASH hash_algo); + #endif /*****************************************************************************/ diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index 08a7caa1a9..16e40fe569 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -352,6 +352,38 @@ uint32_t tlcl_define_space(uint32_t space_index, size_t space_size, } } +uint16_t tlcl_get_hash_size_from_algo(TPMI_ALG_HASH hash_algo) +{ + uint16_t value; + + switch (hash_algo) { + case TPM_ALG_ERROR: + value = 1; + break; + case TPM_ALG_SHA1: + value = SHA1_DIGEST_SIZE; + break; + case TPM_ALG_SHA256: + value = SHA256_DIGEST_SIZE; + break; + case TPM_ALG_SHA384: + value = SHA384_DIGEST_SIZE; + break; + case TPM_ALG_SHA512: + value = SHA512_DIGEST_SIZE; + break; + case TPM_ALG_SM3_256: + value = SM3_256_DIGEST_SIZE; + break; + default: + printk(BIOS_SPEW, "%s: unknown hash algorithm %d\n", __func__, + hash_algo); + value = 0; + }; + + return value; +} + uint32_t tlcl_disable_platform_hierarchy(void) { struct tpm2_response *response; diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index 345aec5124..1bf211a898 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -83,9 +83,30 @@ static int marshal_TPMT_HA(struct obuf *ob, TPMT_HA *tpmtha) int rc = 0; rc |= marshal_TPMI_ALG_HASH(ob, tpmtha->hashAlg); - rc |= obuf_write(ob, tpmtha->digest.sha256, - sizeof(tpmtha->digest.sha256)); - + switch (tpmtha->hashAlg) { + case TPM_ALG_SHA1: + rc |= obuf_write(ob, tpmtha->digest.sha1, + tlcl_get_hash_size_from_algo(tpmtha->hashAlg)); + break; + case TPM_ALG_SHA256: + rc |= obuf_write(ob, tpmtha->digest.sha256, + tlcl_get_hash_size_from_algo(tpmtha->hashAlg)); + break; + case TPM_ALG_SM3_256: + rc |= obuf_write(ob, tpmtha->digest.sm3_256, + tlcl_get_hash_size_from_algo(tpmtha->hashAlg)); + break; + case TPM_ALG_SHA384: + rc |= obuf_write(ob, tpmtha->digest.sha384, + tlcl_get_hash_size_from_algo(tpmtha->hashAlg)); + break; + case TPM_ALG_SHA512: + rc |= obuf_write(ob, tpmtha->digest.sha512, + tlcl_get_hash_size_from_algo(tpmtha->hashAlg)); + break; + default: + rc = -1; + } return rc; } diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index 7332739582..1530613226 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -38,12 +38,28 @@ typedef TPM_HANDLE TPMI_SH_AUTH_SESSION; typedef TPM_HANDLE TPM_RH; /* Some hardcoded algorithm values. */ -#define TPM_ALG_HMAC ((TPM_ALG_ID)0x0005) -#define TPM_ALG_NULL ((TPM_ALG_ID)0x0010) -#define TPM_ALG_SHA1 ((TPM_ALG_ID)0x0004) -#define TPM_ALG_SHA256 ((TPM_ALG_ID)0x000b) +/* Table 7 - TPM_ALG_ID Constants */ +#define TPM_ALG_ERROR ((TPM_ALG_ID)0x0000) +#define TPM_ALG_HMAC ((TPM_ALG_ID)0x0005) +#define TPM_ALG_NULL ((TPM_ALG_ID)0x0010) +#define TPM_ALG_SHA1 ((TPM_ALG_ID)0x0004) +#define TPM_ALG_SHA256 ((TPM_ALG_ID)0x000b) +#define TPM_ALG_SHA384 ((TPM_ALG_ID)0x000C) +#define TPM_ALG_SHA512 ((TPM_ALG_ID)0x000D) +#define TPM_ALG_SM3_256 ((TPM_ALG_ID)0x0012) -#define SHA256_DIGEST_SIZE 32 +/* Annex A Algorithm Constants */ + +/* Table 205 - Defines for SHA1 Hash Values */ +#define SHA1_DIGEST_SIZE 20 +/* Table 206 - Defines for SHA256 Hash Values */ +#define SHA256_DIGEST_SIZE 32 +/* Table 207 - Defines for SHA384 Hash Values */ +#define SHA384_DIGEST_SIZE 48 +/* Table 208 - Defines for SHA512 Hash Values */ +#define SHA512_DIGEST_SIZE 64 +/* Table 209 - Defines for SM3_256 Hash Values */ +#define SM3_256_DIGEST_SIZE 32 /* Some hardcoded hierarchies. */ #define TPM_RH_NULL 0x40000007 @@ -81,6 +97,12 @@ struct tpm_header { space is defined by the lower 16 bits. */ #define TPM_CC_VENDOR_BIT_MASK 0x20000000 +/* Table 15 - TPM_RC Constants (Actions) */ +#define RC_FMT1 (TPM_RC)(0x080) +#define TPM_RC_HASH (TPM_RC)(RC_FMT1 + 0x003) +#define TPM_RC_P (TPM_RC)(0x040) +#define TPM_RC_N_MASK (TPM_RC)(0xF00) + /* Startup values. */ #define TPM_SU_CLEAR 0 #define TPM_SU_STATE 1 @@ -295,12 +317,13 @@ typedef union { TPM2B b; } TPM2B_MAX_NV_BUFFER; -/* - * This is a union, but as of now we support just one digest - sha256, so - * there is just one element. - */ +/* Table 66 - TPMU_HA Union */ typedef union { - uint8_t sha256[SHA256_DIGEST_SIZE]; + uint8_t sha1[SHA1_DIGEST_SIZE]; + uint8_t sha256[SHA256_DIGEST_SIZE]; + uint8_t sm3_256[SM3_256_DIGEST_SIZE]; + uint8_t sha384[SHA384_DIGEST_SIZE]; + uint8_t sha512[SHA512_DIGEST_SIZE]; } TPMU_HA; typedef struct { @@ -308,9 +331,10 @@ typedef struct { TPMU_HA digest; } TPMT_HA; +/* Table 96 -- TPML_DIGEST_VALUES Structure */ typedef struct { uint32_t count; - TPMT_HA digests[1]; /* Limit max number of hashes to 1. */ + TPMT_HA digests[HASH_COUNT]; } TPML_DIGEST_VALUES; struct nv_read_response { diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index c5146c61e7..1e372d86ba 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -286,10 +286,6 @@ config GBB_FLAG_DISABLE_LID_SHUTDOWN bool "Disable shutdown on closed lid" default n -config GBB_FLAG_FORCE_DEV_BOOT_FASTBOOT_FULL_CAP - bool "Allow fastboot even if dev_boot_fastboot_full_cap=0" - default n - config GBB_FLAG_FORCE_MANUAL_RECOVERY bool "Always assume manual recovery in recovery mode" default n diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index d554f103d6..3078e30e21 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -220,7 +220,6 @@ GBB_FLAGS := $(call int-add, \ $(call bool-to-mask,$(CONFIG_GBB_FLAG_DEFAULT_DEV_BOOT_LEGACY),0x400) \ $(call bool-to-mask,$(CONFIG_GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC),0x800) \ $(call bool-to-mask,$(CONFIG_GBB_FLAG_DISABLE_LID_SHUTDOWN),0x1000) \ - $(call bool-to-mask,$(CONFIG_GBB_FLAG_FORCE_DEV_BOOT_FASTBOOT_FULL_CAP),0x2000) \ $(call bool-to-mask,$(CONFIG_GBB_FLAG_FORCE_MANUAL_RECOVERY),0x4000) \ $(call bool-to-mask,$(CONFIG_GBB_FLAG_DISABLE_FWMP),0x8000) \ ) diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 725f5fd436..1458354ffc 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -117,11 +117,7 @@ static inline int vboot_logic_executed(void) return !ENV_BOOTBLOCK; } else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) { /* Post-RAM stages are "after the romstage" */ -#ifdef __PRE_RAM__ - return 0; -#else - return 1; -#endif + return !ENV_ROMSTAGE_OR_BEFORE; } else { dead_code(); } diff --git a/src/security/vboot/secdata_mock.c b/src/security/vboot/secdata_mock.c index 43206df6b9..de58bf5909 100644 --- a/src/security/vboot/secdata_mock.c +++ b/src/security/vboot/secdata_mock.c @@ -38,38 +38,39 @@ #include "antirollback.h" -int vb2ex_tpm_clear_owner(struct vb2_context *ctx) +vb2_error_t vb2ex_tpm_clear_owner(struct vb2_context *ctx) { return VB2_SUCCESS; } -uint32_t antirollback_read_space_firmware(struct vb2_context *ctx) +vb2_error_t antirollback_read_space_firmware(struct vb2_context *ctx) { vb2api_secdata_create(ctx); return VB2_SUCCESS; } -uint32_t antirollback_write_space_firmware(struct vb2_context *ctx) +vb2_error_t antirollback_write_space_firmware(struct vb2_context *ctx) { return VB2_SUCCESS; } -uint32_t antirollback_lock_space_firmware(void) +vb2_error_t antirollback_lock_space_firmware(void) { return VB2_SUCCESS; } -uint32_t antirollback_lock_space_rec_hash(void) +vb2_error_t antirollback_lock_space_rec_hash(void) { return VB2_SUCCESS; } -uint32_t antirollback_read_space_rec_hash(uint8_t *data, uint32_t size) +vb2_error_t antirollback_read_space_rec_hash(uint8_t *data, uint32_t size) { return VB2_SUCCESS; } -uint32_t antirollback_write_space_rec_hash(const uint8_t *data, uint32_t size) +vb2_error_t antirollback_write_space_rec_hash(const uint8_t *data, + uint32_t size) { return VB2_SUCCESS; } diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 09c7e72b9b..38a1810d7f 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -124,18 +124,6 @@ static uint32_t write_secdata(uint32_t index, return TPM_E_CORRUPTED_STATE; } -/* - * This is derived from rollback_index.h of vboot_reference. see struct - * RollbackSpaceKernel for details. - */ -static const uint8_t secdata_kernel[] = { - 0x02, - 0x4C, 0x57, 0x52, 0x47, - 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, - 0xE8, -}; - /* * This is used to initialize the TPM space for recovery hash after defining * it. Since there is no data available to calculate hash at the point where TPM @@ -217,7 +205,7 @@ static uint32_t set_firmware_space(const void *firmware_blob) static uint32_t set_kernel_space(const void *kernel_blob) { return set_space("kernel", KERNEL_NV_INDEX, kernel_blob, - sizeof(secdata_kernel), rw_space_attributes, NULL, 0); + VB2_SECDATAK_SIZE, rw_space_attributes, NULL, 0); } static uint32_t set_rec_hash_space(const uint8_t *data) @@ -238,7 +226,7 @@ static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) * indication that TPM factory initialization was successfully * completed. */ - RETURN_ON_FAILURE(set_kernel_space(secdata_kernel)); + RETURN_ON_FAILURE(set_kernel_space(ctx->secdatak)); if (CONFIG(VBOOT_HAS_REC_HASH_SPACE)) RETURN_ON_FAILURE(set_rec_hash_space(rec_hash_data)); @@ -342,16 +330,15 @@ static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) VBDEBUG("TPM: Clearing owner\n"); RETURN_ON_FAILURE(tpm_clear_and_reenable()); - /* Define and initialize the kernel space */ + /* Define and write secdatak kernel space. */ RETURN_ON_FAILURE(safe_define_space(KERNEL_NV_INDEX, TPM_NV_PER_PPWRITE, - sizeof(secdata_kernel))); + VB2_SECDATAK_SIZE)); RETURN_ON_FAILURE(write_secdata(KERNEL_NV_INDEX, - secdata_kernel, - sizeof(secdata_kernel))); + ctx->secdatak, + VB2_SECDATAK_SIZE)); - /* Defines and sets vb2 secdata space */ - vb2api_secdata_create(ctx); + /* Define and write secdata firmware space. */ RETURN_ON_FAILURE(safe_define_space(FIRMWARE_NV_INDEX, TPM_NV_PER_GLOBALLOCK | TPM_NV_PER_PPWRITE, @@ -393,8 +380,9 @@ static uint32_t factory_initialize_tpm(struct vb2_context *ctx) { uint32_t result; - /* Defines and sets vb2 secdata space */ + /* Set initial values of secdata and secdatak spaces. */ vb2api_secdata_create(ctx); + vb2api_secdatak_create(ctx); VBDEBUG("TPM: factory initialization\n"); @@ -486,7 +474,7 @@ uint32_t antirollback_write_space_rec_hash(const uint8_t *data, uint32_t size) return write_secdata(REC_HASH_NV_INDEX, data, size); } -int vb2ex_tpm_clear_owner(struct vb2_context *ctx) +vb2_error_t vb2ex_tpm_clear_owner(struct vb2_context *ctx) { uint32_t rv; printk(BIOS_INFO, "Clearing TPM owner\n"); diff --git a/src/security/vboot/tpm_common.c b/src/security/vboot/tpm_common.c index 1a07ef6def..0a211c57d4 100644 --- a/src/security/vboot/tpm_common.c +++ b/src/security/vboot/tpm_common.c @@ -30,12 +30,12 @@ uint32_t vboot_setup_tpm(struct vb2_context *ctx) return result; } -uint32_t vboot_extend_pcr(struct vb2_context *ctx, int pcr, - enum vb2_pcr_digest which_digest) +vb2_error_t vboot_extend_pcr(struct vb2_context *ctx, int pcr, + enum vb2_pcr_digest which_digest) { uint8_t buffer[VB2_PCR_DIGEST_RECOMMENDED_SIZE]; uint32_t size = sizeof(buffer); - int rv; + vb2_error_t rv; rv = vb2api_get_pcr_digest(ctx, which_digest, buffer, &size); if (rv != VB2_SUCCESS) @@ -46,7 +46,7 @@ uint32_t vboot_extend_pcr(struct vb2_context *ctx, int pcr, switch (which_digest) { /* SHA1 of (devmode|recmode|keyblock) bits */ case BOOT_MODE_PCR: - return tpm_extend_pcr(pcr, VB2_HASH_SHA1, buffer, size, + return tpm_extend_pcr(pcr, VB2_HASH_SHA256, buffer, size, TPM_PCR_BOOT_MODE); /* SHA256 of HWID */ case HWID_DIGEST_PCR: diff --git a/src/security/vboot/tpm_common.h b/src/security/vboot/tpm_common.h index 6bb32bbf1d..e1faa0ca45 100644 --- a/src/security/vboot/tpm_common.h +++ b/src/security/vboot/tpm_common.h @@ -17,8 +17,8 @@ uint32_t vboot_setup_tpm(struct vb2_context *ctx); /* vboot_extend_pcr function for vb2 context */ -uint32_t vboot_extend_pcr(struct vb2_context *ctx, int pcr, - enum vb2_pcr_digest which_digest); +vb2_error_t vboot_extend_pcr(struct vb2_context *ctx, int pcr, + enum vb2_pcr_digest which_digest); #else diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 7f00df5796..d049740776 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -55,11 +55,11 @@ void vb2ex_printf(const char *func, const char *fmt, ...) return; } -int vb2ex_read_resource(struct vb2_context *ctx, - enum vb2_resource_index index, - uint32_t offset, - void *buf, - uint32_t size) +vb2_error_t vb2ex_read_resource(struct vb2_context *ctx, + enum vb2_resource_index index, + uint32_t offset, + void *buf, + uint32_t size) { struct region_device rdev; const char *name; @@ -88,19 +88,21 @@ int vb2ex_read_resource(struct vb2_context *ctx, } /* No-op stubs that can be overridden by SoCs with hardware crypto support. */ -__weak int vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg, - uint32_t data_size) +__weak vb2_error_t vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg, + uint32_t data_size) { return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED; } -__weak int vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size) +__weak vb2_error_t vb2ex_hwcrypto_digest_extend(const uint8_t *buf, + uint32_t size) { BUG(); /* Should never get called if init() returned an error. */ return VB2_ERROR_UNKNOWN; } -__weak int vb2ex_hwcrypto_digest_finalize(uint8_t *digest, uint32_t digest_size) +__weak vb2_error_t vb2ex_hwcrypto_digest_finalize(uint8_t *digest, + uint32_t digest_size) { BUG(); /* Should never get called if init() returned an error. */ return VB2_ERROR_UNKNOWN; @@ -169,7 +171,8 @@ static int handle_digest_result(void *slot_hash, size_t slot_hash_sz) return 0; } -static int hash_body(struct vb2_context *ctx, struct region_device *fw_main) +static vb2_error_t hash_body(struct vb2_context *ctx, + struct region_device *fw_main) { uint64_t load_ts; uint32_t expected_size; @@ -178,7 +181,7 @@ static int hash_body(struct vb2_context *ctx, struct region_device *fw_main) const size_t hash_digest_sz = sizeof(hash_digest); size_t block_size = sizeof(block); size_t offset; - int rv; + vb2_error_t rv; /* Clear the full digest so that any hash digests less than the * max have trailing zeros. */ @@ -313,7 +316,7 @@ void verstage_main(void) { struct vb2_context ctx; struct region_device fw_main; - int rv; + vb2_error_t rv; timestamp_add_now(TS_START_VBOOT); diff --git a/src/soc/amd/common/block/hda/hda.c b/src/soc/amd/common/block/hda/hda.c index 49fc1a6648..27510c3fad 100644 --- a/src/soc/amd/common/block/hda/hda.c +++ b/src/soc/amd/common/block/hda/hda.c @@ -16,12 +16,10 @@ #include #include #include -#include static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_SB900_HDA, PCI_DEVICE_ID_AMD_CZ_HDA, - PCI_DEVICE_ID_AMD_PCO_HDA0, PCI_DEVICE_ID_AMD_PCO_HDA1, 0 }; diff --git a/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h index 829630bd96..920549981e 100644 --- a/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h +++ b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h @@ -18,6 +18,7 @@ #define __CALLOUTS_AMD_AGESA_H__ #include +#include #define BIOS_HEAP_SIZE 0x30000 #define BSP_STACK_BASE_ADDR 0x30000 diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 32da867137..59ab9e5f4f 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -18,6 +18,7 @@ #ifndef __AMDBLOCKS_ACPIMMIO_H__ #define __AMDBLOCKS_ACPIMMIO_H__ +#include /* iomap.h must indicate if the device uses a block, optional if unused. */ #include #ifndef SUPPORTS_ACPIMMIO_SMI_BASE diff --git a/src/soc/amd/common/block/include/amdblocks/fch_spi.h b/src/soc/amd/common/block/include/amdblocks/fch_spi.h new file mode 100644 index 0000000000..8e288283b1 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/fch_spi.h @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Silverback Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _FCH_SPI_H_ +#define _FCH_SPI_H_ + +#include +#include + +#define GRANULARITY_TEST_4k 0x0000f000 /* bits 15-12 */ +#define WORD_TO_DWORD_UPPER(x) ((x << 16) & 0xffff0000) +#define SPI_PAGE_WRITE 0x02 +#define SPI_WRITE_ENABLE 0x06 +/* + * IDCODE_CONT_LEN may be redefined if a device needs to declare a + * larger "shift" value. IDCODE_PART_LEN generally shouldn't be + * changed. This is the max number of bytes probe functions may + * examine when looking up part-specific identification info. + */ +#define IDCODE_CONT_CODE 0x7f +#define IDCODE_CONT_LEN 1 /* currently support only bank 0 */ +#define IDCODE_PART_LEN 5 +#define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN) + +/* SPI MMIO registers */ +#define SPI_RESTRICTED_CMD1 0x04 +#define SPI_RESTRICTED_CMD2 0x08 +#define SPI_CNTRL1 0x0c +#define SPI_CMD_CODE 0x45 +#define SPI_CMD_TRIGGER 0x47 +#define SPI_CMD_TRIGGER_EXECUTE BIT(7) +#define SPI_TX_BYTE_COUNT 0x48 +#define SPI_RX_BYTE_COUNT 0x4b +#define SPI_STATUS 0x4c +#define SPI_DONE_BYTE_COUNT_SHIFT 0 +#define SPI_DONE_BYTE_COUNT_MASK 0xff +#define SPI_FIFO_WR_PTR_SHIFT 8 +#define SPI_FIFO_WR_PTR_MASK 0x7f +#define SPI_FIFO_RD_PTR_SHIFT 16 +#define SPI_FIFO_RD_PTR_MASK 0x7f + +/* Special SST write commands */ +#define CMD_SST_BP 0x02 /* Byte Program */ +#define CMD_SST_AAI_WP 0xad /* Auto Address Increment Word Program */ + +#define SST_256 0x004b /* Only SST that programs 256 bytes at once */ + +enum non_standard_spi { + NON_STANDARD_SPI_NONE = 0, + NON_STANDARD_SPI_SST, +}; + +struct spi_flash_table { + const u8 shift; + const u8 idcode; + int (*probe)(const struct spi_slave *spi, u8 *idcode, + struct spi_flash *flash); +}; + +struct spi_data { + const char *name; + u32 size; + u32 sector_size; + u32 page_size; + u8 status_cmd; + u8 erase_cmd; + u8 write_cmd; + u8 write_enable_cmd; + u8 read_cmd; + u8 read_cmd_len; + enum non_standard_spi non_standard; +}; + +void fch_spi_init(void); +void fch_spi_flash_ops_init(struct spi_flash *flash); +int fch_spi_flash_cmd(const void *dout, size_t bytes_out, void *din, size_t bytes_in); +int fch_spi_flash_cmd_write(const u8 *cmd, size_t cmd_len, const void *data, size_t data_len); +int fch_spi_wait_cmd_ready(unsigned long timeout); +int non_standard_sst_byte_write(u32 offset, const void *buf); +int non_standard_sst_write_aai(u32 offset, size_t len, const void *buf, size_t start); +const struct spi_flash_table *get_spi_flash_table(int *table_size); +const struct spi_data *get_ctrl_spi_data(void); + +static inline int fch_spi_enable_write(void) +{ + u8 cmd_enable = SPI_WRITE_ENABLE; + return fch_spi_flash_cmd(&cmd_enable, 1, NULL, 0); +} + +#endif /* _FCH_SPI_H_ */ diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h index da841347fb..6427cb696e 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h @@ -59,6 +59,7 @@ struct soc_amd_event { #define GPIO_S4_S5_WAKE_EN (1 << 15) #define GPIO_PIN_STS (1 << 16) +#define GPIO_8KPULLUP_SELECT (1 << 19) #define GPIO_PULLUP_ENABLE (1 << 20) #define GPIO_PULLDOWN_ENABLE (1 << 21) #define GPIO_OUTPUT_SHIFT 22 @@ -107,6 +108,7 @@ enum { #define GPIO_OUTPUT_OUT_HIGH (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE) #define GPIO_OUTPUT_OUT_LOW GPIO_OUTPUT_ENABLE +#define GPIO_PULL_PULL_UP_8K (GPIO_PULLUP_ENABLE | GPIO_8KPULLUP_SELECT) #define GPIO_PULL_PULL_UP GPIO_PULLUP_ENABLE #define GPIO_PULL_PULL_DOWN GPIO_PULLDOWN_ENABLE #define GPIO_PULL_PULL_NONE 0 diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index ab913b2df0..11880eb3e6 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -17,6 +17,7 @@ #define __AMDBLOCKS_LPC_H__ #include +#include /* PCI registers for D14F3 */ #define LPC_PCI_CONTROL 0x40 @@ -67,6 +68,7 @@ #define DECODE_IO_PORT_ENABLE2 BIT(18) #define DECODE_IO_PORT_ENABLE1 BIT(17) #define DECODE_IO_PORT_ENABLE0 BIT(16) +#define LPC_SYNC_TIMEOUT_COUNT_MASK (0xff << 8) #define LPC_SYNC_TIMEOUT_COUNT_ENABLE BIT(7) #define LPC_DECODE_RTC_IO_ENABLE BIT(6) #define DECODE_MEM_PORT_ENABLE0 BIT(5) @@ -88,6 +90,14 @@ #define DECODE_IO_PORT_ENABLE0_H BIT(0) #define LPC_MEM_PORT1 0x4c +#define ROM_PROTECT_RANGE0 0x50 +#define ROM_BASE_MASK 0xfffff000 /* bits 31-12 */ +#define ROM_RANGE_WP BIT(10) +#define ROM_RANGE_RP BIT(9) +#define RANGE_UNIT BIT(8) +#define RANGE_ADDR_MASK 0x000000ff /* Range defined by bits 7-0 */ +#define ROM_PROTECT_RANGE_REG(n) (ROM_PROTECT_RANGE0 + (4 * n)) +#define MAX_ROM_PROTECT_RANGES 4 #define LPC_MEM_PORT0 0x60 /* Register 0x64 is 32-bit, composed by two 16-bit sub-registers. @@ -133,6 +143,9 @@ #define PREFETCH_EN_SPI_FROM_HOST BIT(0) #define T_START_ENH BIT(3) +/* Clear all decoding to the LPC bus and erase any range registers associated + * with the enable bits. */ +void lpc_disable_decodes(void); /* LPC is typically enabled very early, but this function is last opportunity */ void soc_late_lpc_bridge_enable(void); void lpc_enable_port80(void); diff --git a/src/soc/amd/common/block/include/amdblocks/s3_resume.h b/src/soc/amd/common/block/include/amdblocks/s3_resume.h index 13f801021c..9323baf6aa 100644 --- a/src/soc/amd/common/block/include/amdblocks/s3_resume.h +++ b/src/soc/amd/common/block/include/amdblocks/s3_resume.h @@ -17,10 +17,10 @@ #define __AMD_S3_RESUME_H__ #include +#include -int save_s3_info(void *nv_base, size_t nv_size, - void *vol_base, size_t vol_size); -void get_s3nv_info(void **base, size_t *size); -void get_s3vol_info(void **base, size_t *size); +AGESA_STATUS OemInitResume(S3_DATA_BLOCK *dataBlock); +AGESA_STATUS OemS3LateRestore(S3_DATA_BLOCK *dataBlock); +AGESA_STATUS OemS3Save(S3_DATA_BLOCK *dataBlock); #endif /* __AMD_S3_RESUME_H__ */ diff --git a/src/soc/amd/common/block/iommu/iommu.c b/src/soc/amd/common/block/iommu/iommu.c index c068501d49..18c8e665ad 100644 --- a/src/soc/amd/common/block/iommu/iommu.c +++ b/src/soc/amd/common/block/iommu/iommu.c @@ -16,7 +16,6 @@ #include #include #include -#include #include static void iommu_read_resources(struct device *dev) diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index 008d14c34e..1d46acbf5c 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -170,6 +170,25 @@ void lpc_enable_decode(uint32_t decodes) pci_write_config32(_LPCB_DEV, LPC_IO_PORT_DECODE_ENABLE, decodes); } +/* + * Clear all decoding to the LPC bus and erase any range registers associated + * with the enable bits. + */ +void lpc_disable_decodes(void) +{ + uint32_t reg; + + lpc_enable_decode(0); + reg = pci_read_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); + reg &= LPC_SYNC_TIMEOUT_COUNT_MASK | LPC_SYNC_TIMEOUT_COUNT_ENABLE; + pci_write_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, reg); + + /* D14F3x48 enables ranges configured in additional registers */ + pci_write_config32(_LPCB_DEV, LPC_MEM_PORT1, 0); + pci_write_config32(_LPCB_DEV, LPC_MEM_PORT0, 0); + pci_write_config32(_LPCB_DEV, LPC_WIDEIO2_GENERIC_PORT, 0); +} + uintptr_t lpc_spibase(void) { u32 base, enables; diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index a39e29ff48..c5464df834 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -312,10 +312,10 @@ static AGESA_STATUS amd_init_rtb(AMD_RTB_PARAMS *RtbParams) Status = amd_dispatch(RtbParams); timestamp_add_now(TS_AGESA_INIT_RTB_DONE); - if (save_s3_info(RtbParams->S3DataBlock.NvStorage, - RtbParams->S3DataBlock.NvStorageSize, - RtbParams->S3DataBlock.VolatileStorage, - RtbParams->S3DataBlock.VolatileStorageSize)) + if (Status != AGESA_SUCCESS) + return Status; + + if (OemS3Save(&RtbParams->S3DataBlock) != AGESA_SUCCESS) printk(BIOS_ERR, "S3 data not saved, resuming impossible\n"); return Status; @@ -324,10 +324,8 @@ static AGESA_STATUS amd_init_rtb(AMD_RTB_PARAMS *RtbParams) static AGESA_STATUS amd_init_resume(AMD_RESUME_PARAMS *InitResumeParams) { AGESA_STATUS status; - size_t nv_size; - get_s3nv_info(&InitResumeParams->S3DataBlock.NvStorage, &nv_size); - InitResumeParams->S3DataBlock.NvStorageSize = nv_size; + OemInitResume(&InitResumeParams->S3DataBlock); timestamp_add_now(TS_AGESA_INIT_RESUME_START); status = amd_dispatch(InitResumeParams); @@ -339,12 +337,10 @@ static AGESA_STATUS amd_init_resume(AMD_RESUME_PARAMS *InitResumeParams) static AGESA_STATUS amd_s3late_restore(AMD_S3LATE_PARAMS *S3LateParams) { AGESA_STATUS Status; - size_t vol_size; amd_initcpuio(); - get_s3vol_info(&S3LateParams->S3DataBlock.VolatileStorage, &vol_size); - S3LateParams->S3DataBlock.VolatileStorageSize = vol_size; + OemS3LateRestore(&S3LateParams->S3DataBlock); timestamp_add_now(TS_AGESA_S3_LATE_START); Status = amd_dispatch(S3LateParams); @@ -356,10 +352,8 @@ static AGESA_STATUS amd_s3late_restore(AMD_S3LATE_PARAMS *S3LateParams) static AGESA_STATUS amd_s3final_restore(AMD_S3FINAL_PARAMS *S3FinalParams) { AGESA_STATUS Status; - size_t vol_size; - get_s3vol_info(&S3FinalParams->S3DataBlock.VolatileStorage, &vol_size); - S3FinalParams->S3DataBlock.VolatileStorageSize = vol_size; + OemS3LateRestore(&S3FinalParams->S3DataBlock); timestamp_add_now(TS_AGESA_S3_FINAL_START); Status = amd_dispatch(S3FinalParams); diff --git a/src/soc/amd/common/block/pi/amd_late_init.c b/src/soc/amd/common/block/pi/amd_late_init.c index 80c7add261..f2b4ed1d0d 100644 --- a/src/soc/amd/common/block/pi/amd_late_init.c +++ b/src/soc/amd/common/block/pi/amd_late_init.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/amd/common/block/s3/s3_resume.c b/src/soc/amd/common/block/s3/s3_resume.c index 74aa79c398..598036acf2 100644 --- a/src/soc/amd/common/block/s3/s3_resume.c +++ b/src/soc/amd/common/block/s3/s3_resume.c @@ -26,56 +26,73 @@ /* Training data versioning is not supported or tracked. */ #define DEFAULT_MRC_VERSION 0 -static void reboot_from_resume(const char *message) /* Does not return */ +static void __noreturn reboot_from_resume(const char *message) { printk(BIOS_ERR, "%s", message); set_pm1cnt_s5(); board_reset(); } -void get_s3nv_info(void **base, size_t *size) +AGESA_STATUS OemInitResume(S3_DATA_BLOCK *dataBlock) { + void *base; + size_t size; + int i; + uint32_t erased = 0xffffffff; struct region_device rdev; if (mrc_cache_get_current(MRC_TRAINING_DATA, DEFAULT_MRC_VERSION, &rdev)) reboot_from_resume("mrc_cache_get_current error, rebooting.\n"); - *base = rdev_mmap_full(&rdev); - *size = region_device_sz(&rdev); - if (!*base || !*size) + base = rdev_mmap_full(&rdev); + size = region_device_sz(&rdev); + if (!base || !size) reboot_from_resume("Error: S3 NV data not found, rebooting.\n"); /* Read 16 bytes to infer if the NV has been erased from flash. */ - int i; - uint32_t erased = 0xffffffff; for (i = 0; i < 4; i++) - erased &= read32((uint32_t *)*base + i); - + erased &= read32((uint32_t *)base + i); if (erased == 0xffffffff) reboot_from_resume("Error: S3 NV data invalid, rebooting.\n"); - printk(BIOS_SPEW, "S3 NV data @0x%p, 0x%0zx bytes\n", *base, *size); + dataBlock->NvStorage = base; + dataBlock->NvStorageSize = size; + printk(BIOS_SPEW, "S3 NV data @0x%p, 0x%0zx bytes\n", + dataBlock->NvStorage, (size_t)dataBlock->NvStorageSize); + + return AGESA_SUCCESS; } -void get_s3vol_info(void **base, size_t *size) +AGESA_STATUS OemS3LateRestore(S3_DATA_BLOCK *dataBlock) { - stage_cache_get_raw(STAGE_S3_DATA, base, size); - if (!*base || !*size) + void *base = NULL; + size_t size = 0; + + stage_cache_get_raw(STAGE_S3_DATA, &base, &size); + if (!base || !size) { printk(BIOS_ERR, "Error: S3 volatile data not found\n"); - else - printk(BIOS_SPEW, "S3 volatile data @0x%p 0x%0zx total bytes\n", - *base, *size); -} - -int save_s3_info(void *nv_base, size_t nv_size, void *vol_base, size_t vol_size) -{ - if (mrc_cache_stash_data(MRC_TRAINING_DATA, DEFAULT_MRC_VERSION, - nv_base, nv_size) < 0) { - printk(BIOS_ERR, "Failed to stash MRC data\n"); - return -1; + return AGESA_FATAL; } - stage_cache_add_raw(STAGE_S3_DATA, vol_base, vol_size); - return 0; + dataBlock->VolatileStorage = base; + dataBlock->VolatileStorageSize = size; + printk(BIOS_SPEW, "S3 volatile data @0x%p, 0x%0zx bytes\n", + dataBlock->VolatileStorage, (size_t)dataBlock->VolatileStorageSize); + + return AGESA_SUCCESS; +} + +AGESA_STATUS OemS3Save(S3_DATA_BLOCK *dataBlock) +{ + if (mrc_cache_stash_data(MRC_TRAINING_DATA, DEFAULT_MRC_VERSION, + dataBlock->NvStorage, dataBlock->NvStorageSize) < 0) { + printk(BIOS_ERR, "Failed to stash MRC data\n"); + return AGESA_CRITICAL; + } + + stage_cache_add_raw(STAGE_S3_DATA, dataBlock->VolatileStorage, + dataBlock->VolatileStorageSize); + + return AGESA_SUCCESS; } diff --git a/src/soc/amd/common/block/sata/sata.c b/src/soc/amd/common/block/sata/sata.c index cbbc7cfd92..5aa20887dd 100644 --- a/src/soc/amd/common/block/sata/sata.c +++ b/src/soc/amd/common/block/sata/sata.c @@ -16,7 +16,6 @@ #include #include #include -#include #include void __weak soc_enable_sata_features(struct device *dev) { } diff --git a/src/soc/amd/common/block/spi/Kconfig b/src/soc/amd/common/block/spi/Kconfig new file mode 100644 index 0000000000..785e6da6b3 --- /dev/null +++ b/src/soc/amd/common/block/spi/Kconfig @@ -0,0 +1,11 @@ +config SOC_AMD_COMMON_BLOCK_SPI + bool + default n + help + Select this option to add FCH SPI controller functions to the build. + This overwrites the structure spi_flash_ops to use FCH SPI code + instead of individual SPI specific code. + +config SOC_AMD_COMMON_BLOCK_SPI_DEBUG + bool + default n diff --git a/src/soc/amd/common/block/spi/Makefile.inc b/src/soc/amd/common/block/spi/Makefile.inc new file mode 100644 index 0000000000..b94eda405a --- /dev/null +++ b/src/soc/amd/common/block/spi/Makefile.inc @@ -0,0 +1,30 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SPI),y) + +bootblock-y += fch_spi_ctrl.c +bootblock-y += fch_spi_flash.c +bootblock-y += fch_spi_special.c +bootblock-y += fch_spi_table.c +romstage-y += fch_spi_ctrl.c +romstage-y += fch_spi_flash.c +romstage-y += fch_spi_special.c +romstage-y += fch_spi_table.c +verstage-y += fch_spi_ctrl.c +verstage-y += fch_spi_flash.c +verstage-y += fch_spi_special.c +verstage-y += fch_spi_table.c +postcar-y += fch_spi_ctrl.c +postcar-y += fch_spi_flash.c +postcar-y += fch_spi_special.c +postcar-y += fch_spi_table.c +ramstage-y += fch_spi_ctrl.c +ramstage-y += fch_spi_flash.c +ramstage-y += fch_spi_special.c +ramstage-y += fch_spi_table.c +ifeq ($(CONFIG_SPI_FLASH_SMM),y) +smm-y += fch_spi_ctrl.c +smm-y += fch_spi_flash.c +smm-y += fch_spi_special.c +smm-y += fch_spi_table.c +endif + +endif diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c new file mode 100644 index 0000000000..a7d9c77e12 --- /dev/null +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -0,0 +1,441 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Silverback Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct spi_data ctrl_spi_data; +static uint32_t spibar; + +static inline uint8_t spi_read8(uint8_t reg) +{ + return read8((void *)(spibar + reg)); +} + +static inline uint32_t spi_read32(uint8_t reg) +{ + return read32((void *)(spibar + reg)); +} + +static inline void spi_write8(uint8_t reg, uint8_t val) +{ + write8((void *)(spibar + reg), val); +} + +static inline void spi_write32(uint8_t reg, uint32_t val) +{ + write32((void *)(spibar + reg), val); +} + +static void dump_state(const char *str, u8 phase) +{ + u8 dump_size; + u32 addr; + + if (!CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG)) + return; + + printk(BIOS_DEBUG, "SPI: %s\n", str); + printk(BIOS_DEBUG, "Cntrl0: %x\n", spi_read32(SPI_CNTRL0)); + printk(BIOS_DEBUG, "Status: %x\n", spi_read32(SPI_STATUS)); + + addr = spibar + SPI_FIFO; + if (phase == 0) { + dump_size = spi_read8(SPI_TX_BYTE_COUNT); + printk(BIOS_DEBUG, "TxByteCount: %x\n", dump_size); + printk(BIOS_DEBUG, "CmdCode: %x\n", spi_read8(SPI_CMD_CODE)); + } else { + dump_size = spi_read8(SPI_RX_BYTE_COUNT); + printk(BIOS_DEBUG, "RxByteCount: %x\n", dump_size); + addr += spi_read8(SPI_TX_BYTE_COUNT); + } + + if (dump_size > 0) + hexdump((void *)addr, dump_size); +} + +static int wait_for_ready(void) +{ + const uint32_t timeout_ms = 500; + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, timeout_ms); + + do { + if (!(spi_read32(SPI_STATUS) & SPI_BUSY)) + return 0; + } while (!stopwatch_expired(&sw)); + + return -1; +} + +static int execute_command(void) +{ + dump_state("Before execute", 0); + + spi_write8(SPI_CMD_TRIGGER, SPI_CMD_TRIGGER_EXECUTE); + + if (wait_for_ready()) + printk(BIOS_ERR, + "FCH_SC Error: Timeout executing command\n"); + + dump_state("Transaction finished", 1); + + return 0; +} + +void spi_init(void) +{ + spibar = lpc_get_spibase(); + printk(BIOS_DEBUG, "%s: Spibar at 0x%08x\n", __func__, spibar); +} + +const struct spi_data *get_ctrl_spi_data(void) +{ + return &ctrl_spi_data; +} + +static int spi_ctrlr_xfer(const void *dout, size_t bytesout, void *din, size_t bytesin) +{ + size_t count; + uint8_t cmd; + uint8_t *bufin = din; + const uint8_t *bufout = dout; + + if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG)) + printk(BIOS_DEBUG, "%s(%zx, %zx)\n", __func__, bytesout, + bytesin); + + /* First byte is cmd which cannot be sent through FIFO */ + cmd = bufout[0]; + bufout++; + bytesout--; + + /* + * Check if this is a write command attempting to transfer more bytes + * than the controller can handle. Iterations for writes are not + * supported here because each SPI write command needs to be preceded + * and followed by other SPI commands. + */ + if (bytesout + bytesin > SPI_FIFO_DEPTH) { + printk(BIOS_WARNING, "FCH_SC: Too much to transfer, code error!\n"); + return -1; + } + + if (wait_for_ready()) + return -1; + + spi_write8(SPI_CMD_CODE, cmd); + spi_write8(SPI_TX_BYTE_COUNT, bytesout); + spi_write8(SPI_RX_BYTE_COUNT, bytesin); + + for (count = 0; count < bytesout; count++) + spi_write8(SPI_FIFO + count, bufout[count]); + + if (execute_command()) + return -1; + + for (count = 0; count < bytesin; count++) + bufin[count] = spi_read8(SPI_FIFO + count + bytesout); + + return 0; +} + +static int amd_xfer_vectors(struct spi_op vectors[], size_t count) +{ + int ret; + void *din; + size_t bytes_in; + + if (count < 1 || count > 2) + return -1; + + /* SPI flash commands always have a command first... */ + if (!vectors[0].dout || !vectors[0].bytesout) + return -1; + /* And not read any data during the command. */ + if (vectors[0].din || vectors[0].bytesin) + return -1; + + if (count == 2) { + /* If response bytes requested ensure the buffer is valid. */ + if (vectors[1].bytesin && !vectors[1].din) + return -1; + /* No sends can accompany a receive. */ + if (vectors[1].dout || vectors[1].bytesout) + return -1; + din = vectors[1].din; + bytes_in = vectors[1].bytesin; + } else { + din = NULL; + bytes_in = 0; + } + + ret = spi_ctrlr_xfer(vectors[0].dout, vectors[0].bytesout, din, bytes_in); + + if (ret) { + vectors[0].status = SPI_OP_FAILURE; + if (count == 2) + vectors[1].status = SPI_OP_FAILURE; + } else { + vectors[0].status = SPI_OP_SUCCESS; + if (count == 2) + vectors[1].status = SPI_OP_SUCCESS; + } + + return ret; +} + +int fch_spi_flash_cmd(const void *dout, size_t bytes_out, void *din, size_t bytes_in) +{ + /* + * SPI flash requires command-response kind of behavior. Thus, two + * separate SPI vectors are required -- first to transmit dout and other + * to receive in din. + */ + struct spi_op vectors[] = { + [0] = { .dout = dout, .bytesout = bytes_out, + .din = NULL, .bytesin = 0, }, + [1] = { .dout = NULL, .bytesout = 0, + .din = din, .bytesin = bytes_in }, + }; + size_t count = ARRAY_SIZE(vectors); + if (!bytes_in) + count = 1; + + return amd_xfer_vectors(vectors, count); +} + +static void set_ctrl_spi_data(struct spi_flash *flash) +{ + u8 cmd = SPI_PAGE_WRITE; + + ctrl_spi_data.name = flash->name; + ctrl_spi_data.size = flash->size; + ctrl_spi_data.sector_size = flash->sector_size; + ctrl_spi_data.status_cmd = flash->status_cmd; + ctrl_spi_data.erase_cmd = flash->erase_cmd; + ctrl_spi_data.write_enable_cmd = SPI_WRITE_ENABLE; + + if (flash->vendor == VENDOR_ID_SST) { + ctrl_spi_data.non_standard = NON_STANDARD_SPI_SST; + if ((flash->model & 0x00ff) == SST_256) + ctrl_spi_data.page_size = 256; + else { + ctrl_spi_data.page_size = 2; + cmd = CMD_SST_AAI_WP; + } + } else { + ctrl_spi_data.page_size = flash->page_size; + ctrl_spi_data.non_standard = NON_STANDARD_SPI_NONE; + } + ctrl_spi_data.write_cmd = cmd; + + if (CONFIG(SPI_FLASH_NO_FAST_READ)) { + ctrl_spi_data.read_cmd_len = 4; + ctrl_spi_data.read_cmd = CMD_READ_ARRAY_SLOW; + } else { + ctrl_spi_data.read_cmd_len = 5; + ctrl_spi_data.read_cmd = CMD_READ_ARRAY_FAST; + } +} + +static int fch_spi_flash_probe(const struct spi_slave *spi, struct spi_flash *flash) +{ + int ret, i, shift, table_size; + u8 idcode[IDCODE_LEN], *idp, cmd = CMD_READ_ID; + const struct spi_flash_table *flash_ptr = get_spi_flash_table(&table_size); + + /* Read the ID codes */ + ret = fch_spi_flash_cmd(&cmd, 1, idcode, sizeof(idcode)); + if (ret) + return -1; + + if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG)) { + printk(BIOS_SPEW, "SF: Got idcode: "); + for (i = 0; i < sizeof(idcode); i++) + printk(BIOS_SPEW, "%02x ", idcode[i]); + printk(BIOS_SPEW, "\n"); + } + + /* + * All solid state devices have vendor id defined by JEDEC specification JEP106, + * which originally allocated only 7 bits for it plus parity. When number of + * vendors exploded beyond 126, a banking proposition came maintaining + * compatibility with older vendors while allowing for 4 extra bits (16 banks) + * through the introduction of the concept "Continuation Code", denoted by the + * byte value of 0x7f. + * Examples: + * 0xfe, 0x60, 0x18, 0x00, 0x00, 0x00 => vendor 0xfe of bank o + * 0x7f, 0x7f, 0xfe, 0x60, 0x18, 0x00 => vendor 0xfe of bank 2 + * count the number of continuation code bytes + */ + for (shift = 0, idp = idcode; *idp == IDCODE_CONT_CODE; ++shift, ++idp) { + if (shift < IDCODE_CONT_LEN) + continue; + printk(BIOS_ERR, "unsupported ID code bank\n"); + return -1; + } + + printk(BIOS_INFO, "Manufacturer: %02x on bank %d\n", *idp, shift); + + /* search the table for matches in shift and id */ + for (i = 0; i < table_size; ++i) { + if (flash_ptr->shift == shift && flash_ptr->idcode == *idp) { + /* we have a match, call probe */ + if (flash_ptr->probe(spi, idp, flash) == 0) { + flash->vendor = idp[0]; + flash->model = (idp[1] << 8) | idp[2]; + set_ctrl_spi_data(flash); + fch_spi_flash_ops_init(flash); + return 0; + } + } + flash_ptr++; + } + + /* No match, return error. */ + return -1; +} + +static int protect_a_range(u32 value) +{ + u32 reg32; + u8 n; + + /* find a free protection register */ + for (n = 0; n < MAX_ROM_PROTECT_RANGES; n++) { + reg32 = pci_read_config32(SOC_LPC_DEV, ROM_PROTECT_RANGE_REG(n)); + if (!reg32) + break; + } + if (n == MAX_ROM_PROTECT_RANGES) + return -1; /* no free range */ + + pci_write_config32(SOC_LPC_DEV, ROM_PROTECT_RANGE_REG(n), value); + return 0; +} + +/* + * Protect range of SPI flash defined by region using the SPI flash controller. + * + * Note: Up to 4 ranges can be protected, though if a particular region requires more than one + * range, total number of regions decreases accordingly. Each range can be programmed to 4KiB or + * 64KiB granularity. + * + * Warning: If more than 1 region needs protection, and they need mixed protections (read/write) + * than start with the region that requires the most protection. After the restricted commands + * have been written, they can't be changed (write once). So if first region is write protection + * and second region is read protection, it's best to define first region as read and write + * protection. + */ +static int fch_spi_flash_protect(const struct spi_flash *flash, const struct region *region, + const enum ctrlr_prot_type type) +{ + int ret; + u32 reg32, rom_base, range_base; + size_t addr, len, gran_value, total_ranges, range; + bool granularity_64k = true; /* assume 64k granularity */ + + addr = region->offset; + len = region->size; + + reg32 = pci_read_config32(SOC_LPC_DEV, ROM_ADDRESS_RANGE2_START); + rom_base = WORD_TO_DWORD_UPPER(reg32); + if (addr < rom_base) + return -1; + range_base = addr % rom_base; + + /* Define granularity to be used */ + if (GRANULARITY_TEST_4k & range_base) + granularity_64k = false; /* use 4K granularity */ + if (GRANULARITY_TEST_4k & len) + granularity_64k = false; /* use 4K granularity */ + + /* Define the first range and total number of ranges required */ + if (granularity_64k) { + gran_value = 0x00010000; /* 64 KiB */ + range_base = range_base >> 16; + } else { + gran_value = 0x00001000; /* 4 KiB */ + range_base = range_base >> 12; + } + total_ranges = len / gran_value; + range_base &= RANGE_ADDR_MASK; + + /* Create reg32 to be written into a range register and program required ranges */ + reg32 = rom_base & ROM_BASE_MASK; + reg32 |= range_base; + if (granularity_64k) + reg32 |= RANGE_UNIT; + if (type & WRITE_PROTECT) + reg32 |= ROM_RANGE_WP; + if (type & READ_PROTECT) + reg32 |= ROM_RANGE_RP; + + for (range = 0; range < total_ranges; range++) { + ret = protect_a_range(reg32); + if (ret) + return ret; + /* + * Next range (lower 8 bits). Range points to the start address of a region. + * The range value must be multiplied by the granularity (which is also the + * size of the region) to get the actual offset from the SPI start address. + */ + reg32++; + } + + /* define commands to be blocked if in range */ + reg32 = 0; + if (type & WRITE_PROTECT) { + reg32 |= (ctrl_spi_data.write_enable_cmd << 24); + reg32 |= (ctrl_spi_data.write_cmd << 16); + reg32 |= (ctrl_spi_data.erase_cmd << 8); + } + if (type & READ_PROTECT) + reg32 |= ctrl_spi_data.read_cmd; + + /* Final steps to protect region */ + pci_write_config32(SOC_LPC_DEV, SPI_RESTRICTED_CMD1, reg32); + reg32 = spi_read32(SPI_CNTRL0); + reg32 &= ~SPI_ACCESS_MAC_ROM_EN; + spi_write32(SPI_CNTRL0, reg32); + + return 0; +} + +const struct spi_ctrlr fch_spi_flash_ctrlr = { + .max_xfer_size = SPI_FIFO_DEPTH, + .flash_probe = fch_spi_flash_probe, + .flash_protect = fch_spi_flash_protect, +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &fch_spi_flash_ctrlr, + .bus_start = 0, + .bus_end = 0, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/amd/common/block/spi/fch_spi_flash.c b/src/soc/amd/common/block/spi/fch_spi_flash.c new file mode 100644 index 0000000000..40dd0e2996 --- /dev/null +++ b/src/soc/amd/common/block/spi/fch_spi_flash.c @@ -0,0 +1,246 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Silverback Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +static void spi_flash_addr(u32 addr, u8 *cmd) +{ + /* cmd[0] is actual command */ + cmd[1] = addr >> 16; + cmd[2] = addr >> 8; + cmd[3] = addr >> 0; +} + +static int crop_chunk(unsigned int cmd_len, unsigned int buf_len) +{ + return min((SPI_FIFO_DEPTH - (cmd_len - 1)), buf_len); +} + +int fch_spi_flash_cmd_write(const u8 *cmd, size_t cmd_len, const void *data, size_t data_len) +{ + int ret; + u8 buff[SPI_FIFO_DEPTH + 1]; + + if ((cmd_len + data_len) > SPI_FIFO_DEPTH) + return -1; + memcpy(buff, cmd, cmd_len); + memcpy(buff + cmd_len, data, data_len); + + ret = fch_spi_flash_cmd(buff, cmd_len + data_len, NULL, 0); + if (ret) { + printk(BIOS_WARNING, "FCH_SF: Failed to send write command (%zu bytes): %d\n", + data_len, ret); + } + + return ret; +} + +static int fch_spi_flash_status(const struct spi_flash *flash, uint8_t *reg) +{ + int ret; + u8 status, cmd = CMD_READ_STATUS; + + ret = fch_spi_flash_cmd(&cmd, 1, &status, 1); + if (!ret) + *reg = status; + return ret; +} + +int fch_spi_wait_cmd_ready(unsigned long timeout) +{ + struct mono_time current, end; + int ret; + u8 status; + + timer_monotonic_get(¤t); + end = current; + mono_time_add_msecs(&end, timeout); + + do { + ret = fch_spi_flash_status(NULL, &status); + if (ret) + return -1; + if ((status & STATUS_WIP) == 0) + return 0; + timer_monotonic_get(¤t); + } while (!mono_time_after(¤t, &end)); + + printk(BIOS_DEBUG, "FCH_SF: timeout at %ld msec\n", timeout); + return -1; +} + +static int fch_spi_flash_erase(const struct spi_flash *flash, uint32_t offset, size_t len) +{ + u32 start, end, erase_size; + const struct spi_data *spi_data_ptr = get_ctrl_spi_data(); + int ret = -1; + u8 cmd[4]; + + erase_size = spi_data_ptr->sector_size; + if (offset % erase_size || len % erase_size) { + printk(BIOS_WARNING, "%s: Erase offset/length not multiple of erase size\n", + spi_data_ptr->name); + return -1; + } + if (len == 0) { + printk(BIOS_WARNING, "%s: Erase length cannot be 0\n", spi_data_ptr->name); + return -1; + } + + cmd[0] = spi_data_ptr->erase_cmd; + start = offset; + end = start + len; + + while (offset < end) { + spi_flash_addr(offset, cmd); + offset += erase_size; + +#if CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG) + printk(BIOS_DEBUG, "FCH_SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], + cmd[2], cmd[3], offset); +#endif + ret = fch_spi_enable_write(); + if (ret) + goto out; + + ret = fch_spi_flash_cmd_write(cmd, sizeof(cmd), NULL, 0); + if (ret) + goto out; + + ret = fch_spi_wait_cmd_ready(SPI_FLASH_PAGE_ERASE_TIMEOUT_MS); + if (ret) + goto out; + } + + printk(BIOS_DEBUG, "%s: Successfully erased %zu bytes @ %#x\n", spi_data_ptr->name, len, + start); + +out: + return ret; +} + +static int fch_spi_flash_read(const struct spi_flash *flash, uint32_t offset, size_t len, + void *buf) +{ + const struct spi_data *spi_data_ptr = get_ctrl_spi_data(); + uint8_t *data = buf; + int ret; + size_t xfer_len; + u8 cmd[5]; + + cmd[0] = spi_data_ptr->read_cmd; + cmd[4] = 0; + while (len) { + xfer_len = crop_chunk(spi_data_ptr->read_cmd_len, len); + spi_flash_addr(offset, cmd); + ret = fch_spi_flash_cmd(cmd, spi_data_ptr->read_cmd_len, data, xfer_len); + if (ret) { + printk(BIOS_WARNING, + "FCH_SF: Failed to send read command %#.2x(%#x, %#zx): %d\n", + cmd[0], offset, xfer_len, ret); + return ret; + } + offset += xfer_len; + data += xfer_len; + len -= xfer_len; + } + return 0; +} + +static int fch_spi_flash_write(const struct spi_flash *flash, uint32_t offset, size_t len, + const void *buf) +{ + unsigned long byte_addr; + unsigned long page_size; + const struct spi_data *spi_data_ptr = get_ctrl_spi_data(); + size_t chunk_len; + size_t actual, start = 0; + int ret = 0; + u8 cmd[4]; + + page_size = spi_data_ptr->page_size; + if (spi_data_ptr->non_standard == NON_STANDARD_SPI_SST) { + if (offset % 2) { + ret = non_standard_sst_byte_write(offset, buf); + len--; + start++; + offset++; + if (ret) + return ret; + } + if (page_size == 2) + return non_standard_sst_write_aai(offset, len, buf, start); + } + + for (actual = start; actual < len; actual += chunk_len) { + byte_addr = offset % page_size; + chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = crop_chunk(sizeof(cmd), chunk_len); + + cmd[0] = spi_data_ptr->write_cmd; + cmd[1] = (offset >> 16) & 0xff; + cmd[2] = (offset >> 8) & 0xff; + cmd[3] = offset & 0xff; +#if CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG) + printk(BIOS_DEBUG, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu" + "\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); +#endif + + ret = fch_spi_enable_write(); + if (ret < 0) { + printk(BIOS_WARNING, "%s: Enabling Write failed\n", spi_data_ptr->name); + goto out; + } + + ret = fch_spi_flash_cmd_write(cmd, sizeof(cmd), buf + actual, chunk_len); + if (ret < 0) { + printk(BIOS_WARNING, "%s: Page Program failed\n", spi_data_ptr->name); + goto out; + } + + ret = fch_spi_wait_cmd_ready(SPI_FLASH_PROG_TIMEOUT_MS); + if (ret) + goto out; + + offset += chunk_len; + } + +#if CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG) + printk(BIOS_DEBUG, "%s: Successfully programmed %zu bytes @ 0x%lx\n", + spi_data_ptr->name, len, (unsigned long)(offset - len)); +#endif + ret = 0; + +out: + return ret; +} + +static const struct spi_flash_ops fch_spi_flash_ops = { + .read = fch_spi_flash_read, + .write = fch_spi_flash_write, + .erase = fch_spi_flash_erase, + .status = fch_spi_flash_status, +}; + +void fch_spi_flash_ops_init(struct spi_flash *flash) +{ + flash->ops = &fch_spi_flash_ops; +} diff --git a/src/soc/amd/common/block/spi/fch_spi_special.c b/src/soc/amd/common/block/spi/fch_spi_special.c new file mode 100644 index 0000000000..456a3896f5 --- /dev/null +++ b/src/soc/amd/common/block/spi/fch_spi_special.c @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Silverback Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +int non_standard_sst_byte_write(u32 offset, const void *buf) +{ + int ret; + u8 cmd[4] = { + CMD_SST_BP, + offset >> 16, + offset >> 8, + offset, + }; + + ret = fch_spi_enable_write(); + if (ret) + return ret; + + ret = fch_spi_flash_cmd_write(cmd, sizeof(cmd), buf, 1); + if (ret) + return ret; + + return fch_spi_wait_cmd_ready(SPI_FLASH_PROG_TIMEOUT_MS); +} + +int non_standard_sst_write_aai(u32 offset, size_t len, const void *buf, size_t start) +{ + size_t actual, cmd_len; + int ret = 0; + u8 cmd[4]; + + ret = fch_spi_enable_write(); + if (ret) + goto done; + + cmd_len = 4; + cmd[0] = CMD_SST_AAI_WP; + cmd[1] = offset >> 16; + cmd[2] = offset >> 8; + cmd[3] = offset; + + for (actual = start; actual < len - 1; actual += 2) { +#if CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG) + printk(BIOS_DEBUG, "PP: 0x%p => cmd = { 0x%02x 0x%06lx }" + " chunk_len = 2\n", + buf + actual, cmd[0], (offset + actual)); +#endif + + ret = fch_spi_enable_write(); + if (ret < 0) { + printk(BIOS_WARNING, "SF: Enabling Write failed\n"); + break; + } + + ret = fch_spi_flash_cmd_write(cmd, cmd_len, buf + actual, 2); + if (ret < 0) { + printk(BIOS_WARNING, "SF: SST word Program failed\n"); + break; + } + + ret = fch_spi_wait_cmd_ready(SPI_FLASH_PROG_TIMEOUT_MS); + if (ret) + break; + + offset += 2; + cmd_len = 1; + } + /* If there is a single trailing byte, write it out */ + if (!ret && actual != len) + ret = non_standard_sst_byte_write(offset, buf + actual); +done: + return ret; +} diff --git a/src/soc/amd/common/block/spi/fch_spi_table.c b/src/soc/amd/common/block/spi/fch_spi_table.c new file mode 100644 index 0000000000..acea241ea4 --- /dev/null +++ b/src/soc/amd/common/block/spi/fch_spi_table.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Silverback Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +/* + * The following table holds all device probe functions + * + * shift: number of continuation bytes before the ID + * idcode: the expected IDCODE or 0xff for non JEDEC devices + * probe: the function to call + * + * Non JEDEC devices should be ordered in the table such that + * the probe functions with best detection algorithms come first. + * + * Several matching entries are permitted, they will be tried + * in sequence until a probe function returns non NULL. + * + * Probe functions will be given the idcode buffer starting at their + * manu id byte (the "idcode" in the table below). In other words, + * all of the continuation bytes will be skipped (the "shift" below). + */ + +const struct spi_flash_table flashes[] = { + /* Keep it sorted by define name */ +#if CONFIG(SPI_FLASH_ADESTO) + { 0, VENDOR_ID_ADESTO, spi_flash_probe_adesto, }, +#endif +#if CONFIG(SPI_FLASH_AMIC) + { 0, VENDOR_ID_AMIC, spi_flash_probe_amic, }, +#endif +#if CONFIG(SPI_FLASH_ATMEL) + { 0, VENDOR_ID_ATMEL, spi_flash_probe_atmel, }, +#endif +#if CONFIG(SPI_FLASH_EON) + { 0, VENDOR_ID_EON, spi_flash_probe_eon, }, +#endif +#if CONFIG(SPI_FLASH_GIGADEVICE) + { 0, VENDOR_ID_GIGADEVICE, spi_flash_probe_gigadevice, }, +#endif +#if CONFIG(SPI_FLASH_MACRONIX) + { 0, VENDOR_ID_MACRONIX, spi_flash_probe_macronix, }, +#endif +#if CONFIG(SPI_FLASH_SPANSION) + { 0, VENDOR_ID_SPANSION, spi_flash_probe_spansion, }, +#endif +#if CONFIG(SPI_FLASH_SST) + { 0, VENDOR_ID_SST, spi_flash_probe_sst, }, +#endif +#if CONFIG(SPI_FLASH_STMICRO) + { 0, VENDOR_ID_STMICRO, spi_flash_probe_stmicro, }, + { 0, VENDOR_ID_STMICRO_FF, spi_flash_probe_stmicro, }, +#endif +#if CONFIG(SPI_FLASH_WINBOND) + { 0, VENDOR_ID_WINBOND, spi_flash_probe_winbond, }, +#endif + /* Keep it sorted by best detection */ +}; + +const struct spi_flash_table *get_spi_flash_table(int *table_size) +{ + *table_size = (int)ARRAY_SIZE(flashes); + return &flashes[0]; +} diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 1c2ec8400f..f5f926e734 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -27,15 +27,17 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select X86_AMD_FIXED_MTRRS + select X86_AMD_INIT_SIPI select ACPI_AMD_HARDWARE_SLEEP_VALUES - select COLLECT_TIMESTAMPS_NO_TSC select DRIVERS_I2C_DESIGNWARE select GENERIC_GPIO_LIB - select GENERIC_UDELAY select IOAPIC select HAVE_USBDEBUG_OPTIONS - select SPI_FLASH if HAVE_ACPI_RESUME + select TSC_CONSTANT_RATE + select TSC_MONOTONIC_TIMER + select SOC_AMD_COMMON_BLOCK_SPI select TSC_SYNC_LFENCE + select UDELAY_TSC select COLLECT_TIMESTAMPS select SOC_AMD_PI select SOC_AMD_COMMON @@ -55,8 +57,6 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP select PARALLEL_MP_AP_WORK select HAVE_SMI_HANDLER - select POSTCAR_STAGE - select POSTCAR_CONSOLE select SSE2 select RTC @@ -67,10 +67,6 @@ config VBOOT select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH -config UDELAY_LAPIC_FIXED_FSB - int - default 200 - config HAVE_BOOTBLOCK bool default n diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 7f371928c1..38c00a8dd0 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -40,29 +40,25 @@ subdirs-y += ../../../cpu/x86/smm romstage-y += i2c.c romstage-y += romstage.c romstage-y += gpio.c -romstage-y += monotonic_timer.c romstage-y += pmutil.c romstage-y += reset.c romstage-y += smbus.c -romstage-y += ramtop.c +romstage-y += memmap.c romstage-$(CONFIG_PICASSO_UART) += uart.c romstage-y += tsc_freq.c romstage-y += southbridge.c -romstage-$(CONFIG_SPI_FLASH) += spi.c romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c verstage-y += gpio.c verstage-y += i2c.c -verstage-y += monotonic_timer.c verstage-y += pmutil.c verstage-y += reset.c verstage-$(CONFIG_PICASSO_UART) += uart.c verstage-y += tsc_freq.c -verstage-$(CONFIG_SPI_FLASH) += spi.c postcar-y += monotonic_timer.c postcar-$(CONFIG_PICASSO_UART) += uart.c -postcar-y += ramtop.c +postcar-y += memmap.c postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c postcar-y += tsc_freq.c @@ -72,7 +68,6 @@ ramstage-y += cpu.c ramstage-y += mca.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += gpio.c -ramstage-y += monotonic_timer.c ramstage-y += southbridge.c ramstage-y += northbridge.c ramstage-y += pmutil.c @@ -80,21 +75,18 @@ ramstage-y += reset.c ramstage-y += sata.c ramstage-y += sm.c ramstage-y += smbus.c -ramstage-y += ramtop.c +ramstage-y += memmap.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c ramstage-$(CONFIG_PICASSO_UART) += uart.c ramstage-y += usb.c ramstage-y += tsc_freq.c -ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-y += finalize.c -smm-y += monotonic_timer.c smm-y += smihandler.c smm-y += smi_util.c smm-y += tsc_freq.c smm-$(CONFIG_DEBUG_SMI) += uart.c -smm-$(CONFIG_SPI_FLASH) += spi.c smm-y += gpio.c CPPFLAGS_common += -I$(src)/soc/amd/picasso diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index daeb7b60b4..cc06496326 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -47,9 +48,6 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, - CONFIG_MAX_CPUS+1, IO_APIC2_ADDR, 24); - /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ /* 2: APIC 2 */ @@ -241,10 +239,7 @@ void generate_cpu_entries(struct device *device) { int cores, cpu; - /* Picasso is single node, just report # of cores */ - cores = pci_read_config32(SOC_NB_DEV, NB_CAPABILITIES2) & CMP_CAP_MASK; - cores++; /* number of cores is CmpCap+1 */ - + cores = get_cpu_count(); printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores); /* Generate BSP \_PR.P000 */ diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index cc264e6f85..04e41a1b57 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -48,12 +48,11 @@ Field (GNVS, ByteAcc, NoLock, Preserve) TPSV, 8, // 0x2F - Passive Threshold TMAX, 8, // 0x30 - CPU Tj_max Offset (0x34), // 0x34 - AOAC Device Enables - , 5, - IC0E, 1, // I2C0, 5 - IC1E, 1, // I2C1, 6 + , 7, IC2E, 1, // I2C2, 7 IC3E, 1, // I2C3, 8 - , 2, + IC4E, 1, // I2C4, 9 + , 1, UT0E, 1, // UART0, 11 UT1E, 1, // UART1, 12 , 2, diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 206fdfd0e1..b9eeadb4ae 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -484,16 +484,6 @@ Method(FWAK,0, Serialized) /* FCH _WAK */ FDDC(12, 3) } } - if(LEqual(\IC0E, zero)) { - if(LNotEqual(I0TD, 0x03)) { - FDDC(5, 3) - } - } - if(LEqual(\IC1E, zero)) { - if(LNotEqual(I1TD, 0x03)) { - FDDC(6, 3) - } - } if(LEqual(\IC2E, zero)) { if(LNotEqual(I2TD, 0x03)) { FDDC(7, 3) diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 5c2ca432f1..697011af2a 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2015-2016 Intel Corp. - * Copyright (C) 2017 Advanced Micro Devices, Inc. + * Copyright (C) 2017-2019 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -33,13 +34,12 @@ /* * MP and SMM loading initialization. */ -struct smm_relocation_attrs { - uint32_t smbase; - uint32_t tseg_base; - uint32_t tseg_mask; +struct smm_relocation_params { + msr_t tseg_base; + msr_t tseg_mask; }; -static struct smm_relocation_attrs relo_attrs; +static struct smm_relocation_params smm_reloc_params; /* * Do essential initialization tasks before APs can be fired up - @@ -54,46 +54,46 @@ static void pre_mp_init(void) x86_mtrr_check(); } -static int get_cpu_count(void) +int get_cpu_count(void) { - return (pci_read_config16(SOC_HT_DEV, D18F0_CPU_CNT) & CPU_CNT_MASK) - + 1; + return 1 + (cpuid_ecx(0x80000008) & 0xff); +} + +static void fill_in_relocation_params(struct smm_relocation_params *params) +{ + uintptr_t tseg_base; + size_t tseg_size; + + smm_region(&tseg_base, &tseg_size); + + params->tseg_base.lo = ALIGN_DOWN(tseg_base, 128 * KiB); + params->tseg_base.hi = 0; + params->tseg_mask.lo = ALIGN_DOWN(~(tseg_size - 1), 128 * KiB); + params->tseg_mask.hi = ((1 << (cpu_phys_address_size() - 32)) - 1); + + params->tseg_mask.lo |= SMM_TSEG_WB; } static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - uintptr_t smm_base; - size_t smm_size; - uintptr_t handler_base; - size_t handler_size; + printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - /* Initialize global tracking state. */ - smm_region(&smm_base, &smm_size); - smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); + fill_in_relocation_params(&smm_reloc_params); - relo_attrs.smbase = smm_base; - relo_attrs.tseg_base = relo_attrs.smbase; - relo_attrs.tseg_mask = ALIGN_DOWN(~(smm_size - 1), 128 * KiB); - relo_attrs.tseg_mask |= SMM_TSEG_WB; - - *perm_smbase = handler_base; - *perm_smsize = handler_size; + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); } static void relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) { - msr_t tseg_base, tseg_mask; + struct smm_relocation_params *relo_params = &smm_reloc_params; amd64_smm_state_save_area_t *smm_state; - tseg_base.lo = relo_attrs.tseg_base; - tseg_base.hi = 0; - wrmsr(SMM_ADDR_MSR, tseg_base); - tseg_mask.lo = relo_attrs.tseg_mask; - tseg_mask.hi = ((1 << (cpu_phys_address_size() - 32)) - 1); - wrmsr(SMM_MASK_MSR, tseg_mask); + wrmsr(SMM_ADDR_MSR, relo_params->tseg_base); + wrmsr(SMM_MASK_MSR, relo_params->tseg_mask); + smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase); smm_state->smbase = staggered_smbase; } @@ -118,22 +118,22 @@ void picasso_init_cpus(struct device *dev) set_warm_reset_flag(); } -static void model_15_init(struct device *dev) +static void model_17_init(struct device *dev) { check_mca(); setup_lapic(); } static struct device_operations cpu_dev_ops = { - .init = model_15_init, + .init = model_17_init, }; static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x670f00 }, + { X86_VENDOR_AMD, 0x810f81 }, { 0, 0 }, }; -static const struct cpu_driver model_15 __cpu_driver = { +static const struct cpu_driver model_17 __cpu_driver = { .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/soc/amd/picasso/finalize.c b/src/soc/amd/picasso/finalize.c index 5a4627a432..0ec7bd9218 100644 --- a/src/soc/amd/picasso/finalize.c +++ b/src/soc/amd/picasso/finalize.c @@ -44,7 +44,7 @@ static void finalize_cores(void) int r; printk(BIOS_SPEW, "Lock SMM configuration\n"); - r = mp_run_on_all_cpus(per_core_finalize, NULL, 10 * USECS_PER_MSEC); + r = mp_run_on_all_cpus(per_core_finalize, NULL); if (r) printk(BIOS_WARNING, "Failed to finalize all cores\n"); } diff --git a/src/soc/amd/picasso/gpio.c b/src/soc/amd/picasso/gpio.c index f63a0d93a4..ea868ebd02 100644 --- a/src/soc/amd/picasso/gpio.c +++ b/src/soc/amd/picasso/gpio.c @@ -22,6 +22,7 @@ #include static const struct soc_amd_event gpio_event_table[] = { + { GPIO_0, GEVENT_21 }, /* GPIO0 may only be used as PWR_BTN_L in ACPI */ { GPIO_1, GEVENT_19 }, { GPIO_2, GEVENT_8 }, { GPIO_3, GEVENT_2 }, @@ -31,10 +32,6 @@ static const struct soc_amd_event gpio_event_table[] = { { GPIO_7, GEVENT_11 }, { GPIO_8, GEVENT_23 }, { GPIO_9, GEVENT_22 }, - { GPIO_11, GEVENT_18 }, - { GPIO_13, GEVENT_21 }, - { GPIO_14, GEVENT_6 }, - { GPIO_15, GEVENT_20 }, { GPIO_16, GEVENT_12 }, { GPIO_17, GEVENT_13 }, { GPIO_18, GEVENT_14 }, @@ -42,10 +39,13 @@ static const struct soc_amd_event gpio_event_table[] = { { GPIO_22, GEVENT_3 }, { GPIO_23, GEVENT_16 }, { GPIO_24, GEVENT_15 }, - { GPIO_65, GEVENT_0 }, - { GPIO_66, GEVENT_1 }, - { GPIO_68, GEVENT_9 }, - { GPIO_69, GEVENT_17 }, + { GPIO_40, GEVENT_20 }, + { GPIO_84, GEVENT_18 }, + { GPIO_86, GEVENT_9 }, + { GPIO_89, GEVENT_0 }, + { GPIO_90, GEVENT_1 }, + { GPIO_91, GEVENT_6 }, + { GPIO_129, GEVENT_17 }, }; void soc_route_sci(uint8_t event) diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 9fe15886d9..87866433d1 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -25,25 +25,21 @@ #include #include "chip.h" -#define I2C_BUS_ADDRESS(x) (I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * (x)) -#define I2CA_BASE_ADDRESS (I2C_BUS_ADDRESS(0)) -#define I2CB_BASE_ADDRESS (I2C_BUS_ADDRESS(1)) -#define I2CC_BASE_ADDRESS (I2C_BUS_ADDRESS(2)) -#define I2CD_BASE_ADDRESS (I2C_BUS_ADDRESS(3)) - /* Global to provide access to chip.c */ const char *i2c_acpi_name(const struct device *dev); static const uintptr_t i2c_bus_address[] = { - I2CA_BASE_ADDRESS, - I2CB_BASE_ADDRESS, - I2CC_BASE_ADDRESS, - I2CD_BASE_ADDRESS, + APU_I2C2_BASE, + APU_I2C3_BASE, + APU_I2C4_BASE, /* slave device only */ }; uintptr_t dw_i2c_base_address(unsigned int bus) { - return bus < I2C_DEVICE_COUNT ? i2c_bus_address[bus] : 0; + if (bus < APU_I2C_MIN_BUS || bus > APU_I2C_MAX_BUS) + return 0; + + return i2c_bus_address[bus - APU_I2C_MIN_BUS]; } static const struct soc_amd_picasso_config *get_soc_config(void) @@ -63,7 +59,7 @@ const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) { const struct soc_amd_picasso_config *config; - if (bus >= ARRAY_SIZE(i2c_bus_address)) + if (bus < APU_I2C_MIN_BUS || bus > APU_I2C_MAX_BUS) return NULL; config = get_soc_config(); @@ -76,14 +72,12 @@ const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) const char *i2c_acpi_name(const struct device *dev) { switch (dev->path.mmio.addr) { - case I2CA_BASE_ADDRESS: - return "I2CA"; - case I2CB_BASE_ADDRESS: - return "I2CB"; - case I2CC_BASE_ADDRESS: + case APU_I2C2_BASE: return "I2CC"; - case I2CD_BASE_ADDRESS: + case APU_I2C3_BASE: return "I2CD"; + case APU_I2C4_BASE: + return "I2CE"; default: return NULL; } @@ -92,22 +86,24 @@ const char *i2c_acpi_name(const struct device *dev) int dw_i2c_soc_dev_to_bus(struct device *dev) { switch (dev->path.mmio.addr) { - case I2CA_BASE_ADDRESS: - return 0; - case I2CB_BASE_ADDRESS: - return 1; - case I2CC_BASE_ADDRESS: + case APU_I2C2_BASE: return 2; - case I2CD_BASE_ADDRESS: + case APU_I2C3_BASE: return 3; + case APU_I2C4_BASE: + return 4; } return -1; } +__weak void mainboard_i2c_override(int bus, uint32_t *pad_settings) { } + static void dw_i2c_soc_init(bool is_early_init) { size_t i; const struct soc_amd_picasso_config *config; + uint32_t pad_ctrl; + int misc_reg; config = get_soc_config(); @@ -120,8 +116,28 @@ static void dw_i2c_soc_init(bool is_early_init) if (cfg->early_init != is_early_init) continue; - if (dw_i2c_init(i, cfg)) + if (dw_i2c_init(i, cfg)) { printk(BIOS_ERR, "Failed to init i2c bus %zd\n", i); + continue; + } + + misc_reg = MISC_I2C0_PAD_CTRL + sizeof(uint32_t) * i; + pad_ctrl = misc_read32(misc_reg); + + pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK; + pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL; + + pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK; + pad_ctrl |= I2C_PAD_CTRL_RX_SEL_3_3V; + + pad_ctrl &= ~I2C_PAD_CTRL_FALLSLEW_MASK; + pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD + ? I2C_PAD_CTRL_FALLSLEW_STD + : I2C_PAD_CTRL_FALLSLEW_LOW; + pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN; + + mainboard_i2c_override(i, &pad_ctrl); + misc_write32(misc_reg, pad_ctrl); } } @@ -152,10 +168,9 @@ struct device_operations picasso_i2c_mmio_ops = { * conversion of all SCL pins to input with no pull. */ static const struct soc_amd_gpio i2c_2_gpi[] = { - PAD_GPI(I2C0_SCL_PIN, PULL_NONE), - PAD_GPI(I2C1_SCL_PIN, PULL_NONE), PAD_GPI(I2C2_SCL_PIN, PULL_NONE), PAD_GPI(I2C3_SCL_PIN, PULL_NONE), + /* I2C4 is a slave device only */ }; #define saved_pins_count ARRAY_SIZE(i2c_2_gpi) @@ -210,10 +225,6 @@ void sb_reset_i2c_slaves(void) * needed after the writes to force the posted write to complete. */ for (j = 0; j < 9; j++) { - if (control & GPIO_I2C0_SCL) - write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_LOW); - if (control & GPIO_I2C1_SCL) - write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_LOW); if (control & GPIO_I2C2_SCL) write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_LOW); if (control & GPIO_I2C3_SCL) @@ -222,10 +233,6 @@ void sb_reset_i2c_slaves(void) read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ udelay(4); /* 4usec gets 85KHz for 1 pin, 70KHz for 4 pins */ - if (control & GPIO_I2C0_SCL) - write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_HIGH); - if (control & GPIO_I2C1_SCL) - write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_HIGH); if (control & GPIO_I2C2_SCL) write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_HIGH); if (control & GPIO_I2C3_SCL) diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index 7bc1810dba..e57d2d3187 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -22,6 +22,7 @@ #define SOC_EARLY_VMTRR_TEMPRAM 2 void picasso_init_cpus(struct device *dev); +int get_cpu_count(void); void check_mca(void); #endif /* __PICASSO_CPU_H__ */ diff --git a/src/soc/amd/picasso/include/soc/gpio.h b/src/soc/amd/picasso/include/soc/gpio.h index 411144beb6..6e4357ed45 100644 --- a/src/soc/amd/picasso/include/soc/gpio.h +++ b/src/soc/amd/picasso/include/soc/gpio.h @@ -25,7 +25,7 @@ /* The following sections describe only the GPIOs defined for this SOC */ -#define SOC_GPIO_TOTAL_PINS 149 +#define SOC_GPIO_TOTAL_PINS 145 /* Bank 0: GPIO_0 - GPIO_62 */ #define GPIO_0 0 @@ -43,7 +43,6 @@ #define GPIO_12 12 #define GPIO_13 13 #define GPIO_14 14 -#define GPIO_15 15 #define GPIO_16 16 #define GPIO_17 17 #define GPIO_18 18 @@ -53,22 +52,20 @@ #define GPIO_22 22 #define GPIO_23 23 #define GPIO_24 24 -#define GPIO_25 25 #define GPIO_26 26 -#define GPIO_39 39 +#define GPIO_27 27 +#define GPIO_29 29 +#define GPIO_30 30 +#define GPIO_31 31 +#define GPIO_32 32 #define GPIO_40 40 #define GPIO_42 42 /* Bank 1: GPIO_64 - GPIO_127 */ -#define GPIO_64 64 -#define GPIO_65 65 -#define GPIO_66 66 #define GPIO_67 67 #define GPIO_68 68 #define GPIO_69 69 #define GPIO_70 70 -#define GPIO_71 71 -#define GPIO_72 72 #define GPIO_74 74 #define GPIO_75 75 #define GPIO_76 76 @@ -81,34 +78,25 @@ #define GPIO_90 90 #define GPIO_91 91 #define GPIO_92 92 -#define GPIO_93 93 -#define GPIO_95 95 -#define GPIO_96 96 -#define GPIO_97 97 -#define GPIO_98 98 -#define GPIO_99 99 -#define GPIO_100 100 -#define GPIO_101 101 -#define GPIO_102 102 +#define GPIO_103 103 +#define GPIO_104 104 +#define GPIO_105 105 +#define GPIO_106 106 +#define GPIO_107 107 +#define GPIO_108 108 +#define GPIO_109 109 #define GPIO_113 113 #define GPIO_114 114 #define GPIO_115 115 #define GPIO_116 116 -#define GPIO_117 117 -#define GPIO_118 118 -#define GPIO_119 119 #define GPIO_120 120 #define GPIO_121 121 -#define GPIO_122 122 -#define GPIO_126 126 /* Bank 2: GPIO_128 - GPIO_183 */ #define GPIO_129 129 #define GPIO_130 130 #define GPIO_131 131 #define GPIO_132 132 -#define GPIO_133 133 -#define GPIO_134 134 #define GPIO_135 135 #define GPIO_136 136 #define GPIO_137 137 @@ -119,15 +107,11 @@ #define GPIO_142 142 #define GPIO_143 143 #define GPIO_144 144 -#define GPIO_145 145 -#define GPIO_146 146 -#define GPIO_147 147 -#define GPIO_148 148 #define GPIO_SCL_HIGH 0 #define GPIO_SCL_LOW GPIO_OUTPUT_ENABLE -/* IOMUX function names and values generated from BKDG. */ +/* IOMUX function names and values generated from PPR. */ #define GPIO_0_IOMUX_PWR_BTN_L 0 #define GPIO_0_IOMUX_GPIOxx 1 #define GPIO_1_IOMUX_SYS_RESET_L 0 @@ -139,35 +123,32 @@ #define GPIO_5_IOMUX_GPIOxx 0 #define GPIO_5_IOMUX_DEVSLP0_S5 1 #define GPIO_6_IOMUX_GPIOxx 0 -#define GPIO_6_IOMUX_LDT_RST_L 1 +#define GPIO_6_IOMUX_DEVSLP1_S5 1 #define GPIO_7_IOMUX_GPIOxx 0 -#define GPIO_7_IOMUX_LDT_PWROK 1 +#define GPIO_7_IOMUX_ACP_I2S_SDIN 1 #define GPIO_8_IOMUX_GPIOxx 0 -#define GPIO_8_IOMUX_SerPortTX_OUT 1 +#define GPIO_8_IOMUX_ACP_I2S_LRCLK 1 #define GPIO_9_IOMUX_GPIOxx 0 -#define GPIO_9_IOMUX_SerPortRX_OUT 1 -#define GPIO_10_IOMUX_S0A3_GPIO 0 -#define GPIO_10_IOMUX_GPIOxx 1 +#define GPIO_9_IOMUX_SGPIO_DATAOUT 1 +#define GPIO_9_IOMUX_MDIO1_SCL 2 +#define GPIO_10_IOMUX_GPIOxx 0 +#define GPIO_10_IOMUX_S0A3_GPIO 1 +#define GPIO_10_IOMUX_SGPIO_CLK 2 +#define GPIO_10_IOMUX_MDIO0_SCL 3 #define GPIO_11_IOMUX_GPIOxx 0 -#define GPIO_11_IOMUX_USB_OC7_L 1 -#define GPIO_12_IOMUX_IR_LED_L 0 -#define GPIO_12_IOMUX_LLB_L 1 -#define GPIO_12_IOMUX_GPIOxx 2 +#define GPIO_11_IOMUX_BLINK 1 +#define GPIO_12_IOMUX_LLB_L 0 +#define GPIO_12_IOMUX_GPIOxx 1 #define GPIO_13_IOMUX_USB_OC5_L 0 #define GPIO_13_IOMUX_GPIOxx 1 -#define GPIO_14_IOMUX_USB_OC6_L 0 +#define GPIO_14_IOMUX_USB_OC4_L 0 #define GPIO_14_IOMUX_GPIOxx 1 -#define GPIO_15_IOMUX_IR_RX1 0 -#define GPIO_15_IOMUX_GPIOxx 1 #define GPIO_16_IOMUX_USB_OC0_L 0 -#define GPIO_16_IOMUX_TRST_L 1 -#define GPIO_16_IOMUX_GPIOxx 2 +#define GPIO_16_IOMUX_GPIOxx 1 #define GPIO_17_IOMUX_USB_OC1_L 0 -#define GPIO_17_IOMUX_TDI 1 -#define GPIO_17_IOMUX_GPIOxx 2 +#define GPIO_17_IOMUX_GPIOxx 1 #define GPIO_18_IOMUX_USB_OC2_L 0 -#define GPIO_18_IOMUX_TCK 1 -#define GPIO_18_IOMUX_GPIOxx 2 +#define GPIO_18_IOMUX_GPIOxx 1 #define GPIO_19_IOMUX_SCL1 0 #define GPIO_19_IOMUX_I2C3_SCL 1 #define GPIO_19_IOMUX_GPIOxx 2 @@ -175,66 +156,107 @@ #define GPIO_20_IOMUX_I2C3_SDA 1 #define GPIO_20_IOMUX_GPIOxx 2 #define GPIO_21_IOMUX_LPC_PD_L 0 -#define GPIO_21_IOMUX_GPIOxx 1 +#define GPIO_21_IOMUX_EMMC_CMD 1 +#define GPIO_21_IOMUX_GPIOxx 2 #define GPIO_22_IOMUX_LPC_PME_L 0 -#define GPIO_22_IOMUX_GPIOxx 1 -#define GPIO_23_IOMUX_USB_OC4_L 0 -#define GPIO_23_IOMUX_IR_RX0 1 -#define GPIO_23_IOMUX_GPIOxx 2 +#define GPIO_22_IOMUX_EMMC_PRW_CTRL 1 +#define GPIO_22_IOMUX_GPIOxx 2 +#define GPIO_23_IOMUX_ACP_PRES 0 +#define GPIO_23_IOMUX_SGPIO_LOAD 1 +#define GPIO_23_IOMUX_MDIO1_SDA 2 +#define GPIO_23_IOMUX_GPIOxx 3 #define GPIO_24_IOMUX_USB_OC3_L 0 #define GPIO_24_IOMUX_GPIOxx 1 -#define GPIO_25_IOMUX_SD0_CD 0 -#define GPIO_25_IOMUX_GPIOxx 1 #define GPIO_26_IOMUX_PCIE_RST_L 0 #define GPIO_26_IOMUX_GPIOxx 1 -#define GPIO_39_IOMUX_VDDGFX_PD 0 -#define GPIO_39_IOMUX_GPIOxx 1 +#define GPIO_27_IOMUX_GPIOxx 0 +#define GPIO_27_IOMUX_PCIE_RST1_L 1 +#define GPIO_29_IOMUX_SPI_TPM_CS_L 0 +#define GPIO_29_IOMUX_GPIOxx 1 +#define GPIO_29_IOMUX_USB_OC6_L 2 +#define GPIO_30_IOMUX_SPI_CS2_L 0 +#define GPIO_30_IOMUX_ESPI_CS_L 1 +#define GPIO_30_IOMUX_GPIOxx 2 +#define GPIO_31_IOMUX_SPI_CS3_L 0 +#define GPIO_31_IOMUX_ESPI_CS_L 1 +#define GPIO_31_IOMUX_GPIOxx 2 +#define GPIO_32_IOMUX_LPC_RST_L 0 +#define GPIO_32_IOMUX_SD_WP_L 1 +#define GPIO_32_IOMUX_GPIOxx 2 #define GPIO_40_IOMUX_GPIOxx 0 -#define GPIO_42_IOMUX_S5_MUX_CTRL 0 -#define GPIO_42_IOMUX_GPIOxx 1 -#define GPIO_64_IOMUX_GPIOxx 0 -#define GPIO_65_IOMUX_GPIOxx 0 -#define GPIO_66_IOMUX_GPIOxx 0 -#define GPIO_67_IOMUX_GPIOxx 0 -#define GPIO_67_IOMUX_DEVSLP0 1 +#define GPIO_40_IOMUX_SGPIO_DATAIN 1 +#define GPIO_40_IOMUX_MDIO0_SDA 2 +#define GPIO_42_IOMUX_GPIOxx 0 +#define GPIO_67_IOMUX_SPI_ROM_REQ 0 +#define GPIO_67_IOMUX_GPIOxx 1 +#define GPIO_68_IOMUX_GPIOxx 0 +#define GPIO_68_IOMUX_EMMC_CD 1 #define GPIO_69_IOMUX_GPIOxx 0 -#define GPIO_69_IOMUX_SGPIO_LOAD 1 #define GPIO_70_IOMUX_GPIOxx 0 -#define GPIO_70_IOMUX_DEVSLP1 1 +#define GPIO_70_IOMUX_EMMC_CLK 1 +#define GPIO_70_IOMUX_SD_CLK 2 #define GPIO_74_IOMUX_LPCCLK0 0 -#define GPIO_74_IOMUX_GPIOxx 1 +#define GPIO_74_IOMUX_EMMC_DATA4 1 +#define GPIO_74_IOMUX_GPIOxx 2 #define GPIO_75_IOMUX_LPCCLK1 0 -#define GPIO_75_IOMUX_GPIOxx 1 -#define GPIO_76_IOMUX_GPIOxx 0 -#define GPIO_76_IOMUX_SPI_TPM_CS_L 1 +#define GPIO_75_IOMUX_EMMC_DATA6 1 +#define GPIO_75_IOMUX_GPIOxx 2 +#define GPIO_76_IOMUX_SPI_ROM_GNT 0 +#define GPIO_76_IOMUX_GPIOxx 1 #define GPIO_84_IOMUX_FANIN0 0 #define GPIO_84_IOMUX_GPIOxx 1 #define GPIO_85_IOMUX_FANOUT0 0 #define GPIO_85_IOMUX_GPIOxx 1 +#define GPIO_86_IOMUX_LPC_SMI_L 0 #define GPIO_86_IOMUX_GPIOxx 1 #define GPIO_87_IOMUX_SERIRQ 0 -#define GPIO_87_IOMUX_GPIOxx 1 +#define GPIO_87_IOMUX_EMMC_DATA7 1 +#define GPIO_87_IOMUX_GPIOxx 2 #define GPIO_88_IOMUX_LPC_CLKRUN_L 0 -#define GPIO_88_IOMUX_GPIOxx 1 -#define GPIO_90_IOMUX_GPIOxx 0 +#define GPIO_88_IOMUX_EMMC_DATA5 1 +#define GPIO_88_IOMUX_GPIOxx 2 +#define GPIO_89_IOMUX_GENINT1_L 0 +#define GPIO_89_IOMUX_PSP_INTR0 1 +#define GPIO_89_IOMUX_GPIOxx 2 +#define GPIO_90_IOMUX_GENINT2_L 0 +#define GPIO_90_IOMUX_PSP_INTR1 1 +#define GPIO_90_IOMUX_GPIOxx 2 #define GPIO_91_IOMUX_SPKR 0 #define GPIO_91_IOMUX_GPIOxx 1 #define GPIO_92_IOMUX_CLK_REQ0_L 0 #define GPIO_92_IOMUX_SATA_IS0_L 1 #define GPIO_92_IOMUX_SATA_ZP0_L 2 #define GPIO_92_IOMUX_GPIOxx 3 -#define GPIO_93_IOMUX_SD0_LED 0 -#define GPIO_93_IOMUX_GPIOxx 1 #define GPIO_95_IOMUX_GPIOxx 0 +#define GPIO_95_IOMUX_SD0_CLK 1 #define GPIO_96_IOMUX_GPIOxx 0 +#define GPIO_96_IOMUX_SD0_CMD 1 #define GPIO_97_IOMUX_GPIOxx 0 +#define GPIO_97_IOMUX_SD0_DATA0 1 #define GPIO_98_IOMUX_GPIOxx 0 +#define GPIO_98_IOMUX_SD0_DATA1 1 #define GPIO_99_IOMUX_GPIOxx 0 +#define GPIO_99_IOMUX_SD0_DATA2 1 #define GPIO_100_IOMUX_GPIOxx 0 -#define GPIO_101_IOMUX_SD0_WP 0 -#define GPIO_101_IOMUX_GPIOxx 1 -#define GPIO_102_IOMUX_SD0_PWR_CTRL 0 -#define GPIO_102_IOMUX_GPIOxx 1 +#define GPIO_100_IOMUX_SD0_DATA3 1 +#define GPIO_104_IOMUX_LAD0 0 +#define GPIO_104_IOMUX_EMMC_SDATA0 1 +#define GPIO_104_IOMUX_GPIOxx 3 +#define GPIO_105_IOMUX_LAD1 0 +#define GPIO_105_IOMUX_EMMC_DATA1 1 +#define GPIO_105_IOMUX_GPIOxx 3 +#define GPIO_106_IOMUX_LAD2 0 +#define GPIO_106_IOMUX_EMMC_DATA2 1 +#define GPIO_106_IOMUX_GPIOxx 3 +#define GPIO_107_IOMUX_LAD3 0 +#define GPIO_107_IOMUX_EMMC_DATA3 1 +#define GPIO_107_IOMUX_GPIOxx 3 +#define GPIO_108_IOMUX_LDRQ0_L 0 +#define GPIO_108_IOMUX_ESPI_ALERT_D1 1 +#define GPIO_108_IOMUX_GPIOxx 2 +#define GPIO_109_IOMUX_LFRAME_L 0 +#define GPIO_109_IOMUX_EMMC_DS 1 +#define GPIO_109_IOMUX_GPIOxx 2 #define GPIO_113_IOMUX_SCL0 0 #define GPIO_113_IOMUX_I2C2_SCL 1 #define GPIO_113_IOMUX_GPIOxx 2 @@ -245,21 +267,10 @@ #define GPIO_115_IOMUX_GPIOxx 1 #define GPIO_116_IOMUX_CLK_REQ2_L 0 #define GPIO_116_IOMUX_GPIOxx 1 -#define GPIO_117_IOMUX_ESPI_CLK 0 -#define GPIO_117_IOMUX_GPIOxx 1 -#define GPIO_118_IOMUX_SPI_CS1_L 0 -#define GPIO_118_IOMUX_GPIOxx 1 -#define GPIO_119_IOMUX_SPI_CS2_L 0 -#define GPIO_119_IOMUX_ESPI_CS_L 1 -#define GPIO_119_IOMUX_GPIOxx 2 -#define GPIO_120_IOMUX_ESPI_DAT1 0 +#define GPIO_120_IOMUX_CLK_REQ5_L 0 #define GPIO_120_IOMUX_GPIOxx 1 -#define GPIO_121_IOMUX_ESPI_DAT0 0 +#define GPIO_121_IOMUX_CLK_REQ6_L 0 #define GPIO_121_IOMUX_GPIOxx 1 -#define GPIO_122_IOMUX_ESPI_DAT2 0 -#define GPIO_122_IOMUX_GPIOxx 1 -#define GPIO_126_IOMUX_GA20IN 0 -#define GPIO_126_IOMUX_GPIOxx 1 #define GPIO_129_IOMUX_KBRST_L 0 #define GPIO_129_IOMUX_GPIOxx 1 #define GPIO_130_IOMUX_SATA_ACT_L 0 @@ -268,39 +279,33 @@ #define GPIO_131_IOMUX_SATA_IS1_L 1 #define GPIO_131_IOMUX_SATA_ZP1_L 2 #define GPIO_131_IOMUX_GPIOxx 3 -#define GPIO_132_IOMUX_CLK_REQG_L 0 +#define GPIO_132_IOMUX_CLK_REQ4_L 0 #define GPIO_132_IOMUX_OSCIN 1 #define GPIO_132_IOMUX_GPIOxx 2 -#define GPIO_133_IOMUX_ESPI_DAT3 0 -#define GPIO_133_IOMUX_GPIOxx 1 #define GPIO_135_IOMUX_UART0_CTS_L 0 -#define GPIO_135_IOMUX_GPIOxx 1 +#define GPIO_135_IOMUX_UART2_RXD 1 +#define GPIO_135_IOMUX_GPIOxx 2 #define GPIO_136_IOMUX_UART0_RXD 0 #define GPIO_136_IOMUX_GPIOxx 1 #define GPIO_137_IOMUX_UART0_RTS_L 0 -#define GPIO_137_IOMUX_GPIOxx 1 +#define GPIO_137_IOMUX_UART2_TXD 1 +#define GPIO_137_IOMUX_GPIOxx 2 #define GPIO_138_IOMUX_UART0_TXD 0 #define GPIO_138_IOMUX_GPIOxx 1 #define GPIO_139_IOMUX_UART0_INTR 0 #define GPIO_139_IOMUX_GPIOxx 1 #define GPIO_140_IOMUX_UART1_CTS_L 0 -#define GPIO_140_IOMUX_GPIOxx 1 +#define GPIO_140_IOMUX_UART3_TXD 1 +#define GPIO_140_IOMUX_GPIOxx 2 #define GPIO_141_IOMUX_UART1_RXD 0 #define GPIO_141_IOMUX_GPIOxx 1 #define GPIO_142_IOMUX_UART1_RTS_L 0 -#define GPIO_142_IOMUX_GPIOxx 1 +#define GPIO_142_IOMUX_UART3_RXD 1 +#define GPIO_142_IOMUX_GPIOxx 2 #define GPIO_143_IOMUX_UART1_TXD 0 #define GPIO_143_IOMUX_GPIOxx 1 #define GPIO_144_IOMUX_UART1_INTR 0 #define GPIO_144_IOMUX_GPIOxx 1 -#define GPIO_145_IOMUX_I2C0_SCL 0 -#define GPIO_145_IOMUX_GPIOxx 1 -#define GPIO_146_IOMUX_I2C0_SDA 0 -#define GPIO_146_IOMUX_GPIOxx 1 -#define GPIO_147_IOMUX_I2C1_SCL 0 -#define GPIO_147_IOMUX_GPIOxx 1 -#define GPIO_148_IOMUX_I2C1_SDA 0 -#define GPIO_148_IOMUX_GPIOxx 1 #define GPIO_2_EVENT GEVENT_8 diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h index fb9b113c8e..d129fc1f1f 100644 --- a/src/soc/amd/picasso/include/soc/i2c.h +++ b/src/soc/amd/picasso/include/soc/i2c.h @@ -23,24 +23,18 @@ struct soc_amd_i2c_save { uint8_t mux_value; }; -#define GPIO_I2C0_SCL BIT(0) -#define GPIO_I2C1_SCL BIT(1) -#define GPIO_I2C2_SCL BIT(2) -#define GPIO_I2C3_SCL BIT(3) -#define GPIO_I2C_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define GPIO_I2C2_SCL BIT(2) +#define GPIO_I2C3_SCL BIT(3) +#define GPIO_I2C_MASK (BIT(2) | BIT(3)) -#define I2C0_SCL_PIN GPIO_145 -#define I2C1_SCL_PIN GPIO_147 #define I2C2_SCL_PIN GPIO_113 #define I2C3_SCL_PIN GPIO_19 -#define GPIO_I2C0_ADDRESS GPIO_BANK2_CONTROL(I2C0_SCL_PIN) -#define GPIO_I2C1_ADDRESS GPIO_BANK2_CONTROL(I2C1_SCL_PIN) #define GPIO_I2C2_ADDRESS GPIO_BANK1_CONTROL(I2C2_SCL_PIN) #define GPIO_I2C3_ADDRESS GPIO_BANK0_CONTROL(I2C3_SCL_PIN) +#define GPIO_SCL_HIGH 0 +#define GPIO_SCL_LOW GPIO_OUTPUT_ENABLE -#define I2C0_SCL_PIN_IOMUX_GPIOxx GPIO_145_IOMUX_GPIOxx -#define I2C1_SCL_PIN_IOMUX_GPIOxx GPIO_147_IOMUX_GPIOxx #define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_113_IOMUX_GPIOxx #define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 1d89fd7ec0..ad0e7c4609 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -18,8 +18,9 @@ #define __SOC_PICASSO_IOMAP_H__ /* MMIO Ranges */ +/* IO_APIC_ADDR defined in arch/x86 0xfec00000 */ #define SPI_BASE_ADDRESS 0xfec10000 -#define IO_APIC2_ADDR 0xfec20000 +#define ESPI_BASE_ADDRESS 0xfec20000 /* * AcpiMmio blocks are at fixed offsets from FED8_0000h and enabled in PMx04[1]. @@ -43,9 +44,16 @@ #define ALINK_AHB_ADDRESS 0xfedc0000 /* I2C fixed address */ -#define I2C_BASE_ADDRESS 0xfedc2000 +#define APU_I2C2_BASE 0xfedc4000 +#define APU_I2C3_BASE 0xfedc5000 +#define APU_I2C4_BASE 0xfedc6000 +#define APU_I2C_MIN_BUS 2 +#define APU_I2C_MAX_BUS 4 +#define APU_I2C_BLOCK_SIZE 0x1000 +#define I2C_BASE_ADDRESS APU_I2C2_BASE #define I2C_DEVICE_SIZE 0x00001000 -#define I2C_DEVICE_COUNT 4 +#define I2C_DEVICE_COUNT 3 + #if CONFIG(HPET_ADDRESS_OVERRIDE) #error HPET address override is not allowed and must be fixed at 0xfed00000 @@ -69,6 +77,7 @@ #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */ #define ACPI_PM_TMR_BLK (PICASSO_ACPI_IO_BASE + 0x18) /* 4 bytes */ +#define NCP_ERR 0xf0 #define SMB_BASE_ADDR 0xb00 #define PM2_INDEX 0xcd0 #define PM2_DATA 0xcd1 diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h index 57373c9a08..e423ab1aa7 100644 --- a/src/soc/amd/picasso/include/soc/northbridge.h +++ b/src/soc/amd/picasso/include/soc/northbridge.h @@ -20,28 +20,6 @@ #include #include -/* D0F0 - Root Complex */ - -/* NB IOAPIC registers */ -#define NB_IOAPIC_INDEX 0xf8 -#define NB_IOAPIC_DATA 0xfc -#define NB_IOAPIC_FEATURE_CTRL 0x00 -#define NB_IOAPIC_ADDRESS_LOW 0x01 -#define NB_IOAPIC_ADDRESS_HIGH 0x02 -#define NB_IOAPIC_GBIF_IRR 0x0f -#define NB_IOAPIC_BR0_IRR 0x10 -#define NB_IOAPIC_BR1_IRR 0x11 -#define NB_IOAPIC_BR2_IRR 0x12 -#define NB_IOAPIC_BR3_IRR 0x13 -#define NB_IOAPIC_BR4_IRR 0x14 -#define NB_IOAPIC_APG_IRR 0x2f -#define NB_IOAPIC_SPG_IRR 0x30 -#define NB_IOAPIC_SER_IRQ_IRR 0x31 -#define NB_IOAPIC_SCRATCH0 0x3e -#define NB_IOAPIC_SCRATCH1 0x3f - -#define AP_SCRATCH_REG NB_IOAPIC_SCRATCH0 - /* D1F1 - HDA Configuration Registers */ #define HDA_DEV_CTRL_STATUS 0x60 #define HDA_NO_SNOOP_EN BIT(11) @@ -95,19 +73,11 @@ #define D18F1_VGAEN 0xf4 # define VGA_ADDR_ENABLE (1 << 0) -/* D18F5 */ -#define NB_CAPABILITIES2 0x84 -#define CMP_CAP_MASK 0xff - void amd_initcpuio(void); void domain_enable_resources(struct device *dev); void domain_set_resources(struct device *dev); void fam15_finalize(void *chip_info); -uint32_t nb_ioapic_read(unsigned int index); -void nb_ioapic_write(unsigned int index, uint32_t value); -void *get_ap_entry_ptr(void); -void set_ap_entry_ptr(void *entry); void set_warm_reset_flag(void); int is_warm_reset(void); diff --git a/src/soc/amd/picasso/include/soc/romstage.h b/src/soc/amd/picasso/include/soc/romstage.h index d8b2900fb5..c0d03d0ead 100644 --- a/src/soc/amd/picasso/include/soc/romstage.h +++ b/src/soc/amd/picasso/include/soc/romstage.h @@ -16,6 +16,6 @@ #ifndef __PICASSO_ROMSTAGE_H__ #define __PICASSO_ROMSTAGE_H__ -void mainboard_romstage_entry(int s3_resume); +void mainboard_romstage_entry_s3(int s3_resume); #endif /* __PICASSO_ROMSTAGE_H__ */ diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index da32610eed..66c205096e 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Advanced Micro Devices, Inc. + * Copyright (C) 2017-2019 Advanced Micro Devices, Inc. * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify @@ -33,128 +33,125 @@ # define SMI_SCI_MAP(X) (SMI_SCI_MAP0 + (X)) /* SMI source and status */ -#define SMITYPE_AGPIO65 0 -#define SMITYPE_AGPIO66 1 -#define SMITYPE_AGPIO3 2 -#define SMITYPE_LPCPME_AGPIO22 3 -#define SMITYPE_GPIO4 4 -#define SMITYPE_LPCPD_AGPIOG21 5 -#define SMITYPE_IRTX1_G15 6 -#define SMITYPE_AGPIO5_DEVSLP0 7 -#define SMITYPE_WAKE_AGPIO2 8 -#define SMITYPE_APIO68_SGPIOCLK 9 -#define SMITYPE_AGPIO6 10 -#define SMITYPE_GPIO7 11 -#define SMITYPE_USBOC0_TRST_AGPIO16 12 -#define SMITYPE_USB0C1_TDI_AGPIO17 13 -#define SMITYPE_USBOC2_TCK_AGPIO18 14 -#define SMITYPE_TDO_USB0C3_AGPIO24 15 -#define SMITYPE_ACPRES_USBOC4_IRRX0_AGPIO23 16 -/* 17 Reserved */ -#define SMITYPE_BLINK_AGPIO11_USBOC7 18 -#define SMITYPE_SYSRESET_AGPIO1 19 -#define SMITYPE_IRRX1_AGPIO15 20 -#define SMITYPE_IRTX0_USBOC5_AGPIO13 21 -#define SMITYPE_GPIO9_SERPORTRX 22 -#define SMITYPE_GPIO8_SEPORTTX 23 -#define GEVENT_MASK ((1 << SMITYPE_AGPIO65) \ - | (1 << SMITYPE_AGPIO66) \ - | (1 << SMITYPE_AGPIO3) \ - | (1 << SMITYPE_LPCPME_AGPIO22) \ - | (1 << SMITYPE_GPIO4) \ - | (1 << SMITYPE_LPCPD_AGPIOG21) \ - | (1 << SMITYPE_IRTX1_G15) \ - | (1 << SMITYPE_AGPIO5_DEVSLP0) \ - | (1 << SMITYPE_WAKE_AGPIO2) \ - | (1 << SMITYPE_APIO68_SGPIOCLK) \ - | (1 << SMITYPE_AGPIO6) \ - | (1 << SMITYPE_GPIO7) \ - | (1 << SMITYPE_USBOC0_TRST_AGPIO16) \ - | (1 << SMITYPE_USB0C1_TDI_AGPIO17) \ - | (1 << SMITYPE_USBOC2_TCK_AGPIO18) \ - | (1 << SMITYPE_TDO_USB0C3_AGPIO24) \ - | (1 << SMITYPE_ACPRES_USBOC4_IRRX0_AGPIO23) \ - | (1 << SMITYPE_BLINK_AGPIO11_USBOC7) \ - | (1 << SMITYPE_SYSRESET_AGPIO1) \ - | (1 << SMITYPE_IRRX1_AGPIO15) \ - | (1 << SMITYPE_IRTX0_USBOC5_AGPIO13) \ - | (1 << SMITYPE_GPIO9_SERPORTRX)) -#define SMITYPE_EHCI0_WAKE 24 -#define SMITYPE_EHCI1_WAKE 25 -#define SMITYPE_ESPI_SYS 26 -#define SMITYPE_ESPI_WAKE_PME 27 -/* 28-32 Reserved */ -#define SMITYPE_FCH_FAKE0 33 -#define SMITYPE_FCH_FAKE1 34 -#define SMITYPE_FCH_FAKE2 35 -/* 36 Reserved */ -#define SMITYPE_SATA_GEVENT0 37 -#define SMITYPE_SATA_GEVENT1 38 -#define SMITYPE_ACP_WAKE 39 -#define SMITYPE_ECG 40 -#define SMITYPE_GPIO_CTL 41 -#define SMITYPE_CIR_PME 42 -#define SMITYPE_ALT_HPET_ALARM 43 -#define SMITYPE_FAN_THERMAL 44 -#define SMITYPE_ASF_MASTER_SLAVE 45 -#define SMITYPE_I2S_WAKE 46 -#define SMITYPE_SMBUS0_MASTER 47 -#define SMITYPE_TWARN 48 -#define SMITYPE_TRAFFIC_MON 49 -#define SMITYPE_ILLB 50 -#define SMITYPE_PWRBUTTON_UP 51 -#define SMITYPE_PROCHOT 52 -#define SMITYPE_APU_HW 53 -#define SMITYPE_NB_SCI 54 -#define SMITYPE_RAS_SERR 55 -#define SMITYPE_XHC0_PME 56 -/* 57 Reserved */ -#define SMITYPE_ACDC_TIMER 58 -/* 59-62 Reserved */ -#define SMITYPE_TEMP_TSI 63 -#define SMITYPE_KB_RESET 64 -#define SMITYPE_SLP_TYP 65 -#define SMITYPE_AL2H_ACPI 66 -#define SMITYPE_AHCI 67 -/* 68-71 Reserved */ -#define SMITYPE_GBL_RLS 72 -#define SMITYPE_BIOS_RLS 73 -#define SMITYPE_PWRBUTTON_DOWN 74 -#define SMITYPE_SMI_CMD_PORT 75 -#define SMITYPE_USB_SMI 76 -#define SMITYPE_SERIRQ 77 -#define SMITYPE_SMBUS0_INTR 78 -#define SMITYPE_XHC_ERROR 80 -#define SMITYPE_INTRUDER 81 -#define SMITYPE_VBAT_LOW 82 -#define SMITYPE_PROTHOT 83 -#define SMITYPE_PCI_SERR 84 -#define SMITYPE_GPP_SERR 85 -/* 85-88 Reserved */ -#define SMITYPE_TMERTRIP 89 -#define SMITYPE_EMUL60_64 90 -#define SMITYPE_USB_FLR 91 -#define SMITYPE_SATA_FLR 92 -#define SMITYPE_AZ_FLR 93 -/* 94-132 Reserved */ -#define SMITYPE_FANIN0 133 -/* 134-137 Reserved */ -#define SMITYPE_FAKE0 138 -#define SMITYPE_FAKE1 139 -#define SMITYPE_FAKE2 140 -/* 141 Reserved */ -#define SMITYPE_SHORT_TIMER 142 -#define SMITYPE_LONG_TIMER 143 -#define SMITYPE_AB_SMI 144 -#define SMITYPE_SOFT_RESET 145 -/* 146-147 Reserved */ -#define SMITYPE_IOTRAP0 148 -/* 149-151 Reserved */ -#define SMITYPE_MEMTRAP0 152 +#define SMITYPE_G_GENINT1_L 0 +#define SMITYPE_G_GENINT2_L 1 +#define SMITYPE_G_AGPIO3 2 +#define SMITYPE_G_LPCPME 3 +#define SMITYPE_G_AGPIO4 4 +#define SMITYPE_G_LPCPD 5 +#define SMITYPE_G_SPKR 6 +#define SMITYPE_G_AGPIO5 7 +#define SMITYPE_G_WAKE_L 8 +#define SMITYPE_G_LPC_SMI_L 9 +#define SMITYPE_G_AGPIO6 10 +#define SMITYPE_G_AGPIO7 11 +#define SMITYPE_G_USBOC0_L 12 +#define SMITYPE_G_USBOC1_L 13 +#define SMITYPE_G_USBOC2_L 14 +#define SMITYPE_G_USBOC3_L 15 +#define SMITYPE_G_AGPIO23 16 +#define SMITYPE_G_ESPI_RESET_L 17 +#define SMITYPE_G_FANIN0 18 +#define SMITYPE_G_SYSRESET_L 19 +#define SMITYPE_G_AGPIO40 20 +#define SMITYPE_G_PWR_BTN_L 21 +#define SMITYPE_G_AGPIO9 22 +#define SMITYPE_G_AGPIO8 23 +#define GEVENT_MASK ((1 << SMITYPE_G_GENINT1_L) \ + | (1 << SMITYPE_G_GENINT2_L) \ + | (1 << SMITYPE_G_AGPIO3) \ + | (1 << SMITYPE_G_LPCPME) \ + | (1 << SMITYPE_G_AGPIO4) \ + | (1 << SMITYPE_G_LPCPD) \ + | (1 << SMITYPE_G_SPKR) \ + | (1 << SMITYPE_G_AGPIO5) \ + | (1 << SMITYPE_G_WAKE_L) \ + | (1 << SMITYPE_G_LPC_SMI_L) \ + | (1 << SMITYPE_G_AGPIO6) \ + | (1 << SMITYPE_G_AGPIO7) \ + | (1 << SMITYPE_G_USBOC0_L) \ + | (1 << SMITYPE_G_USBOC1_L) \ + | (1 << SMITYPE_G_USBOC2_L) \ + | (1 << SMITYPE_G_USBOC3_L) \ + | (1 << SMITYPE_G_AGPIO23) \ + | (1 << SMITYPE_G_ESPI_RESET_L) \ + | (1 << SMITYPE_G_FANIN0) \ + | (1 << SMITYPE_G_SYSRESET_L) \ + | (1 << SMITYPE_G_AGPIO40) \ + | (1 << SMITYPE_G_PWR_BTN_L)) +#define SMITYPE_MP2_WAKE 24 +#define SMITYPE_MP2_GPIO0 25 +#define SMITYPE_ESPI_SYS 26 +#define SMITYPE_ESPI_WAKE_PME 27 +#define SMITYPE_MP2_GPIO1 28 +#define SMITYPE_GPP_PME 29 +#define SMITYPE_NB_GPP_HOT_PLUG 30 +/* 31 Reserved */ +#define SMITYPE_WAKE_L2 32 +/* 33 - 38 Reserved */ +#define SMITYPE_AZPME 39 +#define SMITYPE_USB_PD_I2C4 40 +#define SMITYPE_GPIO_CTL 41 +/* 42 Reserved */ +#define SMITYPE_ALT_HPET_ALARM 43 +#define SMITYPE_FAN_THERMAL 44 +#define SMITYPE_ASF_MASTER_SLAVE 45 +#define SMITYPE_I2S_WAKE 46 +#define SMITYPE_SMBUS0_MASTER 47 +#define SMITYPE_TWARN 48 +#define SMITYPE_TRAFFIC_MON 49 +#define SMITYPE_ILLB 50 +#define SMITYPE_PWRBUTTON_UP 51 +#define SMITYPE_PROCHOT 52 +#define SMITYPE_APU_HW 53 +#define SMITYPE_NB_SCI 54 +#define SMITYPE_RAS_SERR 55 +#define SMITYPE_XHC0_PME 56 +#define SMITYPE_XHC1_PME 57 +#define SMITYPE_ACDC_TIMER 58 +/* 59-63 Reserved */ +#define SMITYPE_KB_RESET 64 +#define SMITYPE_SLP_TYP 65 +#define SMITYPE_AL2H_ACPI 66 +#define SMITYPE_AHCI 67 +#define SMITYPE_NB_GPP_PME_PULSE 68 +#define SMITYPE_NB_GPP_HP_PULSE 69 +#define SMITYPE_USBPD_I2C_INT 70 +/* 71 Reserved */ +#define SMITYPE_GBL_RLS 72 +#define SMITYPE_BIOS_RLS 73 +#define SMITYPE_PWRBUTTON_DOWN 74 +#define SMITYPE_SMI_CMD_PORT 75 +#define SMITYPE_USB_SMI 76 +#define SMITYPE_SERIRQ 77 +#define SMITYPE_SMBUS0_INTR 78 +/* 79-80 Reserved */ +#define SMITYPE_INTRUDER 81 +#define SMITYPE_VBAT_LOW 82 +#define SMITYPE_PROTHOT 83 +#define SMITYPE_PCI_SERR 84 +#define SMITYPE_GPP_SERR 85 +/* 85-89 Reserved */ +#define SMITYPE_EMUL60_64 90 +/* 91-132 Reserved */ +#define SMITYPE_FANIN0 133 +/* 134-140 Reserved */ +#define SMITYPE_CF9_WRITE 141 +#define SMITYPE_SHORT_TIMER 142 +#define SMITYPE_LONG_TIMER 143 +#define SMITYPE_AB_SMI 144 +/* 145 Reserved */ +#define SMITYPE_ESPI_SMI 146 +/* 147 Reserved */ +#define SMITYPE_IOTRAP0 148 +#define SMITYPE_IOTRAP1 149 +#define SMITYPE_IOTRAP2 150 +#define SMITYPE_IOTRAP3 151 +#define SMITYPE_MEMTRAP0 152 /* 153-155 Reserved */ -#define SMITYPE_CFGTRAP0 156 +#define SMITYPE_CFGTRAP0 156 /* 157-159 Reserved */ -#define NUMBER_SMITYPES 160 +#define NUMBER_SMITYPES 160 #define TYPE_TO_MASK(X) (1 << (X) % 32) #define SMI_REG_SMISTS0 0x80 diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 6fc37f009a..b2ede55f73 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -175,19 +175,49 @@ #define CG1PLL_LF_MODE_MASK (0x1ff << CG1PLL_LF_MODE_SHIFT) #define MISC_CLK_CNTL1 0x40 #define CG1PLL_FBDIV_TEST BIT(26) +#define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */ #define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */ #define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */ +#define MISC_I2C0_PAD_CTRL 0xd8 +#define MISC_I2C1_PAD_CTRL 0xdc +#define MISC_I2C2_PAD_CTRL 0xe0 +#define MISC_I2C3_PAD_CTRL 0xe4 +#define I2C_PAD_CTRL_NG_MASK (BIT(0) + BIT(1) + BIT(2) + BIT(3)) +#define I2C_PAD_CTRL_NG_NORMAL 0xc +#define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) + BIT(5)) +#define I2C_PAD_CTRL_RX_SHIFT 4 +#define I2C_PAD_CTRL_RX_SEL_OFF (0 << I2C_PAD_CTRL_RX_SHIFT) +#define I2C_PAD_CTRL_RX_SEL_3_3V (1 << I2C_PAD_CTRL_RX_SHIFT) +#define I2C_PAD_CTRL_RX_SEL_1_8V (3 << I2C_PAD_CTRL_RX_SHIFT) +#define I2C_PAD_CTRL_PULLDOWN_EN BIT(6) +#define I2C_PAD_CTRL_FALLSLEW_MASK (BIT(7) + BIT(8)) +#define I2C_PAD_CTRL_FALLSLEW_SHIFT 7 +#define I2C_PAD_CTRL_FALLSLEW_STD (0 << I2C_PAD_CTRL_FALLSLEW_SHIFT) +#define I2C_PAD_CTRL_FALLSLEW_LOW (1 << I2C_PAD_CTRL_FALLSLEW_SHIFT) +#define I2C_PAD_CTRL_FALLSLEW_EN BIT(9) +#define I2C_PAD_CTRL_SPIKE_RC_EN BIT(10) +#define I2C_PAD_CTRL_SPIKE_RC_SEL BIT(11) /* 0 = 50ns, 1 = 20ns */ +#define I2C_PAD_CTRL_CAP_DOWN BIT(12) +#define I2C_PAD_CTRL_CAP_UP BIT(13) +#define I2C_PAD_CTRL_RES_DOWN BIT(14) +#define I2C_PAD_CTRL_RES_UP BIT(15) +#define I2C_PAD_CTRL_BIOS_CRT_EN BIT(16) +#define I2C_PAD_CTRL_SPARE0 BIT(17) +#define I2C_PAD_CTRL_SPARE1 BIT(18) /* FCH AOAC Registers 0xfed81e00 */ -#define FCH_AOAC_D3_CONTROL_CLK_GEN 0x40 -#define FCH_AOAC_D3_CONTROL_I2C0 0x4a -#define FCH_AOAC_D3_CONTROL_I2C1 0x4c -#define FCH_AOAC_D3_CONTROL_I2C2 0x4e -#define FCH_AOAC_D3_CONTROL_I2C3 0x50 -#define FCH_AOAC_D3_CONTROL_UART0 0x56 -#define FCH_AOAC_D3_CONTROL_UART1 0x58 -#define FCH_AOAC_D3_CONTROL_AMBA 0x62 -/* Bit definitions for all FCH_AOAC_D3_CONTROL_* Registers */ +#define AOAC_DEV_D3_CTL(device) (0x40 + device * 2) +#define AOAC_DEV_D3_STATE(device) (AOAC_DEV_D3_CTL(device) + 1) + +#define FCH_AOAC_DEV_CLK_GEN 0 +#define FCH_AOAC_DEV_I2C2 7 +#define FCH_AOAC_DEV_I2C3 8 +#define FCH_AOAC_DEV_I2C4 9 +#define FCH_AOAC_DEV_UART0 11 +#define FCH_AOAC_DEV_UART1 12 +#define FCH_AOAC_DEV_AMBA 17 + +/* Bit definitions for Device D3 Control AOACx0000[40...7E] step 2 */ #define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1)) #define FCH_AOAC_DEVICE_STATE BIT(2) #define FCH_AOAC_PWR_ON_DEV BIT(3) @@ -196,15 +226,7 @@ #define FCH_AOAC_SW_RST_B BIT(6) #define FCH_AOAC_IS_SW_CONTROL BIT(7) -#define FCH_AOAC_D3_STATE_CLK_GEN 0x41 -#define FCH_AOAC_D3_STATE_I2C0 0x4b -#define FCH_AOAC_D3_STATE_I2C1 0x4d -#define FCH_AOAC_D3_STATE_I2C2 0x4f -#define FCH_AOAC_D3_STATE_I2C3 0x51 -#define FCH_AOAC_D3_STATE_UART0 0x57 -#define FCH_AOAC_D3_STATE_UART1 0x59 -#define FCH_AOAC_D3_STATE_AMBA 0x63 -/* Bit definitions for all FCH_AOAC_D3_STATE_* Registers */ +/* Bit definitions for Device D3 State AOACx0000[41...7f] step 2 */ #define FCH_AOAC_PWR_RST_STATE BIT(0) #define FCH_AOAC_RST_CLK_OK_STATE BIT(1) #define FCH_AOAC_RST_B_STATE BIT(2) @@ -236,22 +258,10 @@ #define SPI_READ_MODE_QUAD144 (BIT(30) | BIT(18)) #define SPI_READ_MODE_NORMAL66 (BIT(30) | BIT(29) ) #define SPI_READ_MODE_FAST (BIT(30) | BIT(29) | BIT(18)) +#define SPI_ACCESS_MAC_ROM_EN BIT(22) #define SPI_FIFO_PTR_CLR BIT(20) #define SPI_ARB_ENABLE BIT(19) #define EXEC_OPCODE BIT(16) -#define SPI_CNTRL1 0x0c -#define SPI_CMD_CODE 0x45 -#define SPI_CMD_TRIGGER 0x47 -#define SPI_CMD_TRIGGER_EXECUTE BIT(7) -#define SPI_TX_BYTE_COUNT 0x48 -#define SPI_RX_BYTE_COUNT 0x4b -#define SPI_STATUS 0x4c -#define SPI_DONE_BYTE_COUNT_SHIFT 0 -#define SPI_DONE_BYTE_COUNT_MASK 0xff -#define SPI_FIFO_WR_PTR_SHIFT 8 -#define SPI_FIFO_WR_PTR_MASK 0x7f -#define SPI_FIFO_RD_PTR_SHIFT 16 -#define SPI_FIFO_RD_PTR_MASK 0x7f #define SPI_FIFO 0x80 #define SPI_FIFO_DEPTH (0xc7 - SPI_FIFO) @@ -279,18 +289,15 @@ #define RST_CMD BIT(2) #define SYS_RST BIT(1) -struct picasso_aoac { - int enable; - int status; -}; +/* IO 0xf0 NCP Error */ +#define NCP_WARM_BOOT BIT(7) /* Write-once */ typedef struct aoac_devs { - unsigned int :5; - unsigned int ic0e:1; /* 5: I2C0 */ - unsigned int ic1e:1; /* 6: I2C1 */ + unsigned int :7; unsigned int ic2e:1; /* 7: I2C2 */ unsigned int ic3e:1; /* 8: I2C3 */ - unsigned int :2; + unsigned int ic4e:1; /* 9: I2C4 */ + unsigned int :1; unsigned int ut0e:1; /* 11: UART0 */ unsigned int ut1e:1; /* 12: UART1 */ unsigned int :2; @@ -309,7 +316,7 @@ struct soc_power_reg { }; void enable_aoac_devices(void); -void sb_clk_output_48Mhz(u32 osc); +void sb_clk_output_48Mhz(void); void sb_disable_4dw_burst(void); void sb_enable(struct device *dev); void southbridge_final(void *chip_info); @@ -366,4 +373,7 @@ void i2c_soc_early_init(void); /* Initialize all the i2c buses that are not marked with early init. */ void i2c_soc_init(void); +/* Allow the board to change the default I2C pad configuration */ +void mainboard_i2c_override(int bus, uint32_t *pad_settings); + #endif /* __PICASSO_SB_H__ */ diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 8a875d9206..57fa9c6536 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -97,11 +97,6 @@ static void fill_generic_section(cper_proc_generic_error_section_t *sec, * which is the best method to report MSR context. As a result, add two * structures: A "processor generic error" that is parsed, and an IA32/X64 one * to capture complete information. - * - * Future work may attempt to interpret the specific Family 15h error symptoms - * found in the MCA registers. This data could enhance the reporting of the - * Processor Generic section and the failing error/check added to the - * IA32/X64 section. */ static void build_bert_mca_error(struct mca_bank *mci) { @@ -161,6 +156,7 @@ static const char *const mca_bank_name[] = { "Floating point unit" }; +/* Check the Legacy Machine Check Architecture registers */ void check_mca(void) { int i; @@ -173,9 +169,6 @@ void check_mca(void) if (is_warm_reset()) { for (i = 0 ; i < num_banks ; i++) { - if (i == 3) /* Reserved in Family 15h */ - continue; - mci.sts = rdmsr(IA32_MC0_STATUS + (i * 4)); if (mci.sts.hi || mci.sts.lo) { int core = cpuid_ebx(1) >> 24; diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/picasso/memmap.c similarity index 80% rename from src/soc/amd/stoneyridge/ramtop.c rename to src/soc/amd/picasso/memmap.c index e2b0f7d6bc..09af7e4de7 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/picasso/memmap.c @@ -81,12 +81,6 @@ static size_t smm_region_size(void) return CONFIG_SMM_TSEG_SIZE; } -void smm_region(uintptr_t *start, size_t *size) -{ - *start = smm_region_start(); - *size = smm_region_size(); -} - /* * For data stored in TSEG, ensure TValid is clear so R/W access can reach * the DRAM when not in SMM. @@ -109,38 +103,15 @@ static void clear_tvalid(void) wrmsr(SMM_MASK_MSR, mask); } -int smm_subregion(int sub, uintptr_t *start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { static int once; - uintptr_t sub_base; - size_t sub_size; - const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - smm_region(&sub_base, &sub_size); - assert(sub_size > CONFIG_SMM_RESERVED_SIZE); + *start = smm_region_start(); + *size = smm_region_size(); if (!once) { clear_tvalid(); once = 1; } - - switch (sub) { - case SMM_SUBREGION_HANDLER: - /* Handler starts at the base of TSEG. */ - sub_size -= cache_size; - break; - case SMM_SUBREGION_CACHE: - /* External cache is in the middle of TSEG. */ - sub_base += sub_size - cache_size; - sub_size = cache_size; - break; - default: - *start = 0; - *size = 0; - return -1; - } - - *start = sub_base; - *size = sub_size; - return 0; } diff --git a/src/soc/amd/picasso/monotonic_timer.c b/src/soc/amd/picasso/monotonic_timer.c deleted file mode 100644 index 7ea571f635..0000000000 --- a/src/soc/amd/picasso/monotonic_timer.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#define CU_PTSC_MSR 0xc0010280 -#define PTSC_FREQ_MHZ 100 - -void timer_monotonic_get(struct mono_time *mt) -{ - mono_time_set_usecs(mt, timestamp_get()); -} - -uint64_t timestamp_get(void) -{ - unsigned long long val; - msr_t msr; - - msr = rdmsr(CU_PTSC_MSR); - - val = ((unsigned long long)msr.hi << 32) | msr.lo; - - return val / PTSC_FREQ_MHZ; -} diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 627ce03833..36135f989e 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -66,20 +66,12 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, static void read_resources(struct device *dev) { - struct resource *res; - /* * This MMCONF resource must be reserved in the PCI domain. * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ mmconf_resource(dev, MMIO_CONF_BASE); - - /* NB IOAPIC2 resource */ - res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */ - res->base = IO_APIC2_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } static void set_resource(struct device *dev, struct resource *res, u32 nodeid) @@ -168,11 +160,6 @@ static void set_resources(struct device *dev) assign_resources(bus); } -static void northbridge_init(struct device *dev) -{ - setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS+1); -} - unsigned long acpi_fill_mcfg(unsigned long current) { @@ -218,7 +205,6 @@ static struct device_operations northbridge_operations = { .read_resources = read_resources, .set_resources = set_resources, .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator, .write_acpi_tables = agesa_write_acpi_tables, .enable = 0, @@ -267,10 +253,6 @@ void fam15_finalize(void *chip_info) { u32 value; - /* TODO: move IOAPIC code to dsdt.asl */ - pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, 0); - pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, 5); - /* disable No Snoop */ value = pci_read_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS); value &= ~HDA_NO_SNOOP_EN; diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c index ec5ee910d9..98410387fb 100644 --- a/src/soc/amd/picasso/reset.c +++ b/src/soc/amd/picasso/reset.c @@ -25,32 +25,18 @@ void set_warm_reset_flag(void) { - u32 htic; - htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL); - htic |= HTIC_COLD_RST_DET; - pci_write_config32(SOC_HT_DEV, HT_INIT_CONTROL, htic); + uint8_t ncp = inw(NCP_ERR); + + outb(NCP_ERR, ncp | NCP_WARM_BOOT); } int is_warm_reset(void) { - u32 htic; - htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL); - return !!(htic & HTIC_COLD_RST_DET); -} - -/* Clear bits 5, 9 & 10, used to signal the reset type */ -static void clear_bios_reset(void) -{ - u32 htic; - htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_DETECT; - pci_write_config32(SOC_HT_DEV, HT_INIT_CONTROL, htic); + return !!(inb(NCP_ERR) & NCP_WARM_BOOT); } void do_cold_reset(void) { - clear_bios_reset(); - /* De-assert and then assert all PwrGood signals on CF9 reset. */ pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); @@ -60,7 +46,6 @@ void do_cold_reset(void) void do_warm_reset(void) { set_warm_reset_flag(); - clear_bios_reset(); /* Assert reset signals only. */ outb(RST_CMD | SYS_RST, SYS_RESET); diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index dae64cc420..257ae6789d 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -16,6 +16,7 @@ #include #include +#include #include #include #include @@ -34,7 +35,7 @@ #include "chip.h" -void __weak mainboard_romstage_entry(int s3_resume) +void __weak mainboard_romstage_entry_s3(int s3_resume) { /* By default, don't do anything */ } @@ -43,19 +44,15 @@ asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; uintptr_t top_of_ram; - uintptr_t smm_base; - size_t smm_size; int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); console_init(); - mainboard_romstage_entry(s3_resume); + mainboard_romstage_entry_s3(s3_resume); + elog_boot_notify(s3_resume); if (!s3_resume) { post_code(0x40); - - if (CONFIG(ELOG_BOOT_COUNT)) - boot_count_increment(); } else { printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); @@ -67,6 +64,9 @@ asmlinkage void car_stage_entry(void) if (romstage_handoff_init(s3_resume)) printk(BIOS_ERR, "Failed to set romstage handoff data\n"); + if (CONFIG(SMM_TSEG)) + smm_list_regions(); + post_code(0x44); if (postcar_frame_init(&pcf, 1 * KiB)) die("Unable to initialize postcar frame.\n"); @@ -83,15 +83,8 @@ asmlinkage void car_stage_entry(void) /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); + /* Cache the TSEG region */ + postcar_enable_tseg_cache(&pcf); post_code(0x45); run_postcar_phase(&pcf); diff --git a/src/soc/amd/picasso/smi.c b/src/soc/amd/picasso/smi.c index 4a0d833c7b..b11eda6360 100644 --- a/src/soc/amd/picasso/smi.c +++ b/src/soc/amd/picasso/smi.c @@ -19,6 +19,7 @@ */ #include +#include #include #include #include diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index d8438bb366..9eddf853b6 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 84c15a7595..e6fc0dedc2 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -36,20 +36,25 @@ #include #include +#define FCH_AOAC_UART_FOR_CONSOLE \ + (CONFIG_UART_FOR_CONSOLE == 0 ? FCH_AOAC_DEV_UART0 \ + : CONFIG_UART_FOR_CONSOLE == 1 ? FCH_AOAC_DEV_UART1 \ + : -1) +#if FCH_AOAC_UART_FOR_CONSOLE == -1 +# error Unsupported UART_FOR_CONSOLE chosen +#endif + /* * Table of devices that need their AOAC registers enabled and waited * upon (usually about .55 milliseconds). Instead of individual delays * waiting for each device to become available, a single delay will be - * executed. + * executed. The console UART is handled separately from this table. */ -const static struct picasso_aoac aoac_devs[] = { - { (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2), - (FCH_AOAC_D3_STATE_UART0 + CONFIG_UART_FOR_CONSOLE * 2) }, - { FCH_AOAC_D3_CONTROL_AMBA, FCH_AOAC_D3_STATE_AMBA }, - { FCH_AOAC_D3_CONTROL_I2C0, FCH_AOAC_D3_STATE_I2C0 }, - { FCH_AOAC_D3_CONTROL_I2C1, FCH_AOAC_D3_STATE_I2C1 }, - { FCH_AOAC_D3_CONTROL_I2C2, FCH_AOAC_D3_STATE_I2C2 }, - { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 } +const static int aoac_devs[] = { + FCH_AOAC_DEV_AMBA, + FCH_AOAC_DEV_I2C2, + FCH_AOAC_DEV_I2C3, + FCH_AOAC_DEV_I2C4, }; /* @@ -102,21 +107,21 @@ const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) return irq_association; } -static void power_on_aoac_device(int aoac_device_control_register) +static void power_on_aoac_device(int dev) { uint8_t byte; /* Power on the UART and AMBA devices */ - byte = aoac_read8(aoac_device_control_register); + byte = aoac_read8(AOAC_DEV_D3_CTL(dev)); byte |= FCH_AOAC_PWR_ON_DEV; - aoac_write8(aoac_device_control_register, byte); + aoac_write8(AOAC_DEV_D3_CTL(dev), byte); } -static bool is_aoac_device_enabled(int aoac_device_status_register) +static bool is_aoac_device_enabled(int dev) { uint8_t byte; - byte = aoac_read8(aoac_device_status_register); + byte = aoac_read8(AOAC_DEV_D3_STATE(dev)); byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE); if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE)) return true; @@ -124,20 +129,38 @@ static bool is_aoac_device_enabled(int aoac_device_status_register) return false; } +static void enable_aoac_console_uart(void) +{ + if (!CONFIG(PICASSO_UART)) + return; + + power_on_aoac_device(FCH_AOAC_UART_FOR_CONSOLE); +} + +static bool is_aoac_console_uart_enabled(void) +{ + if (!CONFIG(PICASSO_UART)) + return true; + + return is_aoac_device_enabled(FCH_AOAC_UART_FOR_CONSOLE); +} + void enable_aoac_devices(void) { bool status; int i; for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) - power_on_aoac_device(aoac_devs[i].enable); + power_on_aoac_device(aoac_devs[i]); + enable_aoac_console_uart(); /* Wait for AOAC devices to indicate power and clock OK */ do { udelay(100); status = true; for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) - status &= is_aoac_device_enabled(aoac_devs[i].status); + status &= is_aoac_device_enabled(aoac_devs[i]); + status &= is_aoac_console_uart_enabled(); } while (!status); } @@ -190,26 +213,12 @@ static void sb_enable_legacy_io(void) pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN); } -void sb_clk_output_48Mhz(u32 osc) +void sb_clk_output_48Mhz(void) { u32 ctrl; - /* - * Clear the disable for OSCOUT1 (signal typically named XnnM_25M_48M) - * or OSCOUT2 (USBCLK/25M_48M_OSC). The frequency defaults to 48MHz. - */ ctrl = misc_read32(MISC_CLK_CNTL1); - - switch (osc) { - case 1: - ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB; - break; - case 2: - ctrl &= ~OSCOUT2_CLK_OUTPUT_ENB; - break; - default: - return; /* do nothing if invalid */ - } + ctrl |= BP_X48M0_OUTPUT_EN; misc_write32(MISC_CLK_CNTL1, ctrl); } @@ -528,12 +537,11 @@ static void set_sb_final_nvs(void) if (gnvs == NULL) return; - gnvs->aoac.ic0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C0); - gnvs->aoac.ic1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C1); - gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C2); - gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3); - gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART0); - gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART1); + gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C2); + gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C3); + gnvs->aoac.ic4e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C4); + gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_DEV_UART0); + gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_DEV_UART1); /* Rely on these being in sync with devicetree */ sata = pcidev_path_on_root(SATA_DEVFN); gnvs->aoac.st_e = sata && sata->enabled ? 1 : 0; diff --git a/src/soc/amd/picasso/spi.c b/src/soc/amd/picasso/spi.c deleted file mode 100644 index 8abfa160f4..0000000000 --- a/src/soc/amd/picasso/spi.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define SPI_DEBUG_DRIVER CONFIG(DEBUG_SPI_FLASH) - -static uintptr_t spibar; - -static void set_spibar(uintptr_t base) -{ - spibar = base; -} - -static inline uint8_t spi_read8(uint8_t reg) -{ - return read8((void *)(spibar + reg)); -} - -static inline uint32_t spi_read32(uint8_t reg) -{ - return read32((void *)(spibar + reg)); -} - -static inline void spi_write8(uint8_t reg, uint8_t val) -{ - write8((void *)(spibar + reg), val); -} - -static inline void spi_write32(uint8_t reg, uint32_t val) -{ - write32((void *)(spibar + reg), val); -} - -static void dump_state(const char *str) -{ - if (!SPI_DEBUG_DRIVER) - return; - - printk(BIOS_DEBUG, "SPI: %s\n", str); - printk(BIOS_DEBUG, "Cntrl0: %x\n", spi_read32(SPI_CNTRL0)); - printk(BIOS_DEBUG, "Status: %x\n", spi_read32(SPI_STATUS)); - printk(BIOS_DEBUG, "TxByteCount: %x\n", spi_read8(SPI_TX_BYTE_COUNT)); - printk(BIOS_DEBUG, "RxByteCount: %x\n", spi_read8(SPI_RX_BYTE_COUNT)); - printk(BIOS_DEBUG, "CmdCode: %x\n", spi_read8(SPI_CMD_CODE)); - hexdump((void *)(spibar + SPI_FIFO), SPI_FIFO_DEPTH); -} - -static int wait_for_ready(void) -{ - const uint32_t timeout_ms = 500; - struct stopwatch sw; - - stopwatch_init_msecs_expire(&sw, timeout_ms); - - do { - if (!(spi_read32(SPI_STATUS) & SPI_BUSY)) - return 0; - } while (!stopwatch_expired(&sw)); - - return -1; -} - -static int execute_command(void) -{ - dump_state("Before Execute"); - - spi_write8(SPI_CMD_TRIGGER, SPI_CMD_TRIGGER_EXECUTE); - - if (wait_for_ready()) - printk(BIOS_DEBUG, - "FCH SPI Error: Timeout executing command\n"); - - dump_state("Transaction finished"); - - return 0; -} - -void spi_init(void) -{ - set_spibar(lpc_get_spibase()); -} - -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - size_t count; - uint8_t cmd; - uint8_t *bufin = din; - const uint8_t *bufout = dout; - - if (SPI_DEBUG_DRIVER) - printk(BIOS_DEBUG, "%s(%zx, %zx)\n", __func__, bytesout, - bytesin); - - /* First byte is cmd which cannot be sent through FIFO */ - cmd = bufout[0]; - bufout++; - bytesout--; - - /* - * Check if this is a write command attempting to transfer more bytes - * than the controller can handle. Iterations for writes are not - * supported here because each SPI write command needs to be preceded - * and followed by other SPI commands, and this sequence is controlled - * by the SPI chip driver. - */ - if (bytesout + bytesin > SPI_FIFO_DEPTH) { - printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI" - " chip driver use spi_crop_chunk()?\n"); - return -1; - } - - if (wait_for_ready()) - return -1; - - spi_write8(SPI_CMD_CODE, cmd); - spi_write8(SPI_TX_BYTE_COUNT, bytesout); - spi_write8(SPI_RX_BYTE_COUNT, bytesin); - - for (count = 0; count < bytesout; count++) - spi_write8(SPI_FIFO + count, bufout[count]); - - if (execute_command()) - return -1; - - for (count = 0; count < bytesin; count++) - bufin[count] = spi_read8(SPI_FIFO + count + bytesout); - - return 0; -} - -int chipset_volatile_group_begin(const struct spi_flash *flash) -{ - return 0; -} - -int chipset_volatile_group_end(const struct spi_flash *flash) -{ - return 0; -} - -static int xfer_vectors(const struct spi_slave *slave, - struct spi_op vectors[], size_t count) -{ - return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); -} - -static const struct spi_ctrlr spi_ctrlr = { - .xfer_vector = xfer_vectors, - .max_xfer_size = SPI_FIFO_DEPTH, - .flags = SPI_CNTRLR_DEDUCT_CMD_LEN | SPI_CNTRLR_DEDUCT_OPCODE_LEN, -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { - .ctrlr = &spi_ctrlr, - .bus_start = 0, - .bus_end = 0, - }, -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/amd/picasso/tsc_freq.c b/src/soc/amd/picasso/tsc_freq.c index 29121b955e..6167726955 100644 --- a/src/soc/amd/picasso/tsc_freq.c +++ b/src/soc/amd/picasso/tsc_freq.c @@ -19,31 +19,27 @@ #include #include #include -#include -#include + +static unsigned long mhz; unsigned long tsc_freq_mhz(void) { msr_t msr; uint8_t cpufid; uint8_t cpudid; - uint8_t boost_states; + uint8_t high_state; - /* - * See the Family 15h Models 70h-7Fh BKDG (PID 55072) definition for - * MSR0000_0010. The TSC increments at the P0 frequency. According - * to the "Software P-state Numbering" section, P0 is the highest - * non-boosted state. freq = 100MHz * (CpuFid + 10h) / (2^(CpuDid)). - */ - boost_states = (pci_read_config32(SOC_PM_DEV, CORE_PERF_BOOST_CTRL) - >> 2) & 0x7; + if (mhz) + return mhz; - msr = rdmsr(PSTATE_0_MSR + boost_states); + high_state = rdmsr(PS_LIM_REG).lo & 0x7; + msr = rdmsr(PSTATE_0_MSR + high_state); if (!(msr.hi & 0x80000000)) die("Unknown error: cannot determine P-state 0\n"); cpufid = (msr.lo & 0x3f); cpudid = (msr.lo & 0x1c0) >> 6; - return (100 * (cpufid + 0x10)) / (0x01 << cpudid); + mhz = (100 * (cpufid + 0x10)) / (0x01 << cpudid); + return mhz; } diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 5f1d2f3ad5..72719d7179 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -52,7 +52,7 @@ config CPU_SPECIFIC_OPTIONS select GENERIC_UDELAY select IOAPIC select HAVE_USBDEBUG_OPTIONS - select SPI_FLASH if HAVE_ACPI_RESUME + select SOC_AMD_COMMON_BLOCK_SPI select TSC_SYNC_LFENCE select COLLECT_TIMESTAMPS select SOC_AMD_PI @@ -76,8 +76,6 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP select PARALLEL_MP_AP_WORK select HAVE_SMI_HANDLER - select POSTCAR_STAGE - select POSTCAR_CONSOLE select SSE2 select RTC diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 150df3abd9..53aabf5d65 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -49,7 +49,6 @@ bootblock-y += reset.c bootblock-y += tsc_freq.c bootblock-y += southbridge.c bootblock-y += nb_util.c -bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c romstage-y += BiosCallOuts.c @@ -62,12 +61,11 @@ romstage-y += pmutil.c romstage-y += reset.c romstage-y += smbus.c romstage-y += smbus_spd.c -romstage-y += ramtop.c +romstage-y += memmap.c romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c romstage-y += tsc_freq.c romstage-y += southbridge.c romstage-y += nb_util.c -romstage-$(CONFIG_SPI_FLASH) += spi.c romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c verstage-y += gpio.c @@ -78,11 +76,10 @@ verstage-y += reset.c verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c verstage-y += tsc_freq.c verstage-y += nb_util.c -verstage-$(CONFIG_SPI_FLASH) += spi.c postcar-y += monotonic_timer.c postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c -postcar-y += ramtop.c +postcar-y += memmap.c postcar-y += nb_util.c postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c postcar-y += tsc_freq.c @@ -103,13 +100,12 @@ ramstage-y += reset.c ramstage-y += sata.c ramstage-y += sm.c ramstage-y += smbus.c -ramstage-y += ramtop.c +ramstage-y += memmap.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c ramstage-y += usb.c ramstage-y += tsc_freq.c -ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-y += finalize.c ramstage-y += nb_util.c @@ -118,7 +114,6 @@ smm-y += smihandler.c smm-y += smi_util.c smm-y += tsc_freq.c smm-$(CONFIG_DEBUG_SMI) += uart.c -smm-$(CONFIG_SPI_FLASH) += spi.c smm-y += nb_util.c smm-y += gpio.c diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 9239030d6c..a079ec2561 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -88,7 +88,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) } /* TSC cannot be relied upon. Override the TSC value passed in. */ - bootblock_main_with_timestamp(timestamp_get(), NULL, 0); + bootblock_main_with_basetime(timestamp_get()); } void bootblock_soc_early_init(void) diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 4684aeaf8c..d7823934d6 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -33,13 +34,12 @@ /* * MP and SMM loading initialization. */ -struct smm_relocation_attrs { - uint32_t smbase; - uint32_t tseg_base; - uint32_t tseg_mask; +struct smm_relocation_params { + msr_t tseg_base; + msr_t tseg_mask; }; -static struct smm_relocation_attrs relo_attrs; +static struct smm_relocation_params smm_reloc_params; /* * Do essential initialization tasks before APs can be fired up - @@ -60,40 +60,41 @@ static int get_cpu_count(void) + 1; } +static void fill_in_relocation_params(struct smm_relocation_params *params) +{ + uintptr_t tseg_base; + size_t tseg_size; + + smm_region(&tseg_base, &tseg_size); + + params->tseg_base.lo = ALIGN_DOWN(tseg_base, 128 * KiB); + params->tseg_base.hi = 0; + params->tseg_mask.lo = ALIGN_DOWN(~(tseg_size - 1), 128 * KiB); + params->tseg_mask.hi = ((1 << (cpu_phys_address_size() - 32)) - 1); + + params->tseg_mask.lo |= SMM_TSEG_WB; +} + static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - uintptr_t smm_base; - size_t smm_size; - uintptr_t handler_base; - size_t handler_size; + printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - /* Initialize global tracking state. */ - smm_region(&smm_base, &smm_size); - smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); + fill_in_relocation_params(&smm_reloc_params); - relo_attrs.smbase = smm_base; - relo_attrs.tseg_base = relo_attrs.smbase; - relo_attrs.tseg_mask = ALIGN_DOWN(~(smm_size - 1), 128 * KiB); - relo_attrs.tseg_mask |= SMM_TSEG_WB; - - *perm_smbase = handler_base; - *perm_smsize = handler_size; + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); } static void relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) { - msr_t tseg_base, tseg_mask; + struct smm_relocation_params *relo_params = &smm_reloc_params; amd64_smm_state_save_area_t *smm_state; - tseg_base.lo = relo_attrs.tseg_base; - tseg_base.hi = 0; - wrmsr(SMM_ADDR_MSR, tseg_base); - tseg_mask.lo = relo_attrs.tseg_mask; - tseg_mask.hi = ((1 << (cpu_phys_address_size() - 32)) - 1); - wrmsr(SMM_MASK_MSR, tseg_mask); + wrmsr(SMM_ADDR_MSR, relo_params->tseg_base); + wrmsr(SMM_MASK_MSR, relo_params->tseg_mask); + smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase); smm_state->smbase = staggered_smbase; } diff --git a/src/soc/amd/stoneyridge/finalize.c b/src/soc/amd/stoneyridge/finalize.c index 5a4627a432..0ec7bd9218 100644 --- a/src/soc/amd/stoneyridge/finalize.c +++ b/src/soc/amd/stoneyridge/finalize.c @@ -44,7 +44,7 @@ static void finalize_cores(void) int r; printk(BIOS_SPEW, "Lock SMM configuration\n"); - r = mp_run_on_all_cpus(per_core_finalize, NULL, 10 * USECS_PER_MSEC); + r = mp_run_on_all_cpus(per_core_finalize, NULL); if (r) printk(BIOS_WARNING, "Failed to finalize all cores\n"); } diff --git a/src/soc/amd/stoneyridge/include/soc/romstage.h b/src/soc/amd/stoneyridge/include/soc/romstage.h index 6ce79b424e..598b409ba5 100644 --- a/src/soc/amd/stoneyridge/include/soc/romstage.h +++ b/src/soc/amd/stoneyridge/include/soc/romstage.h @@ -16,6 +16,6 @@ #ifndef __STONEYRIDGE_ROMSTAGE_H__ #define __STONEYRIDGE_ROMSTAGE_H__ -void mainboard_romstage_entry(int s3_resume); +void mainboard_romstage_entry_s3(int s3_resume); #endif /* __STONEYRIDGE_ROMSTAGE_H__ */ diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 07c92a185c..dd514ab88f 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -265,22 +265,10 @@ #define SPI_READ_MODE_QUAD144 (BIT(30) | BIT(18)) #define SPI_READ_MODE_NORMAL66 (BIT(30) | BIT(29) ) #define SPI_READ_MODE_FAST (BIT(30) | BIT(29) | BIT(18)) +#define SPI_ACCESS_MAC_ROM_EN BIT(22) #define SPI_FIFO_PTR_CLR BIT(20) #define SPI_ARB_ENABLE BIT(19) #define EXEC_OPCODE BIT(16) -#define SPI_CNTRL1 0x0c -#define SPI_CMD_CODE 0x45 -#define SPI_CMD_TRIGGER 0x47 -#define SPI_CMD_TRIGGER_EXECUTE BIT(7) -#define SPI_TX_BYTE_COUNT 0x48 -#define SPI_RX_BYTE_COUNT 0x4b -#define SPI_STATUS 0x4c -#define SPI_DONE_BYTE_COUNT_SHIFT 0 -#define SPI_DONE_BYTE_COUNT_MASK 0xff -#define SPI_FIFO_WR_PTR_SHIFT 8 -#define SPI_FIFO_WR_PTR_MASK 0x7f -#define SPI_FIFO_RD_PTR_SHIFT 16 -#define SPI_FIFO_RD_PTR_MASK 0x7f #define SPI_FIFO 0x80 #define SPI_FIFO_DEPTH (0xc7 - SPI_FIFO) diff --git a/src/soc/amd/picasso/ramtop.c b/src/soc/amd/stoneyridge/memmap.c similarity index 80% rename from src/soc/amd/picasso/ramtop.c rename to src/soc/amd/stoneyridge/memmap.c index 672fdd8194..09af7e4de7 100644 --- a/src/soc/amd/picasso/ramtop.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -81,12 +81,6 @@ static size_t smm_region_size(void) return CONFIG_SMM_TSEG_SIZE; } -void smm_region(uintptr_t *start, size_t *size) -{ - *start = smm_region_start(); - *size = smm_region_size(); -} - /* * For data stored in TSEG, ensure TValid is clear so R/W access can reach * the DRAM when not in SMM. @@ -109,39 +103,15 @@ static void clear_tvalid(void) wrmsr(SMM_MASK_MSR, mask); } -int smm_subregion(int sub, uintptr_t *start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { static int once; - uintptr_t sub_base; - size_t sub_size; - const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - smm_region(&sub_base, &sub_size); - assert(sub_size > CONFIG_SMM_RESERVED_SIZE); + *start = smm_region_start(); + *size = smm_region_size(); if (!once) { clear_tvalid(); once = 1; } - - switch (sub) { - case SMM_SUBREGION_HANDLER: - /* Handler starts at the base of TSEG. */ - sub_size -= cache_size; - break; - case SMM_SUBREGION_CACHE: - /* External cache is in the middle of TSEG. */ - sub_base += sub_size - cache_size; - sub_size = cache_size; - break; - default: - *start = 0; - *size = 0; - return -1; - } - - *start = (void *)sub_base; - *size = sub_size; - - return 0; } diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 42b08338d4..2228c1a23e 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -16,6 +16,7 @@ #include #include +#include #include #include #include @@ -37,7 +38,7 @@ #include "chip.h" -void __weak mainboard_romstage_entry(int s3_resume) +void __weak mainboard_romstage_entry_s3(int s3_resume) { /* By default, don't do anything */ } @@ -84,8 +85,6 @@ asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; uintptr_t top_of_ram; - uintptr_t smm_base; - size_t smm_size; msr_t base, mask; msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT; @@ -97,7 +96,8 @@ asmlinkage void car_stage_entry(void) if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) load_smu_fw1(); - mainboard_romstage_entry(s3_resume); + mainboard_romstage_entry_s3(s3_resume); + elog_boot_notify(s3_resume); bsp_agesa_call(); @@ -133,8 +133,6 @@ asmlinkage void car_stage_entry(void) msr_t sys_cfg = rdmsr(SYSCFG_MSR); sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB; wrmsr(SYSCFG_MSR, sys_cfg); - if (CONFIG(ELOG_BOOT_COUNT)) - boot_count_increment(); } else { printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); @@ -152,6 +150,9 @@ asmlinkage void car_stage_entry(void) if (romstage_handoff_init(s3_resume)) printk(BIOS_ERR, "Failed to set romstage handoff data\n"); + if (CONFIG(SMM_TSEG)) + smm_list_regions(); + post_code(0x44); if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); @@ -168,15 +169,8 @@ asmlinkage void car_stage_entry(void) /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); + /* Cache the TSEG region */ + postcar_enable_tseg_cache(&pcf); post_code(0x45); run_postcar_phase(&pcf); diff --git a/src/soc/amd/stoneyridge/sm.c b/src/soc/amd/stoneyridge/sm.c index 803e628320..fbcddfab84 100644 --- a/src/soc/amd/stoneyridge/sm.c +++ b/src/soc/amd/stoneyridge/sm.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c index 4a0d833c7b..b11eda6360 100644 --- a/src/soc/amd/stoneyridge/smi.c +++ b/src/soc/amd/stoneyridge/smi.c @@ -19,6 +19,7 @@ */ #include +#include #include #include #include diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index d8438bb366..9eddf853b6 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/amd/stoneyridge/spi.c b/src/soc/amd/stoneyridge/spi.c deleted file mode 100644 index 8abfa160f4..0000000000 --- a/src/soc/amd/stoneyridge/spi.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define SPI_DEBUG_DRIVER CONFIG(DEBUG_SPI_FLASH) - -static uintptr_t spibar; - -static void set_spibar(uintptr_t base) -{ - spibar = base; -} - -static inline uint8_t spi_read8(uint8_t reg) -{ - return read8((void *)(spibar + reg)); -} - -static inline uint32_t spi_read32(uint8_t reg) -{ - return read32((void *)(spibar + reg)); -} - -static inline void spi_write8(uint8_t reg, uint8_t val) -{ - write8((void *)(spibar + reg), val); -} - -static inline void spi_write32(uint8_t reg, uint32_t val) -{ - write32((void *)(spibar + reg), val); -} - -static void dump_state(const char *str) -{ - if (!SPI_DEBUG_DRIVER) - return; - - printk(BIOS_DEBUG, "SPI: %s\n", str); - printk(BIOS_DEBUG, "Cntrl0: %x\n", spi_read32(SPI_CNTRL0)); - printk(BIOS_DEBUG, "Status: %x\n", spi_read32(SPI_STATUS)); - printk(BIOS_DEBUG, "TxByteCount: %x\n", spi_read8(SPI_TX_BYTE_COUNT)); - printk(BIOS_DEBUG, "RxByteCount: %x\n", spi_read8(SPI_RX_BYTE_COUNT)); - printk(BIOS_DEBUG, "CmdCode: %x\n", spi_read8(SPI_CMD_CODE)); - hexdump((void *)(spibar + SPI_FIFO), SPI_FIFO_DEPTH); -} - -static int wait_for_ready(void) -{ - const uint32_t timeout_ms = 500; - struct stopwatch sw; - - stopwatch_init_msecs_expire(&sw, timeout_ms); - - do { - if (!(spi_read32(SPI_STATUS) & SPI_BUSY)) - return 0; - } while (!stopwatch_expired(&sw)); - - return -1; -} - -static int execute_command(void) -{ - dump_state("Before Execute"); - - spi_write8(SPI_CMD_TRIGGER, SPI_CMD_TRIGGER_EXECUTE); - - if (wait_for_ready()) - printk(BIOS_DEBUG, - "FCH SPI Error: Timeout executing command\n"); - - dump_state("Transaction finished"); - - return 0; -} - -void spi_init(void) -{ - set_spibar(lpc_get_spibase()); -} - -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - size_t count; - uint8_t cmd; - uint8_t *bufin = din; - const uint8_t *bufout = dout; - - if (SPI_DEBUG_DRIVER) - printk(BIOS_DEBUG, "%s(%zx, %zx)\n", __func__, bytesout, - bytesin); - - /* First byte is cmd which cannot be sent through FIFO */ - cmd = bufout[0]; - bufout++; - bytesout--; - - /* - * Check if this is a write command attempting to transfer more bytes - * than the controller can handle. Iterations for writes are not - * supported here because each SPI write command needs to be preceded - * and followed by other SPI commands, and this sequence is controlled - * by the SPI chip driver. - */ - if (bytesout + bytesin > SPI_FIFO_DEPTH) { - printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI" - " chip driver use spi_crop_chunk()?\n"); - return -1; - } - - if (wait_for_ready()) - return -1; - - spi_write8(SPI_CMD_CODE, cmd); - spi_write8(SPI_TX_BYTE_COUNT, bytesout); - spi_write8(SPI_RX_BYTE_COUNT, bytesin); - - for (count = 0; count < bytesout; count++) - spi_write8(SPI_FIFO + count, bufout[count]); - - if (execute_command()) - return -1; - - for (count = 0; count < bytesin; count++) - bufin[count] = spi_read8(SPI_FIFO + count + bytesout); - - return 0; -} - -int chipset_volatile_group_begin(const struct spi_flash *flash) -{ - return 0; -} - -int chipset_volatile_group_end(const struct spi_flash *flash) -{ - return 0; -} - -static int xfer_vectors(const struct spi_slave *slave, - struct spi_op vectors[], size_t count) -{ - return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); -} - -static const struct spi_ctrlr spi_ctrlr = { - .xfer_vector = xfer_vectors, - .max_xfer_size = SPI_FIFO_DEPTH, - .flags = SPI_CNTRLR_DEDUCT_CMD_LEN | SPI_CNTRLR_DEDUCT_OPCODE_LEN, -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { - .ctrlr = &spi_ctrlr, - .bus_start = 0, - .bus_end = 0, - }, -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/cavium/cn81xx/bl31_plat_params.c b/src/soc/cavium/cn81xx/bl31_plat_params.c index 5d4dead71e..661f3efb85 100644 --- a/src/soc/cavium/cn81xx/bl31_plat_params.c +++ b/src/soc/cavium/cn81xx/bl31_plat_params.c @@ -14,13 +14,13 @@ * */ -#include #include +#include #include static struct bl31_plat_param *plat_params; -void register_bl31_param(struct bl31_plat_param *param) +void cn81xx_register_bl31_param(struct bl31_plat_param *param) { ASSERT(param); @@ -28,7 +28,7 @@ void register_bl31_param(struct bl31_plat_param *param) plat_params = param; } -void *soc_get_bl31_plat_params(bl31_params_t *bl31_params) +void *soc_get_bl31_plat_params(void) { return plat_params; } diff --git a/src/soc/cavium/cn81xx/include/soc/bl31_plat_params.h b/src/soc/cavium/cn81xx/include/soc/bl31_plat_params.h index f365aad059..e47de899e4 100644 --- a/src/soc/cavium/cn81xx/include/soc/bl31_plat_params.h +++ b/src/soc/cavium/cn81xx/include/soc/bl31_plat_params.h @@ -19,6 +19,6 @@ #include -void register_bl31_param(struct bl31_plat_param *param); +void cn81xx_register_bl31_param(struct bl31_plat_param *param); #endif/* __BL31_PLAT_PARAMS_H__ */ diff --git a/src/soc/cavium/cn81xx/include/soc/soc.h b/src/soc/cavium/cn81xx/include/soc/soc.h index a751e64846..582cff3e29 100644 --- a/src/soc/cavium/cn81xx/include/soc/soc.h +++ b/src/soc/cavium/cn81xx/include/soc/soc.h @@ -16,7 +16,7 @@ #ifndef __SOC_CAVIUM_CN81XX_INCLUDE_SOC_SOC_H #define __SOC_CAVIUM_CN81XX_INCLUDE_SOC_SOC_H -#include +#include #include /* MIO BOOT Registers */ diff --git a/src/soc/cavium/cn81xx/include/soc/timer.h b/src/soc/cavium/cn81xx/include/soc/timer.h index 4e4131136e..5e6673e0ea 100644 --- a/src/soc/cavium/cn81xx/include/soc/timer.h +++ b/src/soc/cavium/cn81xx/include/soc/timer.h @@ -16,7 +16,7 @@ #ifndef __SOC_CAVIUM_CN81XX_TIMER_H__ #define __SOC_CAVIUM_CN81XX_TIMER_H__ -#include +#include #include /* Watchdog functions */ diff --git a/src/soc/cavium/cn81xx/include/soc/uart.h b/src/soc/cavium/cn81xx/include/soc/uart.h index e4022068bc..baa06e1f89 100644 --- a/src/soc/cavium/cn81xx/include/soc/uart.h +++ b/src/soc/cavium/cn81xx/include/soc/uart.h @@ -16,7 +16,7 @@ #ifndef __SOC_CAVIUM_COMMON_INCLUDE_SOC_UART_H #define __SOC_CAVIUM_COMMON_INCLUDE_SOC_UART_H -#include +#include #include int uart_is_enabled(const size_t bus); diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index f1e11d335b..8abb328ba8 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -354,7 +354,7 @@ static void soc_init_atf(void) /* Point to devicetree in secure memory */ fdt_param.fdt_ptr = (uintptr_t)_sff8104; - register_bl31_param(&fdt_param.h); + cn81xx_register_bl31_param(&fdt_param.h); static struct bl31_u64_param cbtable_param = { .h = { .type = PARAM_COREBOOT_TABLE, }, @@ -362,7 +362,7 @@ static void soc_init_atf(void) /* Point to coreboot tables */ cbtable_param.value = (uint64_t)cbmem_find(CBMEM_ID_CBTABLE); if (cbtable_param.value) - register_bl31_param(&cbtable_param.h); + cn81xx_register_bl31_param(&cbtable_param.h); } static void soc_init(struct device *dev) diff --git a/src/soc/cavium/cn81xx/timer.c b/src/soc/cavium/cn81xx/timer.c index b333c7e4d6..bd67d8a888 100644 --- a/src/soc/cavium/cn81xx/timer.c +++ b/src/soc/cavium/cn81xx/timer.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/imgtec/pistachio/uart.c b/src/soc/imgtec/pistachio/uart.c index a39f2ec4d8..1eb232aa13 100644 --- a/src/soc/imgtec/pistachio/uart.c +++ b/src/soc/imgtec/pistachio/uart.c @@ -143,7 +143,6 @@ void uart_tx_flush(int idx) uart8250_mem_tx_flush(CONFIG_CONSOLE_SERIAL_UART_ADDRESS); } -#ifndef __PRE_RAM__ void uart_fill_lb(void *data) { struct lb_serial serial; @@ -151,8 +150,9 @@ void uart_fill_lb(void *data) serial.baseaddr = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; serial.baud = get_uart_baudrate(); serial.regwidth = 1 << UART_SHIFT; + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } -#endif diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index ee74dbf997..a1d3c07093 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -57,8 +57,6 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_CLK_PM select PCIEXP_L1_SUB_STATE select PCIEX_LENGTH_256MB - select POSTCAR_CONSOLE - select POSTCAR_STAGE select PMC_INVALID_READ_AFTER_WRITE select PMC_GLOBAL_RESET_ENABLE_LOCK select REG_SCRIPT diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 60b1a3c4f5..41faf7243b 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -21,6 +21,7 @@ bootblock-y += spi.c bootblock-y += uart.c romstage-y += car.c +romstage-y += ../../../cpu/intel/car/romstage.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c romstage-y += gspi.c romstage-y += heci.c diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 7b4eaef430..a07c4620af 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -68,7 +69,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) enable_rtc_upper_bank(); /* Call lib/bootblock.c main */ - bootblock_main_with_timestamp(base_timestamp, NULL, 0); + bootblock_main_with_basetime(base_timestamp); } static void enable_pmcbar(void) @@ -96,6 +97,8 @@ void bootblock_soc_early_init(void) /* Prepare UART for serial console. */ if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); + if (CONFIG(DRIVERS_UART_8250IO)) + lpc_io_setup_comm_a_b(); if (CONFIG(TPM_ON_FAST_SPI)) tpm_enable(); diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 361e6a417e..b69f9eeeef 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -764,7 +764,7 @@ struct chip_operations soc_intel_apollolake_ops = { static void drop_privilege_all(void) { /* Drop privilege level on all the CPUs */ - if (mp_run_on_all_cpus(&cpu_enable_untrusted_mode, NULL, 1000) < 0) + if (mp_run_on_all_cpus(&cpu_enable_untrusted_mode, NULL) < 0) printk(BIOS_ERR, "failed to enable untrusted mode\n"); } diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 9b9b722bb3..3f06026336 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -30,6 +30,8 @@ #include #include #include +#include +#include #include #include #include @@ -38,7 +40,6 @@ #include #include #include -#include #include #include #include @@ -255,7 +256,7 @@ static void post_mp_init(void) smm_southbridge_enable(PWRBTN_EN | GBL_EN); if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) - mp_run_on_all_cpus(sgx_configure, NULL, 2000); + mp_run_on_all_cpus(sgx_configure, NULL); } static const struct mp_ops mp_ops = { diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index 82226ecf43..6ee1a155ea 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -28,12 +28,6 @@ #include #include -#define PCI_ME_HFSTS1 0x40 -#define PCI_ME_HFSTS2 0x48 -#define PCI_ME_HFSTS3 0x60 -#define PCI_ME_HFSTS4 0x64 -#define PCI_ME_HFSTS5 0x68 -#define PCI_ME_HFSTS6 0x6c #define MKHI_GROUP_ID_MCA 0x0a #define READ_FILE 0x02 @@ -58,17 +52,6 @@ static enum fuse_flash_state { #define FPF_STATUS_FMAP "FPF_STATUS" -union mkhi_header { - uint32_t data; - struct { - uint32_t group_id: 8; - uint32_t command: 7; - uint32_t is_response: 1; - uint32_t reserved: 8; - uint32_t result: 8; - } __packed fields; -}; - /* * Read file from CSE internal filesystem. * size is maximum length of provided buffer buff, which is updated with actual @@ -82,7 +65,7 @@ static int read_cse_file(const char *path, void *buff, size_t *size, size_t reply_size; struct mca_command { - union mkhi_header mkhi_hdr; + struct mkhi_hdr hdr; char file_name[MCA_MAX_FILE_PATH_SIZE]; uint32_t offset; uint32_t data_size; @@ -90,7 +73,7 @@ static int read_cse_file(const char *path, void *buff, size_t *size, } __packed msg; struct mca_response { - union mkhi_header mkhi_hdr; + struct mkhi_hdr hdr; uint32_t data_size; uint8_t buffer[128]; } __packed rmsg; @@ -105,8 +88,8 @@ static int read_cse_file(const char *path, void *buff, size_t *size, return 0; } strncpy(msg.file_name, path, sizeof(msg.file_name)); - msg.mkhi_hdr.fields.group_id = MKHI_GROUP_ID_MCA; - msg.mkhi_hdr.fields.command = READ_FILE; + msg.hdr.group_id = MKHI_GROUP_ID_MCA; + msg.hdr.command = READ_FILE; msg.flags = flags; msg.data_size = *size; msg.offset = offset; @@ -188,7 +171,9 @@ static void fpf_blown(void *unused) static uint32_t dump_status(int index, int reg_addr) { - uint32_t reg = pci_read_config32(PCH_DEV_CSE, reg_addr); + uint32_t reg; + + reg = me_read_config32(reg_addr); printk(BIOS_DEBUG, "CSE FWSTS%d: 0x%08x\n", index, reg); @@ -199,11 +184,7 @@ static void dump_cse_version(void *unused) { int res; size_t reply_size; - - struct fw_version_cmd { - union mkhi_header mkhi_hdr; - } __packed msg; - + struct mkhi_hdr msg; struct version { uint16_t minor; uint16_t major; @@ -212,7 +193,7 @@ static void dump_cse_version(void *unused) } __packed; struct fw_version_response { - union mkhi_header mkhi_hdr; + struct mkhi_hdr hdr; struct version code; struct version nftp; struct version fitc; @@ -225,8 +206,8 @@ static void dump_cse_version(void *unused) if (!CONFIG(CONSOLE_SERIAL)) return; - msg.mkhi_hdr.fields.group_id = MKHI_GROUP_ID_GEN; - msg.mkhi_hdr.fields.command = GET_FW_VERSION; + msg.group_id = MKHI_GROUP_ID_GEN; + msg.command = GET_FW_VERSION; res = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR); @@ -243,7 +224,7 @@ static void dump_cse_version(void *unused) return; } - if (rsp.mkhi_hdr.fields.result != 0) { + if (rsp.hdr.result != 0) { printk(BIOS_ERR, "Failed to get ME version.\n"); return; } @@ -256,6 +237,9 @@ static void dump_cse_state(void) { uint32_t fwsts1; + if (!is_cse_enabled()) + return; + fwsts1 = dump_status(1, PCI_ME_HFSTS1); dump_status(2, PCI_ME_HFSTS2); dump_status(3, PCI_ME_HFSTS3); diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 17dfb3f545..905fa64571 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -15,12 +15,13 @@ * GNU General Public License for more details. */ +#include #include #include #include +#include #include #include -#include #include #include @@ -49,31 +50,21 @@ void smm_region(uintptr_t *start, size_t *size) *size = sa_get_tseg_size(); } -int smm_subregion(int sub, uintptr_t *start, size_t *size) +void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t sub_base; - size_t sub_size; - const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + uintptr_t top_of_ram; - smm_region(&sub_base, &sub_size); + /* + * We need to make sure ramstage will be run cached. At this point exact + * location of ramstage in cbmem is not known. Instruct postcar to cache + * 16 megs under cbmem top which is a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t) cbmem_top(); + /* cbmem_top() needs to be at least 16 MiB aligned */ + assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); + postcar_frame_add_mtrr(pcf, top_of_ram - 16*MiB, 16*MiB, + MTRR_TYPE_WRBACK); - switch (sub) { - case SMM_SUBREGION_HANDLER: - /* Handler starts at the base of TSEG. */ - sub_size -= cache_size; - break; - case SMM_SUBREGION_CACHE: - /* External cache is in the middle of TSEG. */ - sub_base += sub_size - cache_size; - sub_size = cache_size; - break; - default: - *start = 0; - *size = 0; - return -1; - } - - *start = sub_base; - *size = sub_size; - return 0; + /* Cache the TSEG region */ + postcar_enable_tseg_cache(pcf); } diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 3ce63704fb..29498656dc 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -16,7 +16,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include @@ -36,7 +35,6 @@ #include #include #include -#include #include #include #include @@ -48,7 +46,6 @@ #include #include #include -#include #include "chip.h" static const uint8_t hob_variable_guid[16] = { @@ -92,9 +89,6 @@ static void soc_early_romstage_init(void) /* Enable decoding for HPET. Needed for FSP global pointer storage */ pci_write_config8(PCH_DEV_P2SB, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 | P2SB_HPTC_ADDRESS_ENABLE); - - if (CONFIG(DRIVERS_UART_8250IO)) - lpc_io_setup_comm_a_b(); } /* Thermal throttle activation offset */ @@ -196,22 +190,15 @@ void set_max_freq(void) cpu_set_p_state_to_turbo_ratio(); } -asmlinkage void car_stage_entry(void) +void mainboard_romstage_entry(void) { - struct postcar_frame pcf; - uintptr_t top_of_ram; bool s3wake; + size_t var_size; struct chipset_power_state *ps = pmc_get_power_state(); - uintptr_t smm_base; - size_t smm_size, var_size; const void *new_var_data; - timestamp_add_now(TS_START_ROMSTAGE); - soc_early_romstage_init(); - console_init(); - s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); @@ -230,36 +217,7 @@ asmlinkage void car_stage_entry(void) else printk(BIOS_ERR, "Failed to determine variable data\n"); - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - mainboard_save_dimm_info(); - - /* - * We need to make sure ramstage will be run cached. At this point exact - * location of ramstage in cbmem is not known. Instruct postcar to cache - * 16 megs under cbmem top which is a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - /* cbmem_top() needs to be at least 16 MiB aligned */ - assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); - postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, - MTRR_TYPE_WRBACK); - - /* Cache the memory-mapped boot media. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); - - run_postcar_phase(&pcf); } static void fill_console_params(FSPM_UPD *mupd) diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index 7a3400ed3b..53d2b7e858 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -15,6 +15,7 @@ */ #include +#include #include #include #include diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 4b816a20b6..c833c5360f 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -36,8 +36,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_SPI_CONSOLE_SUPPORT select INTEL_GMA_ACPI select INTEL_GMA_SWSMISCI - select POSTCAR_STAGE - select POSTCAR_CONSOLE select CPU_INTEL_COMMON select CPU_HAS_L2_ENABLE_MSR diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index acac67930e..6f0d98acbe 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -15,7 +15,6 @@ #include #include -#include #include #include diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index 00e7fd6f73..f153913a0f 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -87,5 +87,4 @@ struct soc_intel_baytrail_config { int disable_ddr_2x_refresh_rate; }; -extern struct chip_operations soc_intel_baytrail_ops; #endif /* _BAYTRAIL_CHIP_H_ */ diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 952693217c..edc4e83da5 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -17,7 +17,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -86,13 +88,12 @@ static const struct cpu_driver driver __cpu_driver = { * MP and SMM loading initialization. */ -struct smm_relocation_attrs { - uint32_t smbase; - uint32_t smrr_base; - uint32_t smrr_mask; +struct smm_relocation_params { + msr_t smrr_base; + msr_t smrr_mask; }; -static struct smm_relocation_attrs relo_attrs; +static struct smm_relocation_params smm_reloc_params; /* Package level MSRs */ static const struct reg_script package_msr_script[] = { @@ -138,20 +139,32 @@ static int get_cpu_count(void) return pattrs->num_cpus; } +static void fill_in_relocation_params(struct smm_relocation_params *params) +{ + uintptr_t tseg_base; + size_t tseg_size; + + /* All range registers are aligned to 4KiB */ + const u32 rmask = ~((1 << 12) - 1); + + smm_region(&tseg_base, &tseg_size); + + /* SMRR has 32-bits of valid address aligned to 4KiB. */ + params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.hi = 0; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; + params->smrr_mask.hi = 0; +} + static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - /* All range registers are aligned to 4KiB */ - const uint32_t rmask = ~((1 << 12) - 1); + printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - /* Initialize global tracking state. */ - relo_attrs.smbase = (uint32_t)smm_region_start(); - relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; - relo_attrs.smrr_mask = ~(smm_region_size() - 1) & rmask; - relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; + fill_in_relocation_params(&smm_reloc_params); + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - *perm_smbase = relo_attrs.smbase; - *perm_smsize = smm_region_size() - CONFIG_SMM_RESERVED_SIZE; *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); } @@ -177,16 +190,12 @@ static void per_cpu_smm_trigger(void) static void relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) { - msr_t smrr; + struct smm_relocation_params *relo_params = &smm_reloc_params; em64t100_smm_state_save_area_t *smm_state; /* Set up SMRR. */ - smrr.lo = relo_attrs.smrr_base; - smrr.hi = 0; - wrmsr(IA32_SMRR_PHYS_BASE, smrr); - smrr.lo = relo_attrs.smrr_mask; - smrr.hi = 0; - wrmsr(IA32_SMRR_PHYS_MASK, smrr); + wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); smm_state->smbase = staggered_smbase; @@ -197,10 +206,10 @@ static const struct mp_ops mp_ops = { .get_cpu_count = get_cpu_count, .get_smm_info = get_smm_info, .get_microcode_info = get_microcode_info, - .pre_mp_smm_init = southcluster_smm_clear_state, + .pre_mp_smm_init = smm_southbridge_clear_state, .per_cpu_smm_trigger = per_cpu_smm_trigger, .relocation_handler = relocation_handler, - .post_mp_init = southcluster_smm_enable_smi, + .post_mp_init = smm_southbridge_enable_smi, }; void baytrail_init_cpus(struct device *dev) diff --git a/src/soc/intel/baytrail/elog.c b/src/soc/intel/baytrail/elog.c index 45dcec8b3a..d7a0460816 100644 --- a/src/soc/intel/baytrail/elog.c +++ b/src/soc/intel/baytrail/elog.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c index 8d9ce0075e..3460a5f049 100644 --- a/src/soc/intel/baytrail/gpio.c +++ b/src/soc/intel/baytrail/gpio.c @@ -190,7 +190,7 @@ static void setup_gpio_route(const struct soc_gpio_map *sus, route_reg |= ROUTE_SCI << (2 * (i + 8)); } } - southcluster_smm_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg); + smm_southcluster_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg); } static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS], diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h index e39758c64b..5038bf87db 100644 --- a/src/soc/intel/baytrail/include/soc/msr.h +++ b/src/soc/intel/baytrail/include/soc/msr.h @@ -40,5 +40,6 @@ /* Read BCLK from MSR */ unsigned bus_freq_khz(void); +void set_max_freq(void); #endif /* _BAYTRAIL_MSR_H_ */ diff --git a/src/soc/intel/baytrail/include/soc/ramstage.h b/src/soc/intel/baytrail/include/soc/ramstage.h index d20859d055..f98a79b2ea 100644 --- a/src/soc/intel/baytrail/include/soc/ramstage.h +++ b/src/soc/intel/baytrail/include/soc/ramstage.h @@ -23,7 +23,6 @@ * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(struct soc_intel_baytrail_config *config); void baytrail_init_cpus(struct device *dev); -void set_max_freq(void); void southcluster_enable_dev(struct device *dev); #if CONFIG(HAVE_REFCODE_BLOB) void baytrail_run_reference_code(void); diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index fffce7e317..e86861c4bf 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -16,32 +16,16 @@ #ifndef _BAYTRAIL_ROMSTAGE_H_ #define _BAYTRAIL_ROMSTAGE_H_ -#if !defined(__PRE_RAM__) -#error "Don't include romstage.h from a ramstage compilation unit!" -#endif - #include #include #include -struct romstage_params { - unsigned long bist; - struct mrc_params *mrc_params; -}; - -void mainboard_romstage_entry(struct romstage_params *params); -void romstage_common(struct romstage_params *params); +void mainboard_fill_mrc_params(struct mrc_params *mp); void raminit(struct mrc_params *mp, int prev_sleep_state); void gfx_init(void); void tco_disable(void); void punit_init(void); -void set_max_freq(void); - -#if CONFIG(ENABLE_BUILTIN_COM1) void byt_config_com1_and_enable(void); -#else -static inline void byt_config_com1_and_enable(void) { } -#endif #endif /* _BAYTRAIL_ROMSTAGE_H_ */ diff --git a/src/soc/intel/baytrail/include/soc/smm.h b/src/soc/intel/baytrail/include/soc/smm.h index ac0910f306..a2b7ec02d7 100644 --- a/src/soc/intel/baytrail/include/soc/smm.h +++ b/src/soc/intel/baytrail/include/soc/smm.h @@ -16,25 +16,7 @@ #ifndef _BAYTRAIL_SMM_H_ #define _BAYTRAIL_SMM_H_ -/* There is a bug in the order of Kconfig includes in that arch/x86/Kconfig - * is included after chipset code. This causes the chipset's Kconfig to be - * clobbered by the arch/x86/Kconfig if they have the same name. */ -static inline int smm_region_size(void) -{ - /* Make it 8MiB by default. */ - if (CONFIG_SMM_TSEG_SIZE == 0) - return (8 << 20); - return CONFIG_SMM_TSEG_SIZE; -} - -uintptr_t smm_region_start(void); - -#if !defined(__PRE_RAM__) && !defined(__SMM___) -#include -void southcluster_smm_clear_state(void); -void southcluster_smm_enable_smi(void); -void southcluster_smm_save_param(int param, uint32_t data); -#endif +#include enum { SMM_SAVE_PARAM_GPIO_ROUTE = 0, @@ -42,4 +24,6 @@ enum { SMM_SAVE_PARAM_COUNT }; +void smm_southcluster_save_param(int param, uint32_t data); + #endif /* _BAYTRAIL_SMM_H_ */ diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index 94e91ca7a1..d9f6160dfc 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -13,30 +13,42 @@ * GNU General Public License for more details. */ +#include #include -#include +#include +#include #include -#include -uintptr_t smm_region_start(void) +static uintptr_t smm_region_start(void) { return (iosf_bunit_read(BUNIT_SMRRL) << 20); } +static size_t smm_region_size(void) +{ + return CONFIG_SMM_TSEG_SIZE; +} + void *cbmem_top(void) { return (void *) smm_region_start(); } -void stage_cache_external_region(void **base, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - char *smm_base; - /* 1MiB cache size */ - const long cache_size = CONFIG_SMM_RESERVED_SIZE; - - /* Ramstage cache lives in TSEG region which is the definition of - * cbmem_top(). */ - smm_base = cbmem_top(); - *size = cache_size; - *base = &smm_base[smm_region_size() - cache_size]; + *start = (iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20; + *size = smm_region_size(); +} + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + + /* Cache at least 8 MiB below the top of ram, and at most 8 MiB + * above top of the ram. This satisfies MTRR alignment requirement + * with different TSEG size configurations. + */ + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, + MTRR_TYPE_WRBACK); } diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index 5f33c86c9b..654d2371e7 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -64,7 +64,7 @@ uint32_t nc_read_top_of_low_memory(void) { - MAYBE_STATIC uint32_t tolm = 0; + MAYBE_STATIC_BSS uint32_t tolm = 0; if (tolm) return tolm; diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index b2b2d3c3b4..6dc0346b23 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -215,7 +215,7 @@ static void byt_pcie_enable(struct device *dev) strpfusecfg = pci_read_config32(dev, STRPFUSECFG); if (config->pcie_wake_enable) - southcluster_smm_save_param( + smm_southcluster_save_param( SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, 1); } diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc index d43a6fb6e3..2effbb08f6 100644 --- a/src/soc/intel/baytrail/romstage/Makefile.inc +++ b/src/soc/intel/baytrail/romstage/Makefile.inc @@ -1,5 +1,7 @@ cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S cpu_incs-y += $(obj)/fmap_config.h + +romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += raminit.c romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 7e2bb64ba6..7c129e258e 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -14,43 +14,29 @@ */ #include -#include #include +#include #include #include -#include #include #include -#include #if CONFIG(EC_GOOGLE_CHROMEEC) #include #endif #include -#include #include -#include #include #include #include #include #include #include +#include #include #include #include -#include #include -/* The cache-as-ram assembly file calls romstage_main() after setting up - * cache-as-ram. romstage_main() will then call the mainboards's - * mainboard_romstage_entry() function. That function then calls - * romstage_common() below. The reason for the back and forth is to provide - * common entry point from cache-as-ram while still allowing for code sharing. - * Because we can't use global variables the stack is used for allocations -- - * thus the need to call back and forth. */ - -static void platform_enter_postcar(void); - static void program_base_addresses(void) { uint32_t reg; @@ -96,52 +82,6 @@ static void spi_init(void) write32(bcr, reg); } -/* Entry from cache-as-ram.inc. */ -static void romstage_main(uint64_t tsc, uint32_t bist) -{ - struct romstage_params rp = { - .bist = bist, - .mrc_params = NULL, - }; - - /* Save initial timestamp from bootblock. */ - timestamp_init(tsc); - - /* Save romstage begin */ - timestamp_add_now(TS_START_ROMSTAGE); - - program_base_addresses(); - - tco_disable(); - - byt_config_com1_and_enable(); - - console_init(); - - spi_init(); - - set_max_freq(); - - punit_init(); - - gfx_init(); - - /* Call into mainboard. */ - mainboard_romstage_entry(&rp); - - platform_enter_postcar(); - - /* We don't return here */ -} - -/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, - * keeping changes in cache_as_ram.S easy to manage. - */ -asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) -{ - romstage_main(base_timestamp, bist); -} - static struct chipset_power_state power_state; static void migrate_power_state(int is_recovery) @@ -211,11 +151,32 @@ static int chipset_prev_sleep_state(struct chipset_power_state *ps) return prev_sleep_state; } -/* Entry from the mainboard. */ -void romstage_common(struct romstage_params *params) +/* Entry from cpu/intel/car/romstage.c */ +void mainboard_romstage_entry(void) { struct chipset_power_state *ps; int prev_sleep_state; + struct mrc_params mp; + + program_base_addresses(); + + tco_disable(); + + if (CONFIG(ENABLE_BUILTIN_COM1)) + byt_config_com1_and_enable(); + + console_init(); + + spi_init(); + + set_max_freq(); + + punit_init(); + + gfx_init(); + + memset(&mp, 0, sizeof(mp)); + mainboard_fill_mrc_params(&mp); timestamp_add_now(TS_BEFORE_INITRAM); @@ -224,42 +185,12 @@ void romstage_common(struct romstage_params *params) printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state); -#if CONFIG(ELOG_BOOT_COUNT) - if (prev_sleep_state != ACPI_S3) - boot_count_increment(); -#endif - + elog_boot_notify(prev_sleep_state == ACPI_S3); /* Initialize RAM */ - raminit(params->mrc_params, prev_sleep_state); + raminit(&mp, prev_sleep_state); timestamp_add_now(TS_AFTER_INITRAM); romstage_handoff_init(prev_sleep_state == ACPI_S3); } - -/* setup_stack_and_mtrrs() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use. */ -static void platform_enter_postcar(void) -{ - struct postcar_frame pcf; - uintptr_t top_of_ram; - - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB - * above top of the ram. This satisfies MTRR alignment requirement - * with different TSEG size configurations. - */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, - MTRR_TYPE_WRBACK); - - run_postcar_phase(&pcf); -} diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 1bc9ed1c34..7de9d960a0 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index 42bc518f36..4f019229e4 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -27,12 +28,12 @@ /* Save settings which will be committed in SMI functions. */ static uint32_t smm_save_params[SMM_SAVE_PARAM_COUNT]; -void southcluster_smm_save_param(int param, uint32_t data) +void smm_southcluster_save_param(int param, uint32_t data) { smm_save_params[param] = data; } -void southcluster_smm_clear_state(void) +void smm_southbridge_clear_state(void) { uint32_t smi_en; @@ -57,7 +58,7 @@ void southcluster_smm_clear_state(void) clear_pmc_status(); } -static void southcluster_smm_route_gpios(void) +static void smm_southcluster_route_gpios(void) { u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT); const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI; @@ -82,7 +83,7 @@ static void southcluster_smm_route_gpios(void) outl(alt_gpio_reg, alt_gpio_smi); } -void southcluster_smm_enable_smi(void) +void smm_southbridge_enable_smi(void) { uint16_t pm1_events = PWRBTN_EN | GBL_EN; @@ -93,7 +94,7 @@ void southcluster_smm_enable_smi(void) disable_gpe(PME_B0_EN); /* Set up the GPIO route. */ - southcluster_smm_route_gpios(); + smm_southcluster_route_gpios(); /* Enable SMI generation: * - on APMC writes (io 0xb2) diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index d5b962ffe7..26b717c65e 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -248,6 +248,8 @@ static ich9_spi_regs *spi_regs(void) return (void *)sbase; } +#define MENU_BYTES member_size(struct ich9_spi_regs, opmenu) + void spi_init(void) { ich9_spi_regs *ich9_spi = spi_regs(); @@ -332,7 +334,7 @@ static void spi_setup_type(spi_transaction *trans) static int spi_setup_opcode(spi_transaction *trans) { uint16_t optypes; - uint8_t opmenu[cntlr.menubytes]; + uint8_t opmenu[MENU_BYTES]; trans->opcode = trans->out[0]; spi_use_out(trans, 1); @@ -353,13 +355,12 @@ static int spi_setup_opcode(spi_transaction *trans) return 0; read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < cntlr.menubytes; - opcode_index++) { + for (opcode_index = 0; opcode_index < ARRAY_SIZE(opmenu); opcode_index++) { if (opmenu[opcode_index] == trans->opcode) break; } - if (opcode_index == cntlr.menubytes) { + if (opcode_index == ARRAY_SIZE(opmenu)) { printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", trans->opcode); return -1; diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c index f9c3014273..5b2d13599d 100644 --- a/src/soc/intel/baytrail/tsc_freq.c +++ b/src/soc/intel/baytrail/tsc_freq.c @@ -47,13 +47,6 @@ unsigned long tsc_freq_mhz(void) return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000; } -#if !defined(__SMM__) -#if !defined(__PRE_RAM__) -#include -#else -#include -#endif - void set_max_freq(void) { msr_t perf_ctl; @@ -76,5 +69,3 @@ void set_max_freq(void) wrmsr(IA32_PERF_CTL, perf_ctl); } - -#endif /* __SMM__ */ diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index 2d1a3e8687..d8d953c8a7 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -31,7 +31,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { /* Call lib/bootblock.c main */ - bootblock_main_with_timestamp(base_timestamp, NULL, 0); + bootblock_main_with_basetime(base_timestamp); } static void program_base_addresses(void) diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 5a00328f4d..747b941f55 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -171,6 +171,4 @@ struct soc_intel_braswell_config { UINT8 I2C6Frequency; }; -extern struct chip_operations soc_intel_braswell_ops; - #endif /* _SOC_CHIP_H_ */ diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 1cee4b9ca4..665b030245 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -18,8 +18,11 @@ #include #include #include +#include #include +#include #include +#include #include #include #include @@ -95,13 +98,12 @@ static const struct cpu_driver driver __cpu_driver = { * MP and SMM loading initialization. */ -struct smm_relocation_attrs { - uint32_t smbase; - uint32_t smrr_base; - uint32_t smrr_mask; +struct smm_relocation_params { + msr_t smrr_base; + msr_t smrr_mask; }; -static struct smm_relocation_attrs relo_attrs; +static struct smm_relocation_params smm_reloc_params; /* Package level MSRs */ static const struct reg_script package_msr_script[] = { @@ -147,24 +149,32 @@ static int get_cpu_count(void) return pattrs->num_cpus; } +static void fill_in_relocation_params(struct smm_relocation_params *params) +{ + uintptr_t tseg_base; + size_t tseg_size; + + /* All range registers are aligned to 4KiB */ + const u32 rmask = ~((1 << 12) - 1); + + smm_region(&tseg_base, &tseg_size); + + /* SMRR has 32-bits of valid address aligned to 4KiB. */ + params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.hi = 0; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; + params->smrr_mask.hi = 0; +} + static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - uintptr_t smm_base; - size_t smm_size; + printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - /* All range registers are aligned to 4KiB */ - const uint32_t rmask = ~((1 << 12) - 1); + fill_in_relocation_params(&smm_reloc_params); - /* Initialize global tracking state. */ - smm_region(&smm_base, &smm_size); - relo_attrs.smbase = smm_base; - relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; - relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; - relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - *perm_smbase = relo_attrs.smbase; - *perm_smsize = smm_size - CONFIG_SMM_RESERVED_SIZE; *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); } @@ -196,16 +206,12 @@ static void per_cpu_smm_trigger(void) static void relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) { - msr_t smrr; + struct smm_relocation_params *relo_params = &smm_reloc_params; em64t100_smm_state_save_area_t *smm_state; /* Set up SMRR. */ - smrr.lo = relo_attrs.smrr_base; - smrr.hi = 0; - wrmsr(IA32_SMRR_PHYS_BASE, smrr); - smrr.lo = relo_attrs.smrr_mask; - smrr.hi = 0; - wrmsr(IA32_SMRR_PHYS_MASK, smrr); + wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); smm_state->smbase = staggered_smbase; @@ -216,10 +222,10 @@ static const struct mp_ops mp_ops = { .get_cpu_count = get_cpu_count, .get_smm_info = get_smm_info, .get_microcode_info = get_microcode_info, - .pre_mp_smm_init = southcluster_smm_clear_state, + .pre_mp_smm_init = smm_southbridge_clear_state, .per_cpu_smm_trigger = per_cpu_smm_trigger, .relocation_handler = relocation_handler, - .post_mp_init = southcluster_smm_enable_smi, + .post_mp_init = smm_southbridge_enable_smi, }; void soc_init_cpus(struct device *dev) diff --git a/src/soc/intel/braswell/elog.c b/src/soc/intel/braswell/elog.c index f1fc7d4e24..6efcef1452 100644 --- a/src/soc/intel/braswell/elog.c +++ b/src/soc/intel/braswell/elog.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/braswell/gpio.c b/src/soc/intel/braswell/gpio.c index 77547b8a8e..14f95e1867 100644 --- a/src/soc/intel/braswell/gpio.c +++ b/src/soc/intel/braswell/gpio.c @@ -176,7 +176,7 @@ static void setup_gpio_route(const struct soc_gpio_map *sw_gpios, route_reg, alt_gpio_smi, gpe0a_en); #endif /* Save as an smm param */ - southcluster_smm_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg); + smm_southcluster_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg); } diff --git a/src/soc/intel/braswell/include/soc/smm.h b/src/soc/intel/braswell/include/soc/smm.h index 93065a2a94..68b4cb0025 100644 --- a/src/soc/intel/braswell/include/soc/smm.h +++ b/src/soc/intel/braswell/include/soc/smm.h @@ -17,13 +17,7 @@ #ifndef _SOC_SMM_H_ #define _SOC_SMM_H_ - -#if ENV_RAMSTAGE -#include -void southcluster_smm_clear_state(void); -void southcluster_smm_enable_smi(void); -void southcluster_smm_save_param(int param, uint32_t data); -#endif +#include enum { SMM_SAVE_PARAM_GPIO_ROUTE = 0, @@ -31,4 +25,6 @@ enum { SMM_SAVE_PARAM_COUNT }; +void smm_southcluster_save_param(int param, uint32_t data); + #endif /* _SOC_SMM_H_ */ diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index 51b7b36db4..d502aed9f9 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -17,7 +17,6 @@ #include #include #include -#include static size_t smm_region_size(void) { @@ -34,44 +33,6 @@ void smm_region(uintptr_t *start, size_t *size) *size = smm_region_size(); } -/* - * Subregions within SMM - * +-------------------------+ BUNIT_SMRRH - * | External Stage Cache | SMM_RESERVED_SIZE - * +-------------------------+ - * | code and data | - * | (TSEG) | - * +-------------------------+ BUNIT_SMRRL - */ -int smm_subregion(int sub, uintptr_t *start, size_t *size) -{ - uintptr_t sub_base; - size_t sub_size; - const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - - smm_region(&sub_base, &sub_size); - - switch (sub) { - case SMM_SUBREGION_HANDLER: - /* Handler starts at the base of TSEG. */ - sub_size -= cache_size; - break; - case SMM_SUBREGION_CACHE: - /* External cache is in the middle of TSEG. */ - sub_base += sub_size - cache_size; - sub_size = cache_size; - break; - default: - *start = 0; - *size = 0; - return -1; - } - - *start = sub_base; - *size = sub_size; - return 0; -} - void *cbmem_top(void) { uintptr_t smm_base; diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index ff58ebfeec..e3e3aa79ff 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include @@ -72,7 +71,7 @@ uint32_t nc_read_top_of_low_memory(void) { - MAYBE_STATIC uint32_t tolm = 0; + MAYBE_STATIC_BSS uint32_t tolm = 0; if (tolm) return tolm; diff --git a/src/soc/intel/braswell/pcie.c b/src/soc/intel/braswell/pcie.c index dc779bbb80..4ae7f3f236 100644 --- a/src/soc/intel/braswell/pcie.c +++ b/src/soc/intel/braswell/pcie.c @@ -148,7 +148,7 @@ static void pcie_enable(struct device *dev) strpfusecfg = pci_read_config32(dev, STRPFUSECFG); if (config->pcie_wake_enable) - southcluster_smm_save_param( + smm_southcluster_save_param( SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, 1); } diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index a72330915e..174cd5d7ef 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c index fe681c9d90..364cda5b5a 100644 --- a/src/soc/intel/braswell/smm.c +++ b/src/soc/intel/braswell/smm.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -28,12 +29,12 @@ /* Save settings which will be committed in SMI functions. */ static uint32_t smm_save_params[SMM_SAVE_PARAM_COUNT]; -void southcluster_smm_save_param(int param, uint32_t data) +void smm_southcluster_save_param(int param, uint32_t data) { smm_save_params[param] = data; } -void southcluster_smm_clear_state(void) +void smm_southbridge_clear_state(void) { uint32_t smi_en; @@ -58,7 +59,7 @@ void southcluster_smm_clear_state(void) clear_pmc_status(); } -static void southcluster_smm_route_gpios(void) +static void smm_southcluster_route_gpios(void) { void *gpio_rout = (void *)(PMC_BASE_ADDRESS + GPIO_ROUT); const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI; @@ -82,7 +83,7 @@ static void southcluster_smm_route_gpios(void) outl(alt_gpio_reg, alt_gpio_smi); } -void southcluster_smm_enable_smi(void) +void smm_southbridge_enable_smi(void) { uint16_t pm1_events = PWRBTN_EN | GBL_EN; @@ -93,7 +94,7 @@ void southcluster_smm_enable_smi(void) disable_gpe(PME_B0_EN); /* Set up the GPIO route. */ - southcluster_smm_route_gpios(); + smm_southcluster_route_gpios(); /* * Enable SMI generation: diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c index b968283fe7..00ec48f978 100644 --- a/src/soc/intel/braswell/spi.c +++ b/src/soc/intel/braswell/spi.c @@ -221,6 +221,8 @@ static ich9_spi_regs *spi_regs(void) return (void *)sbase; } +#define MENU_BYTES member_size(struct ich9_spi_regs, opmenu) + void spi_init(void) { ich9_spi_regs *ich9_spi; @@ -310,7 +312,7 @@ static void spi_setup_type(spi_transaction *trans) static int spi_setup_opcode(spi_transaction *trans) { uint16_t optypes; - uint8_t opmenu[cntlr.menubytes]; + uint8_t opmenu[MENU_BYTES]; trans->opcode = trans->out[0]; spi_use_out(trans, 1); @@ -332,13 +334,12 @@ static int spi_setup_opcode(spi_transaction *trans) return 0; read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < cntlr.menubytes; - opcode_index++) { + for (opcode_index = 0; opcode_index < ARRAY_SIZE(opmenu); opcode_index++) { if (opmenu[opcode_index] == trans->opcode) break; } - if (opcode_index == cntlr.menubytes) { + if (opcode_index == ARRAY_SIZE(opmenu)) { printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", trans->opcode); return -1; diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 696cf98ef9..5856ef1e50 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -36,8 +36,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_SPI_CONSOLE_SUPPORT select CPU_INTEL_COMMON select INTEL_GMA_ACPI - select POSTCAR_STAGE - select POSTCAR_CONSOLE select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select NO_FIXED_XIP_ROM_SIZE diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c index caff026f45..2b9f6a1dda 100644 --- a/src/soc/intel/broadwell/chip.c +++ b/src/soc/intel/broadwell/chip.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 0885c2dd5b..456a4354ca 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -164,6 +164,4 @@ struct soc_intel_broadwell_config { typedef struct soc_intel_broadwell_config config_t; -extern struct chip_operations soc_ops; - #endif diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 5ccaeaf810..54a695eec1 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -651,7 +652,7 @@ static void post_mp_init(void) /* Now that all APs have been relocated as well as the BSP let SMIs * start flowing. */ - southbridge_smm_enable_smi(); + smm_southbridge_enable_smi(); /* Lock down the SMRAM space. */ smm_lock(); diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index e8e3aa281c..9e196c16b5 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -87,6 +87,6 @@ /* MTRR_CAP_MSR bits */ #define SMRR_SUPPORTED (1<<11) -#define EMRR_SUPPORTED (1<<12) +#define PRMRR_SUPPORTED (1<<12) #endif diff --git a/src/soc/intel/broadwell/include/soc/smm.h b/src/soc/intel/broadwell/include/soc/smm.h index d3e1cddb81..909294c6e6 100644 --- a/src/soc/intel/broadwell/include/soc/smm.h +++ b/src/soc/intel/broadwell/include/soc/smm.h @@ -19,56 +19,20 @@ #include #include -struct ied_header { - char signature[10]; - u32 size; - u8 reserved[34]; -} __packed; struct smm_relocation_params { - u32 smram_base; - u32 smram_size; - u32 ied_base; - u32 ied_size; + uintptr_t ied_base; + size_t ied_size; msr_t smrr_base; msr_t smrr_mask; - msr_t emrr_base; - msr_t emrr_mask; - msr_t uncore_emrr_base; - msr_t uncore_emrr_mask; + msr_t prmrr_base; + msr_t prmrr_mask; + msr_t uncore_prmrr_base; + msr_t uncore_prmrr_mask; /* The smm_save_state_in_msrs field indicates if SMM save state * locations live in MSRs. This indicates to the CPUs how to adjust * the SMMBASE and IEDBASE */ int smm_save_state_in_msrs; }; -/* There is a bug in the order of Kconfig includes in that arch/x86/Kconfig - * is included after chipset code. This causes the chipset's Kconfig to be - * clobbered by the arch/x86/Kconfig if they have the same name. */ -static inline int smm_region_size(void) -{ - /* Make it 8MiB by default. */ - if (CONFIG_SMM_TSEG_SIZE == 0) - return (8 << 20); - return CONFIG_SMM_TSEG_SIZE; -} - -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); -void smm_relocate(void); -void smm_lock(void); - -/* These helpers are for performing SMM relocation. */ -void southbridge_trigger_smi(void); -void southbridge_clear_smi_status(void); - -/* The initialization of the southbridge is split into 2 components. One is - * for clearing the state in the SMM registers. The other is for enabling - * SMIs. They are split so that other work between the 2 actions. */ -void southbridge_smm_clear_state(void); -void southbridge_smm_enable_smi(void); - #endif diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index 7c53fa6468..f4a9d0ed24 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -16,12 +16,12 @@ #define __SIMPLE_DEVICE__ #include +#include #include #include #include #include #include -#include #include static uintptr_t dpr_region_start(void) @@ -46,14 +46,13 @@ void *cbmem_top(void) return (void *) dpr_region_start(); } -void stage_cache_external_region(void **base, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - /* The ramstage cache lives in the TSEG region. - * The top of RAM is defined to be the TSEG base address. */ - u32 offset = smm_region_size(); - offset -= CONFIG_IED_REGION_SIZE; - offset -= CONFIG_SMM_RESERVED_SIZE; + uintptr_t tseg = pci_read_config32(PCI_DEV(0, 0, 0), TSEG); + uintptr_t bgsm = pci_read_config32(PCI_DEV(0, 0, 0), BGSM); - *base = (void *)(cbmem_top() + offset); - *size = CONFIG_SMM_RESERVED_SIZE; + tseg = ALIGN_DOWN(tseg, 1 * MiB); + bgsm = ALIGN_DOWN(bgsm, 1 * MiB); + *start = tseg; + *size = bgsm - tseg; } diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c index e555588a2e..e6c231924a 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch.c @@ -73,7 +73,7 @@ u32 pch_read_soft_strap(int id) return SPIBAR32(SPIBAR_FDOD); } -#ifndef __PRE_RAM__ +#ifndef __SIMPLE_DEVICE__ /* Put device in D3Hot Power State */ static void pch_enable_d3hot(struct device *dev) diff --git a/src/soc/intel/broadwell/pei_data.c b/src/soc/intel/broadwell/pei_data.c index d8059ec5d2..f745348a7f 100644 --- a/src/soc/intel/broadwell/pei_data.c +++ b/src/soc/intel/broadwell/pei_data.c @@ -38,7 +38,7 @@ void broadwell_fill_pei_data(struct pei_data *pei_data) pei_data->gttbar = EARLY_GTT_BAR; pei_data->pmbase = ACPI_BASE_ADDRESS; pei_data->gpiobase = GPIO_BASE_ADDRESS; - pei_data->tseg_size = smm_region_size(); + pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; pei_data->temp_mmio_base = EARLY_TEMP_MMIO; pei_data->tx_byte = &send_to_console; pei_data->ddr_refresh_2x = 1; diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 9c86809368..96218f4ba4 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -16,17 +16,15 @@ #include #include #include -#include +#include #include #include #include #include -#include #include #include #include #include -#include #include #include #include @@ -35,35 +33,21 @@ #include #include -/* platform_enter_postcar() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use, - * and continues execution in postcar stage. */ -void platform_enter_postcar(void) +void fill_postcar_frame(struct postcar_frame *pcf) { - struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, + postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); - - run_postcar_phase(&pcf); } /* Entry from cpu/intel/car/romstage.c. */ -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { struct romstage_params rp = { 0 }; @@ -78,6 +62,8 @@ void mainboard_romstage_entry(unsigned long bist) /* Get power state */ rp.power_state = fill_power_state(); + elog_boot_notify(rp.power_state->prev_sleep_state == ACPI_S3); + /* Print useful platform information */ report_platform_info(); @@ -96,10 +82,6 @@ void mainboard_romstage_entry(unsigned long bist) rp.pei_data.boot_mode = rp.power_state->prev_sleep_state; - if (CONFIG(ELOG_BOOT_COUNT) - && rp.power_state->prev_sleep_state != ACPI_S3) - boot_count_increment(); - /* Print ME state before MRC */ intel_me_status(); diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/smi.c index 9aab0d10a6..17196da438 100644 --- a/src/soc/intel/broadwell/smi.c +++ b/src/soc/intel/broadwell/smi.c @@ -20,12 +20,13 @@ #include #include #include +#include #include #include #include #include -void southbridge_smm_clear_state(void) +void smm_southbridge_clear_state(void) { u32 smi_en; @@ -47,7 +48,7 @@ void southbridge_smm_clear_state(void) clear_gpe_status(); } -void southbridge_smm_enable_smi(void) +void smm_southbridge_enable_smi(void) { printk(BIOS_DEBUG, "Enabling SMIs.\n"); /* Configure events */ @@ -65,7 +66,7 @@ void southbridge_smm_enable_smi(void) enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); } -void southbridge_trigger_smi(void) +static void __unused southbridge_trigger_smi(void) { /** * There are several methods of raising a controlled SMI# via @@ -85,7 +86,7 @@ void southbridge_trigger_smi(void) outb(0x00, 0xb2); } -void southbridge_clear_smi_status(void) +static void __unused southbridge_clear_smi_status(void) { /* Clear SMI status */ clear_smi_status(); diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index b36b99dd4e..bad158748d 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index 9ea73b2054..21c534a4c6 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -24,6 +24,8 @@ #include #include #include +#include +#include #include #include #include @@ -42,22 +44,22 @@ static inline void write_smrr(struct smm_relocation_params *relo_params) wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); } -static inline void write_emrr(struct smm_relocation_params *relo_params) +static inline void write_prmrr(struct smm_relocation_params *relo_params) { - printk(BIOS_DEBUG, "Writing EMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->emrr_base.lo, relo_params->emrr_mask.lo); - wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->emrr_base); - wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->emrr_mask); + printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo); + wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base); + wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask); } -static inline void write_uncore_emrr(struct smm_relocation_params *relo_params) +static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params) { printk(BIOS_DEBUG, - "Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->uncore_emrr_base.lo, - relo_params->uncore_emrr_mask.lo); - wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_emrr_base); - wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_emrr_mask); + "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->uncore_prmrr_base.lo, + relo_params->uncore_prmrr_mask.lo); + wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base); + wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask); } static void update_save_state(int cpu, uintptr_t curr_smbase, @@ -165,38 +167,26 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, /* Make appropriate changes to the save state map. */ update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); - /* Write EMRR and SMRR MSRs based on indicated support. */ + /* Write PRMRR and SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); if (mtrr_cap.lo & SMRR_SUPPORTED) write_smrr(relo_params); - if (mtrr_cap.lo & EMRR_SUPPORTED) { - write_emrr(relo_params); - /* UNCORE_EMRR msrs are package level. Therefore, only + if (mtrr_cap.lo & PRMRR_SUPPORTED) { + write_prmrr(relo_params); + /* UNCORE_PRMRR msrs are package level. Therefore, only * configure these MSRs on the BSP. */ if (cpu == 0) - write_uncore_emrr(relo_params); + write_uncore_prmrr(relo_params); } } -static u32 northbridge_get_base_reg(struct device *dev, int reg) +static void fill_in_relocation_params(struct smm_relocation_params *params) { - u32 value; - - value = pci_read_config32(dev, reg); - /* Base registers are at 1MiB granularity. */ - value &= ~((1 << 20) - 1); - return value; -} - -static void fill_in_relocation_params(struct device *dev, - struct smm_relocation_params *params) -{ - u32 tseg_size; - u32 tsegmb; - u32 bgsm; - u32 emrr_base; - u32 emrr_size; + uintptr_t tseg_base; + size_t tseg_size; + u32 prmrr_base; + u32 prmrr_size; int phys_bits; /* All range registers are aligned to 4KiB */ const u32 rmask = ~((1 << 12) - 1); @@ -209,43 +199,34 @@ static void fill_in_relocation_params(struct device *dev, * SMRAM range as well as the IED range. However, the SMRAM available * to the handler is 4MiB since the IEDRAM lives TSEGMB + 4MiB. */ - tsegmb = northbridge_get_base_reg(dev, TSEG); - bgsm = northbridge_get_base_reg(dev, BGSM); - tseg_size = bgsm - tsegmb; - - params->smram_base = tsegmb; - params->smram_size = 4 << 20; - params->ied_base = tsegmb + params->smram_size; - params->ied_size = tseg_size - params->smram_size; - - /* Adjust available SMM handler memory size. */ - params->smram_size -= CONFIG_SMM_RESERVED_SIZE; + smm_region(&tseg_base, &tseg_size); /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) - | MTRR_PHYS_MASK_VALID; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; params->smrr_mask.hi = 0; - /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */ - emrr_base = (params->ied_base + (2 << 20)) & rmask; - emrr_size = params->ied_size - (2 << 20); + smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); - /* EMRR has 46 bits of valid address aligned to 4KiB. It's dependent + /* The PRMRR and UNCORE_PRMRR are at IEDBASE + 2MiB */ + prmrr_base = (params->ied_base + (2 << 20)) & rmask; + prmrr_size = params->ied_size - (2 << 20); + + /* PRMRR has 46 bits of valid address aligned to 4KiB. It's dependent * on the number of physical address bits supported. */ - params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK; - params->emrr_base.hi = 0; - params->emrr_mask.lo = (~(emrr_size - 1) & rmask) + params->prmrr_base.lo = prmrr_base | MTRR_TYPE_WRBACK; + params->prmrr_base.hi = 0; + params->prmrr_mask.lo = (~(prmrr_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1; + params->prmrr_mask.hi = (1 << (phys_bits - 32)) - 1; - /* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */ - params->uncore_emrr_base.lo = emrr_base; - params->uncore_emrr_base.hi = 0; - params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) | + /* UNCORE_PRMRR has 39 bits of valid address aligned to 4KiB. */ + params->uncore_prmrr_base.lo = prmrr_base; + params->uncore_prmrr_base.hi = 0; + params->uncore_prmrr_mask.lo = (~(prmrr_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1; + params->uncore_prmrr_mask.hi = (1 << (39 - 32)) - 1; } static void setup_ied_area(struct smm_relocation_params *params) @@ -270,23 +251,21 @@ static void setup_ied_area(struct smm_relocation_params *params) void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - fill_in_relocation_params(dev, &smm_reloc_params); + fill_in_relocation_params(&smm_reloc_params); + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); setup_ied_area(&smm_reloc_params); - *perm_smbase = smm_reloc_params.smram_base; - *perm_smsize = smm_reloc_params.smram_size; *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); } void smm_initialize(void) { /* Clear the SMM state in the southbridge. */ - southbridge_smm_clear_state(); + smm_southbridge_clear_state(); /* * Run the relocation handler for on the BSP to check and set up diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 01d2830481..ac893ea33d 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -231,6 +231,8 @@ static void ich_set_bbar(uint32_t minaddr) writel_(ichspi_bbar, cntlr.bbar); } +#define MENU_BYTES member_size(struct ich9_spi_regs, opmenu) + void spi_init(void) { uint8_t *rcrb; /* Root Complex Register Block */ @@ -332,7 +334,7 @@ static void spi_setup_type(spi_transaction *trans) static int spi_setup_opcode(spi_transaction *trans) { uint16_t optypes; - uint8_t opmenu[cntlr.menubytes]; + uint8_t opmenu[MENU_BYTES]; trans->opcode = trans->out[0]; spi_use_out(trans, 1); @@ -354,13 +356,12 @@ static int spi_setup_opcode(spi_transaction *trans) return 0; read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < cntlr.menubytes; - opcode_index++) { + for (opcode_index = 0; opcode_index < ARRAY_SIZE(opmenu); opcode_index++) { if (opmenu[opcode_index] == trans->opcode) break; } - if (opcode_index == cntlr.menubytes) { + if (opcode_index == ARRAY_SIZE(opmenu)) { printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", trans->opcode); return -1; diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 4bc6a65448..c1fda951c2 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -29,6 +29,7 @@ config SOC_INTEL_COFFEELAKE config SOC_INTEL_WHISKEYLAKE bool select SOC_INTEL_CANNONLAKE_BASE + select FSP_USES_CB_STACK help Intel Whiskeylake support @@ -76,8 +77,6 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 - select POSTCAR_CONSOLE - select POSTCAR_STAGE select REG_SCRIPT select SMP select SOC_AHCI_PORT_IMPLEMENTED_INVERT @@ -127,6 +126,15 @@ config DCACHE_BSP_STACK_SIZE The amount of anticipated stack usage in CAR by bootblock and other stages. +config FSP_TEMP_RAM_SIZE + hex + depends on FSP_USES_CB_STACK + default 0x10000 + help + The amount of anticipated heap usage in CAR by FSP. + Refer to Platform FSP integration guide document to know + the exact FSP requirement for Heap setup. + config IFD_CHIPSET string default "cnl" @@ -320,4 +328,8 @@ config PRERAM_CBMEM_CONSOLE_SIZE hex default 0xe00 +config INTEL_TXT_BIOSACM_ALIGNMENT + hex + default 0x40000 # 256KB + endif diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 30c2266096..653ba30563 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -44,7 +44,7 @@ const FSPT_UPD temp_ram_init_params = { asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { /* Call lib/bootblock.c main */ - bootblock_main_with_timestamp(base_timestamp, NULL, 0); + bootblock_main_with_basetime(base_timestamp); } void bootblock_soc_early_init(void) diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index c43d6d8bd1..a3252c2560 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -159,7 +159,7 @@ static int pch_check_decode_enable(void) void pch_early_iorange_init(void) { - uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | + uint16_t io_enables = LPC_IOE_EC_4E_4F | LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; /* IO Decode Range */ diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 480b3b835b..3d46916133 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -56,14 +56,22 @@ static struct { { PCI_DEVICE_ID_INTEL_CNL_ID_U, "Cannonlake-U" }, { PCI_DEVICE_ID_INTEL_CNL_ID_Y, "Cannonlake-Y" }, { PCI_DEVICE_ID_INTEL_CFL_ID_U, "Coffeelake U (4+3e)" }, + { PCI_DEVICE_ID_INTEL_CFL_ID_U_2, "Coffeelake U (2)" }, { PCI_DEVICE_ID_INTEL_WHL_ID_W_4, "Whiskeylake W (4+2)" }, { PCI_DEVICE_ID_INTEL_WHL_ID_W_2, "Whiskeylake W (2+2)" }, { PCI_DEVICE_ID_INTEL_CFL_ID_H, "Coffeelake-H" }, + { PCI_DEVICE_ID_INTEL_CFL_ID_H_4, "Coffeelake-H (4)" }, { PCI_DEVICE_ID_INTEL_CFL_ID_H_8, "Coffeelake-H (8+2)" }, { PCI_DEVICE_ID_INTEL_CFL_ID_S, "Coffeelake-S" }, + { PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2, "Coffeelake-S DT(2)" }, { PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4, "Coffeelake-S DT(4)" }, { PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8, "Coffeelake-S DT(8+2)" }, + { PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_4, "Coffeelake-S WS(4+2)" }, + { PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6, "Coffeelake-S WS(6+2)" }, { PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8, "Coffeelake-S WS(8+2)" }, + { PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4, "Coffeelake-S S(4)" }, + { PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6, "Coffeelake-S S(6)" }, + { PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8, "Coffeelake-S S(8)" }, { PCI_DEVICE_ID_INTEL_CML_ULT, "CometLake-U (4+2)" }, { PCI_DEVICE_ID_INTEL_CML_ULT_2_2, "CometLake-U (2+2)" }, { PCI_DEVICE_ID_INTEL_CML_ULT_6_2, "CometLake-U (6+2)" }, @@ -127,6 +135,8 @@ static struct { { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_4, "CometLake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_3, "CometLake ULT GT2" }, { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_4, "CometLake ULT GT2" }, + { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_5, "CometLake ULT GT2" }, + { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_6, "CometLake ULT GT2" }, { PCI_DEVICE_ID_INTEL_CML_GT1_ULX_1, "CometLake ULX GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT2_ULX_1, "CometLake ULX GT2" }, { PCI_DEVICE_ID_INTEL_CML_GT1_S_1, "CometLake S GT1" }, diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index cc2a2fb87d..aff2b9fddc 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -136,9 +136,19 @@ struct soc_intel_cannonlake_config { Sata_AHCI, Sata_RAID, } SataMode; + + /* SATA devslp pad reset configuration */ + enum { + SataDevSlpResumeReset = 1, + SataDevSlpHostDeepReset = 3, + SataDevSlpPlatformReset = 5, + SataDevSlpDswReset = 7 + } SataDevSlpRstConfig; + uint8_t SataSalpSupport; uint8_t SataPortsEnable[8]; uint8_t SataPortsDevSlp[8]; + uint8_t SataPortsDevSlpResetConfig[8]; /* Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable */ uint8_t SlpS0WithGbeSupport; @@ -154,6 +164,7 @@ struct soc_intel_cannonlake_config { /* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */ uint8_t PchHdaAudioLinkHda; + uint8_t PchHdaIDispCodecDisconnect; uint8_t PchHdaAudioLinkDmic0; uint8_t PchHdaAudioLinkDmic1; uint8_t PchHdaAudioLinkSsp0; @@ -186,6 +197,8 @@ struct soc_intel_cannonlake_config { uint8_t EmmcHs400RxStrobeDll1; /* 0-78: number of active delay for TX data, unit is 125 psec */ uint8_t EmmcHs400TxDataDll; + /* Enable/disable SD card write protect pin configuration on CML */ + uint8_t ScsSdCardWpPinEnabled; /* Integrated Sensor */ uint8_t PchIshEnable; @@ -379,9 +392,6 @@ struct soc_intel_cannonlake_config { uint8_t SlowSlewRateForSa; uint8_t SlowSlewRateForFivr; - /* DMI Power Optimizer */ - uint8_t dmipwroptimize; - /* SATA Power Optimizer */ uint8_t satapwroptimize; diff --git a/src/soc/intel/cannonlake/cnl_memcfg_init.c b/src/soc/intel/cannonlake/cnl_memcfg_init.c index d3e5e837fd..6c551ad563 100644 --- a/src/soc/intel/cannonlake/cnl_memcfg_init.c +++ b/src/soc/intel/cannonlake/cnl_memcfg_init.c @@ -81,6 +81,7 @@ static void meminit_spd_data(FSP_M_CONFIG *mem_cfg, uint8_t mem_slot, default: die("nonexistent memory slot"); } + printk(BIOS_INFO, "memory slot: %d configuration done.\n", mem_slot); } /* @@ -112,6 +113,7 @@ static void meminit_cbfs_spd_index(FSP_M_CONFIG *mem_cfg, spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); last_spd_index = spd_index; + print_spd_info((unsigned char *)spd_data_ptr); } meminit_spd_data(mem_cfg, mem_slot, spd_data_len, spd_data_ptr); diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 6682cdc7b9..0f4d52e790 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -19,10 +19,10 @@ #include #include #include +#include #include #include #include -#include #include #include #include diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 9c4f0ec29c..54ed439a0a 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -186,6 +186,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) sizeof(params->SataPortsEnable)); memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, sizeof(params->SataPortsDevSlp)); +#if CONFIG(SOC_INTEL_COMETLAKE) + memcpy(params->SataPortsDevSlpResetConfig, + config->SataPortsDevSlpResetConfig, + sizeof(params->SataPortsDevSlpResetConfig)); +#endif } /* Lan */ @@ -205,6 +210,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Audio */ params->PchHdaDspEnable = config->PchHdaDspEnable; + params->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect; params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda; params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0; params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1; @@ -336,6 +342,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->ScsSdCardEnabled = dev->enabled; params->SdCardPowerEnableActiveHigh = CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE); +#if CONFIG(SOC_INTEL_COMETLAKE) + params->ScsSdCardWpPinEnabled = config->ScsSdCardWpPinEnabled; +#endif } dev = pcidev_path_on_root(PCH_DEVFN_UFS); @@ -345,6 +354,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->ScsUfsEnabled = dev->enabled; params->Heci3Enabled = config->Heci3Enabled; +#if !CONFIG(HECI_DISABLE_USING_SMM) + params->Heci1Disabled = !config->HeciEnabled; +#endif params->Device4Enable = config->Device4Enable; /* VrConfig Settings for 5 domains @@ -365,7 +377,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->FastPkgCRampDisableFivr = config->FastPkgCRampDisableFivr; /* Power Optimizer */ - params->PchPwrOptEnable = config->dmipwroptimize; params->SataPwrOptEnable = config->satapwroptimize; /* Disable PCH ACPI timer */ @@ -417,31 +428,29 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) tconfig->PchLockDownBiosInterface = 0; params->PchLockDownBiosLock = 0; params->PchLockDownRtcMemoryLock = 0; +#if CONFIG(SOC_INTEL_COMETLAKE) /* - * TODO: Disable SpiFlashCfgLockDown config after FSP provides - * dedicated UPD - * * Skip SPI Flash Lockdown from inside FSP. * Making this config "0" means FSP won't set the FLOCKDN bit * of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL). * So, it becomes coreboot's responsibility to set this bit * before end of POST for security concerns. */ - // params->SpiFlashCfgLockDown = 0; + params->SpiFlashCfgLockDown = 0; +#endif } else { tconfig->PchLockDownGlobalSmi = 1; tconfig->PchLockDownBiosInterface = 1; params->PchLockDownBiosLock = 1; params->PchLockDownRtcMemoryLock = 1; +#if CONFIG(SOC_INTEL_COMETLAKE) /* - * TODO: Enable SpiFlashCfgLockDown config after FSP provides - * dedicated UPD - * * Enable SPI Flash Lockdown from inside FSP. * Making this config "1" means FSP will set the FLOCKDN bit * of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL). */ - // params->SpiFlashCfgLockDown = 1; + params->SpiFlashCfgLockDown = 1; +#endif } } diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h index 9cfb59e7d0..1ebaf3f7b6 100644 --- a/src/soc/intel/cannonlake/include/soc/iomap.h +++ b/src/soc/intel/cannonlake/include/soc/iomap.h @@ -68,10 +68,6 @@ #define HECI1_BASE_ADDRESS 0xfeda2000 -/* PTT registers */ -#define PTT_TXT_BASE_ADDRESS 0xfed30800 -#define PTT_PRESENT 0x00070000 - #define VTD_BASE_ADDRESS 0xFED90000 #define VTD_BASE_SIZE 0x00004000 /* diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h index e2367a7795..95c1abd622 100644 --- a/src/soc/intel/cannonlake/include/soc/smm.h +++ b/src/soc/intel/cannonlake/include/soc/smm.h @@ -22,21 +22,12 @@ #include #include -struct ied_header { - char signature[10]; - u32 size; - u8 reserved[34]; -} __packed; struct smm_relocation_params { uintptr_t ied_base; size_t ied_size; msr_t smrr_base; msr_t smrr_mask; - msr_t emrr_base; - msr_t emrr_mask; - msr_t uncore_emrr_base; - msr_t uncore_emrr_mask; /* * The smm_save_state_in_msrs field indicates if SMM save state * locations live in MSRs. This indicates to the CPUs how to adjust @@ -45,15 +36,4 @@ struct smm_relocation_params { int smm_save_state_in_msrs; }; -/* Mainboard handler for eSPI SMIs */ -void mainboard_smi_espi_handler(void); - -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); -void smm_relocate(void); -void smm_lock(void); - #endif diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c index b8b4245d43..776ff8bae0 100644 --- a/src/soc/intel/cannonlake/me.c +++ b/src/soc/intel/cannonlake/me.c @@ -32,40 +32,6 @@ enum { ME_WSTATE_NORMAL = 0x05, }; -/* HFSTS register offsets in PCI config space */ -enum { - PCI_ME_HFSTS1 = 0x40, - PCI_ME_HFSTS2 = 0x48, - PCI_ME_HFSTS3 = 0x60, - PCI_ME_HFSTS4 = 0x64, - PCI_ME_HFSTS5 = 0x68, - PCI_ME_HFSTS6 = 0x6C, -}; - -/* Host Firmware Status Register 1 */ -union hfsts1 { - uint32_t raw; - struct { - uint32_t working_state : 4; - uint32_t mfg_mode : 1; - uint32_t fpt_bad : 1; - uint32_t operation_state : 3; - uint32_t fw_init_complete : 1; - uint32_t ft_bup_ld_flr : 1; - uint32_t fw_upd_in_progress : 1; - uint32_t error_code : 4; - uint32_t operation_mode : 4; - uint32_t reset_count : 4; - uint32_t boot_options : 1; - uint32_t rsvd0 : 1; - uint32_t bist_state : 1; - uint32_t bist_reset_req : 1; - uint32_t power_source : 2; - uint32_t reserved1 : 1; - uint32_t d0i3_support_valid : 1; - } __packed fields; -}; - /* Host Firmware Status Register 2 */ union hfsts2 { uint32_t raw; @@ -155,11 +121,6 @@ union hfsts6 { } __packed fields; }; -static uint32_t me_read_config32(int offset) -{ - return pci_read_config32(PCH_DEV_CSE, offset); -} - /* * From reading the documentation, this should work for both WHL and CML * platforms. Also, calling this function from dump_me_status() does not @@ -167,14 +128,6 @@ static uint32_t me_read_config32(int offset) */ static void print_me_version(void *unused) { - struct mkhi_hdr { - uint8_t group_id; - uint8_t command :7; - uint8_t is_resp :1; - uint8_t rsvd; - uint8_t result; - } __packed; - struct version { uint16_t minor; uint16_t major; @@ -189,7 +142,7 @@ static void print_me_version(void *unused) struct version fitc; } __packed; - union hfsts1 hfsts1; + union me_hfsts1 hfsts1; const struct mkhi_hdr fw_ver_msg = { .group_id = MKHI_GEN_GROUP_ID, .command = MKHI_GET_FW_VERSION, @@ -201,7 +154,10 @@ static void print_me_version(void *unused) if (!CONFIG(CONSOLE_SERIAL)) return; - hfsts1.raw = me_read_config32(PCI_ME_HFSTS1); + if (!is_cse_enabled()) + return; + + hfsts1.data = me_read_config32(PCI_ME_HFSTS1); /* * Prerequisites: @@ -237,14 +193,17 @@ BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_version, NULL); void dump_me_status(void *unused) { - union hfsts1 hfsts1; + union me_hfsts1 hfsts1; union hfsts2 hfsts2; union hfsts3 hfsts3; union hfsts4 hfsts4; union hfsts5 hfsts5; union hfsts6 hfsts6; - hfsts1.raw = me_read_config32(PCI_ME_HFSTS1); + if (!is_cse_enabled()) + return; + + hfsts1.data = me_read_config32(PCI_ME_HFSTS1); hfsts2.raw = me_read_config32(PCI_ME_HFSTS2); hfsts3.raw = me_read_config32(PCI_ME_HFSTS3); hfsts4.raw = me_read_config32(PCI_ME_HFSTS4); @@ -252,7 +211,7 @@ void dump_me_status(void *unused) hfsts6.raw = me_read_config32(PCI_ME_HFSTS6); printk(BIOS_DEBUG, "ME: HFSTS1 : 0x%08X\n", - hfsts1.raw); + hfsts1.data); printk(BIOS_DEBUG, "ME: HFSTS2 : 0x%08X\n", hfsts2.raw); printk(BIOS_DEBUG, "ME: HFSTS3 : 0x%08X\n", @@ -273,9 +232,9 @@ void dump_me_status(void *unused) printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", hfsts1.fields.fw_init_complete ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", - hfsts1.fields.boot_options ? "YES" : "NO"); + hfsts1.fields.boot_options_present ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", - hfsts1.fields.fw_upd_in_progress ? "YES" : "NO"); + hfsts1.fields.update_in_progress ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: D0i3 Support : %s\n", hfsts1.fields.d0i3_support_valid ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: Low Power State Enabled : %s\n", diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 9b75f167e8..f3286cce66 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -14,16 +14,18 @@ * GNU General Public License for more details. */ +#include #include #include #include +#include +#include #include #include #include #include #include #include -#include #include #include @@ -35,69 +37,6 @@ void smm_region(uintptr_t *start, size_t *size) *size = sa_get_tseg_size(); } -/* - * Subregions within SMM - * +-------------------------+ BGSM - * | IED | IED_REGION_SIZE - * +-------------------------+ - * | External Stage Cache | SMM_RESERVED_SIZE - * +-------------------------+ - * | code and data | - * | (TSEG) | - * +-------------------------+ TSEG - */ -int smm_subregion(int sub, uintptr_t *start, size_t *size) -{ - uintptr_t sub_base; - size_t sub_size; - const size_t ied_size = CONFIG_IED_REGION_SIZE; - const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - - smm_region(&sub_base, &sub_size); - - switch (sub) { - case SMM_SUBREGION_HANDLER: - /* Handler starts at the base of TSEG. */ - sub_size -= ied_size; - sub_size -= cache_size; - break; - case SMM_SUBREGION_CACHE: - /* External cache is in the middle of TSEG. */ - sub_base += sub_size - (ied_size + cache_size); - sub_size = cache_size; - break; - case SMM_SUBREGION_CHIPSET: - /* IED is at the top. */ - sub_base += sub_size - ied_size; - sub_size = ied_size; - break; - default: - *start = 0; - *size = 0; - return -1; - } - - *start = sub_base; - *size = sub_size; - return 0; -} - -static bool is_ptt_enable(void) -{ - if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) == - PTT_PRESENT) - return true; - - return false; -} - -/* Calculate PTT size */ -static size_t get_ptt_size(void) -{ - /* Allocate 4KB for PTT if enabled */ - return is_ptt_enable() ? 4*KiB : 0; -} - /* Calculate ME Stolen size */ static size_t get_imr_size(void) { @@ -191,9 +130,6 @@ static size_t calculate_reserved_mem_size(uintptr_t dram_base, /* Get Tracehub size */ reserve_mem_base -= get_imr_size(); - /* Get PTT size */ - reserve_mem_base -= get_ptt_size(); - /* Traditional Area Size */ reserve_mem_size = dram_base - reserve_mem_base; @@ -330,3 +266,21 @@ void *cbmem_top(void) return (void *)(uintptr_t)ebda_cfg.tolum_base; } + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + /* + * We need to make sure ramstage will be run cached. At this + * point exact location of ramstage in cbmem is not known. + * Instruct postcar to cache 16 megs under cbmem top which is + * a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t) cbmem_top(); + printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); + top_of_ram -= 16*MiB; + postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); + + /* Cache the TSEG region */ + postcar_enable_tseg_cache(pcf); +} diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index 0e7cc17b4a..b9f455ff68 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c index e92396f39a..e01c22c463 100644 --- a/src/soc/intel/cannonlake/reset.c +++ b/src/soc/intel/cannonlake/reset.c @@ -22,65 +22,10 @@ #include #include -/* Reset Request */ -#define MKHI_GLOBAL_RESET 0x0b -#define MKHI_STATUS_SUCCESS 0 - -#define GR_ORIGIN_BIOS_MEM_INIT 0x01 -#define GR_ORIGIN_BIOS_POST 0x02 -#define GR_ORIGIN_MEBX 0x03 - -#define GLOBAL_RST_TYPE 0x01 - -#define BIOS_HOST_ADD 0x00 -#define HECI_MKHI_ADD 0x07 - -static int send_heci_reset_message(void) -{ - int status; - struct reset_reply { - u8 group_id; - u8 command; - u8 reserved; - u8 result; - } __packed reply; - struct reset_message { - u8 group_id; - u8 cmd; - u8 reserved; - u8 result; - u8 req_origin; - u8 reset_type; - } __packed; - struct reset_message msg = { - .cmd = MKHI_GLOBAL_RESET, - .req_origin = GR_ORIGIN_BIOS_POST, - .reset_type = GLOBAL_RST_TYPE - }; - size_t reply_size; - - heci_reset(); - - status = heci_send(&msg, sizeof(msg), BIOS_HOST_ADD, HECI_MKHI_ADD); - if (status != 1) - return -1; - - reply_size = sizeof(reply); - memset(&reply, 0, reply_size); - if (!heci_receive(&reply, &reply_size)) - return -1; - if (reply.result != MKHI_STATUS_SUCCESS) { - printk(BIOS_DEBUG, "Returned Mkhi Status is not success!\n"); - return -1; - } - printk(BIOS_DEBUG, "Heci receive success!\n"); - return 0; -} - void do_global_reset(void) { /* Ask CSE to do the global reset */ - if (!send_heci_reset_message()) + if (!send_heci_reset_req_message(GLOBAL_RESET)) return; /* global reset if CSE fail to reset */ diff --git a/src/soc/intel/cannonlake/romstage/Makefile.inc b/src/soc/intel/cannonlake/romstage/Makefile.inc index 75d79856e4..33d9629e1d 100644 --- a/src/soc/intel/cannonlake/romstage/Makefile.inc +++ b/src/soc/intel/cannonlake/romstage/Makefile.inc @@ -13,6 +13,7 @@ # GNU General Public License for more details. # +romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += fsp_params.c romstage-y += systemagent.c diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 94b9899422..ba583b9a6e 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -13,8 +13,7 @@ * GNU General Public License for more details. */ -#include -#include +#include #include #include #include @@ -28,7 +27,6 @@ #include #include #include -#include #include "../chip.h" @@ -127,42 +125,19 @@ static void save_dimm_info(void) printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } -asmlinkage void car_stage_entry(void) +void mainboard_romstage_entry(void) { bool s3wake; - struct postcar_frame pcf; - uintptr_t top_of_ram; struct chipset_power_state *ps = pmc_get_power_state(); - console_init(); - /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); /* initialize Heci interface */ heci_init(HECI1_BASE_ADDRESS); - timestamp_add_now(TS_START_ROMSTAGE); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); if (!s3wake) save_dimm_info(); - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - /* - * We need to make sure ramstage will be run cached. At this - * point exact location of ramstage in cbmem is not known. - * Instruct postcar to cache 16 megs under cbmem top which is - * a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); - - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - run_postcar_phase(&pcf); } diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index 9a23d5a8f9..493d0030cf 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -26,8 +26,9 @@ #include #include #include +#include +#include #include -#include #include #include #include @@ -165,7 +166,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, /* Make appropriate changes to the save state map. */ update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); - /* Write EMRR and SMRR MSRs based on indicated support. */ + /* Write SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); if (mtrr_cap.lo & SMRR_SUPPORTED) write_smrr(relo_params); @@ -175,18 +176,9 @@ static void fill_in_relocation_params(struct smm_relocation_params *params) { uintptr_t tseg_base; size_t tseg_size; - u32 emrr_base; - u32 emrr_size; - int phys_bits; /* All range registers are aligned to 4KiB */ const u32 rmask = ~(4 * KiB - 1); - /* - * Some of the range registers are dependent on the number of physical - * address bits supported. - */ - phys_bits = cpu_phys_address_size(); - smm_region(&tseg_base, &tseg_size); smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); @@ -195,27 +187,6 @@ static void fill_in_relocation_params(struct smm_relocation_params *params) params->smrr_base.hi = 0; params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; params->smrr_mask.hi = 0; - - /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */ - emrr_base = (params->ied_base + 2 * MiB) & rmask; - emrr_size = params->ied_size - 2 * MiB; - - /* - * EMRR has 46 bits of valid address aligned to 4KiB. It's dependent - * on the number of physical address bits supported. - */ - params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK; - params->emrr_base.hi = 0; - params->emrr_mask.lo = (~(emrr_size - 1) & rmask) - | MTRR_PHYS_MASK_VALID; - params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1; - - /* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */ - params->uncore_emrr_base.lo = emrr_base; - params->uncore_emrr_base.hi = 0; - params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) | - MTRR_PHYS_MASK_VALID; - params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1; } static void setup_ied_area(struct smm_relocation_params *params) diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 523d1f56f4..44c2392abc 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -15,10 +15,6 @@ source "src/soc/intel/common/pch/Kconfig" comment "Intel SoC Common coreboot stages" source "src/soc/intel/common/basecode/Kconfig" -config DISPLAY_SMM_MEMORY_MAP - bool "SMM: Display the SMM memory map" - default n - config SOC_INTEL_COMMON_RESET bool default n diff --git a/src/soc/intel/common/acpi/dptf/thermal.asl b/src/soc/intel/common/acpi/dptf/thermal.asl index c8aa03749b..d41f62354b 100644 --- a/src/soc/intel/common/acpi/dptf/thermal.asl +++ b/src/soc/intel/common/acpi/dptf/thermal.asl @@ -59,7 +59,50 @@ Method (TINI) #endif } +/* Thermal Trip Points Change Event Handler */ +Method (TPET) +{ #ifdef DPTF_TSR0_SENSOR_ID + Notify (^TSR0, 0x81) +#endif +#ifdef DPTF_TSR1_SENSOR_ID + Notify (^TSR1, 0x81) +#endif +#ifdef DPTF_TSR2_SENSOR_ID + Notify (^TSR2, 0x81) +#endif +#ifdef DPTF_TSR3_SENSOR_ID + Notify (^TSR3, 0x81) +#endif +} + +/* + * Method to return trip temperature value depending upon the device mode. + * Arg0 --> Value to return when device is in tablet mode + * Arg1 --> Value to return when device is not in tablet mode. + */ +Method (DTRP, 2, Serialized) +{ +#ifdef EC_ENABLE_MULTIPLE_DPTF_PROFILES + If (LEqual (\_SB.PCI0.LPCB.EC0.RCDP, One)) { + Return (CTOK (Arg0)) + } Else { +#endif + Return (CTOK (Arg1)) +#ifdef EC_ENABLE_MULTIPLE_DPTF_PROFILES + } +#endif +} + +#ifdef DPTF_TSR0_SENSOR_ID + +#ifndef DPTF_TSR0_TABLET_PASSIVE +#define DPTF_TSR0_TABLET_PASSIVE DPTF_TSR0_PASSIVE +#endif +#ifndef DPTF_TSR0_TABLET_CRITICAL +#define DPTF_TSR0_TABLET_CRITICAL DPTF_TSR0_CRITICAL +#endif + Device (TSR0) { Name (_HID, EISAID ("INT3403")) @@ -85,12 +128,12 @@ Device (TSR0) Method (_PSV) { - Return (CTOK (DPTF_TSR0_PASSIVE)) + Return (DTRP (DPTF_TSR0_TABLET_PASSIVE, DPTF_TSR0_PASSIVE)) } Method (_CRT) { - Return (CTOK (DPTF_TSR0_CRITICAL)) + Return (DTRP (DPTF_TSR0_TABLET_CRITICAL, DPTF_TSR0_CRITICAL)) } Name (PATC, 2) @@ -112,10 +155,63 @@ Device (TSR0) { \_SB.PCI0.LPCB.EC0.PATD (TMPI) } + +#ifdef DPTF_ENABLE_FAN_CONTROL +#ifdef DPTF_TSR0_ACTIVE_AC0 + Method (_AC0) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC0)) + } +#endif +#ifdef DPTF_TSR0_ACTIVE_AC1 + Method (_AC1) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC1)) + } +#endif +#ifdef DPTF_TSR0_ACTIVE_AC2 + Method (_AC2) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC2)) + } +#endif +#ifdef DPTF_TSR0_ACTIVE_AC3 + Method (_AC3) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC3)) + } +#endif +#ifdef DPTF_TSR0_ACTIVE_AC4 + Method (_AC4) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC4)) + } +#endif +#ifdef DPTF_TSR0_ACTIVE_AC5 + Method (_AC5) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC5)) + } +#endif +#ifdef DPTF_TSR0_ACTIVE_AC6 + Method (_AC6) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC6)) + } +#endif +#endif } #endif #ifdef DPTF_TSR1_SENSOR_ID + +#ifndef DPTF_TSR1_TABLET_PASSIVE +#define DPTF_TSR1_TABLET_PASSIVE DPTF_TSR1_PASSIVE +#endif +#ifndef DPTF_TSR1_TABLET_CRITICAL +#define DPTF_TSR1_TABLET_CRITICAL DPTF_TSR1_CRITICAL +#endif + Device (TSR1) { Name (_HID, EISAID ("INT3403")) @@ -141,12 +237,12 @@ Device (TSR1) Method (_PSV) { - Return (CTOK (DPTF_TSR1_PASSIVE)) + Return (DTRP (DPTF_TSR1_TABLET_PASSIVE, DPTF_TSR1_PASSIVE)) } Method (_CRT) { - Return (CTOK (DPTF_TSR1_CRITICAL)) + Return (DTRP (DPTF_TSR1_TABLET_CRITICAL, DPTF_TSR1_CRITICAL)) } Name (PATC, 2) @@ -168,10 +264,63 @@ Device (TSR1) { \_SB.PCI0.LPCB.EC0.PATD (TMPI) } + +#ifdef DPTF_ENABLE_FAN_CONTROL +#ifdef DPTF_TSR1_ACTIVE_AC0 + Method (_AC0) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC0)) + } +#endif +#ifdef DPTF_TSR1_ACTIVE_AC1 + Method (_AC1) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC1)) + } +#endif +#ifdef DPTF_TSR1_ACTIVE_AC2 + Method (_AC2) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC2)) + } +#endif +#ifdef DPTF_TSR1_ACTIVE_AC3 + Method (_AC3) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC3)) + } +#endif +#ifdef DPTF_TSR1_ACTIVE_AC4 + Method (_AC4) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC4)) + } +#endif +#ifdef DPTF_TSR1_ACTIVE_AC5 + Method (_AC5) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC5)) + } +#endif +#ifdef DPTF_TSR1_ACTIVE_AC6 + Method (_AC6) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC6)) + } +#endif +#endif } #endif #ifdef DPTF_TSR2_SENSOR_ID + +#ifndef DPTF_TSR2_TABLET_PASSIVE +#define DPTF_TSR2_TABLET_PASSIVE DPTF_TSR2_PASSIVE +#endif +#ifndef DPTF_TSR2_TABLET_CRITICAL +#define DPTF_TSR2_TABLET_CRITICAL DPTF_TSR2_CRITICAL +#endif + Device (TSR2) { Name (_HID, EISAID ("INT3403")) @@ -197,12 +346,12 @@ Device (TSR2) Method (_PSV) { - Return (CTOK (DPTF_TSR2_PASSIVE)) + Return (DTRP (DPTF_TSR2_TABLET_PASSIVE, DPTF_TSR2_PASSIVE)) } Method (_CRT) { - Return (CTOK (DPTF_TSR2_CRITICAL)) + Return (DTRP (DPTF_TSR2_TABLET_CRITICAL, DPTF_TSR2_CRITICAL)) } Name (PATC, 2) @@ -224,10 +373,63 @@ Device (TSR2) { \_SB.PCI0.LPCB.EC0.PATD (TMPI) } + +#ifdef DPTF_ENABLE_FAN_CONTROL +#ifdef DPTF_TSR2_ACTIVE_AC0 + Method (_AC0) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC0)) + } +#endif +#ifdef DPTF_TSR2_ACTIVE_AC1 + Method (_AC1) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC1)) + } +#endif +#ifdef DPTF_TSR2_ACTIVE_AC2 + Method (_AC2) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC2)) + } +#endif +#ifdef DPTF_TSR2_ACTIVE_AC3 + Method (_AC3) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC3)) + } +#endif +#ifdef DPTF_TSR2_ACTIVE_AC4 + Method (_AC4) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC4)) + } +#endif +#ifdef DPTF_TSR2_ACTIVE_AC5 + Method (_AC5) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC5)) + } +#endif +#ifdef DPTF_TSR2_ACTIVE_AC6 + Method (_AC6) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC6)) + } +#endif +#endif } #endif #ifdef DPTF_TSR3_SENSOR_ID + +#ifndef DPTF_TSR3_TABLET_PASSIVE +#define DPTF_TSR3_TABLET_PASSIVE DPTF_TSR3_PASSIVE +#endif +#ifndef DPTF_TSR3_TABLET_CRITICAL +#define DPTF_TSR3_TABLET_CRITICAL DPTF_TSR3_CRITICAL +#endif + Device (TSR3) { Name (_HID, EISAID ("INT3403")) @@ -253,12 +455,12 @@ Device (TSR3) Method (_PSV) { - Return (CTOK (DPTF_TSR3_PASSIVE)) + Return (DTRP (DPTF_TSR3_TABLET_PASSIVE, DPTF_TSR3_PASSIVE)) } Method (_CRT) { - Return (CTOK (DPTF_TSR3_CRITICAL)) + Return (DTRP (DPTF_TSR3_TABLET_CRITICAL, DPTF_TSR3_CRITICAL)) } Name (PATC, 2) @@ -280,5 +482,50 @@ Device (TSR3) { \_SB.PCI0.LPCB.EC0.PATD (TMPI) } + +#ifdef DPTF_ENABLE_FAN_CONTROL +#ifdef DPTF_TSR3_ACTIVE_AC0 + Method (_AC0) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC0)) + } +#endif +#ifdef DPTF_TSR3_ACTIVE_AC1 + Method (_AC1) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC1)) + } +#endif +#ifdef DPTF_TSR3_ACTIVE_AC2 + Method (_AC2) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC2)) + } +#endif +#ifdef DPTF_TSR3_ACTIVE_AC3 + Method (_AC3) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC3)) + } +#endif +#ifdef DPTF_TSR3_ACTIVE_AC4 + Method (_AC4) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC4)) + } +#endif +#ifdef DPTF_TSR3_ACTIVE_AC5 + Method (_AC5) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC5)) + } +#endif +#ifdef DPTF_TSR3_ACTIVE_AC6 + Method (_AC6) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC6)) + } +#endif +#endif } #endif diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index b1648e8eed..d5f5081c3c 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -365,7 +365,7 @@ find_llc_subleaf: jnz find_llc_subleaf /* - * Set MSR 0xC91 IA32_L3_MASK_! = 0xE/0xFE/0xFFE/0xFFFE + * Set MSR 0xC91 IA32_L3_MASK_1 = 0xE/0xFE/0xFFE/0xFFFE * for 4/8/16 way of LLC */ shr $22, %ebx diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 9a8ab5ba42..091fc4a06b 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -89,11 +89,11 @@ CAR_init_done: /* Setup bootblock stack */ mov %edx, %esp - /* clear CAR_GLOBAL area as it is not shared */ + /* clear .bss section as it is not shared */ cld xor %eax, %eax - movl $(_car_global_end), %ecx - movl $(_car_global_start), %edi + movl $(_ebss), %ecx + movl $(_bss), %edi sub %edi, %ecx shrl $2, %ecx rep stosl diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index d941ab28bb..e0cee1771e 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -159,7 +159,7 @@ static void post_cpus_init(void *unused) if (CONFIG(USE_INTEL_FSP_MP_INIT)) return; - if (mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL, 1000) < 0) + if (mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL) < 0) printk(BIOS_ERR, "MTRR programming failure\n"); x86_mtrr_check(); diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 7bd46ceba9..0bd5c72ef5 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -67,6 +67,24 @@ #define MEI_HDR_CSE_ADDR_START 0 #define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START) +#define HECI_OP_MODE_SEC_OVERRIDE 5 + +/* Global Reset Command ID */ +#define MKHI_GLOBAL_RESET_REQ 0xb +#define MKHI_GROUP_ID_CBM 0 + +/* RST Origin */ +#define GR_ORIGIN_BIOS_POST 2 + +#define MKHI_HMRFPO_GROUP_ID 5 + +/* HMRFPO Command Ids */ +#define MKHI_HMRFPO_ENABLE 1 +#define MKHI_HMRFPO_GET_STATUS 3 + +#define ME_HFS_CWS_NORMAL 5 +#define ME_HFS_MODE_NORMAL 0 +#define ME_HFS_TEMP_DISABLE 3 static struct cse_device { uintptr_t sec_bar; @@ -239,6 +257,43 @@ static int cse_ready(void) return csr & CSR_READY; } +/* + * Checks if CSE is in SEC_OVERRIDE operation mode. This is the mode where + * CSE will allow reflashing of CSE region. + */ +static uint8_t check_cse_sec_override_mode(void) +{ + union me_hfsts1 hfs1; + hfs1.data = me_read_config32(PCI_ME_HFSTS1); + if (hfs1.fields.operation_mode == HECI_OP_MODE_SEC_OVERRIDE) + return 1; + return 0; +} + +/* Makes the host ready to communicate with CSE */ +void set_host_ready(void) +{ + uint32_t csr; + csr = read_host_csr(); + csr &= ~CSR_RESET; + csr |= (CSR_IG | CSR_READY); + write_host_csr(csr); +} + +/* Polls for ME state 'HECI_OP_MODE_SEC_OVERRIDE' for 15 seconds */ +uint8_t wait_cse_sec_override_mode(void) +{ + struct stopwatch sw; + stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY); + while (!check_cse_sec_override_mode()) { + udelay(HECI_DELAY); + if (stopwatch_expired(&sw)) + return 0; + } + + return 1; +} + static int wait_heci_ready(void) { struct stopwatch sw; @@ -458,6 +513,22 @@ int heci_receive(void *buff, size_t *maxlen) return 0; } +int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t *rcv_sz) +{ + if (!heci_send(snd_msg, snd_sz, BIOS_HOST_ADDR, HECI_MKHI_ADDR)) { + printk(BIOS_ERR, "HECI: send Failed\n"); + return 0; + } + + if (rcv_msg != NULL) { + if (!heci_receive(rcv_msg, rcv_sz)) { + printk(BIOS_ERR, "HECI: receive Failed\n"); + return 0; + } + } + return 1; +} + /* * Attempt to reset the device. This is useful when host and ME are out * of sync during transmission or ME didn't understand the message. @@ -468,17 +539,12 @@ int heci_reset(void) /* Send reset request */ csr = read_host_csr(); - csr |= CSR_RESET; - csr |= CSR_IG; + csr |= (CSR_RESET | CSR_IG); write_host_csr(csr); if (wait_heci_ready()) { /* Device is back on its imaginary feet, clear reset */ - csr = read_host_csr(); - csr &= ~CSR_RESET; - csr |= CSR_IG; - csr |= CSR_READY; - write_host_csr(csr); + set_host_ready(); return 1; } @@ -487,6 +553,174 @@ int heci_reset(void) return 0; } +bool is_cse_enabled(void) +{ + const struct device *cse_dev = pcidev_path_on_root(PCH_DEVFN_CSE); + + if (!cse_dev || !cse_dev->enabled) { + printk(BIOS_WARNING, "HECI: No CSE device\n"); + return false; + } + + if (pci_read_config16(PCH_DEV_CSE, PCI_VENDOR_ID) == 0xFFFF) { + printk(BIOS_WARNING, "HECI: CSE device is hidden\n"); + return false; + } + + return true; +} + +uint32_t me_read_config32(int offset) +{ + return pci_read_config32(PCH_DEV_CSE, offset); +} + +/* + * Sends GLOBAL_RESET_REQ cmd to CSE.The reset type can be GLOBAL_RESET/ + * HOST_RESET_ONLY/CSE_RESET_ONLY. + */ +int send_heci_reset_req_message(uint8_t rst_type) +{ + int status; + struct mkhi_hdr reply; + struct reset_message { + struct mkhi_hdr hdr; + uint8_t req_origin; + uint8_t reset_type; + } __packed; + struct reset_message msg = { + .hdr = { + .group_id = MKHI_GROUP_ID_CBM, + .command = MKHI_GLOBAL_RESET_REQ, + }, + .req_origin = GR_ORIGIN_BIOS_POST, + .reset_type = rst_type + }; + size_t reply_size; + + if (!((rst_type == GLOBAL_RESET) || + (rst_type == HOST_RESET_ONLY) || (rst_type == CSE_RESET_ONLY))) + return -1; + + heci_reset(); + + reply_size = sizeof(reply); + memset(&reply, 0, reply_size); + + printk(BIOS_DEBUG, "HECI: Global Reset(Type:%d) Command\n", rst_type); + if (rst_type == CSE_RESET_ONLY) + status = heci_send_receive(&msg, sizeof(msg), NULL, 0); + else + status = heci_send_receive(&msg, sizeof(msg), &reply, + &reply_size); + + if (status != 1) + return -1; + + printk(BIOS_DEBUG, "HECI: Global Reset success!\n"); + return 0; +} + +/* Sends HMRFPO Enable command to CSE */ +int send_hmrfpo_enable_msg(void) +{ + struct hmrfpo_enable_msg { + struct mkhi_hdr hdr; + uint32_t nonce[2]; + } __packed; + + /* HMRFPO Enable message */ + struct hmrfpo_enable_msg msg = { + .hdr = { + .group_id = MKHI_HMRFPO_GROUP_ID, + .command = MKHI_HMRFPO_ENABLE, + }, + .nonce = {0}, + }; + + /* HMRFPO Enable response */ + struct hmrfpo_enable_resp { + struct mkhi_hdr hdr; + uint32_t fct_base; + uint32_t fct_limit; + uint8_t status; + uint8_t padding[3]; + } __packed; + + struct hmrfpo_enable_resp resp; + size_t resp_size = sizeof(struct hmrfpo_enable_resp); + union me_hfsts1 hfs1; + + printk(BIOS_DEBUG, "HECI: Send HMRFPO Enable Command\n"); + hfs1.data = me_read_config32(PCI_ME_HFSTS1); + /* + * This command can be run only if: + * - Working state is normal and + * - Operation mode is normal or temporary disable mode. + */ + if (hfs1.fields.working_state != ME_HFS_CWS_NORMAL || + (hfs1.fields.operation_mode != ME_HFS_MODE_NORMAL && + hfs1.fields.operation_mode != ME_HFS_TEMP_DISABLE)) { + printk(BIOS_ERR, "HECI: ME not in required Mode\n"); + goto failed; + } + + if (!heci_send_receive(&msg, sizeof(struct hmrfpo_enable_msg), + &resp, &resp_size)) + goto failed; + + if (resp.hdr.result) { + printk(BIOS_ERR, "HECI: Resp Failed:%d\n", resp.hdr.result); + goto failed; + } + return 1; + +failed: + return 0; +} + +/* + * Sends HMRFPO Get Status command to CSE to get the HMRFPO status. + * The status can be DISABLES/LOCKED/ENABLED + */ +int send_hmrfpo_get_status_msg(void) +{ + struct hmrfpo_get_status_msg { + struct mkhi_hdr hdr; + } __packed; + + struct hmrfpo_get_status_resp { + struct mkhi_hdr hdr; + uint8_t status; + uint8_t padding[3]; + } __packed; + + struct hmrfpo_get_status_msg msg = { + .hdr = { + .group_id = MKHI_HMRFPO_GROUP_ID, + .command = MKHI_HMRFPO_GET_STATUS, + }, + }; + struct hmrfpo_get_status_resp resp; + size_t resp_size = sizeof(struct hmrfpo_get_status_resp); + + printk(BIOS_INFO, "HECI: Sending Get HMRFPO Status Command\n"); + + if (!heci_send_receive(&msg, sizeof(struct hmrfpo_get_status_msg), + &resp, &resp_size)) { + printk(BIOS_ERR, "HECI: HMRFPO send/receive fail\n"); + return -1; + } + + if (resp.hdr.result) { + printk(BIOS_ERR, "HECI: HMRFPO Resp Failed:%d\n", + resp.hdr.result); + return -1; + } + + return resp.status; +} + #if ENV_RAMSTAGE static void update_sec_bar(struct device *dev) @@ -515,6 +749,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_GLK_CSE0, PCI_DEVICE_ID_INTEL_CNL_CSE0, PCI_DEVICE_ID_INTEL_SKL_CSE0, + PCI_DEVICE_ID_INTEL_LWB_CSE0, + PCI_DEVICE_ID_INTEL_LWB_CSE0_SUPER, PCI_DEVICE_ID_INTEL_CNP_H_CSE0, PCI_DEVICE_ID_INTEL_ICL_CSE0, PCI_DEVICE_ID_INTEL_CMP_CSE0, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 2b4c4a74db..7aece76ca6 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -177,6 +177,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_2, PCI_DEVICE_ID_INTEL_CML_GT1_ULT_3, PCI_DEVICE_ID_INTEL_CML_GT1_ULT_4, + PCI_DEVICE_ID_INTEL_CML_GT2_ULT_5, + PCI_DEVICE_ID_INTEL_CML_GT2_ULT_6, PCI_DEVICE_ID_INTEL_CML_GT2_ULT_3, PCI_DEVICE_ID_INTEL_CML_GT2_ULT_4, PCI_DEVICE_ID_INTEL_CML_GT1_ULX_1, diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index 8ab835e577..0cf9baa3ef 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include @@ -75,6 +74,8 @@ static struct device_operations hda_ops = { static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_SKL_AUDIO, PCI_DEVICE_ID_INTEL_SKL_H_AUDIO, + PCI_DEVICE_ID_INTEL_LWB_AUDIO, + PCI_DEVICE_ID_INTEL_LWB_AUDIO_SUPER, PCI_DEVICE_ID_INTEL_KBL_AUDIO, PCI_DEVICE_ID_INTEL_CNL_AUDIO, PCI_DEVICE_ID_INTEL_CNP_H_AUDIO, diff --git a/src/soc/intel/common/block/imc/Kconfig b/src/soc/intel/common/block/imc/Kconfig new file mode 100644 index 0000000000..490b80ebeb --- /dev/null +++ b/src/soc/intel/common/block/imc/Kconfig @@ -0,0 +1,7 @@ +config SOC_INTEL_COMMON_BLOCK_IMC + bool + depends on MMCONF_SUPPORT + default n + help + Driver for communication with Integrated Memory Controller that is found on + some Xeon server processors. diff --git a/src/soc/intel/common/block/imc/Makefile.inc b/src/soc/intel/common/block/imc/Makefile.inc new file mode 100644 index 0000000000..a6bc985eb2 --- /dev/null +++ b/src/soc/intel/common/block/imc/Makefile.inc @@ -0,0 +1,9 @@ +ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_IMC),y) + +bootblock-y += imc.c +romstage-y += imc.c +verstage-y += imc.c +postcar-y += imc.c +ramstage-y += imc.c + +endif diff --git a/src/soc/intel/common/block/imc/imc.c b/src/soc/intel/common/block/imc/imc.c new file mode 100644 index 0000000000..e7f20bef03 --- /dev/null +++ b/src/soc/intel/common/block/imc/imc.c @@ -0,0 +1,171 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Please note: the driver uses MMIO PCIe register access. IO based access will + * not work. + */ + +#include +#include +#include +#include +#include +#include + +#define IMC_SMBUS_TIMEOUT_MS 100 +#define IMC_SMBCNTL_DTI_TSOD 0x3 +#define IMC_SMBCNTL_DTI_EEPROM 0xa +#define IMC_SMBCNTL_DTI_WP_EEPROM 0x6 + +#define SMBSTAT(i) (0x180 + 0x10 * i) +#define SMBCMD(i) (0x184 + 0x10 * i) +#define SMBCNTL(i) (0x188 + 0x10 * i) + +#define SMBSTAT_RDO (1u << 31) /* Read Data Valid */ +#define SMBSTAT_WOD (1u << 30) /* Write Operation Done */ +#define SMBSTAT_SBE (1u << 29) /* SMBus Error */ +#define SMBSTAT_SMB_BUSY (1u << 28) /* SMBus Busy State */ + +#define SMBCMD_TRIGGER (1u << 31) /* CMD Trigger */ +#define SMBCMD_PNTR_SEL (1u << 30) /* HW polls TSOD with pointer */ +#define SMBCMD_WORD_ACCESS (1u << 29) /* word (vs byte) access */ +#define SMBCMD_TYPE_MASK (3u << 27) /* Mask for access type */ +#define SMBCMD_TYPE_READ (0u << 27) /* Read */ +#define SMBCMD_TYPE_WRITE (1u << 27) /* Write */ +#define SMBCMD_TYPE_PNTR_WRITE (3u << 27) /* Write to pointer */ +#define SMBCMD_SA_MASK (7u << 24) /* Slave Address high bits */ +#define SMBCMD_SA_SHIFT 24 +#define SMBCMD_BA_MASK 0xff0000 /* Bus Txn address */ +#define SMBCMD_BA_SHIFT 16 +#define SMBCMD_WDATA_MASK 0xffff /* data to write */ + +#define SMBCNTL_DTI_MASK 0xf0000000 /* Slave Address low bits */ +#define SMBCNTL_DTI_SHIFT 28 /* Slave Address low bits */ +#define SMBCNTL_CKOVRD (1u << 27) /* # Clock Override */ +#define SMBCNTL_DIS_WRT (1u << 26) /* Disable Write (sadly) */ +#define SMBCNTL_SOFT_RST (1u << 10) /* Soft Reset */ +#define SMBCNTL_TSOD_POLL_EN (1u << 8) /* TSOD Polling Enable */ + +static bool poll_ready(pci_devfn_t dev, enum memory_controller_id mcid, uint32_t *status) +{ + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, IMC_SMBUS_TIMEOUT_MS); + + do { + *status = pci_mmio_read_config32(dev, SMBSTAT(mcid)); + if (!(*status & SMBSTAT_SMB_BUSY)) + break; + } while (!stopwatch_expired(&sw)); + + return (!(*status & SMBSTAT_SMB_BUSY)); +} + +static bool claim_controller(pci_devfn_t dev, enum memory_controller_id mcid) +{ + uint32_t cntl, status; + + cntl = pci_mmio_read_config32(dev, SMBCNTL(mcid)); + cntl &= ~SMBCNTL_TSOD_POLL_EN; + cntl &= ~SMBCNTL_DIS_WRT; + pci_mmio_write_config32(dev, SMBCNTL(mcid), cntl); + + return poll_ready(dev, mcid, &status); +} + + +static void release_controller(pci_devfn_t dev, enum memory_controller_id mcid) +{ + uint32_t cntl, status; + + cntl = pci_mmio_read_config32(dev, SMBCNTL(mcid)); + cntl |= SMBCNTL_TSOD_POLL_EN; + pci_mmio_write_config32(dev, SMBCNTL(mcid), cntl); + + poll_ready(dev, mcid, &status); +} + +int imc_smbus_spd_xfer(pci_devfn_t dev, uint8_t slave_addr, uint8_t bus_addr, + enum device_type_id dti, enum access_width width, + enum memory_controller_id mcid, enum smbus_command cmd, void *data) +{ + int ret = -1; + uint32_t cmdbits = 0, stat = 0, cntlbits = 0, data_mask = 0; + uint16_t wdata = 0, rdata = 0; + + /* slaves addresses are 7 bits length */ + if (slave_addr > (1 << 7) - 1) { + printk(BIOS_ERR, "invalid SMBus address, aborting xfer\n"); + return -1; + } + + if (!claim_controller(dev, mcid)) { + printk(BIOS_ERR, "ayee! couldn't claim controller, giving up xfer\n"); + return -1; + } + + cmdbits = (slave_addr << SMBCMD_SA_SHIFT); + cmdbits |= (bus_addr << SMBCMD_BA_SHIFT); + + if (cmd == IMC_WRITE) { + wdata = (width == IMC_DATA_BYTE ? read8(data) : cpu_to_be16(read16(data))); + cmdbits |= (SMBCMD_TYPE_WRITE | wdata); + } else { + cmdbits |= SMBCMD_TYPE_READ; + } + + if (width == IMC_DATA_WORD) { + cmdbits |= SMBCMD_WORD_ACCESS; + data_mask = 0xffff; + } else { + data_mask = 0xff; + } + + cntlbits = pci_mmio_read_config32(dev, SMBCNTL(mcid)); + cntlbits &= ~SMBCNTL_DTI_MASK; + cntlbits |= (dti << SMBCNTL_DTI_SHIFT); + + pci_mmio_write_config32(dev, SMBCNTL(mcid), cntlbits); + + /* Pull the trigger */ + cmdbits |= SMBCMD_TRIGGER; + pci_mmio_write_config32(dev, SMBCMD(mcid), cmdbits); + + if (!poll_ready(dev, mcid, &stat)) { + printk(BIOS_ERR, "IMC xfer failed for slave %x", slave_addr); + ret = -1; + goto cleanup; + } + + if (stat & SMBSTAT_SBE) { + ret = -1; + goto cleanup; + } + + if (cmd == IMC_READ) { + rdata = stat & data_mask; + if (width == IMC_DATA_WORD) + write16(data, cpu_to_be16(rdata)); + else + write8(data, rdata); + } + + ret = 0; +cleanup: + release_controller(dev, SMBSTAT(mcid)); + + return ret; +} diff --git a/src/soc/intel/common/block/include/intelblocks/chip.h b/src/soc/intel/common/block/include/intelblocks/chip.h index 9fe165e5b1..1e830d5d17 100644 --- a/src/soc/intel/common/block/include/intelblocks/chip.h +++ b/src/soc/intel/common/block/include/intelblocks/chip.h @@ -18,6 +18,7 @@ #include #include +#include enum { CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */ @@ -35,6 +36,7 @@ struct soc_intel_common_config { struct dw_i2c_bus_config i2c[CONFIG_SOC_INTEL_I2C_DEV_MAX]; /* PCH Thermal Trip Temperature in deg C */ uint8_t pch_thermal_trip; + struct mmc_dll_params emmc_dll; }; /* This function to retrieve soc config structure required by common code */ diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index d7c4d9f93e..b4bfe68924 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -19,6 +19,49 @@ #include +/* HFSTS register offsets in PCI config space */ +enum { + PCI_ME_HFSTS1 = 0x40, + PCI_ME_HFSTS2 = 0x48, + PCI_ME_HFSTS3 = 0x60, + PCI_ME_HFSTS4 = 0x64, + PCI_ME_HFSTS5 = 0x68, + PCI_ME_HFSTS6 = 0x6C, +}; + +/* ME Host Firmware Status register 1 */ +union me_hfsts1 { + u32 data; + struct { + u32 working_state: 4; + u32 mfg_mode: 1; + u32 fpt_bad: 1; + u32 operation_state: 3; + u32 fw_init_complete: 1; + u32 ft_bup_ld_flr: 1; + u32 update_in_progress: 1; + u32 error_code: 4; + u32 operation_mode: 4; + u32 reset_count: 4; + u32 boot_options_present: 1; + u32 reserved1: 1; + u32 bist_test_state: 1; + u32 bist_reset_request: 1; + u32 current_power_source: 2; + u32 d3_support_valid: 1; + u32 d0i3_support_valid: 1; + } __packed fields; +}; + +/* HECI Message Header */ +struct mkhi_hdr { + uint8_t group_id; + uint8_t command:7; + uint8_t is_resp:1; + uint8_t rsvd; + uint8_t result; +} __packed; + /* set up device for use in early boot enviroument with temp bar */ void heci_init(uintptr_t bar); /* @@ -37,6 +80,14 @@ int heci_receive(void *buff, size_t *maxlen); */ int heci_send(const void *msg, size_t len, uint8_t host_addr, uint8_t cse_addr); + +/* + * Sends snd_msg of size snd_sz, and reads message into buffer pointed by + * rcv_msg of size rcv_sz + * Returns 0 on failure a 1 on success. + */ +int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t *rcv_sz); + /* * Attempt device reset. This is useful and perhaps only thing left to do when * CPU and CSE are out of sync or CSE fails to respond. @@ -44,7 +95,58 @@ heci_send(const void *msg, size_t len, uint8_t host_addr, uint8_t cse_addr); */ int heci_reset(void); +/* Reads config value from a specified offset in the CSE PCI Config space. */ +uint32_t me_read_config32(int offset); + +/* + * Check if the CSE device is enabled in device tree. Also check if the device + * is visible on the PCI bus by reading config space. + * Return true if device present and config space enabled, else return false. + */ +bool is_cse_enabled(void); + + +/* Makes the host ready to communicate with CSE*/ +void set_host_ready(void); + +/* + * Polls for ME state 'HECI_OP_MODE_SEC_OVERRIDE' for 15 seconds. + * Returns 0 on failure a 1 on success. + */ +uint8_t wait_cse_sec_override_mode(void); + +/* + * Sends GLOBAL_RESET_REQ cmd to CSE.The reset type can be + * GLOBAL_RESET/HOST_RESET_ONLY/CSE_RESET_ONLY. + * Returns -1 on failure a 0 on success. + */ +int send_heci_reset_req_message(uint8_t rst_type); + +/* + * Send HMRFPO_ENABLE command. + * returns 0 on failure and 1 on success. + */ +int send_hmrfpo_enable_msg(void); + +/* + * Send HMRFPO_GET_STATUS command. + * returns -1 on failure and 0 (DISABLED)/ 1 (LOCKED)/ 2 (ENABLED) + * on success. + */ +int send_hmrfpo_get_status_msg(void); + + #define BIOS_HOST_ADDR 0x00 #define HECI_MKHI_ADDR 0x07 +/* Command GLOBAL_RESET_REQ Reset Types */ +#define GLOBAL_RESET 1 +#define HOST_RESET_ONLY 2 +#define CSE_RESET_ONLY 3 + +/*HMRFPO Status types */ +#define MKHI_HMRFPO_DISABLED 0 +#define MKHI_HMRFPO_LOCKED 1 +#define MKHI_HMRFPO_ENABLED 2 + #endif // SOC_INTEL_COMMON_MSR_H diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 744095207d..15df187d5b 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -228,34 +228,34 @@ #define PAD_CFG_GPO(pad, val, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_CFG0_TRIG_OFF | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE)) /* General purpose output, with termination specified */ #define PAD_CFG_TERM_GPO(pad, val, pull, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_CFG0_TRIG_OFF | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) /* General purpose output, no pullup/down. */ #define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_CFG0_TRIG_OFF | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_GPIO_DRIVER) /* General purpose output. */ #define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_CFG0_TRIG_OFF | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm)) /* General purpose input */ #define PAD_CFG_GPI(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) /* General purpose input. The following macro sets the @@ -263,50 +263,48 @@ */ #define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxDRxE)) #define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ - PAD_CFG0_RX_DISABLE, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_RX_DISABLE), \ PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) #define PAD_CFG_GPIO_HI_Z(pad, pull, rst, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ - PAD_CFG0_RX_DISABLE, PAD_PULL(pull) | \ - PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_RX_DISABLE), \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) /* GPIO Interrupt */ #define PAD_CFG_GPI_INT(pad, pull, rst, trig) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_CFG0_TRIG_##trig | PAD_CFG0_RX_POL_NONE, \ PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxDRxE)) /* * No Connect configuration for unused pad. * Both TX and RX are disabled. RX disabling is done to avoid unnecessary - * setting of GPI_STS. + * setting of GPI_STS. RX Level/Edge Trig Configuration set to disable */ #define PAD_NC(pad, pull) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | \ - PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE, \ + PAD_CFG0_TRIG_OFF | PAD_BUF(TX_RX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS) #define PAD_CFG_GPI_APIC(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(IOAPIC, LEVEL, NONE), PAD_PULL(pull)) #define PAD_CFG_GPI_APIC_INVERT(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(IOAPIC, LEVEL, INVERT), PAD_PULL(pull)) #define PAD_CFG_GPI_ACPI_SCI(pad, pull, rst, inv) \ @@ -327,7 +325,7 @@ /* General purpose input, routed to APIC */ #define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE)) #endif @@ -335,7 +333,7 @@ /* General purpose input, routed to APIC - with IOStandby Config*/ #define PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) @@ -356,14 +354,14 @@ /* General purpose input, routed to SMI */ #define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE)) /* General purpose input, routed to SMI */ #define PAD_CFG_GPI_SMI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) @@ -376,14 +374,14 @@ /* General purpose input, routed to SCI */ #define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE)) /* General purpose input, routed to SCI */ #define PAD_CFG_GPI_SCI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) @@ -395,7 +393,7 @@ #define PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, inv, dur) \ _PAD_CFG_STRUCT_3(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE), PAD_CFG2_DEBEN | PAD_CFG2_##dur) @@ -408,21 +406,14 @@ /* General purpose input, routed to NMI */ #define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE)) #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) -/* GPI, GPIO Driver, SCI interrupt */ -#define PAD_CFG_GPI_GPIO_DRIVER_SCI(pad, pull, rst, trig, inv) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ - PAD_IRQ_CFG(SCI, trig, inv), \ - PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxDRxE)) - #define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) diff --git a/src/soc/intel/common/block/include/intelblocks/imc.h b/src/soc/intel/common/block/include/intelblocks/imc.h new file mode 100644 index 0000000000..fc3c241564 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/imc.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#ifndef SOC_INTEL_COMMON_BLOCK_IMC_H +#define SOC_INTEL_COMMON_BLOCK_IMC_H + +enum smbus_command { IMC_READ, IMC_WRITE }; + +enum access_width { IMC_DATA_BYTE, IMC_DATA_WORD }; + +enum memory_controller_id { IMC_CONTROLLER_ID0 = 0, IMC_CONTROLLER_ID1 }; + +enum device_type_id { + IMC_DEVICE_TSOD = 0x3, + IMC_DEVICE_WP_EEPROM = 0x6, + IMC_DEVICE_EEPROM = 0xa +}; + +/* Initiate SMBus/I2C transaction to DIMM EEPROM */ +int imc_smbus_spd_xfer(pci_devfn_t dev, uint8_t slave_addr, uint8_t bus_addr, + enum device_type_id dti, enum access_width width, + enum memory_controller_id mcid, enum smbus_command cmd, void *data); +#endif diff --git a/src/soc/intel/common/block/include/intelblocks/early_mmc.h b/src/soc/intel/common/block/include/intelblocks/mmc.h similarity index 82% rename from src/soc/intel/common/block/include/intelblocks/early_mmc.h rename to src/soc/intel/common/block/include/intelblocks/mmc.h index 39aaf58fcf..a8776ea842 100644 --- a/src/soc/intel/common/block/include/intelblocks/early_mmc.h +++ b/src/soc/intel/common/block/include/intelblocks/mmc.h @@ -13,17 +13,11 @@ * GNU General Public License for more details. */ -#ifndef SOC_INTEL_COMMON_BLOCK_EARLY_MMC_H -#define SOC_INTEL_COMMON_BLOCK_EARLY_MMC_H +#ifndef SOC_INTEL_COMMON_BLOCK_MMC_H +#define SOC_INTEL_COMMON_BLOCK_MMC_H #include -/* - * Following should be defined in soc/iomap.h - * PRERAM_MMC_BASE_ADDRESS - Provide an address to setup emmc controller's - PCI BAR. - */ - /* * Structure for the following delay registers * emmc_tx_data_cntl1: Tx Delay Control 1 (Tx_DATA_dly_1)-Offset 824h @@ -60,8 +54,27 @@ int soc_configure_mmc_gpios(void); * returns 0, if able to get register settings; otherwise returns -1 */ int soc_get_mmc_dll(struct mmc_dll_params *params); +/* + * Set mmc delay register settings. + * bar: eMMC controller MMIO base address. + * returns 0, if able to set register settings; otherwise returns -1 + */ +int set_mmc_dll(void *bar); + +#define EMMC_TX_CMD_CNTL_OFFSET 0x820 +#define EMMC_TX_DATA_CNTL1_OFFSET 0x824 +#define EMMC_TX_DATA_CNTL2_OFFSET 0x828 +#define EMMC_RX_CMD_DATA_CNTL1_OFFSET 0x82C +#define EMMC_RX_STROBE_CNTL_OFFSET 0x830 +#define EMMC_RX_CMD_DATA_CNTL2_OFFSET 0x834 #if CONFIG(SOC_INTEL_COMMON_EARLY_MMC_WAKE) +/* + * Following should be defined in soc/iomap.h + * PRERAM_MMC_BASE_ADDRESS - Provide an address to setup emmc controller's + PCI BAR. + */ + /* * Initializes sdhci / mmc controller and sends CMD0, CMD1 to emmc card. * In case of success: It returns 0 and adds cbmem entry CBMEM_ID_MMC_STATUS @@ -77,4 +90,4 @@ static inline int early_mmc_wake_hw(void) return -1; } #endif /* CONFIG_SOC_INTEL_COMMON_EARLY_MMC_WAKE */ -#endif /* SOC_INTEL_COMMON_BLOCK_EARLY_MMC_H */ +#endif /* SOC_INTEL_COMMON_BLOCK_MMC_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/smm.h b/src/soc/intel/common/block/include/intelblocks/smm.h index 25ff8f4ec9..8b13789179 100644 --- a/src/soc/intel/common/block/include/intelblocks/smm.h +++ b/src/soc/intel/common/block/include/intelblocks/smm.h @@ -1,36 +1 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef SOC_INTEL_COMMON_BLOCK_SMM_H -#define SOC_INTEL_COMMON_BLOCK_SMM_H - -#include - -/* - * This common code block relies on each specific SOC defining the macro - * ENABLE_SMI_PARAMS for the values needed for SMI enabling on the - * specific SOC - */ - -/* - * The initialization of the southbridge is split into 2 compoments. One is - * for clearing the state in the SMM registers. The other is for enabling - * SMIs. - */ -void smm_southbridge_clear_state(void); -void smm_southbridge_enable(uint16_t pm1_events); - -#endif diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index d7917d6262..46dfd7ff57 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -138,6 +138,19 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_SPT_H_HM175, PCI_DEVICE_ID_INTEL_SPT_H_QM175, PCI_DEVICE_ID_INTEL_SPT_H_CM238, + PCI_DEVICE_ID_INTEL_LWB_C621, + PCI_DEVICE_ID_INTEL_LWB_C622, + PCI_DEVICE_ID_INTEL_LWB_C624, + PCI_DEVICE_ID_INTEL_LWB_C625, + PCI_DEVICE_ID_INTEL_LWB_C626, + PCI_DEVICE_ID_INTEL_LWB_C627, + PCI_DEVICE_ID_INTEL_LWB_C628, + PCI_DEVICE_ID_INTEL_LWB_C629, + PCI_DEVICE_ID_INTEL_LWB_C624_SUPER, + PCI_DEVICE_ID_INTEL_LWB_C627_SUPER_1, + PCI_DEVICE_ID_INTEL_LWB_C621_SUPER, + PCI_DEVICE_ID_INTEL_LWB_C627_SUPER_2, + PCI_DEVICE_ID_INTEL_LWB_C628_SUPER, PCI_DEVICE_ID_INTEL_KBP_H_Q270, PCI_DEVICE_ID_INTEL_KBP_H_H270, PCI_DEVICE_ID_INTEL_KBP_H_Z270, diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 24cde1b6c9..1df05679dd 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -168,6 +168,8 @@ static const struct device_operations device_ops = { static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_APL_P2SB, PCI_DEVICE_ID_INTEL_GLK_P2SB, + PCI_DEVICE_ID_INTEL_LWB_P2SB, + PCI_DEVICE_ID_INTEL_LWB_P2SB_SUPER, PCI_DEVICE_ID_INTEL_CNL_P2SB, PCI_DEVICE_ID_INTEL_CNP_H_P2SB, PCI_DEVICE_ID_INTEL_ICL_P2SB, diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index e8b1050f4a..94fa63122e 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -113,6 +113,46 @@ static const unsigned short pcie_device_ids[] = { PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP18, PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP19, PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP20, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP1, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP2, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP3, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP4, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP5, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP6, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP7, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP8, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP9, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP10, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP11, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP12, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP13, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP14, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP15, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP16, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP17, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP18, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP19, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP20, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP1_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP2_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP3_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP4_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP5_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP6_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP7_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP8_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP9_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP10_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP11_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP12_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP13_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP14_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP15_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP16_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP17_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP18_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP19_SUPER, + PCI_DEVICE_ID_INTEL_LWB_PCIE_RP20_SUPER, PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1, PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP2, PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP3, diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index eaaf1252ea..f6f0983227 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -125,6 +125,8 @@ static struct device_operations device_ops = { static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_SPT_LP_PMC, PCI_DEVICE_ID_INTEL_SPT_H_PMC, + PCI_DEVICE_ID_INTEL_LWB_PMC, + PCI_DEVICE_ID_INTEL_LWB_PMC_SUPER, PCI_DEVICE_ID_INTEL_KBP_H_PMC, PCI_DEVICE_ID_INTEL_APL_PMC, PCI_DEVICE_ID_INTEL_GLK_PMC, diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 7dacc6ed92..0c278f37f2 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -75,6 +75,18 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_SPT_U_SATA, PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA, PCI_DEVICE_ID_INTEL_SPT_KBL_SATA, + PCI_DEVICE_ID_INTEL_LWB_SATA_AHCI, + PCI_DEVICE_ID_INTEL_LWB_SSATA_AHCI, + PCI_DEVICE_ID_INTEL_LWB_SATA_RAID, + PCI_DEVICE_ID_INTEL_LWB_SSATA_RAID, + PCI_DEVICE_ID_INTEL_LWB_SATA_AHCI_SUPER, + PCI_DEVICE_ID_INTEL_LWB_SSATA_AHCI_SUPER, + PCI_DEVICE_ID_INTEL_LWB_SATA_RAID_SUPER, + PCI_DEVICE_ID_INTEL_LWB_SSATA_RAID_SUPER, + PCI_DEVICE_ID_INTEL_LWB_SATA_ALT, + PCI_DEVICE_ID_INTEL_LWB_SATA_ALT_RST, + PCI_DEVICE_ID_INTEL_LWB_SSATA_ALT, + PCI_DEVICE_ID_INTEL_LWB_SSATA_ALT_RST, PCI_DEVICE_ID_INTEL_CNL_SATA, PCI_DEVICE_ID_INTEL_CNL_PREMIUM_SATA, PCI_DEVICE_ID_INTEL_CNP_CMP_COMPAT_SATA, diff --git a/src/soc/intel/common/block/scs/Kconfig b/src/soc/intel/common/block/scs/Kconfig index 06ad8e4fa8..192425c4a0 100644 --- a/src/soc/intel/common/block/scs/Kconfig +++ b/src/soc/intel/common/block/scs/Kconfig @@ -12,3 +12,10 @@ config SOC_INTEL_COMMON_EARLY_MMC_WAKE help Send CMD1 early in romstage to improve boot time. It requires emmc DLL tuning parameters to be added to devicetree.cb + +config SOC_INTEL_COMMON_MMC_OVERRIDE + bool + default n + help + Override the MMC settings after FSP-S. + It should be used only when there is no FSP UPDs for certain setting. diff --git a/src/soc/intel/common/block/scs/Makefile.inc b/src/soc/intel/common/block/scs/Makefile.inc index 1160802d03..707a3342ad 100644 --- a/src/soc/intel/common/block/scs/Makefile.inc +++ b/src/soc/intel/common/block/scs/Makefile.inc @@ -1,2 +1,3 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SCS) += sd.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SCS) += mmc.c romstage-$(CONFIG_SOC_INTEL_COMMON_EARLY_MMC_WAKE) += early_mmc.c diff --git a/src/soc/intel/common/block/scs/early_mmc.c b/src/soc/intel/common/block/scs/early_mmc.c index 8f47ec7d9e..80364500b9 100644 --- a/src/soc/intel/common/block/scs/early_mmc.c +++ b/src/soc/intel/common/block/scs/early_mmc.c @@ -21,18 +21,11 @@ #include #include #include -#include +#include #include #include #include -#define EMMC_TX_CMD_CNTL_OFFSET 0x820 -#define EMMC_TX_DATA_CNTL1_OFFSET 0x824 -#define EMMC_TX_DATA_CNTL2_OFFSET 0x828 -#define EMMC_RX_CMD_DATA_CNTL1_OFFSET 0x82C -#define EMMC_RX_STROBE_CNTL_OFFSET 0x830 -#define EMMC_RX_CMD_DATA_CNTL2_OFFSET 0x834 - void soc_sd_mmc_controller_quirks(struct sd_mmc_ctrlr *ctrlr) { uint32_t f_min, f_max; @@ -62,32 +55,6 @@ static void disable_mmc_controller_bar(void) ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)); } -static int set_mmc_dll(void *ioaddr) -{ - struct mmc_dll_params dll_params; - - if (soc_get_mmc_dll(&dll_params) < 0) { - printk(BIOS_ERR, - "MMC early init: failed to get mmc DLL parameters\n"); - return -1; - } - - write32(ioaddr + EMMC_TX_DATA_CNTL1_OFFSET, - dll_params.emmc_tx_data_cntl1); - write32(ioaddr + EMMC_TX_DATA_CNTL2_OFFSET, - dll_params.emmc_tx_data_cntl2); - write32(ioaddr + EMMC_RX_CMD_DATA_CNTL1_OFFSET, - dll_params.emmc_rx_cmd_data_cntl1); - write32(ioaddr + EMMC_RX_CMD_DATA_CNTL2_OFFSET, - dll_params.emmc_rx_cmd_data_cntl2); - write32(ioaddr + EMMC_RX_STROBE_CNTL_OFFSET, - dll_params.emmc_rx_strobe_cntl); - write32(ioaddr + EMMC_TX_CMD_CNTL_OFFSET, - dll_params.emmc_tx_cmd_cntl); - - return 0; -} - static void set_early_mmc_wake_status(int32_t status) { int32_t *ms_cbmem; diff --git a/src/soc/intel/common/block/scs/mmc.c b/src/soc/intel/common/block/scs/mmc.c new file mode 100644 index 0000000000..5b2e2c7d33 --- /dev/null +++ b/src/soc/intel/common/block/scs/mmc.c @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +static int mmc_write_dll_reg(void *bar, uint32_t reg, uint32_t val) +{ + int ret = 0; + if (val) { + write32(bar + reg, val); + ret = 1; + } + return ret; +} + +int set_mmc_dll(void *bar) +{ + const struct soc_intel_common_config *common_config; + const struct mmc_dll_params *dll_params; + int override = 0; + + common_config = chip_get_common_soc_structure(); + dll_params = &common_config->emmc_dll; + + override |= mmc_write_dll_reg(bar, EMMC_TX_CMD_CNTL_OFFSET, + dll_params->emmc_tx_cmd_cntl); + + override |= mmc_write_dll_reg(bar, EMMC_TX_DATA_CNTL1_OFFSET, + dll_params->emmc_tx_data_cntl1); + + override |= mmc_write_dll_reg(bar, EMMC_TX_DATA_CNTL2_OFFSET, + dll_params->emmc_tx_data_cntl2); + + override |= mmc_write_dll_reg(bar, EMMC_RX_CMD_DATA_CNTL1_OFFSET, + dll_params->emmc_rx_cmd_data_cntl1); + + override |= mmc_write_dll_reg(bar, EMMC_RX_STROBE_CNTL_OFFSET, + dll_params->emmc_rx_strobe_cntl); + + override |= mmc_write_dll_reg(bar, EMMC_RX_CMD_DATA_CNTL2_OFFSET, + dll_params->emmc_rx_cmd_data_cntl2); + + if (override == 0) { + printk(BIOS_INFO, "Skip Emmc dll value programming\n"); + return -1; + } + + return 0; +} + +static void mmc_soc_init(struct device *dev) +{ + const struct resource *res; + + if (!CONFIG(SOC_INTEL_COMMON_MMC_OVERRIDE)) + return; + + res = find_resource(dev, PCI_BASE_ADDRESS_0); + set_mmc_dll((void *)(uintptr_t)(res->base)); +} + +static struct device_operations dev_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = mmc_soc_init, + .ops_pci = &pci_dev_ops_pci, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_CMP_EMMC, + 0 +}; + +static const struct pci_driver pch_sd __pci_driver = { + .ops = &dev_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index fc2257719a..77b05c1826 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include "smbuslib.h" @@ -92,7 +91,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNL_SMBUS, PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS, PCI_DEVICE_ID_INTEL_SPT_H_SMBUS, - PCI_DEVICE_ID_INTEL_KBP_H_SMBUS, + PCI_DEVICE_ID_INTEL_LWB_SMBUS_SUPER, + PCI_DEVICE_ID_INTEL_KBP_H_LWB_SMBUS, PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS, PCI_DEVICE_ID_INTEL_CMP_SMBUS, 0 diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 58026cea5f..97a4f4aa63 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -20,6 +20,8 @@ #include #include #include +#include +#include #include #include #include diff --git a/src/soc/intel/common/block/smm/smitraphandler.c b/src/soc/intel/common/block/smm/smitraphandler.c index bfa984651e..974c4897a8 100644 --- a/src/soc/intel/common/block/smm/smitraphandler.c +++ b/src/soc/intel/common/block/smm/smitraphandler.c @@ -108,6 +108,7 @@ void smihandler_southbridge_monitor( /* Trapped write data */ data = pcr_read32(PID_PSTH, PCR_PSTH_TRPD); data &= mask; + printk(BIOS_DEBUG, " iotrap read data = 0x%08x\n", data); } } diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index 12c057b25a..bef923ac1a 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -18,8 +18,8 @@ #include #include #include +#include #include -#include #include #include diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index af5087f716..365da2faa6 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -71,6 +71,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNP_H_SPI1, PCI_DEVICE_ID_INTEL_CNP_H_SPI2, PCI_DEVICE_ID_INTEL_CNP_H_HWSEQ_SPI, + PCI_DEVICE_ID_INTEL_LWB_SPI, + PCI_DEVICE_ID_INTEL_LWB_SPI_SUPER, PCI_DEVICE_ID_INTEL_ICP_SPI0, PCI_DEVICE_ID_INTEL_ICP_SPI1, PCI_DEVICE_ID_INTEL_ICP_SPI2, diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index c9abb55490..b19b8ca64f 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -348,7 +348,6 @@ static const unsigned short systemagent_ids[] = { PCI_DEVICE_ID_INTEL_WHL_ID_W_4, PCI_DEVICE_ID_INTEL_KBL_ID_S, PCI_DEVICE_ID_INTEL_SKL_ID_H_EM, - PCI_DEVICE_ID_INTEL_SKL_ID_DT, PCI_DEVICE_ID_INTEL_KBL_ID_U, PCI_DEVICE_ID_INTEL_KBL_ID_Y, PCI_DEVICE_ID_INTEL_KBL_ID_H, @@ -356,12 +355,20 @@ static const unsigned short systemagent_ids[] = { PCI_DEVICE_ID_INTEL_KBL_ID_DT, PCI_DEVICE_ID_INTEL_KBL_ID_DT_2, PCI_DEVICE_ID_INTEL_CFL_ID_U, + PCI_DEVICE_ID_INTEL_CFL_ID_U_2, PCI_DEVICE_ID_INTEL_CFL_ID_H, + PCI_DEVICE_ID_INTEL_CFL_ID_H_4, PCI_DEVICE_ID_INTEL_CFL_ID_H_8, PCI_DEVICE_ID_INTEL_CFL_ID_S, + PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2, PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4, PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8, + PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_4, + PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6, PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8, + PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4, + PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6, + PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8, PCI_DEVICE_ID_INTEL_ICL_ID_U, PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2, PCI_DEVICE_ID_INTEL_ICL_ID_Y, diff --git a/src/soc/intel/common/block/timer/timer.c b/src/soc/intel/common/block/timer/timer.c index e60ac4d26d..70072cc850 100644 --- a/src/soc/intel/common/block/timer/timer.c +++ b/src/soc/intel/common/block/timer/timer.c @@ -14,12 +14,14 @@ */ #include -#include #include #include #include #include +/* Goldmont Microserver */ +#define CPU_MODEL_INTEL_ATOM_DENVERTON 0x5F + static int get_processor_model(void) { struct cpuinfo_x86 c; @@ -29,8 +31,31 @@ static int get_processor_model(void) return c.x86_model; } +static unsigned int get_max_cpuid_func(void) +{ + return cpuid_eax(0); +} + +static unsigned long get_hardcoded_crystal_freq(void) +{ + unsigned long core_crystal_nominal_freq_khz = 0; + + /* + * Denverton SoCs don't report crystal clock, and also don't support + * CPUID.0x16, so hardcode the 25MHz crystal clock. + */ + switch (get_processor_model()) { + case CPU_MODEL_INTEL_ATOM_DENVERTON: + core_crystal_nominal_freq_khz = 25000; + break; + } + + return core_crystal_nominal_freq_khz; +} + /* - * Nominal TSC frequency = "core crystal clock frequency" * EBX/EAX + * Nominal TSC frequency = "core crystal clock frequency" * + * CPUID_15h.EBX/CPUID_15h.EAX * * Time Stamp Counter * CPUID Initial EAX value = 0x15 @@ -42,41 +67,61 @@ static int get_processor_model(void) * core crystal clock in Hz. * EDX Bit 31-0 : Reserved = 0 * - * Refer to Intel SDM Jan 2019 Vol 3B Section 18.7.3 */ -unsigned long tsc_freq_mhz(void) +static unsigned long calculate_tsc_freq_from_core_crystal(void) { - unsigned int core_crystal_nominal_freq_khz; - struct cpuid_result cpuidr; + unsigned long core_crystal_nominal_freq_khz; + struct cpuid_result cpuidr_15h; - /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */ - cpuidr = cpuid(0x15); - - if (!cpuidr.ebx || !cpuidr.eax) + if (get_max_cpuid_func() < 0x15) return 0; - core_crystal_nominal_freq_khz = cpuidr.ecx / 1000; + /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */ + cpuidr_15h = cpuid(0x15); - if (!core_crystal_nominal_freq_khz) { - switch (get_processor_model()) { - case CPU_MODEL_INTEL_SKYLAKE_MOBILE: - case CPU_MODEL_INTEL_SKYLAKE_DESKTOP: - case CPU_MODEL_INTEL_KABYLAKE_MOBILE: - case CPU_MODEL_INTEL_KABYLAKE_DESKTOP: - case CPU_MODEL_INTEL_CANNONLAKE_MOBILE: - case CPU_MODEL_INTEL_ICELAKE_MOBILE: - core_crystal_nominal_freq_khz = 24000; - break; - case CPU_MODEL_INTEL_ATOM_DENVERTON: - core_crystal_nominal_freq_khz = 25000; - break; - case CPU_MODEL_INTEL_ATOM_GOLDMONT: - case CPU_MODEL_INTEL_ATOM_GEMINI_LAKE: - core_crystal_nominal_freq_khz = 19200; - break; - } - } + if (!cpuidr_15h.ebx || !cpuidr_15h.eax) + return 0; - return (core_crystal_nominal_freq_khz * cpuidr.ebx / cpuidr.eax) / - 1000; + core_crystal_nominal_freq_khz = cpuidr_15h.ecx / 1000; + + if (!core_crystal_nominal_freq_khz) + core_crystal_nominal_freq_khz = get_hardcoded_crystal_freq(); + + return (core_crystal_nominal_freq_khz * cpuidr_15h.ebx / + cpuidr_15h.eax) / 1000; +} + +/* + * Processor Frequency Information + * CPUID Initial EAX value = 0x16 + * EAX Bit 31-0 : An unsigned integer which has the processor base frequency + * information + * EBX Bit 31-0 : An unsigned integer which has maximum frequency information + * ECX Bit 31-0 : An unsigned integer which has bus frequency information + * EDX Bit 31-0 : Reserved = 0 + * + * Refer to Intel SDM Jan 2019 Vol 3B Section 18.7.3 + */ +static unsigned long get_freq_from_cpuid16h(void) +{ + if (get_max_cpuid_func() < 0x16) + return 0; + + return cpuid_eax(0x16); +} + +unsigned long tsc_freq_mhz(void) +{ + unsigned long tsc_freq; + + tsc_freq = calculate_tsc_freq_from_core_crystal(); + + if (tsc_freq) + return tsc_freq; + + /* + * Some Intel SoCs like Skylake, Kabylake and Cometlake don't report + * the crystal clock, in that case return bus frequency using CPUID.16h + */ + return get_freq_from_cpuid16h(); } diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index f556aed3d6..364835dd0f 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -33,8 +33,11 @@ extern const struct uart_gpio_pad_config uart_gpio_pads[]; extern const int uart_max_index; -static void uart_lpss_init(uintptr_t baseaddr) +static void uart_lpss_init(const struct device *dev, uintptr_t baseaddr) { + /* Ensure controller is in D0 state */ + lpss_set_power_state(dev, STATE_D0); + /* Take UART out of reset */ lpss_reset_release(baseaddr); @@ -79,7 +82,7 @@ void uart_common_init(const struct device *device, uintptr_t baseaddr) /* Enable memory access and bus master */ pci_write_config32(dev, PCI_COMMAND, UART_PCI_ENABLE); - uart_lpss_init(baseaddr); + uart_lpss_init(device, baseaddr); } const struct device *uart_get_device(void) @@ -231,7 +234,7 @@ static void uart_common_enable_resources(struct device *dev) base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xFFF; if (base) - uart_lpss_init(base); + uart_lpss_init(dev, base); } } diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 0bdf1d97ba..c5c5e6c6d6 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -125,6 +125,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_GLK_XHCI, PCI_DEVICE_ID_INTEL_SPT_LP_XHCI, PCI_DEVICE_ID_INTEL_SPT_H_XHCI, + PCI_DEVICE_ID_INTEL_LWB_XHCI, + PCI_DEVICE_ID_INTEL_LWB_XHCI_SUPER, PCI_DEVICE_ID_INTEL_KBP_H_XHCI, PCI_DEVICE_ID_INTEL_CNP_H_XHCI, PCI_DEVICE_ID_INTEL_ICP_LP_XHCI, diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index c230337449..2aadcae584 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -29,11 +29,9 @@ config CPU_SPECIFIC_OPTIONS select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select DEBUG_GPIO - select POSTCAR_CONSOLE select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET select PLATFORM_USES_FSP2_0 - select POSTCAR_STAGE select C_ENVIRONMENT_BOOTBLOCK select IOAPIC select HAVE_SMI_HANDLER diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index f01fadbdfe..10bb665bd0 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -36,6 +36,7 @@ postcar-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c romstage-y += memmap.c romstage-y += reset.c +romstage-y += ../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += tsc_freq.c romstage-y += gpio_dnv.c diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c index e9800c8ae5..f75de1f2d0 100644 --- a/src/soc/intel/denverton_ns/bootblock/bootblock.c +++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c @@ -51,7 +51,7 @@ const FSPT_UPD temp_ram_init_params = { asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { /* Call lib/bootblock.c main */ - bootblock_main_with_timestamp(base_timestamp, NULL, 0); + bootblock_main_with_basetime(base_timestamp); }; void bootblock_soc_early_init(void) diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index b72bf28a76..c21a2a7a1b 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/denverton_ns/chip.h b/src/soc/intel/denverton_ns/chip.h index f2a67dd9f9..53e86f97b0 100644 --- a/src/soc/intel/denverton_ns/chip.h +++ b/src/soc/intel/denverton_ns/chip.h @@ -72,8 +72,6 @@ struct soc_intel_denverton_ns_config { uint32_t ipc3; }; -extern struct chip_operations soc_intel_denverton_ns_ops; - typedef struct soc_intel_denverton_ns_config config_t; #endif /* SOC_INTEL_FSP_DENVERTON_NS_CHIP_H */ diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 067f59fb3a..dd6f00eaf0 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -22,6 +22,8 @@ #include #include #include +#include +#include #include #include #include @@ -253,7 +255,7 @@ static void post_mp_init(void) * Now that all APs have been relocated as well as the BSP let SMIs * start flowing. */ - southcluster_smm_enable_smi(); + smm_southbridge_enable_smi(); } /* @@ -267,7 +269,7 @@ static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, .get_smm_info = get_smm_info, - .pre_mp_smm_init = southcluster_smm_clear_state, + .pre_mp_smm_init = smm_southbridge_clear_state, .relocation_handler = relocation_handler, .post_mp_init = post_mp_init, }; diff --git a/src/soc/intel/denverton_ns/include/soc/smm.h b/src/soc/intel/denverton_ns/include/soc/smm.h index a020891dd5..0444699d3b 100644 --- a/src/soc/intel/denverton_ns/include/soc/smm.h +++ b/src/soc/intel/denverton_ns/include/soc/smm.h @@ -24,11 +24,4 @@ struct smm_relocation_attrs { uint32_t smrr_mask; }; -#if !defined(__PRE_RAM__) && !defined(__SMM___) -#include -void southcluster_smm_clear_state(void); -void southcluster_smm_enable_smi(void); -void southcluster_smm_save_gpio_route(uint32_t route); -#endif - #endif /* _DENVERTON_NS_SMM_H_ */ diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index 9507d7f238..9f788ddb41 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -14,8 +14,10 @@ * GNU General Public License for more details. */ +#include #include #include +#include #include #include #include @@ -76,32 +78,19 @@ void smm_region(uintptr_t *start, size_t *size) *size = smm_region_size(); } -int smm_subregion(int sub, uintptr_t *start, size_t *size) +void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t sub_base; - size_t sub_size; - const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + uintptr_t top_of_ram; - smm_region(&sub_base, &sub_size); - assert(sub_size > CONFIG_SMM_RESERVED_SIZE); + /* + * We need to make sure ramstage will be run cached. At this point exact + * location of ramstage in cbmem is not known. Instruct postcar to cache + * 16 megs under cbmem top which is a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t)cbmem_top(); + postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, + MTRR_TYPE_WRBACK); - switch (sub) { - case SMM_SUBREGION_HANDLER: - /* Handler starts at the base of TSEG. */ - sub_size -= cache_size; - break; - case SMM_SUBREGION_CACHE: - /* External cache is in the middle of TSEG. */ - sub_base += sub_size - cache_size; - sub_size = cache_size; - break; - default: - *start = 0; - *size = 0; - return -1; - } - - *start = sub_base; - *size = sub_size; - return 0; + /* Cache the TSEG region */ + postcar_enable_tseg_cache(pcf); } diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 53c51f488c..cb6ba11386 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include @@ -136,16 +136,8 @@ static void early_tco_init(void) outw(reg16, tco_base + TCO2_STS); } -asmlinkage void car_stage_entry(void) +void mainboard_romstage_entry(void) { - - struct postcar_frame pcf; - uintptr_t top_of_ram; - uintptr_t smm_base; - size_t smm_size; - - console_init(); - printk(BIOS_DEBUG, "FSP TempRamInit was successful...\n"); mainboard_config_gpios(); @@ -157,35 +149,6 @@ asmlinkage void car_stage_entry(void) #if CONFIG(DISPLAY_HOBS) display_fsp_smbios_memory_info_hob(); #endif - - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - /* - * We need to make sure ramstage will be run cached. At this point exact - * location of ramstage in cbmem is not known. Instruct postcar to cache - * 16 megs under cbmem top which is a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 16 * MiB, 16 * MiB, - MTRR_TYPE_WRBACK); - - /* Cache the memory-mapped boot media. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - if (CONFIG(HAVE_SMI_HANDLER)) { - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); - } - - run_postcar_phase(&pcf); } static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index 4d748b2a71..c292e4d79d 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -23,8 +23,8 @@ #include #include #include +#include #include -#include #include #include #include diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c index 2df6994fcd..d05e76bcf9 100644 --- a/src/soc/intel/denverton_ns/smm.c +++ b/src/soc/intel/denverton_ns/smm.c @@ -21,19 +21,14 @@ #include #include #include +#include #include #include #include #include -/* Save the gpio route register. The settings are committed from - * southcluster_smm_enable_smi(). */ -static uint32_t gpio_route; - -void southcluster_smm_save_gpio_route(uint32_t route) { gpio_route = route; } - -void southcluster_smm_clear_state(void) +void smm_southbridge_clear_state(void) { uint32_t smi_en; @@ -54,7 +49,7 @@ void southcluster_smm_clear_state(void) clear_pmc_status(); } -void southcluster_smm_enable_smi(void) +void smm_southbridge_enable_smi(void) { printk(BIOS_DEBUG, "Enabling SMIs.\n"); diff --git a/src/soc/intel/fsp_baytrail/chip.c b/src/soc/intel/fsp_baytrail/chip.c index 9e8627993c..3ca26add30 100644 --- a/src/soc/intel/fsp_baytrail/chip.c +++ b/src/soc/intel/fsp_baytrail/chip.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/fsp_baytrail/chip.h b/src/soc/intel/fsp_baytrail/chip.h index 156a08434c..b73aa14904 100644 --- a/src/soc/intel/fsp_baytrail/chip.h +++ b/src/soc/intel/fsp_baytrail/chip.h @@ -353,5 +353,4 @@ struct soc_intel_fsp_baytrail_config { }; -extern struct chip_operations soc_intel_fsp_baytrail_ops; #endif /* _FSP_BAYTRAIL_CHIP_H_ */ diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index 15dc851b96..787a41015a 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -17,8 +17,11 @@ #include #include #include +#include #include +#include #include +#include #include #include #include @@ -27,6 +30,7 @@ #include #include +#include #include #include #include @@ -82,13 +86,12 @@ static const struct cpu_driver driver __cpu_driver = { * MP and SMM loading initialization. */ -struct smm_relocation_attrs { - uint32_t smbase; - uint32_t smrr_base; - uint32_t smrr_mask; +struct smm_relocation_params { + msr_t smrr_base; + msr_t smrr_mask; }; -static struct smm_relocation_attrs relo_attrs; +static struct smm_relocation_params smm_reloc_params; static void pre_mp_init(void) { @@ -105,20 +108,32 @@ static int get_cpu_count(void) return pattrs->num_cpus; } -static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) +static void fill_in_relocation_params(struct smm_relocation_params *params) { + uintptr_t tseg_base; + size_t tseg_size; + /* All range registers are aligned to 4KiB */ - const uint32_t rmask = ~((1 << 12) - 1); + const u32 rmask = ~(4 * KiB - 1); - /* Initialize global tracking state. */ - relo_attrs.smbase = (uint32_t)smm_region_start(); - relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; - relo_attrs.smrr_mask = ~(smm_region_size() - 1) & rmask; - relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; + smm_region(&tseg_base, &tseg_size); + + /* SMRR has 32-bits of valid address aligned to 4KiB. */ + params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.hi = 0; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; + params->smrr_mask.hi = 0; +} + +static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size) +{ + printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); + + fill_in_relocation_params(&smm_reloc_params); + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - *perm_smbase = relo_attrs.smbase; - *perm_smsize = smm_region_size() - CONFIG_SMM_RESERVED_SIZE; *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); } @@ -133,16 +148,12 @@ static void get_microcode_info(const void **microcode, int *parallel) static void relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) { - msr_t smrr; + struct smm_relocation_params *relo_params = &smm_reloc_params; em64t100_smm_state_save_area_t *smm_state; /* Set up SMRR. */ - smrr.lo = relo_attrs.smrr_base; - smrr.hi = 0; - wrmsr(IA32_SMRR_PHYS_BASE, smrr); - smrr.lo = relo_attrs.smrr_mask; - smrr.hi = 0; - wrmsr(IA32_SMRR_PHYS_MASK, smrr); + wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); smm_state->smbase = staggered_smbase; @@ -151,7 +162,7 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase, static void enable_smis(void) { if (CONFIG(HAVE_SMI_HANDLER)) - southcluster_smm_enable_smi(); + smm_southbridge_enable_smi(); } static const struct mp_ops mp_ops = { @@ -159,7 +170,7 @@ static const struct mp_ops mp_ops = { .get_cpu_count = get_cpu_count, .get_smm_info = get_smm_info, .get_microcode_info = get_microcode_info, - .pre_mp_smm_init = southcluster_smm_clear_state, + .pre_mp_smm_init = smm_southbridge_clear_state, .relocation_handler = relocation_handler, .post_mp_init = enable_smis, }; diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index f11b206ed4..c0b0998d42 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -29,13 +29,6 @@ #include #include #include -#include - -#ifdef __PRE_RAM__ -#include -#endif - -#ifdef __PRE_RAM__ /* Copy the default UPD region and settings to a buffer for modification */ static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData) @@ -121,7 +114,7 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U else if ((config->PcdeMMCBootMode != EMMC_USE_DEFAULT)) UpdData->PcdeMMCBootMode = config->PcdeMMCBootMode - EMMC_DISABLED; - UpdData->PcdMrcInitTsegSize = smm_region_size() >> 20; + UpdData->PcdMrcInitTsegSize = CONFIG_SMM_TSEG_SIZE >> 20; printk(FSP_INFO_LEVEL, "GTT Size:\t\t%d MB\n", UpdData->PcdGttSize); printk(FSP_INFO_LEVEL, "Tseg Size:\t\t%d MB\n", UpdData->PcdMrcInitTsegSize); @@ -307,10 +300,9 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, ConfigureDefaultUpdData(fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); pFspInitParams->NvsBufferPtr = NULL; -#if CONFIG(ENABLE_MRC_CACHE) /* Find the fastboot cache that was saved in the ROM */ - pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); -#endif + if (CONFIG(ENABLE_MRC_CACHE)) + pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); if (prev_sleep_state == ACPI_S3) { /* S3 resume */ @@ -335,5 +327,3 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, return; } - -#endif /* __PRE_RAM__ */ diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c index 2409eaa541..3e2499accd 100644 --- a/src/soc/intel/fsp_baytrail/gpio.c +++ b/src/soc/intel/fsp_baytrail/gpio.c @@ -19,7 +19,6 @@ #include #include #include -#include /* * GPIO-to-Pad LUTs @@ -30,13 +29,11 @@ * PCU iLB GPIO CFIO_SCORE Address Map * PCU iLB GPIO CFIO_SSUS Address Map */ -#ifndef __PRE_RAM__ static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] = { 19, 18, 17, 20, 21, 22, 24, 25, /* [ 0: 7] */ 23, 16, 14, 15, 12, 26, 27, 1, /* [ 8:15] */ 4, 8, 11, 0, 3, 6, 10, 13, /* [16:23] */ 2, 5, 9 }; /* [24:26] */ -#endif static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] = { 85, 89, 93, 96, 99, 102, 98, 101, /* [ 0: 7] */ @@ -62,8 +59,6 @@ static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] = 52, 53, 59, 40 }; /* [40:43] */ -#ifndef __PRE_RAM__ - /* GPIO bank descriptions */ static const struct gpio_bank gpncore_bank = { .gpio_count = GPNCORE_COUNT, @@ -211,7 +206,7 @@ static void setup_gpio_route(const struct soc_gpio_map *sus, } } - southcluster_smm_save_gpio_route(route_reg); + smm_southcluster_save_gpio_route(route_reg); } static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS], @@ -254,7 +249,6 @@ struct soc_gpio_config* __weak mainboard_get_gpios(void) printk(BIOS_DEBUG, "Default/empty GPIO config\n"); return NULL; } -#endif /* #ifndef __PRE_RAM__ */ /** \brief returns the input / output value from an SCORE GPIO * diff --git a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h index 34831b13bb..3a2fcaa635 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h +++ b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h @@ -35,23 +35,24 @@ #else #define DEFAULT_RCBA 0xfed1c000 #endif -/* Everything below this line is ignored in the DSDT */ -#ifndef __ACPI__ /* Device 0:0.0 PCI configuration space (Host Bridge) */ +#define SKPAD 0xFC /* SOC types */ #define SOC_TYPE_BAYTRAIL 0x0F1C +/* Everything below this line is ignored in the DSDT */ +#ifndef __ACPI__ #ifndef __ASSEMBLER__ -static inline void barrier(void) { asm("" ::: "memory"); } +#include -#define SKPAD 0xFC +static inline void barrier(void) { asm("" ::: "memory"); } int bridge_silicon_revision(void); void rangeley_early_initialization(void); +void set_max_freq(void); -#ifndef __PRE_RAM__ /* soc.c */ int soc_silicon_revision(void); int soc_silicon_type(void); @@ -60,8 +61,7 @@ void soc_enable(struct device *dev); void report_platform_info(void); -#endif /* __PRE_RAM__ */ #endif /* __ASSEMBLER__ */ - #endif /* __ACPI__ */ + #endif diff --git a/src/soc/intel/fsp_baytrail/include/soc/gpio.h b/src/soc/intel/fsp_baytrail/include/soc/gpio.h index 3549894287..68c62350ce 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/gpio.h +++ b/src/soc/intel/fsp_baytrail/include/soc/gpio.h @@ -349,6 +349,7 @@ struct gpio_bank { const u8 gpio_f1_range_end; }; +void smm_southcluster_save_gpio_route(uint32_t route); void setup_soc_gpios(struct soc_gpio_config *config); /* This function is weak and can be overridden by a mainboard function. */ struct soc_gpio_config* mainboard_get_gpios(void); diff --git a/src/soc/intel/fsp_baytrail/include/soc/pmc.h b/src/soc/intel/fsp_baytrail/include/soc/pmc.h index 75daba540e..71c8e10446 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/pmc.h +++ b/src/soc/intel/fsp_baytrail/include/soc/pmc.h @@ -283,6 +283,8 @@ void enable_gpe(uint32_t mask); void disable_gpe(uint32_t mask); void disable_all_gpe(void); +uint32_t chipset_prev_sleep_state(uint32_t clear); + #if CONFIG(ELOG) void southcluster_log_state(void); #else diff --git a/src/soc/intel/fsp_baytrail/include/soc/ramstage.h b/src/soc/intel/fsp_baytrail/include/soc/ramstage.h index e8f81bb5c0..45fda9e937 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/ramstage.h +++ b/src/soc/intel/fsp_baytrail/include/soc/ramstage.h @@ -22,7 +22,6 @@ * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(void); void baytrail_init_cpus(struct device *dev); -void set_max_freq(void); void southcluster_enable_dev(struct device *dev); void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); diff --git a/src/soc/intel/fsp_baytrail/include/soc/romstage.h b/src/soc/intel/fsp_baytrail/include/soc/romstage.h index 5f0bd8d9c3..dce953993a 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/romstage.h +++ b/src/soc/intel/fsp_baytrail/include/soc/romstage.h @@ -17,31 +17,18 @@ #ifndef _BAYTRAIL_ROMSTAGE_H_ #define _BAYTRAIL_ROMSTAGE_H_ -#if !defined(__PRE_RAM__) -#error "Don't include romstage.h from a ramstage compilation unit!" -#endif - -void report_platform_info(void); - #include #include void main(FSP_INFO_HEADER *fsp_info_header); -uint32_t chipset_prev_sleep_state(uint32_t clear); #define NUM_ROMSTAGE_TS 4 void tco_disable(void); void punit_init(void); -void set_max_freq(void); void early_mainboard_romstage_entry(void); void late_mainboard_romstage_entry(void); void get_func_disables(uint32_t *mask, uint32_t *mask2); - -#if CONFIG(ENABLE_BUILTIN_COM1) void byt_config_com1_and_enable(void); -#else -static inline void byt_config_com1_and_enable(void) { } -#endif #endif /* _BAYTRAIL_ROMSTAGE_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/smm.h b/src/soc/intel/fsp_baytrail/include/soc/smm.h index c929572dbc..b6e24a8a0f 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/smm.h +++ b/src/soc/intel/fsp_baytrail/include/soc/smm.h @@ -17,24 +17,5 @@ #ifndef _BAYTRAIL_SMM_H_ #define _BAYTRAIL_SMM_H_ -/* There is a bug in the order of Kconfig includes in that arch/x86/Kconfig - * is included after chipset code. This causes the chipset's Kconfig to be - * clobbered by the arch/x86/Kconfig if they have the same name. */ -static inline int smm_region_size(void) -{ - /* Make it 8MiB by default. */ - if (CONFIG_SMM_TSEG_SIZE == 0) - return (8 << 20); - return CONFIG_SMM_TSEG_SIZE; -} - -uintptr_t smm_region_start(void); - -#if !defined(__PRE_RAM__) && !defined(__SMM___) -#include -void southcluster_smm_clear_state(void); -void southcluster_smm_enable_smi(void); -void southcluster_smm_save_gpio_route(uint32_t route); -#endif #endif /* _BAYTRAIL_SMM_H_ */ diff --git a/src/soc/intel/fsp_baytrail/memmap.c b/src/soc/intel/fsp_baytrail/memmap.c index 77ba406507..7fec7f9764 100644 --- a/src/soc/intel/fsp_baytrail/memmap.c +++ b/src/soc/intel/fsp_baytrail/memmap.c @@ -15,13 +15,19 @@ */ #include +#include #include -#include #include +#include -uintptr_t smm_region_start(void) +static uintptr_t smm_region_start(void) { - return (iosf_bunit_read(BUNIT_SMRRL) << 20); + return (iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20; +} + +static size_t smm_region_size(void) +{ + return CONFIG_SMM_TSEG_SIZE; } /** @brief get the top of usable low memory from the FSP's HOB list @@ -38,3 +44,9 @@ void *cbmem_top(void) { return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); } + +void smm_region(uintptr_t *start, size_t *size) +{ + *start = smm_region_start(); + *size = smm_region_size(); +} diff --git a/src/soc/intel/fsp_baytrail/romstage/report_platform.c b/src/soc/intel/fsp_baytrail/romstage/report_platform.c index 98f35f06d4..2b5dad7ab7 100644 --- a/src/soc/intel/fsp_baytrail/romstage/report_platform.c +++ b/src/soc/intel/fsp_baytrail/romstage/report_platform.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index 52f4dc9d63..f347591599 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -166,7 +167,8 @@ void main(FSP_INFO_HEADER *fsp_info_header) tco_disable(); post_code(0x42); - byt_config_com1_and_enable(); + if (CONFIG(ENABLE_BUILTIN_COM1)) + byt_config_com1_and_enable(); post_code(0x43); console_init(); @@ -255,9 +257,11 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) romstage_handoff_init(prev_sleep_state == ACPI_S3); - post_code(0x4f); + if (CONFIG(SMM_TSEG)) + smm_list_regions(); /* Load the ramstage. */ + post_code(0x4f); run_ramstage(); while (1); } diff --git a/src/soc/intel/fsp_baytrail/smihandler.c b/src/soc/intel/fsp_baytrail/smihandler.c index f2abd9975a..2a7376ad7d 100644 --- a/src/soc/intel/fsp_baytrail/smihandler.c +++ b/src/soc/intel/fsp_baytrail/smihandler.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/intel/fsp_baytrail/smm.c b/src/soc/intel/fsp_baytrail/smm.c index df55433314..0c40429aae 100644 --- a/src/soc/intel/fsp_baytrail/smm.c +++ b/src/soc/intel/fsp_baytrail/smm.c @@ -20,21 +20,22 @@ #include #include #include +#include #include +#include #include #include -#include /* Save the gpio route register. The settings are committed from - * southcluster_smm_enable_smi(). */ + * smm_southbridge_enable_smi(). */ static uint32_t gpio_route; -void southcluster_smm_save_gpio_route(uint32_t route) +void smm_southcluster_save_gpio_route(uint32_t route) { gpio_route = route; } -void southcluster_smm_clear_state(void) +void smm_southbridge_clear_state(void) { uint32_t smi_en; @@ -59,7 +60,7 @@ void southcluster_smm_clear_state(void) clear_pmc_status(); } -static void southcluster_smm_route_gpios(void) +static void smm_southcluster_route_gpios(void) { u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT); const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI; @@ -84,7 +85,7 @@ static void southcluster_smm_route_gpios(void) outl(alt_gpio_reg, alt_gpio_smi); } -void southcluster_smm_enable_smi(void) +void smm_southbridge_enable_smi(void) { printk(BIOS_DEBUG, "Enabling SMIs.\n"); @@ -93,7 +94,7 @@ void southcluster_smm_enable_smi(void) disable_gpe(PME_B0_EN); /* Set up the GPIO route. */ - southcluster_smm_route_gpios(); + smm_southcluster_route_gpios(); /* Enable SMI generation: * - on APMC writes (io 0xb2) diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 9375d19547..0b52ea9611 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -237,6 +237,8 @@ static ich9_spi_regs *spi_regs(void) return (void *)sbase; } +#define MENU_BYTES member_size(struct ich9_spi_regs, opmenu) + void spi_init(void) { ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); @@ -314,7 +316,7 @@ static int spi_setup_opcode(spi_transaction *trans) { ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t optypes; - uint8_t opmenu[cntlr->menubytes]; + uint8_t opmenu[MENU_BYTES]; trans->opcode = trans->out[0]; spi_use_out(trans, 1); @@ -335,13 +337,12 @@ static int spi_setup_opcode(spi_transaction *trans) return 0; read_reg(cntlr->opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < cntlr->menubytes; - opcode_index++) { + for (opcode_index = 0; opcode_index < ARRAY_SIZE(opmenu); opcode_index++) { if (opmenu[opcode_index] == trans->opcode) break; } - if (opcode_index == cntlr->menubytes) { + if (opcode_index == ARRAY_SIZE(opmenu)) { printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", trans->opcode); return -1; diff --git a/src/soc/intel/fsp_baytrail/tsc_freq.c b/src/soc/intel/fsp_baytrail/tsc_freq.c index f9c3014273..6605575691 100644 --- a/src/soc/intel/fsp_baytrail/tsc_freq.c +++ b/src/soc/intel/fsp_baytrail/tsc_freq.c @@ -17,6 +17,7 @@ #include #include #include +#include unsigned bus_freq_khz(void) { @@ -47,13 +48,6 @@ unsigned long tsc_freq_mhz(void) return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000; } -#if !defined(__SMM__) -#if !defined(__PRE_RAM__) -#include -#else -#include -#endif - void set_max_freq(void) { msr_t perf_ctl; @@ -76,5 +70,3 @@ void set_max_freq(void) wrmsr(IA32_PERF_CTL, perf_ctl); } - -#endif /* __SMM__ */ diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index 0af2aad228..9c91d7c5fc 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -26,6 +26,9 @@ config CPU_SPECIFIC_OPTIONS select TSC_CONSTANT_RATE select HAVE_FSP_BIN select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_IMC config VBOOT select VBOOT_STARTS_IN_ROMSTAGE @@ -70,15 +73,10 @@ config INTEGRATED_UART bool "Integrated UART ports" default y select DRIVERS_UART_8250IO - select DRIVERS_UART_8250IO_SKIP_INIT select CONSOLE_SERIAL help Use Broadwell-DE Integrated UART ports @3F8h and 2F8h. -config CONSOLE_CBMEM - bool "Send console output to a CBMEM buffer" - default n - config SERIRQ_CONTINUOUS_MODE bool default n @@ -86,6 +84,14 @@ config SERIRQ_CONTINUOUS_MODE If you set this option to y, the serial IRQ machine will be operated in continuous mode. +config DIMM_SPD_SIZE + int + default 512 + +config HPET_MIN_TICKS + hex + default 0x80 + ## Broadwell-DE Specific FSP Kconfig source src/soc/intel/fsp_broadwell_de/fsp/Kconfig diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc index 52f16d3ade..f0944da175 100644 --- a/src/soc/intel/fsp_broadwell_de/Makefile.inc +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -14,6 +14,9 @@ subdirs-y += ../../../lib/fsp romstage-y += gpio.c romstage-y += memmap.c romstage-y += tsc_freq.c +romstage-y += smbus-imc.c +romstage-y += ubox.c +romstage-y += vtd.c postcar-y += tsc_freq.c @@ -31,6 +34,7 @@ ramstage-y += smi.c ramstage-y += southcluster.c ramstage-y += tsc_freq.c ramstage-y += vtd.c +ramstage-y += ubox.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c index fef7773cf9..6b1d3f621b 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi.c +++ b/src/soc/intel/fsp_broadwell_de/acpi.c @@ -566,3 +566,14 @@ unsigned long acpi_madt_irq_overrides(unsigned long current) return current; } + +unsigned long southcluster_write_acpi_tables(struct device *device, + unsigned long current, + acpi_rsdp_t *rsdp) +{ + current = acpi_write_hpet(device, current, rsdp); + current = acpi_align_current(current); + + printk(BIOS_DEBUG, "current = %lx\n", current); + return current; +} diff --git a/src/soc/intel/fsp_broadwell_de/chip.c b/src/soc/intel/fsp_broadwell_de/chip.c index a0b3f7ca6c..a1978fa4e1 100644 --- a/src/soc/intel/fsp_broadwell_de/chip.c +++ b/src/soc/intel/fsp_broadwell_de/chip.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/fsp_broadwell_de/chip.h b/src/soc/intel/fsp_broadwell_de/chip.h index b7f59f7f12..bf2896238a 100644 --- a/src/soc/intel/fsp_broadwell_de/chip.h +++ b/src/soc/intel/fsp_broadwell_de/chip.h @@ -29,5 +29,4 @@ struct soc_intel_fsp_broadwell_de_config { typedef struct soc_intel_fsp_broadwell_de_config config_t; -extern struct chip_operations soc_intel_fsp_broadwell_de_ops; #endif /* _SOC_CHIP_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/cpu.c b/src/soc/intel/fsp_broadwell_de/cpu.c index 0b933c5db7..ac4dcc92dd 100644 --- a/src/soc/intel/fsp_broadwell_de/cpu.c +++ b/src/soc/intel/fsp_broadwell_de/cpu.c @@ -19,13 +19,18 @@ #include #include #include +#include #include #include #include #include #include +#include +#include +#include #include #include +#include #include #include @@ -93,16 +98,29 @@ static void set_max_ratio(void) wrmsr(IA32_PERF_CTL, perf_ctl); } +static void alt_smm_lock(void) +{ + struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); + uint16_t smi_lock; + + /* There is no register to lock SMRAM region on Broadwell-DE. + Use this function to lock the SMI control bits. */ + printk(BIOS_DEBUG, "Locking SMM.\n"); + smi_lock = pci_read_config16(dev, GEN_PMCON_1); + smi_lock |= (SMI_LOCK | SMI_LOCK_GP6 | SMI_LOCK_GP22); + pci_write_config16(dev, GEN_PMCON_1, smi_lock); +} + static void post_mp_init(void) { /* Set Max Ratio */ set_max_ratio(); /* Now that all APs have been relocated as well as the BSP let SMIs start flowing. */ - southbridge_smm_enable_smi(); + smm_southbridge_enable_smi(); /* Set SMI lock bits. */ - smm_lock(); + alt_smm_lock(); } static const struct mp_ops mp_ops = { diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h b/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h index da302520e0..44e17d0daf 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h @@ -27,5 +27,7 @@ uint16_t get_pmbase(void); unsigned long vtd_write_acpi_tables(struct device *const dev, unsigned long current, struct acpi_rsdp *const rsdp); - +unsigned long southcluster_write_acpi_tables(struct device *device, + unsigned long start, + acpi_rsdp_t *rsdp); #endif /* _SOC_ACPI_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h b/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h index edfeafc8a4..4167895729 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h @@ -18,6 +18,9 @@ #ifndef _SOC_BROADWELL_DE_H_ #define _SOC_BROADWELL_DE_H_ +uintptr_t sa_get_tseg_base(void); +size_t sa_get_tseg_size(void); + #define VTBAR_OFFSET 0x180 #define VTBAR_MASK 0xffffe000 #define VTBAR_ENABLED 0x01 diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/memory.h b/src/soc/intel/fsp_broadwell_de/include/soc/memory.h new file mode 100644 index 0000000000..3bdba2ef56 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/include/soc/memory.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_MEMORY_H_ +#define _SOC_MEMORY_H_ + +/* EDS vol 2, 9.2.24 */ +#define REG_MC_BIOS_REQ 0x98 +#define REG_MC_BIOS_REQ_FREQ_MSK ((1u << 6) - 1) +#define REG_MC_MULTIPLIER 133.33f + +#define IMC_MAX_CHANNELS 2 + +#define SPD_SLAVE_ADDR(chan, slot) (2 * chan + slot) + +void save_dimm_info(void); + +#endif diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h b/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h index 5fb8113980..ad8d80a71b 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h @@ -20,105 +20,130 @@ #include -#define BUS0 0 +#define BUS0 0 -#define SOC_DEV 0 -#define SOC_FUNC 0 -#define SOC_DEVID 0x2F00 -#define SOC_DEVID_ES2 0x6F00 -#define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV, SOC_FUNC) +#define SOC_DEV 0 +#define SOC_FUNC 0 +#define SOC_DEVID 0x2F00 +#define SOC_DEVID_ES2 0x6F00 +#define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV, SOC_FUNC) -#define VTD_DEV 5 -#define VTD_FUNC 0 -#define VTD_DEVID 0x6f28 -#define VTD_DEV_FUNC PCI_DEVFN(VTD_DEV, VTD_FUNC) +/* DMI2/PCIe link to PCH */ +#define PCIE_IIO_PORT_0_DEV 0x00 +#define PCIE_IIO_PORT_0_FUNC 0x00 -#define LPC_DEV 31 -#define LPC_FUNC 0 -#define LPC_DEVID 0x8C42 -#define LPC_DEVID_ES2 0x8C54 -#define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV, LPC_FUNC) +/* IOU2, x8 PCIe Gen3 port */ +#define PCIE_IIO_PORT_1_DEV 0x01 +#define PCIE_IIO_PORT_1A_FUNC 0x00 +#define PCIE_IIO_PORT_1B_FUNC 0x01 -#define SATA_DEV 31 -#define SATA_FUNC 2 -#define AHCI_DEVID 0x8C02 -#define SATA_DEV_FUNC PCI_DEVFN(SATA_DEV, SATA_FUNC) +/* IOU0: Internal IOSF bridge to 10 GbE and CBDMA */ +#define PCIE_IIO_PORT_2_DEV 0x02 +#define PCIE_IIO_PORT_2A_FUNC 0x00 +#define PCIE_IIO_PORT_2B_FUNC 0x01 +#define PCIE_IIO_PORT_2C_FUNC 0x02 +#define PCIE_IIO_PORT_2D_FUNC 0x03 -#define SMBUS_DEV 31 -#define SMBUS_FUNC 3 -#define SMBUS_DEVID 0x8C22 -#define SMBUS_DEV_FUNC PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) +/* IOU1: x16 PCIe Gen3 port */ +#define PCIE_IIO_PORT_3_DEV 0x03 +#define PCIE_IIO_PORT_3A_FUNC 0x00 +#define PCIE_IIO_PORT_3B_FUNC 0x01 +#define PCIE_IIO_PORT_3C_FUNC 0x02 +#define PCIE_IIO_PORT_3D_FUNC 0x03 -#define SATA2_DEV 31 -#define SATA2_FUNC 5 -#define SATA2_DEV_FUNC PCI_DEVFN(SATA2_DEV, SATA2_FUNC) +#define VTD_DEV 5 +#define VTD_FUNC 0 +#define VTD_DEVID 0x6f28 +#define VTD_DEV_FUNC PCI_DEVFN(VTD_DEV, VTD_FUNC) +#define VTD_PCI_DEV PCI_DEV(BUS0, VTD_DEV, VTD_FUNC) -#define EHCI1_DEV 29 -#define EHCI1_FUNC 0 -#define EHCI1_DEVID 0x8C26 -#define EHCI1_DEV_FUNC PCI_DEVFN(EHCI_DEV1, EHCI_FUNC1) +#define LPC_DEV 31 +#define LPC_FUNC 0 +#define LPC_DEVID 0x8C42 +#define LPC_DEVID_ES2 0x8C54 +#define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV, LPC_FUNC) -#define EHCI2_DEV 26 -#define EHCI2_FUNC 0 -#define EHCI2_DEVID 0x8C2D -#define EHCI2_DEV_FUNC PCI_DEVFN(EHCI_DEV2, EHCI_FUNC2) +#define SATA_DEV 31 +#define SATA_FUNC 2 +#define AHCI_DEVID 0x8C02 +#define SATA_DEV_FUNC PCI_DEVFN(SATA_DEV, SATA_FUNC) -#define XHCI_DEV 20 -#define XHCI_FUNC 0 -#define XHCI_DEVID 0x8C31 -#define XHCI_FUS_REG 0xE0 -#define XHCI_FUNC_DISABLE (1 << 0) -#define XHCI_USB2PR_REG 0xD0 -#define XHCI_DEV_FUNC PCI_DEVFN(XHCI_DEV, XHCI_FUNC) +#define SMBUS_DEV 31 +#define SMBUS_FUNC 3 +#define SMBUS_DEVID 0x8C22 +#define SMBUS_DEV_FUNC PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) -#define GBE_DEV 25 -#define GBE_FUNC 0 -#define GBE_DEVID 0x8C33 -#define GBE_DEV_FUNC PCI_DEVFN(GBE_DEV, GBE_FUNC) +#define SATA2_DEV 31 +#define SATA2_FUNC 5 +#define SATA2_DEV_FUNC PCI_DEVFN(SATA2_DEV, SATA2_FUNC) -#define ME_DEV 22 -#define ME_FUNC 0 -#define ME_DEVID 0x8C3A -#define ME_DEV_FUNC PCI_DEVFN(ME_DEV, ME_FUNC) +#define EHCI1_DEV 29 +#define EHCI1_FUNC 0 +#define EHCI1_DEVID 0x8C26 +#define EHCI1_DEV_FUNC PCI_DEVFN(EHCI_DEV1, EHCI_FUNC1) -#define HDA_DEV 27 -#define HDA_FUNC 0 -#define HDA_DEVID 0x8C20 -#define HDA_DEV_FUNC PCI_DEVFN(HDA_DEV, HDA_FUNC) +#define EHCI2_DEV 26 +#define EHCI2_FUNC 0 +#define EHCI2_DEVID 0x8C2D +#define EHCI2_DEV_FUNC PCI_DEVFN(EHCI_DEV2, EHCI_FUNC2) -#define PCIE_DEV 28 -#define PCIE_PORT1_DEV PCIE_DEV -#define PCIE_PORT1_FUNC 0 -#define PCIE_PORT1_DEVID 0x8C10 -#define PCIE_PORT2_DEV PCIE_DEV -#define PCIE_PORT2_FUNC 1 -#define PCIE_PORT2_DEVID 0x8C12 -#define PCIE_PORT3_DEV PCIE_DEV -#define PCIE_PORT3_FUNC 2 -#define PCIE_PORT3_DEVID 0x8C14 -#define PCIE_PORT4_DEV PCIE_DEV -#define PCIE_PORT4_FUNC 3 -#define PCIE_PORT4_DEVID 0x8C16 -#define PCIE_PORT5_DEV PCIE_DEV -#define PCIE_PORT5_FUNC 4 -#define PCIE_PORT5_DEVID 0x8C18 -#define PCIE_PORT6_DEV PCIE_DEV -#define PCIE_PORT6_FUNC 5 -#define PCIE_PORT6_DEVID 0x8C1A -#define PCIE_PORT7_DEV PCIE_DEV -#define PCIE_PORT7_FUNC 6 -#define PCIE_PORT7_DEVID 0x8C1C -#define PCIE_PORT8_DEV PCIE_DEV -#define PCIE_PORT8_FUNC 7 -#define PCIE_PORT8_DEVID 0x8C1E -#define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT1_FUNC) -#define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT2_FUNC) -#define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT3_FUNC) -#define PCIE_PORT4_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT4_FUNC) -#define PCIE_PORT5_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT5_FUNC) -#define PCIE_PORT6_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT6_FUNC) -#define PCIE_PORT7_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT7_FUNC) -#define PCIE_PORT8_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT8_FUNC) +#define XHCI_DEV 20 +#define XHCI_FUNC 0 +#define XHCI_DEVID 0x8C31 +#define XHCI_FUS_REG 0xE0 +#define XHCI_FUNC_DISABLE (1 << 0) +#define XHCI_USB2PR_REG 0xD0 +#define XHCI_DEV_FUNC PCI_DEVFN(XHCI_DEV, XHCI_FUNC) + +#define GBE_DEV 25 +#define GBE_FUNC 0 +#define GBE_DEVID 0x8C33 +#define GBE_DEV_FUNC PCI_DEVFN(GBE_DEV, GBE_FUNC) + +#define ME_DEV 22 +#define ME_FUNC 0 +#define ME_DEVID 0x8C3A +#define ME_DEV_FUNC PCI_DEVFN(ME_DEV, ME_FUNC) + +#define HDA_DEV 27 +#define HDA_FUNC 0 +#define HDA_DEVID 0x8C20 +#define HDA_DEV_FUNC PCI_DEVFN(HDA_DEV, HDA_FUNC) + +/* Ports from PCH block with adjustable burification settings */ +#define PCIE_DEV 28 +#define PCIE_PORT1_DEV PCIE_DEV +#define PCIE_PORT1_FUNC 0 +#define PCIE_PORT1_DEVID 0x8C10 +#define PCIE_PORT2_DEV PCIE_DEV +#define PCIE_PORT2_FUNC 1 +#define PCIE_PORT2_DEVID 0x8C12 +#define PCIE_PORT3_DEV PCIE_DEV +#define PCIE_PORT3_FUNC 2 +#define PCIE_PORT3_DEVID 0x8C14 +#define PCIE_PORT4_DEV PCIE_DEV +#define PCIE_PORT4_FUNC 3 +#define PCIE_PORT4_DEVID 0x8C16 +#define PCIE_PORT5_DEV PCIE_DEV +#define PCIE_PORT5_FUNC 4 +#define PCIE_PORT5_DEVID 0x8C18 +#define PCIE_PORT6_DEV PCIE_DEV +#define PCIE_PORT6_FUNC 5 +#define PCIE_PORT6_DEVID 0x8C1A +#define PCIE_PORT7_DEV PCIE_DEV +#define PCIE_PORT7_FUNC 6 +#define PCIE_PORT7_DEVID 0x8C1C +#define PCIE_PORT8_DEV PCIE_DEV +#define PCIE_PORT8_FUNC 7 +#define PCIE_PORT8_DEVID 0x8C1E +#define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT1_FUNC) +#define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT2_FUNC) +#define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT3_FUNC) +#define PCIE_PORT4_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT4_FUNC) +#define PCIE_PORT5_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT5_FUNC) +#define PCIE_PORT6_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT6_FUNC) +#define PCIE_PORT7_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT7_FUNC) +#define PCIE_PORT8_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT8_FUNC) /* The SMM device is located on bus 0xff (QPI) */ #define QPI_BUS 0xff @@ -126,4 +151,14 @@ #define SMM_FUNC 0x06 #define SMM_DEV_FUNC PCI_DEVFN(SMM_DEV, SMM_FUNC) +#define IMC_DEV0 19 +#define IMC_FUNC0 0 + +#define IMC_DEV PCI_DEV(QPI_BUS, IMC_DEV0, IMC_FUNC0) + +#define PCU1_DEV 30 +#define PCU1_FUNC 01 +#define UBOX_DEV 16 +#define UBOX_FUNC 7 + #endif /* _SOC_PCI_DEVS_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h b/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h index 63b7fbaff9..6ee160de28 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h @@ -17,10 +17,6 @@ #ifndef _SOC_ROMSTAGE_H_ #define _SOC_ROMSTAGE_H_ -#if !defined(__PRE_RAM__) -#error "Don't include romstage.h from a ramstage compilation unit!" -#endif - #include #include diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h index 72aa7fa4f2..867bf60a5e 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h @@ -20,17 +20,10 @@ #include #include -struct ied_header { - char signature[10]; - u32 size; - u8 reserved[34]; -} __packed; struct smm_relocation_params { - u32 smram_base; - u32 smram_size; - u32 ied_base; - u32 ied_size; + uintptr_t ied_base; + size_t ied_size; msr_t smrr_base; msr_t smrr_mask; msr_t prmrr_base; @@ -41,37 +34,5 @@ struct smm_relocation_params { int smm_save_state_in_msrs; }; -/* - * There is a bug in the order of Kconfig includes in that arch/x86/Kconfig - * is included after chipset code. This causes the chipset's Kconfig to be - * clobbered by the arch/x86/Kconfig if they have the same name. - */ -static inline int smm_region_size(void) -{ - /* Make it 8MiB by default. */ - if (CONFIG_SMM_TSEG_SIZE == 0) - return (8 << 20); - return CONFIG_SMM_TSEG_SIZE; -} - -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); -void smm_relocate(void); -void smm_lock(void); - -/* These helpers are for performing SMM relocation. */ -void southbridge_trigger_smi(void); -void southbridge_clear_smi_status(void); - -/* - * The initialization of the southbridge is split into 2 components. One is - * for clearing the state in the SMM registers. The other is for enabling - * SMIs. They are split so that other work between the 2 actions. - */ -void southbridge_smm_clear_state(void); -void southbridge_smm_enable_smi(void); #endif diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/ubox.h b/src/soc/intel/fsp_broadwell_de/include/soc/ubox.h new file mode 100644 index 0000000000..baaeac55cb --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/include/soc/ubox.h @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * As per "Intel Xeon Processor D-1500 Product Family" volume 2, + * "The UBOX [Processor Utility Box] is the piece of processor logic that deals with + * the non mainstream flows in the system. This includes transactions like the register + * accesses, interrupt flows, lock flows and events. In addition, the UBOX houses + * coordination for the performance architecture, and also houses scratchpad and + * semaphore registers." + * + * In other words, this is a one-die block that has all the useful magic registers. +*/ + +#ifndef _BROADWELL_UBOX_H_ +#define _BROADWELL_UBOX_H_ + +#include +#include +#include + +#define UBOX_UART_ENABLE 0xf8 +#define UBOX_UART_ENABLE_PORT0 (1u << 0) +#define UBOX_UART_ENABLE_PORT1 (1u << 1) + +#define UBOX_SC_RESET_STATUS 0xc8 +#define UBOX_SC_BYPASS (1u << 3) + +#define UBOX_DEVHIDE0 0xb0 + +void iio_hide(const uint8_t devno, const uint8_t funcno); + +#endif diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/vtd.h b/src/soc/intel/fsp_broadwell_de/include/soc/vtd.h new file mode 100644 index 0000000000..f1087d1997 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/include/soc/vtd.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _BROADWELL_VTD_H_ +#define _BROADWELL_VTD_H_ + +#include +#include + +#define VTD_CPUBUSNO 0x108 +#define VTD_CPUBUSNO_BUS0_MASK 0xff +#define VTD_CPUBUSNO_BUS0_SHIFT 0 +#define VTD_CPUBUSNO_BUS1_MASK 0xff +#define VTD_CPUBUSNO_BUS1_SHIFT 8 +#define VTD_CPUBUSNO_ISVALID (1u << 16) + +#define VTD_DFX1 0x804 +#define VTD_DFX1_RANGE_3F8_DISABLE (1u << 29) +#define VTD_DFX1_RANGE_2F8_DISABLE (1u << 30) + +uint8_t get_busno1(void); + +#endif diff --git a/src/soc/intel/fsp_broadwell_de/memmap.c b/src/soc/intel/fsp_broadwell_de/memmap.c index 75100948b9..cbd3cf7788 100644 --- a/src/soc/intel/fsp_broadwell_de/memmap.c +++ b/src/soc/intel/fsp_broadwell_de/memmap.c @@ -14,10 +14,47 @@ * GNU General Public License for more details. */ +#define __SIMPLE_DEVICE__ + #include +#include #include +#include +#include +#include void *cbmem_top(void) { return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); } + +/* + * Get TSEG base. + */ +uintptr_t sa_get_tseg_base(void) +{ + const pci_devfn_t dev = PCI_DEV(BUS0, VTD_DEV, VTD_FUNC); + + /* All regions concerned for have 1 MiB alignment. */ + return ALIGN_DOWN(pci_read_config32(dev, TSEG_BASE), 1 * MiB); +} + +size_t sa_get_tseg_size(void) +{ + const pci_devfn_t dev = PCI_DEV(BUS0, VTD_DEV, VTD_FUNC); + + /* All regions concerned for have 1 MiB alignment. */ + size_t ret = ALIGN_DOWN(pci_read_config32(dev, TSEG_LIMIT), 1 * MiB); + + /* Lower 20bit of TSEG_LIMIT are don't care, need to add 1MiB */ + ret += 1 * MiB; + + /* Subtract base to get the size */ + return ret - sa_get_tseg_base(); +} + +void smm_region(uintptr_t *start, size_t *size) +{ + *start = sa_get_tseg_base(); + *size = sa_get_tseg_size(); +} diff --git a/src/soc/intel/fsp_broadwell_de/romstage/Makefile.inc b/src/soc/intel/fsp_broadwell_de/romstage/Makefile.inc index 5ef9a9251d..5c332018e0 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/Makefile.inc +++ b/src/soc/intel/fsp_broadwell_de/romstage/Makefile.inc @@ -1,3 +1,4 @@ romstage-y += romstage.c +romstage-y += memory.c $(obj)/soc/intel/fsp_broadwell_de/romstage/romstage.romstage.o : $(obj)/build.h diff --git a/src/soc/intel/fsp_broadwell_de/romstage/memory.c b/src/soc/intel/fsp_broadwell_de/romstage/memory.c new file mode 100644 index 0000000000..afbf97bf57 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/romstage/memory.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +static uint32_t get_memory_dclk(void) +{ + uint32_t reg32 = + pci_mmio_read_config32(PCI_DEV(QPI_BUS, PCU1_DEV, PCU1_FUNC), REG_MC_BIOS_REQ); + return (reg32 & REG_MC_BIOS_REQ_FREQ_MSK) * REG_MC_MULTIPLIER; +} + +void save_dimm_info(void) +{ + int index = 0; + uint32_t dclk_mhz = 0; + + /* + * When talking to SPD chips through IMC slave offset of 0x50 is automagically added + * by hardware. Real-world slave numbers translate to: 0xa0, 0xa2, 0xa4, 0xa6. + */ + struct spd_block blk = {.addr_map = {SPD_SLAVE_ADDR(0, 0), SPD_SLAVE_ADDR(0, 1), + SPD_SLAVE_ADDR(1, 0), SPD_SLAVE_ADDR(1, 1)} }; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + + dclk_mhz = get_memory_dclk(); + + /* + * The platform is limited to 2 channels and max 2 dimms per channel. + * It doesn't look like DDR3 is supported so we assume memory is all DDR4. + */ + + for (int channel = 0; channel < IMC_MAX_CHANNELS; channel++) { + for (int slot = 0; slot < CONFIG_DIMM_MAX / IMC_MAX_CHANNELS; slot++) { + dimm_attr dimm = {0}; + u8 *spd_data = blk.spd_array[index]; + if (spd_decode_ddr4(&dimm, spd_data) == SPD_STATUS_OK) + spd_add_smbios17_ddr4(channel, slot, dclk_mhz, &dimm); + index++; + } + } +} diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 38cd9476c5..b0fad3f02b 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -29,9 +30,12 @@ #include #include #include +#include #include #include #include +#include +#include #include static void init_rtc(void) @@ -55,16 +59,57 @@ static void setup_gpio_io_address(void) } +static void enable_integrated_uart(uint8_t port) +{ + uint32_t ubox_uart_en = 0, dfx1 = 0; + pci_devfn_t ubox_dev; + + /* UBOX sits on CPUBUSNO(1) */ + ubox_dev = PCI_DEV(get_busno1(), UBOX_DEV, UBOX_FUNC); + uint32_t reset_sts = pci_mmio_read_config32(ubox_dev, UBOX_SC_RESET_STATUS); + + /* In case we are in bypass mode do nothing */ + if (reset_sts & UBOX_SC_BYPASS) + return; + + dfx1 = pci_mmio_read_config32(VTD_PCI_DEV, VTD_DFX1); + ubox_uart_en = pci_mmio_read_config32(ubox_dev, UBOX_UART_ENABLE); + + switch (port) { + case 0: + ubox_uart_en |= UBOX_UART_ENABLE_PORT0; + dfx1 |= VTD_DFX1_RANGE_3F8_DISABLE; + break; + case 1: + ubox_uart_en |= UBOX_UART_ENABLE_PORT1; + dfx1 |= VTD_DFX1_RANGE_2F8_DISABLE; + break; + default: + printk(BIOS_ERR, "incorrect port number\n"); + return; + } + + /* Disable decoding and enable the port we want */ + pci_mmio_write_config32(VTD_PCI_DEV, VTD_DFX1, dfx1); + pci_mmio_write_config32(ubox_dev, UBOX_UART_ENABLE, ubox_uart_en); +} + /* Entry from cache-as-ram.inc. */ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header) { post_code(0x40); + + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + if (!CONFIG(INTEGRATED_UART)) { /* Enable decoding of I/O locations for Super I/O devices */ pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_IO_DEC, 0x0010); pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_EN, 0x340f); + } else { + enable_integrated_uart(CONFIG_UART_FOR_CONSOLE); } /* Call into mainboard. */ @@ -76,6 +121,8 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header) init_rtc(); setup_gpio_io_address(); + timestamp_add_now(TS_BEFORE_INITRAM); + /* * Call early init to initialize memory and chipset. This function returns * to the romstage_main_continue function with a pointer to the HOB @@ -97,7 +144,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) void *cbmem_hob_ptr; post_code(0x4a); - timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_AFTER_INITRAM); printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", __func__, (u32) status, (u32) hob_list_ptr); @@ -120,6 +166,12 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) die("Could not allocate cbmem for HOB pointer"); *(u32 *)cbmem_hob_ptr = (u32)hob_list_ptr; + if (!CONFIG(FSP_MEMORY_DOWN)) + save_dimm_info(); + + if (CONFIG(SMM_TSEG)) + smm_list_regions(); + /* Load the ramstage. */ post_code(0x4e); run_ramstage(); diff --git a/src/soc/intel/fsp_broadwell_de/smbus-imc.c b/src/soc/intel/fsp_broadwell_de/smbus-imc.c new file mode 100644 index 0000000000..35e42da409 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/smbus-imc.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* read word, return value on success */ +uint16_t smbus_read_word(u32 smbus_dev, u8 addr, u8 offset) +{ + uint16_t res = 0; + + if (imc_smbus_spd_xfer(IMC_DEV, addr, offset, IMC_DEVICE_EEPROM, IMC_DATA_WORD, + IMC_CONTROLLER_ID0, IMC_READ, &res) + == 0) { + return res; + } + return 0; +} + +/* read byte, return value on success */ +uint8_t smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset) +{ + uint16_t res = 0; + + if (imc_smbus_spd_xfer(IMC_DEV, addr, offset, IMC_DEVICE_EEPROM, IMC_DATA_BYTE, + IMC_CONTROLLER_ID0, IMC_READ, &res) + == 0) { + return res; + } + return 0; +} + +/* write byte, return 0 on success, -1 otherwise */ +uint8_t smbus_write_byte(u32 smbus_dev, u8 addr, u8 offset, u8 value) +{ + if (imc_smbus_spd_xfer(IMC_DEV, addr, offset, IMC_DEVICE_WP_EEPROM, IMC_DATA_BYTE, + IMC_CONTROLLER_ID0, IMC_WRITE, &value) + == 0) { + return 0; + } + return -1; +} diff --git a/src/soc/intel/fsp_broadwell_de/smi.c b/src/soc/intel/fsp_broadwell_de/smi.c index 5411bcaed0..299ba531c5 100644 --- a/src/soc/intel/fsp_broadwell_de/smi.c +++ b/src/soc/intel/fsp_broadwell_de/smi.c @@ -16,12 +16,13 @@ */ #include +#include #include #include #include #include -void southbridge_smm_clear_state(void) +void smm_southbridge_clear_state(void) { u32 smi_en; @@ -41,7 +42,9 @@ void southbridge_smm_clear_state(void) clear_pm1_status(); } -void southbridge_smm_enable_smi(void) +static void southbridge_clear_smi_status(void); + +void smm_southbridge_enable_smi(void) { printk(BIOS_DEBUG, "Enabling SMIs.\n"); @@ -54,7 +57,7 @@ void southbridge_smm_enable_smi(void) enable_smi(EOS | GBL_SMI_EN); } -void southbridge_trigger_smi(void) +static void __unused southbridge_trigger_smi(void) { /* * There are several methods of raising a controlled SMI# via @@ -74,7 +77,7 @@ void southbridge_trigger_smi(void) outb(0x00, 0xb2); } -void southbridge_clear_smi_status(void) +static void southbridge_clear_smi_status(void) { /* Clear SMI status */ clear_smi_status(); diff --git a/src/soc/intel/fsp_broadwell_de/smihandler.c b/src/soc/intel/fsp_broadwell_de/smihandler.c index 854bd76a38..bb1bbf8409 100644 --- a/src/soc/intel/fsp_broadwell_de/smihandler.c +++ b/src/soc/intel/fsp_broadwell_de/smihandler.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/fsp_broadwell_de/smmrelocate.c b/src/soc/intel/fsp_broadwell_de/smmrelocate.c index 57ba432806..efd42e9607 100644 --- a/src/soc/intel/fsp_broadwell_de/smmrelocate.c +++ b/src/soc/intel/fsp_broadwell_de/smmrelocate.c @@ -23,9 +23,10 @@ #include #include #include +#include +#include #include #include -#include #include #include #include @@ -190,22 +191,10 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, write_prmrr(relo_params); } -static u32 northbridge_get_base_reg(pci_devfn_t dev, int reg) +static void fill_in_relocation_params(struct smm_relocation_params *params) { - u32 value; - - value = pci_read_config32(dev, reg); - /* Base registers are at 1MiB granularity. */ - value &= ~((1 << 20) - 1); - return value; -} - -static void fill_in_relocation_params(pci_devfn_t dev, - struct smm_relocation_params *params) -{ - u32 tseg_size; - u32 tseg_base; - u32 tseg_limit; + uintptr_t tseg_base; + size_t tseg_size; u32 prmrr_base; u32 prmrr_size; int phys_bits; @@ -225,25 +214,17 @@ static void fill_in_relocation_params(pci_devfn_t dev, * The result is that BASE[19:0] is effectively 00000h and LIMIT is * effectively FFFFFh. */ - tseg_base = northbridge_get_base_reg(dev, TSEG_BASE); - tseg_limit = northbridge_get_base_reg(dev, TSEG_LIMIT) + 1 * MiB; - tseg_size = tseg_limit - tseg_base; - params->smram_base = tseg_base; - params->smram_size = 4 << 20; - params->ied_base = tseg_base + params->smram_size; - params->ied_size = tseg_size - params->smram_size; - - /* Adjust available SMM handler memory size. */ - params->smram_size -= CONFIG_SMM_RESERVED_SIZE; + smm_region(&tseg_base, &tseg_size); /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | - MTRR_PHYS_MASK_VALID; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; params->smrr_mask.hi = 0; + smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); + /* The PRMRR is at IEDBASE + 2MiB */ prmrr_base = (params->ied_base + (2 << 20)) & rmask; prmrr_size = params->ied_size - (2 << 20); @@ -279,23 +260,21 @@ static void setup_ied_area(struct smm_relocation_params *params) void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - pci_devfn_t dev = PCI_DEV(BUS0, VTD_DEV, VTD_FUNC); - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - fill_in_relocation_params(dev, &smm_reloc_params); + fill_in_relocation_params(&smm_reloc_params); + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); setup_ied_area(&smm_reloc_params); - *perm_smbase = smm_reloc_params.smram_base; - *perm_smsize = smm_reloc_params.smram_size; *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); } void smm_initialize(void) { /* Clear the SMM state in the southbridge. */ - southbridge_smm_clear_state(); + smm_southbridge_clear_state(); /* Run the relocation handler for on the BSP to check and set up parallel SMM relocation. */ @@ -325,16 +304,3 @@ void smm_relocate(void) else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - pci_devfn_t dev = PCI_DEV(BUS0, LPC_DEV, LPC_FUNC); - uint16_t smi_lock; - - /* There is no register to lock SMRAM region on Broadwell-DE. - Use this function to lock the SMI control bits. */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - smi_lock = pci_read_config16(dev, GEN_PMCON_1); - smi_lock |= (SMI_LOCK | SMI_LOCK_GP6 | SMI_LOCK_GP22); - pci_write_config16(dev, GEN_PMCON_1, smi_lock); -} diff --git a/src/soc/intel/fsp_broadwell_de/southcluster.c b/src/soc/intel/fsp_broadwell_de/southcluster.c index 2f87cad9da..cb52e56e8a 100644 --- a/src/soc/intel/fsp_broadwell_de/southcluster.c +++ b/src/soc/intel/fsp_broadwell_de/southcluster.c @@ -32,7 +32,8 @@ #include #include #include - +#include +#include #include "chip.h" typedef struct soc_intel_fsp_broadwell_de_config config_t; @@ -250,12 +251,25 @@ void southcluster_enable_dev(struct device *dev) { uint32_t reg32; - if (!dev->enabled) { - int slot = PCI_SLOT(dev->path.pci.devfn); - int func = PCI_FUNC(dev->path.pci.devfn); - printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", - dev_path(dev), slot, func); + if (dev->enabled) + return; + const int slot = PCI_SLOT(dev->path.pci.devfn); + const int func = PCI_FUNC(dev->path.pci.devfn); + + switch (slot) { + case PCIE_IIO_PORT_0_DEV: + die("should not hide PCH link"); + case PCIE_IIO_PORT_1_DEV: /* fallthrough */ + case PCIE_IIO_PORT_2_DEV: /* fallthrough */ + case PCIE_IIO_PORT_3_DEV: /* fallthrough */ + printk(BIOS_DEBUG, "%s: Disabling IOU bridge %02x.%01x\n", dev_path(dev), slot, + func); + iio_hide(slot, func); + break; + default: + printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", dev_path(dev), slot, + func); /* Ensure memory, io, and bus master are all disabled */ reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); @@ -277,6 +291,7 @@ static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = NULL, + .write_acpi_tables = southcluster_write_acpi_tables, .init = sc_init, .enable = southcluster_enable_dev, .scan_bus = scan_lpc_bus, diff --git a/src/cpu/intel/haswell/tsc_freq.c b/src/soc/intel/fsp_broadwell_de/ubox.c similarity index 65% rename from src/cpu/intel/haswell/tsc_freq.c rename to src/soc/intel/fsp_broadwell_de/ubox.c index b05cae53e3..d7352ad667 100644 --- a/src/cpu/intel/haswell/tsc_freq.c +++ b/src/soc/intel/fsp_broadwell_de/ubox.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2019 Facebook Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,15 +13,15 @@ * GNU General Public License for more details. */ +#define __SIMPLE_DEVICE__ + #include -#include -#include -#include "cpu/intel/haswell/haswell.h" +#include -unsigned long tsc_freq_mhz(void) +void iio_hide(const uint8_t devno, const uint8_t funcno) { - msr_t platform_info; + pci_devfn_t ubox_dev; - platform_info = rdmsr(MSR_PLATFORM_INFO); - return HASWELL_BCLK * ((platform_info.lo >> 8) & 0xff); + ubox_dev = PCI_DEV(get_busno1(), UBOX_DEV, UBOX_FUNC); + pci_or_config32(ubox_dev, UBOX_DEVHIDE0 + funcno * 4, 1 << devno); } diff --git a/src/soc/intel/fsp_broadwell_de/vtd.c b/src/soc/intel/fsp_broadwell_de/vtd.c index 318927ab80..9e03e9ba6a 100644 --- a/src/soc/intel/fsp_broadwell_de/vtd.c +++ b/src/soc/intel/fsp_broadwell_de/vtd.c @@ -18,8 +18,10 @@ #include #include #include +#include #include +#if ENV_RAMSTAGE static void vtd_read_resources(struct device *dev) { @@ -44,3 +46,14 @@ static const struct pci_driver vtd_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = VTD_DEVID, }; + +#endif + +uint8_t get_busno1(void) +{ + uint32_t reg32; + + /* Figure out what bus number is assigned for CPUBUSNO(1) */ + reg32 = pci_mmio_read_config32(VTD_PCI_DEV, VTD_CPUBUSNO); + return ((reg32 >> VTD_CPUBUSNO_BUS1_SHIFT) & VTD_CPUBUSNO_BUS1_MASK); +} diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 7931018021..05fe423fac 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -32,8 +32,6 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 - select POSTCAR_CONSOLE - select POSTCAR_STAGE select REG_SCRIPT select SMP select SOC_AHCI_PORT_IMPLEMENTED_INVERT @@ -78,6 +76,15 @@ config DCACHE_BSP_STACK_SIZE The amount of anticipated stack usage in CAR by bootblock and other stages. +config FSP_TEMP_RAM_SIZE + hex + depends on FSP_USES_CB_STACK + default 0x10000 + help + The amount of anticipated heap usage in CAR by FSP. + Refer to Platform FSP integration guide document to know + the exact FSP requirement for Heap setup. + config IFD_CHIPSET string default "icl" diff --git a/src/soc/intel/icelake/bootblock/bootblock.c b/src/soc/intel/icelake/bootblock/bootblock.c index b76dc4ba37..db43e50ec8 100644 --- a/src/soc/intel/icelake/bootblock/bootblock.c +++ b/src/soc/intel/icelake/bootblock/bootblock.c @@ -23,7 +23,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { /* Call lib/bootblock.c main */ - bootblock_main_with_timestamp(base_timestamp, NULL, 0); + bootblock_main_with_basetime(base_timestamp); } void bootblock_soc_early_init(void) diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index cf92cd9c3f..8a65ccf5d3 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -19,12 +19,12 @@ #include #include #include +#include #include #include #include #include #include -#include #include #include #include diff --git a/src/soc/intel/icelake/include/soc/smm.h b/src/soc/intel/icelake/include/soc/smm.h index 2d4adf7e8c..43931679bf 100644 --- a/src/soc/intel/icelake/include/soc/smm.h +++ b/src/soc/intel/icelake/include/soc/smm.h @@ -21,21 +21,12 @@ #include #include -struct ied_header { - char signature[10]; - u32 size; - u8 reserved[34]; -} __packed; struct smm_relocation_params { uintptr_t ied_base; size_t ied_size; msr_t smrr_base; msr_t smrr_mask; - msr_t emrr_base; - msr_t emrr_mask; - msr_t uncore_emrr_base; - msr_t uncore_emrr_mask; /* * The smm_save_state_in_msrs field indicates if SMM save state * locations live in MSRs. This indicates to the CPUs how to adjust @@ -44,15 +35,4 @@ struct smm_relocation_params { int smm_save_state_in_msrs; }; -/* Mainboard handler for eSPI SMIs */ -void mainboard_smi_espi_handler(void); - -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); -void smm_relocate(void); -void smm_lock(void); - #endif diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 13eb947935..20c4e6fb7d 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -13,16 +13,18 @@ * GNU General Public License for more details. */ +#include #include #include #include +#include +#include #include #include #include #include #include #include -#include #include #include #include @@ -33,53 +35,6 @@ void smm_region(uintptr_t *start, size_t *size) *size = sa_get_tseg_size(); } -/* - * Subregions within SMM - * +-------------------------+ BGSM - * | IED | IED_REGION_SIZE - * +-------------------------+ - * | External Stage Cache | SMM_RESERVED_SIZE - * +-------------------------+ - * | code and data | - * | (TSEG) | - * +-------------------------+ TSEG - */ -int smm_subregion(int sub, uintptr_t *start, size_t *size) -{ - uintptr_t sub_base; - size_t sub_size; - const size_t ied_size = CONFIG_IED_REGION_SIZE; - const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - - smm_region(&sub_base, &sub_size); - - switch (sub) { - case SMM_SUBREGION_HANDLER: - /* Handler starts at the base of TSEG. */ - sub_size -= ied_size; - sub_size -= cache_size; - break; - case SMM_SUBREGION_CACHE: - /* External cache is in the middle of TSEG. */ - sub_base += sub_size - (ied_size + cache_size); - sub_size = cache_size; - break; - case SMM_SUBREGION_CHIPSET: - /* IED is at the top. */ - sub_base += sub_size - ied_size; - sub_size = ied_size; - break; - default: - *start = 0; - *size = 0; - return -1; - } - - *start = sub_base; - *size = sub_size; - return 0; -} - /* Calculate ME Stolen size */ static size_t get_imr_size(void) { @@ -309,3 +264,21 @@ void *cbmem_top(void) return (void *)(uintptr_t)ebda_cfg.tolum_base; } + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + /* + * We need to make sure ramstage will be run cached. At this + * point exact location of ramstage in cbmem is not known. + * Instruct postcar to cache 16 megs under cbmem top which is + * a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t) cbmem_top(); + printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); + top_of_ram -= 16*MiB; + postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); + + /* Cache the TSEG region */ + postcar_enable_tseg_cache(pcf); +} diff --git a/src/soc/intel/icelake/pmc.c b/src/soc/intel/icelake/pmc.c index 1889c4b82a..28fc01d029 100644 --- a/src/soc/intel/icelake/pmc.c +++ b/src/soc/intel/icelake/pmc.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/icelake/reset.c b/src/soc/intel/icelake/reset.c index 470b5f4fde..d83b3ee3fa 100644 --- a/src/soc/intel/icelake/reset.c +++ b/src/soc/intel/icelake/reset.c @@ -22,65 +22,10 @@ #include #include -/* Reset Request */ -#define MKHI_GLOBAL_RESET 0x0b -#define MKHI_STATUS_SUCCESS 0 - -#define GR_ORIGIN_BIOS_MEM_INIT 0x01 -#define GR_ORIGIN_BIOS_POST 0x02 -#define GR_ORIGIN_MEBX 0x03 - -#define GLOBAL_RST_TYPE 0x01 - -#define BIOS_HOST_ADD 0x00 -#define HECI_MKHI_ADD 0x07 - -static int send_heci_reset_message(void) -{ - int status; - struct reset_reply { - u8 group_id; - u8 command; - u8 reserved; - u8 result; - } __packed reply; - struct reset_message { - u8 group_id; - u8 cmd; - u8 reserved; - u8 result; - u8 req_origin; - u8 reset_type; - } __packed; - struct reset_message msg = { - .cmd = MKHI_GLOBAL_RESET, - .req_origin = GR_ORIGIN_BIOS_POST, - .reset_type = GLOBAL_RST_TYPE - }; - size_t reply_size; - - heci_reset(); - - status = heci_send(&msg, sizeof(msg), BIOS_HOST_ADD, HECI_MKHI_ADD); - if (status != 1) - return -1; - - reply_size = sizeof(reply); - memset(&reply, 0, reply_size); - if (!heci_receive(&reply, &reply_size)) - return -1; - if (reply.result != MKHI_STATUS_SUCCESS) { - printk(BIOS_DEBUG, "Returned Mkhi Status is not success!\n"); - return -1; - } - printk(BIOS_DEBUG, "Heci receive success!\n"); - return 0; -} - void do_global_reset(void) { /* Ask CSE to do the global reset */ - if (!send_heci_reset_message()) + if (!send_heci_reset_req_message(GLOBAL_RESET)) return; /* global reset if CSE fail to reset */ diff --git a/src/soc/intel/icelake/romstage/Makefile.inc b/src/soc/intel/icelake/romstage/Makefile.inc index 28e7eada55..baa4d46e55 100644 --- a/src/soc/intel/icelake/romstage/Makefile.inc +++ b/src/soc/intel/icelake/romstage/Makefile.inc @@ -14,5 +14,6 @@ # romstage-y += fsp_params.c +romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += systemagent.c diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 65e65cc80e..3d21a45e33 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -13,8 +13,7 @@ * GNU General Public License for more details. */ -#include -#include +#include #include #include #include @@ -29,7 +28,6 @@ #include #include #include -#include #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ @@ -111,42 +109,19 @@ static void save_dimm_info(void) printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } -asmlinkage void car_stage_entry(void) +void mainboard_romstage_entry(void) { bool s3wake; - struct postcar_frame pcf; - uintptr_t top_of_ram; struct chipset_power_state *ps = pmc_get_power_state(); - console_init(); - /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); /* initialize Heci interface */ heci_init(HECI1_BASE_ADDRESS); - timestamp_add_now(TS_START_ROMSTAGE); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); if (!s3wake) save_dimm_info(); - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - /* - * We need to make sure ramstage will be run cached. At this - * point exact location of ramstage in cbmem is not known. - * Instruct postcar to cache 16 megs under cbmem top which is - * a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); - - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - run_postcar_phase(&pcf); } diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index edda5400c0..65505c4b27 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -25,8 +25,9 @@ #include #include #include +#include +#include #include -#include #include #include #include @@ -164,7 +165,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, /* Make appropriate changes to the save state map. */ update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); - /* Write EMRR and SMRR MSRs based on indicated support. */ + /* Write SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); if (mtrr_cap.lo & SMRR_SUPPORTED) write_smrr(relo_params); @@ -174,18 +175,9 @@ static void fill_in_relocation_params(struct smm_relocation_params *params) { uintptr_t tseg_base; size_t tseg_size; - u32 emrr_base; - u32 emrr_size; - int phys_bits; /* All range registers are aligned to 4KiB */ const u32 rmask = ~(4 * KiB - 1); - /* - * Some of the range registers are dependent on the number of physical - * address bits supported. - */ - phys_bits = cpu_phys_address_size(); - smm_region(&tseg_base, &tseg_size); smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); @@ -194,27 +186,6 @@ static void fill_in_relocation_params(struct smm_relocation_params *params) params->smrr_base.hi = 0; params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; params->smrr_mask.hi = 0; - - /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */ - emrr_base = (params->ied_base + 2 * MiB) & rmask; - emrr_size = params->ied_size - 2 * MiB; - - /* - * EMRR has 46 bits of valid address aligned to 4KiB. It's dependent - * on the number of physical address bits supported. - */ - params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK; - params->emrr_base.hi = 0; - params->emrr_mask.lo = (~(emrr_size - 1) & rmask) - | MTRR_PHYS_MASK_VALID; - params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1; - - /* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */ - params->uncore_emrr_base.lo = emrr_base; - params->uncore_emrr_base.hi = 0; - params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) | - MTRR_PHYS_MASK_VALID; - params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1; } static void setup_ied_area(struct smm_relocation_params *params) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 4aa641cc70..4ed0377a7b 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -38,6 +38,7 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select UNCOMPRESSED_RAMSTAGE select USE_MARCH_586 + select NO_SMM ##### # Debug serial output diff --git a/src/soc/intel/quark/bootblock/bootblock.c b/src/soc/intel/quark/bootblock/bootblock.c index ff5b9b2a52..2b2fc29f59 100644 --- a/src/soc/intel/quark/bootblock/bootblock.c +++ b/src/soc/intel/quark/bootblock/bootblock.c @@ -82,7 +82,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) if (CONFIG(ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY)) light_sd_led(); - bootblock_main_with_timestamp(base_timestamp, NULL, 0); + bootblock_main_with_basetime(base_timestamp); } void bootblock_soc_early_init(void) diff --git a/src/soc/intel/quark/chip.h b/src/soc/intel/quark/chip.h index 25d734a7df..4e57273ffe 100644 --- a/src/soc/intel/quark/chip.h +++ b/src/soc/intel/quark/chip.h @@ -113,6 +113,4 @@ struct soc_intel_quark_config { uint8_t SmmTsegSize; /* SMM size in MiB */ }; -extern struct chip_operations soc_ops; - #endif diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index bb1a26437f..b09852bc3f 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -118,7 +118,6 @@ static int platform_i2c_read(uint32_t restart, uint8_t *rx_buffer, int length, int bytes_transferred; uint32_t cmd; int fifo_bytes; - uint8_t junk; I2C_REGS *regs; uint32_t status; @@ -129,7 +128,7 @@ static int platform_i2c_read(uint32_t restart, uint8_t *rx_buffer, int length, /* Empty the FIFO */ status = regs->ic_status; while (status & IC_STATUS_RFNE) { - junk = (uint8_t)regs->ic_data_cmd; + (void)regs->ic_data_cmd; status = regs->ic_status; } diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h index 56be795dcd..ada8899e9c 100644 --- a/src/soc/intel/quark/include/soc/ramstage.h +++ b/src/soc/intel/quark/include/soc/ramstage.h @@ -19,7 +19,6 @@ #include #include -#include #include #include "../../chip.h" diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index c7de080146..453b4bbc08 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -18,14 +18,9 @@ #ifndef _QUARK_ROMSTAGE_H_ #define _QUARK_ROMSTAGE_H_ -#if !defined(__PRE_RAM__) -#error "Don't include romstage.h from a ramstage compilation unit!" -#endif - #include #include -asmlinkage void car_stage_c_entry(void); void clear_smi_and_wake_events(void); void disable_rom_shadow(void); void *locate_rmu_file(size_t *rmu_file_len); diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index d67856cc74..b8b85063a8 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include +#include #include #include @@ -32,3 +34,28 @@ void *cbmem_top(void) /* Return the top of memory */ return (void *)top_of_memory; } + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + uintptr_t top_of_low_usable_memory; + + /* Locate the top of RAM */ + top_of_low_usable_memory = (uintptr_t) cbmem_top(); + top_of_ram = ALIGN(top_of_low_usable_memory, 16 * MiB); + + /* Cache postcar and ramstage */ + postcar_frame_add_mtrr(pcf, top_of_ram - (16 * MiB), 16 * MiB, + MTRR_TYPE_WRBACK); + + /* Cache RMU area */ + postcar_frame_add_mtrr(pcf, (uintptr_t) top_of_low_usable_memory, + 0x10000, MTRR_TYPE_WRTHROUGH); + + /* Cache ESRAM */ + postcar_frame_add_mtrr(pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK); + + pcf->skip_common_mtrr = 1; + /* Cache SPI flash - Write protect not supported */ + postcar_frame_add_romcache(pcf, MTRR_TYPE_WRTHROUGH); +} diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 742a4faba7..13963d4b23 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -14,7 +14,6 @@ # romstage-y += car.c -romstage-y += car_stage_entry.S ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) romstage-$(CONFIG_DISPLAY_UPD_DATA) += debug.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c @@ -23,5 +22,6 @@ romstage-y += mtrr.c romstage-y += pcie.c romstage-y += report_platform.c romstage-y += romstage.c +romstage-y += ../../../../cpu/intel/car/romstage.c postcar-y += mtrr.c diff --git a/src/soc/intel/quark/romstage/car_stage_entry.S b/src/soc/intel/quark/romstage/car_stage_entry.S deleted file mode 100644 index c9847eaac7..0000000000 --- a/src/soc/intel/quark/romstage/car_stage_entry.S +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000,2007 Ronald G. Minnich - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2015-2016 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Replacement for cache_as_ram.inc when using the C environment boot block. - */ - -#include -#include - - .section ".text" - .global car_stage_entry - -car_stage_entry: - - /* Enter the C code */ - call car_stage_c_entry - - /* The code should never reach this point */ - movb $0x69, %ah - jmp .Lhlt - -#---------------------------------------------------------------------------- -# -# Procedure: .Lhlt -# -# Input: ah - Upper 8-bits of POST code -# al - Lower 8-bits of POST code -# -# Description: -# Infinite loop displaying alternating POST code values -# -#---------------------------------------------------------------------------- - -#define FLASH_DELAY 0x1000 /* I/O delay between post codes on failure */ -#define POST_DELAY 0x50 - -.Lhlt: - xchg %al, %ah - mov $POST_DELAY, %dh -#if CONFIG(POST_IO) - outb %al, $CONFIG_POST_IO_PORT -#else - post_code(POST_DEAD_CODE) -#endif -.flash_setup: - movl $FLASH_DELAY, %ecx -.flash_delay: - outb %al, $0xED - loop .flash_delay -#if CONFIG(ENABLE_DEBUG_LED) - movl $SD_HOST_CTRL, %ebx - movb 0(%ebx), %dl - xorb $1, %dl - movb %dl, 0(%ebx) -#endif /* CONFIG_ENABLE_DEBUG_LED */ - decb %dh - jnz .flash_setup - jmp .Lhlt diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 20f2ad776b..a64fed4868 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include @@ -27,12 +27,9 @@ #include #include -asmlinkage void car_stage_c_entry(void) +void mainboard_romstage_entry(void) { - struct postcar_frame pcf; bool s3wake; - uintptr_t top_of_ram; - uintptr_t top_of_low_usable_memory; post_code(0x20); console_init(); @@ -61,29 +58,6 @@ asmlinkage void car_stage_c_entry(void) /* Initialize the PCIe bridges */ pcie_init(); - - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - /* Locate the top of RAM */ - top_of_low_usable_memory = (uintptr_t) cbmem_top(); - top_of_ram = ALIGN(top_of_low_usable_memory, 16 * MiB); - - /* Cache postcar and ramstage */ - postcar_frame_add_mtrr(&pcf, top_of_ram - (16 * MiB), 16 * MiB, - MTRR_TYPE_WRBACK); - - /* Cache RMU area */ - postcar_frame_add_mtrr(&pcf, (uintptr_t) top_of_low_usable_memory, - 0x10000, MTRR_TYPE_WRTHROUGH); - - /* Cache ESRAM */ - postcar_frame_add_mtrr(&pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK); - - /* Cache SPI flash - Write protect not supported */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRTHROUGH); - - run_postcar_phase(&pcf); } static struct chipset_power_state power_state; @@ -141,7 +115,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) aupd->StackBase); printk(BIOS_SPEW, "| |\n"); printk(BIOS_SPEW, "+-------------------+ 0x%p\n", - _car_relocatable_data_end); + _car_unallocated_start); printk(BIOS_SPEW, "| coreboot data |\n"); printk(BIOS_SPEW, "+-------------------+ 0x%p\n", _car_stack_end); diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index ca5968cf00..901e5f9b21 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -78,6 +78,11 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select UDELAY_TSC +config FSP_HYPERTHREADING + bool "Enable Hyper-Threading" + depends on MAINBOARD_USES_FSP2_0 + default y + config CPU_INTEL_NUM_FIT_ENTRIES int default 10 @@ -92,8 +97,6 @@ config USE_FSP2_0_DRIVER select PLATFORM_USES_FSP2_0 select UDK_2015_BINDING select INTEL_GMA_ADD_VBT if RUN_FSP_GOP - select POSTCAR_CONSOLE - select POSTCAR_STAGE config USE_FSP1_1_DRIVER def_bool y @@ -304,4 +307,8 @@ config IFD_CHIPSET string default "sklkbl" +config INTEL_TXT_BIOSACM_ALIGNMENT + hex + default 0x40000 # 256KB + endif diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 869ca7f1ee..c3757b0bd3 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include #include @@ -39,7 +38,6 @@ #include #include #include -#include #include #include #include @@ -350,25 +348,26 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_gpe1_blk.addrh = 0x0; } -static void generate_c_state_entries(int s0ix_enable, int max_cstate) +static void write_c_state_entries(acpi_cstate_t *map, const int *set, size_t max_c_state) { - - acpi_cstate_t map[max_cstate]; - int *set; - int i; - - if (s0ix_enable) - set = cstate_set_s0ix; - else - set = cstate_set_non_s0ix; - - for (i = 0; i < max_cstate; i++) { + for (size_t i = 0; i < max_c_state; i++) { memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); map[i].ctype = i + 1; } /* Generate C-state tables */ - acpigen_write_CST_package(map, ARRAY_SIZE(map)); + acpigen_write_CST_package(map, max_c_state); +} + +static void generate_c_state_entries(int s0ix_enable) +{ + if (s0ix_enable) { + acpi_cstate_t map[ARRAY_SIZE(cstate_set_s0ix)]; + write_c_state_entries(map, cstate_set_s0ix, ARRAY_SIZE(map)); + } else { + acpi_cstate_t map[ARRAY_SIZE(cstate_set_non_s0ix)]; + write_c_state_entries(map, cstate_set_non_s0ix, ARRAY_SIZE(map)); + } } static int calculate_power(int tdp, int p1_ratio, int ratio) @@ -506,12 +505,6 @@ void generate_cpu_entries(struct device *device) int numcpus = totalcores/cores_per_package; config_t *config = config_of_path(SA_DEVFN_ROOT); int is_s0ix_enable = config->s0ix_enable; - int max_c_state; - - if (is_s0ix_enable) - max_c_state = ARRAY_SIZE(cstate_set_s0ix); - else - max_c_state = ARRAY_SIZE(cstate_set_non_s0ix); printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package); @@ -534,8 +527,7 @@ void generate_cpu_entries(struct device *device) cpu_id*cores_per_package+core_id, pcontrol_blk, plen); /* Generate C-state tables */ - generate_c_state_entries(is_s0ix_enable, - max_c_state); + generate_c_state_entries(is_s0ix_enable); if (config->eist_enable) { /* Generate P-state tables */ @@ -581,30 +573,20 @@ static unsigned long acpi_fill_dmar(unsigned long current) acpi_dmar_rmrr_fixup(tmp, current); } - struct device *const p2sb_dev = pcidev_path_on_root(PCH_DEVFN_P2SB); const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; const bool vtvc0en = MCHBAR32(VTVC0BAR) & 1; /* General VTBAR has to be set and in 32-bit space. */ - if (p2sb_dev && vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { + if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { const unsigned long tmp = current; - /* P2SB may already be hidden. There's no clear rule, when. */ - const u8 p2sb_hidden = - pci_read_config8(p2sb_dev, PCH_P2SB_E0 + 1); - pci_write_config8(p2sb_dev, PCH_P2SB_E0 + 1, 0); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - const u16 ibdf = pci_read_config16(p2sb_dev, PCH_P2SB_IBDF); - const u16 hbdf = pci_read_config16(p2sb_dev, PCH_P2SB_HBDF); + current += acpi_create_dmar_ds_ioapic(current, 2, V_P2SB_IBDF_BUS, + V_P2SB_IBDF_DEV, V_P2SB_IBDF_FUN); - pci_write_config8(p2sb_dev, PCH_P2SB_E0 + 1, p2sb_hidden); - - current += acpi_create_dmar_drhd(current, - DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - current += acpi_create_dmar_ds_ioapic(current, - 2, ibdf >> 8, PCI_SLOT(ibdf), PCI_FUNC(ibdf)); - current += acpi_create_dmar_ds_msi_hpet(current, - 0, hbdf >> 8, PCI_SLOT(hbdf), PCI_FUNC(hbdf)); + current += acpi_create_dmar_ds_msi_hpet(current, 0, V_P2SB_HBDF_BUS, + V_P2SB_HBDF_DEV, V_P2SB_HBDF_FUN); acpi_dmar_drhd_fixup(tmp, current); } @@ -811,6 +793,10 @@ const char *soc_acpi_name(const struct device *dev) case PCH_DEVFN_PCIE10: return "RP10"; case PCH_DEVFN_PCIE11: return "RP11"; case PCH_DEVFN_PCIE12: return "RP12"; + case PCH_DEVFN_PCIE13: return "RP13"; + case PCH_DEVFN_PCIE14: return "RP14"; + case PCH_DEVFN_PCIE15: return "RP15"; + case PCH_DEVFN_PCIE16: return "RP16"; case PCH_DEVFN_UART0: return "UAR0"; case PCH_DEVFN_UART1: return "UAR1"; case PCH_DEVFN_GSPI0: return "SPI0"; diff --git a/src/soc/intel/skylake/acpi/pcie.asl b/src/soc/intel/skylake/acpi/pcie.asl index 84cb4370b6..b039f539ee 100644 --- a/src/soc/intel/skylake/acpi/pcie.asl +++ b/src/soc/intel/skylake/acpi/pcie.asl @@ -69,7 +69,7 @@ Method (IRQM, 1, Serialized) { Switch (ToInteger (Arg0)) { - Case (Package () { 1, 5, 9 }) { + Case (Package () { 1, 5, 9, 13 }) { If (PICM) { Return (IQAA) } Else { @@ -77,7 +77,7 @@ Method (IRQM, 1, Serialized) { } } - Case (Package () { 2, 6, 10 }) { + Case (Package () { 2, 6, 10, 14 }) { If (PICM) { Return (IQBA) } Else { @@ -85,7 +85,7 @@ Method (IRQM, 1, Serialized) { } } - Case (Package () { 3, 7, 11 }) { + Case (Package () { 3, 7, 11, 15 }) { If (PICM) { Return (IQCA) } Else { @@ -93,7 +93,7 @@ Method (IRQM, 1, Serialized) { } } - Case (Package () { 4, 8, 12 }) { + Case (Package () { 4, 8, 12, 16 }) { If (PICM) { Return (IQDA) } Else { @@ -314,3 +314,71 @@ Device (RP12) Return (IRQM (RPPN)) } } + +Device (RP13) +{ + Name (_ADR, 0x001D0004) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP14) +{ + Name (_ADR, 0x001D0005) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP15) +{ + Name (_ADR, 0x001D0006) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP16) +{ + Name (_ADR, 0x001D0007) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index 4358fba40f..e9ca2d8af2 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -22,7 +22,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { /* Call lib/bootblock.c main */ - bootblock_main_with_timestamp(base_timestamp, NULL, 0); + bootblock_main_with_basetime(base_timestamp); } void bootblock_soc_early_init(void) diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index a643bbedf2..fcfd874c8f 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -52,10 +52,9 @@ static struct { { PCI_DEVICE_ID_INTEL_SKL_ID_ULX, "Skylake-ULX" }, { PCI_DEVICE_ID_INTEL_SKL_ID_H, "Skylake-H" }, { PCI_DEVICE_ID_INTEL_SKL_ID_H_EM, "Skylake-H Embedded" }, - { PCI_DEVICE_ID_INTEL_SKL_ID_DT, "Skylake-DT" }, { PCI_DEVICE_ID_INTEL_SKL_ID_H_2, "Skylake-H (2 Core)" }, { PCI_DEVICE_ID_INTEL_SKL_ID_S_2, "Skylake-S (2 Core)" }, - { PCI_DEVICE_ID_INTEL_SKL_ID_S_4, "Skylake-S (4 Core)" }, + { PCI_DEVICE_ID_INTEL_SKL_ID_S_4, "Skylake-S (4 Core) / Skylake-DT" }, { PCI_DEVICE_ID_INTEL_KBL_ID_U, "Kabylake-U" }, { PCI_DEVICE_ID_INTEL_KBL_U_R, "Kabylake-R ULT"}, { PCI_DEVICE_ID_INTEL_KBL_ID_Y, "Kabylake-Y" }, @@ -87,6 +86,19 @@ static struct { { PCI_DEVICE_ID_INTEL_SPT_H_HM175, "Skylake PCH-H HM175" }, { PCI_DEVICE_ID_INTEL_SPT_H_QM175, "Skylake PCH-H QM175" }, { PCI_DEVICE_ID_INTEL_SPT_H_CM238, "Skylake PCH-H CM238" }, + { PCI_DEVICE_ID_INTEL_LWB_C621, "Lewisburg PCH C621" }, + { PCI_DEVICE_ID_INTEL_LWB_C622, "Lewisburg PCH C622" }, + { PCI_DEVICE_ID_INTEL_LWB_C624, "Lewisburg PCH C624" }, + { PCI_DEVICE_ID_INTEL_LWB_C625, "Lewisburg PCH C625" }, + { PCI_DEVICE_ID_INTEL_LWB_C626, "Lewisburg PCH C626" }, + { PCI_DEVICE_ID_INTEL_LWB_C627, "Lewisburg PCH C627" }, + { PCI_DEVICE_ID_INTEL_LWB_C628, "Lewisburg PCH C628" }, + { PCI_DEVICE_ID_INTEL_LWB_C629, "Lewisburg PCH C629" }, + { PCI_DEVICE_ID_INTEL_LWB_C624_SUPER, "Lewisburg PCH C624 Super SKU" }, + { PCI_DEVICE_ID_INTEL_LWB_C627_SUPER_1, "Lewisburg PCH C627 Super SKU" }, + { PCI_DEVICE_ID_INTEL_LWB_C621_SUPER, "Lewisburg PCH C621 Super SKU" }, + { PCI_DEVICE_ID_INTEL_LWB_C627_SUPER_2, "Lewisburg PCH C627 Super SKU" }, + { PCI_DEVICE_ID_INTEL_LWB_C628_SUPER, "Lewisburg PCH C628 Super SKU" }, { PCI_DEVICE_ID_INTEL_KBP_H_Q270, "Kabylake-H Q270" }, { PCI_DEVICE_ID_INTEL_KBP_H_H270, "Kabylake-H H270" }, { PCI_DEVICE_ID_INTEL_KBP_H_Z270, "Kabylake-H Z270" }, diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index a7d58720a5..212c24467e 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -153,10 +153,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) /* Enable ISH if device is on */ dev = pcidev_path_on_root(PCH_DEVFN_ISH); - if (dev) - params->IshEnable = dev->enabled; - else - params->IshEnable = 0; + params->IshEnable = dev ? dev->enabled : 0; params->EnableAzalia = config->EnableAzalia; params->IoBufferOwnership = config->IoBufferOwnership; @@ -210,23 +207,24 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) * do the changes and then lock it back in coreboot * */ - if (config->HeciEnabled == 0) - params->PsfUnlock = 1; - else - params->PsfUnlock = 0; + params->PsfUnlock = !config->HeciEnabled; for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) fill_vr_domain_config(params, i, &config->domain_vr_config[i]); /* Show SPI controller if enabled in devicetree.cb */ dev = pcidev_path_on_root(PCH_DEVFN_SPI); - params->ShowSpiController = dev->enabled; + params->ShowSpiController = dev ? dev->enabled : 0; /* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); - if (!xdci_can_enable()) - dev->enabled = 0; - params->XdciEnable = dev->enabled; + if (dev) { + if (!xdci_can_enable()) + dev->enabled = 0; + params->XdciEnable = dev->enabled; + } else { + params->XdciEnable = 0; + } params->SendVrMbxCmd = config->SendVrMbxCmd; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 6c105cea8c..fee14d8d7e 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -200,6 +200,8 @@ struct soc_intel_skylake_config { u8 SataSalpSupport; u8 SataPortsEnable[8]; u8 SataPortsDevSlp[8]; + u8 SataPortsSpinUp[8]; + u8 SataPortsHotPlug[8]; u8 SataSpeedLimit; /* Audio related */ @@ -587,10 +589,11 @@ struct soc_intel_skylake_config { /* Enable/Disable Sata power optimization */ u8 SataPwrOptEnable; + + /* Enable/Disable Sata test mode */ + u8 SataTestMode; }; typedef struct soc_intel_skylake_config config_t; -extern struct chip_operations soc_ops; - #endif diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 064f71e2f2..d1d7d6f50a 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -283,6 +283,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) sizeof(params->SataPortsEnable)); memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, sizeof(params->SataPortsDevSlp)); + memcpy(params->SataPortsHotPlug, config->SataPortsHotPlug, + sizeof(params->SataPortsHotPlug)); + memcpy(params->SataPortsSpinUp, config->SataPortsSpinUp, + sizeof(params->SataPortsSpinUp)); memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, sizeof(params->PcieRpClkReqSupport)); memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, @@ -354,10 +358,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* If ISH is enabled, enable ISH elements */ dev = pcidev_path_on_root(PCH_DEVFN_ISH); - if (dev) - params->PchIshEnable = dev->enabled; - else - params->PchIshEnable = 0; + params->PchIshEnable = dev ? dev->enabled : 0; params->PchHdaEnable = config->EnableAzalia; params->PchHdaIoBufferOwnership = config->IoBufferOwnership; @@ -372,6 +373,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; tconfig->PowerLimit4 = config->PowerLimit4; + tconfig->SataTestMode = config->SataTestMode; /* * To disable HECI, the Psf needs to be left unlocked * by FSP till end of post sequence. Based on the devicetree @@ -433,13 +435,21 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Show SPI controller if enabled in devicetree.cb */ dev = pcidev_path_on_root(PCH_DEVFN_SPI); - params->ShowSpiController = dev->enabled; + params->ShowSpiController = dev ? dev->enabled : 0; /* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); - if (!xdci_can_enable()) - dev->enabled = 0; - params->XdciEnable = dev->enabled; + if (dev) { + if (!xdci_can_enable()) + dev->enabled = 0; + params->XdciEnable = dev->enabled; + } else { + params->XdciEnable = 0; + } + + /* Enable or disable Gaussian Mixture Model in devicetree */ + dev = pcidev_path_on_root(SA_DEVFN_GMM); + params->GmmEnable = dev ? dev->enabled : 0; /* * Send VR specific mailbox commands: @@ -485,9 +495,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) tconfig->VtdDisable = 0; params->PchIoApicBdfValid = 1; - params->PchIoApicBusNumber = 250; - params->PchIoApicDeviceNumber = 31; - params->PchIoApicFunctionNumber = 0; + params->PchIoApicBusNumber = V_P2SB_IBDF_BUS; + params->PchIoApicDeviceNumber = V_P2SB_IBDF_DEV; + params->PchIoApicFunctionNumber = V_P2SB_IBDF_FUN; } soc_irq_settings(params); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index eecb0048b9..0d49d28d3d 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -31,11 +31,11 @@ #include #include #include +#include #include #include #include #include -#include #include #include #include @@ -491,11 +491,11 @@ static void post_mp_init(void) if (CONFIG(HAVE_SMI_HANDLER)) smm_lock(); - ret |= mp_run_on_all_cpus(vmx_configure, NULL, 2 * USECS_PER_MSEC); + ret |= mp_run_on_all_cpus(vmx_configure, NULL); - ret |= mp_run_on_all_cpus(sgx_configure, NULL, 14 * USECS_PER_MSEC); + ret |= mp_run_on_all_cpus(sgx_configure, NULL); - ret |= mp_run_on_all_cpus(fc_lock_configure, NULL, 2 * USECS_PER_MSEC); + ret |= mp_run_on_all_cpus(fc_lock_configure, NULL); if (ret) printk(BIOS_CRIT, "CRITICAL ERROR: MP post init failed\n"); diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 8afaf4d344..0d6f7370a5 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -72,6 +73,8 @@ static void pch_finalize_script(struct device *dev) config_t *config; u8 reg8; + tco_lockdown(); + /* Display me status before we hide it */ intel_me_status(); diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h index 5a9acd51f3..c1fdc8154a 100644 --- a/src/soc/intel/skylake/include/soc/me.h +++ b/src/soc/intel/skylake/include/soc/me.h @@ -21,7 +21,6 @@ /* * Management Engine PCI registers */ -#define PCI_ME_HFSTS1 0x40 #define ME_HFS_CWS_RESET 0 #define ME_HFS_CWS_INIT 1 #define ME_HFS_CWS_REC 2 @@ -48,30 +47,6 @@ #define ME_HFS_POWER_SOURCE_AC 1 #define ME_HFS_POWER_SOURCE_DC 2 -union me_hfs { - u32 data; - struct { - u32 working_state: 4; - u32 mfg_mode: 1; - u32 fpt_bad: 1; - u32 operation_state: 3; - u32 fw_init_complete: 1; - u32 ft_bup_ld_flr: 1; - u32 update_in_progress: 1; - u32 error_code: 4; - u32 operation_mode: 4; - u32 reset_count: 4; - u32 boot_options_present: 1; - u32 reserved1: 1; - u32 bist_test_state: 1; - u32 bist_reset_request: 1; - u32 current_power_source: 2; - u32 d3_support_valid: 1; - u32 d0i3_support_valid: 1; - } __packed fields; -}; - -#define PCI_ME_HFSTS2 0x48 /* Infrastructure Progress Values */ #define ME_HFS2_PHASE_ROM 0 #define ME_HFS2_PHASE_UKERNEL 2 @@ -169,7 +144,6 @@ union me_hfs2 { } __packed fields; }; -#define PCI_ME_HFSTS3 0x60 #define ME_HFS3_FW_SKU_CONSUMER 0x2 #define ME_HFS3_FW_SKU_CORPORATE 0x3 @@ -186,9 +160,6 @@ union me_hfs3 { } __packed fields; }; -#define PCI_ME_HFSTS4 0x64 -#define PCI_ME_HFSTS5 0x68 -#define PCI_ME_HFSTS6 0x6c #define ME_HFS6_FPF_NOT_COMMITTED 0x0 #define ME_HFS6_FPF_ERROR 0x2 @@ -202,20 +173,8 @@ union me_hfs6 { #define MKHI_GEN_GROUP_ID 0xff -/* Reset Request */ -#define MKHI_GLOBAL_RESET 0x0b - #define MKHI_GET_FW_VERSION 0x02 -#define GR_ORIGIN_BIOS_MEM_INIT 0x01 -#define GR_ORIGIN_BIOS_POST 0x02 -#define GR_ORIGIN_MEBX 0x03 - -#define GLOBAL_RST_TYPE 0x01 - -#define BIOS_HOST_ADD 0x00 -#define HECI_MKHI_ADD 0x07 - void intel_me_status(void); int send_global_reset(void); diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 0e8bb6841f..ff6b8c1c23 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -42,6 +42,9 @@ #define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) #define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) +#define SA_DEV_SLOT_GMM 0x08 +#define SA_DEVFN_GMM PCI_DEVFN(SA_DEV_SLOT_GMM, 0) +#define SA_DEV_GMM PCI_DEV(0, SA_DEV_SLOT_GMM, 0) /* PCH Devices */ #define PCH_DEV_SLOT_ISH 0x13 diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 9c15db2915..88ce9e35c3 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -23,21 +23,12 @@ #include #include -struct ied_header { - char signature[10]; - u32 size; - u8 reserved[34]; -} __packed; struct smm_relocation_params { uintptr_t ied_base; size_t ied_size; msr_t smrr_base; msr_t smrr_mask; - msr_t emrr_base; - msr_t emrr_mask; - msr_t uncore_emrr_base; - msr_t uncore_emrr_mask; /* * The smm_save_state_in_msrs field indicates if SMM save state * locations live in MSRs. This indicates to the CPUs how to adjust @@ -46,12 +37,4 @@ struct smm_relocation_params { int smm_save_state_in_msrs; }; -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); -void smm_relocate(void); -void smm_lock(void); - #endif diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h index d7dec65f58..565c885893 100644 --- a/src/soc/intel/skylake/include/soc/systemagent.h +++ b/src/soc/intel/skylake/include/soc/systemagent.h @@ -61,4 +61,14 @@ static const struct sa_mmio_descriptor soc_vtvc0_mmio_descriptor = { VTVC0_BASE_SIZE, "VTVC0BAR" }; + +/* Hardcoded default values for PCI Bus:Dev.Fun for IOAPIC and HPET */ +#define V_P2SB_IBDF_BUS 250 +#define V_P2SB_IBDF_DEV 31 +#define V_P2SB_IBDF_FUN 0 + +#define V_P2SB_HBDF_BUS 250 +#define V_P2SB_HBDF_DEV 15 +#define V_P2SB_HBDF_FUN 0 + #endif diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h index 465e248700..aebbbdff4a 100644 --- a/src/soc/intel/skylake/include/soc/vr_config.h +++ b/src/soc/intel/skylake/include/soc/vr_config.h @@ -68,6 +68,7 @@ struct vr_config { }; #define VR_CFG_AMP(i) ((i) * 4) +#define VR_CFG_MOHMS(i) (uint16_t)((i) * 100) #if CONFIG(PLATFORM_USES_FSP1_1) /* VrConfig Settings for 5 domains diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index f7aa584f37..5a378a2954 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -26,10 +26,6 @@ #include #include -static inline u32 me_read_config32(int offset) -{ - return pci_read_config32(PCH_DEV_CSE, offset); -} /* HFSTS1[3:0] Current Working State Values */ static const char *const me_cws_values[] = { @@ -204,14 +200,6 @@ static const char *const me_progress_bup_values[] = { static void print_me_version(void *unused) { - struct mkhi_hdr { - uint8_t group_id; - uint8_t command:7; - uint8_t is_resp:1; - uint8_t rsvd; - uint8_t result; - } __packed; - struct version { uint16_t minor; uint16_t major; @@ -233,7 +221,7 @@ static void print_me_version(void *unused) struct fw_ver_resp resp; size_t resp_size = sizeof(resp); - union me_hfs hfs; + union me_hfsts1 hfs1; /* * Print ME version only if UART debugging is enabled. Else, it takes ~1 @@ -242,14 +230,17 @@ static void print_me_version(void *unused) if (!CONFIG(CONSOLE_SERIAL)) return; - hfs.data = me_read_config32(PCI_ME_HFSTS1); + if (!is_cse_enabled()) + return; + + hfs1.data = me_read_config32(PCI_ME_HFSTS1); /* * This command can be run only if: * - Working state is normal and * - Operation mode is normal. */ - if ((hfs.fields.working_state != ME_HFS_CWS_NORMAL) || - (hfs.fields.operation_mode != ME_HFS_MODE_NORMAL)) + if ((hfs1.fields.working_state != ME_HFS_CWS_NORMAL) || + (hfs1.fields.operation_mode != ME_HFS_MODE_NORMAL)) goto failed; /* @@ -258,8 +249,8 @@ static void print_me_version(void *unused) */ heci_reset(); - if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADD, - HECI_MKHI_ADD)) + if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADDR, + HECI_MKHI_ADDR)) goto failed; if (!heci_receive(&resp, &resp_size)) @@ -283,18 +274,21 @@ BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_version, NULL); void intel_me_status(void) { - union me_hfs hfs; + union me_hfsts1 hfs1; union me_hfs2 hfs2; union me_hfs3 hfs3; union me_hfs6 hfs6; - hfs.data = me_read_config32(PCI_ME_HFSTS1); + if (!is_cse_enabled()) + return; + + hfs1.data = me_read_config32(PCI_ME_HFSTS1); hfs2.data = me_read_config32(PCI_ME_HFSTS2); hfs3.data = me_read_config32(PCI_ME_HFSTS3); hfs6.data = me_read_config32(PCI_ME_HFSTS6); printk(BIOS_DEBUG, "ME: Host Firmware Status Register 1 : 0x%08X\n", - hfs.data); + hfs1.data); printk(BIOS_DEBUG, "ME: Host Firmware Status Register 2 : 0x%08X\n", hfs2.data); printk(BIOS_DEBUG, "ME: Host Firmware Status Register 3 : 0x%08X\n", @@ -307,21 +301,21 @@ void intel_me_status(void) hfs6.data); /* Check Current States */ printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", - hfs.fields.fpt_bad ? "BAD" : "OK"); + hfs1.fields.fpt_bad ? "BAD" : "OK"); printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", - hfs.fields.ft_bup_ld_flr ? "YES" : "NO"); + hfs1.fields.ft_bup_ld_flr ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", - hfs.fields.fw_init_complete ? "YES" : "NO"); + hfs1.fields.fw_init_complete ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", - hfs.fields.mfg_mode ? "YES" : "NO"); + hfs1.fields.mfg_mode ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", - hfs.fields.boot_options_present ? "YES" : "NO"); + hfs1.fields.boot_options_present ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", - hfs.fields.update_in_progress ? "YES" : "NO"); + hfs1.fields.update_in_progress ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: D3 Support : %s\n", - hfs.fields.d3_support_valid ? "YES" : "NO"); + hfs1.fields.d3_support_valid ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: D0i3 Support : %s\n", - hfs.fields.d0i3_support_valid ? "YES" : "NO"); + hfs1.fields.d0i3_support_valid ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: Low Power State Enabled : %s\n", hfs2.fields.low_power_state ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: CPU Replaced : %s\n", @@ -329,13 +323,13 @@ void intel_me_status(void) printk(BIOS_DEBUG, "ME: CPU Replacement Valid : %s\n", hfs2.fields.cpu_replaced_valid ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: Current Working State : %s\n", - me_cws_values[hfs.fields.working_state]); + me_cws_values[hfs1.fields.working_state]); printk(BIOS_DEBUG, "ME: Current Operation State : %s\n", - me_opstate_values[hfs.fields.operation_state]); + me_opstate_values[hfs1.fields.operation_state]); printk(BIOS_DEBUG, "ME: Current Operation Mode : %s\n", - me_opmode_values[hfs.fields.operation_mode]); + me_opmode_values[hfs1.fields.operation_mode]); printk(BIOS_DEBUG, "ME: Error Code : %s\n", - me_error_values[hfs.fields.error_code]); + me_error_values[hfs1.fields.error_code]); printk(BIOS_DEBUG, "ME: Progress Phase : %s\n", me_progress_values[hfs2.fields.progress_code]); printk(BIOS_DEBUG, "ME: Power Management Event : %s\n", @@ -435,62 +429,21 @@ void intel_me_status(void) } } -static int send_heci_reset_message(void) -{ - int status; - struct reset_reply { - u8 group_id; - u8 command; - u8 reserved; - u8 result; - } __packed reply; - struct reset_message { - u8 group_id; - u8 cmd; - u8 reserved; - u8 result; - u8 req_origin; - u8 reset_type; - } __packed; - struct reset_message msg = { - .cmd = MKHI_GLOBAL_RESET, - .req_origin = GR_ORIGIN_BIOS_POST, - .reset_type = GLOBAL_RST_TYPE - }; - size_t reply_size; - - heci_reset(); - - status = heci_send(&msg, sizeof(msg), BIOS_HOST_ADD, HECI_MKHI_ADD); - if (!status) - return -1; - - reply_size = sizeof(reply); - memset(&reply, 0, reply_size); - status = heci_receive(&reply, &reply_size); - if (!status) - return -1; - /* get reply result from HECI MSG */ - if (reply.result) { - printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__); - return -1; - } - printk(BIOS_DEBUG, "%s: Exit with Success\n", __func__); - return 0; -} - int send_global_reset(void) { int status = -1; - union me_hfs hfs; + union me_hfsts1 hfs1; + + if (!is_cse_enabled()) + goto ret; /* Check ME operating mode */ - hfs.data = me_read_config32(PCI_ME_HFSTS1); - if (hfs.fields.operation_mode) + hfs1.data = me_read_config32(PCI_ME_HFSTS1); + if (hfs1.fields.operation_mode) goto ret; /* ME should be in Normal Mode for this command */ - status = send_heci_reset_message(); + status = send_heci_reset_req_message(GLOBAL_RESET); ret: return status; } diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 963a5003e8..29f2517468 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -14,10 +14,12 @@ * GNU General Public License for more details. */ +#include #include #include #include #include +#include #include #include #include @@ -25,7 +27,6 @@ #include #include #include -#include #include #include @@ -37,53 +38,6 @@ void smm_region(uintptr_t *start, size_t *size) *size = sa_get_tseg_size(); } -/* - * Subregions within SMM - * +-------------------------+ BGSM - * | IED | IED_REGION_SIZE - * +-------------------------+ - * | External Stage Cache | SMM_RESERVED_SIZE - * +-------------------------+ - * | code and data | - * | (TSEG) | - * +-------------------------+ TSEG - */ -int smm_subregion(int sub, uintptr_t *start, size_t *size) -{ - uintptr_t sub_base; - size_t sub_size; - const size_t ied_size = CONFIG_IED_REGION_SIZE; - const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - - smm_region(&sub_base, &sub_size); - - switch (sub) { - case SMM_SUBREGION_HANDLER: - /* Handler starts at the base of TSEG. */ - sub_size -= ied_size; - sub_size -= cache_size; - break; - case SMM_SUBREGION_CACHE: - /* External cache is in the middle of TSEG. */ - sub_base += sub_size - (ied_size + cache_size); - sub_size = cache_size; - break; - case SMM_SUBREGION_CHIPSET: - /* IED is at the top. */ - sub_base += sub_size - ied_size; - sub_size = ied_size; - break; - default: - *start = 0; - *size = 0; - return -1; - } - - *start = sub_base; - *size = sub_size; - return 0; -} - static bool is_ptt_enable(void) { if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) == @@ -337,3 +291,24 @@ void *cbmem_top(void) return (void *)(uintptr_t)ebda_cfg.tolum_base; } + +#if CONFIG(PLATFORM_USES_FSP2_0) +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + + /* + * We need to make sure ramstage will be run cached. At this + * point exact location of ramstage in cbmem is not known. + * Instruct postcar to cache 16 megs under cbmem top which is + * a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t) cbmem_top(); + printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); + top_of_ram -= 16*MiB; + postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); + + /* Cache the TSEG region */ + postcar_enable_tseg_cache(pcf); +} +#endif diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index e929ebaf17..7bb9d4bc03 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,4 +1,4 @@ -romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += ../../../../cpu/intel/car/romstage.c +romstage-y += ../../../../cpu/intel/car/romstage.c romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c romstage-y += systemagent.c diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 2d0de2f5e9..a8bbfb633d 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 221c6c41d5..deda53312c 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -13,10 +13,9 @@ * GNU General Public License for more details. */ -#include +#include #include #include -#include #include #include #include @@ -31,8 +30,8 @@ #include #include #include +#include #include -#include #include #include "../chip.h" @@ -139,59 +138,20 @@ static void save_dimm_info(void) printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } -asmlinkage void car_stage_entry(void) +void mainboard_romstage_entry(void) { bool s3wake; - struct postcar_frame pcf; - uintptr_t top_of_ram; struct chipset_power_state *ps; - console_init(); - /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); ps = pmc_get_power_state(); - timestamp_add_now(TS_START_ROMSTAGE); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); if (!s3wake) save_dimm_info(); - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - /* - * We need to make sure ramstage will be run cached. At this - * point exact location of ramstage in cbmem is not known. - * Instruct postcar to cache 16 megs under cbmem top which is - * a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); - - if (CONFIG(HAVE_SMI_HANDLER)) { - uintptr_t smm_base; - size_t smm_size; - - /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, smm_base, smm_size, - MTRR_TYPE_WRBACK); - } - - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - run_postcar_phase(&pcf); } static void cpu_flex_override(FSP_M_CONFIG *m_cfg) @@ -288,10 +248,11 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, if (!config->ignore_vtd) { m_cfg->PchHpetBdfValid = 1; - m_cfg->PchHpetBusNumber = 250; - m_cfg->PchHpetDeviceNumber = 15; - m_cfg->PchHpetFunctionNumber = 0; + m_cfg->PchHpetBusNumber = V_P2SB_HBDF_BUS; + m_cfg->PchHpetDeviceNumber = V_P2SB_HBDF_DEV; + m_cfg->PchHpetFunctionNumber = V_P2SB_HBDF_FUN; } + m_cfg->HyperThreading = CONFIG(FSP_HYPERTHREADING); } static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg, diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index 9bc599a3cd..e1779d1141 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -25,8 +25,9 @@ #include #include #include +#include +#include #include -#include #include #include #include @@ -45,16 +46,6 @@ static inline void write_smrr(struct smm_relocation_params *relo_params) wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); } -static inline void write_uncore_emrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, - "Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->uncore_emrr_base.lo, - relo_params->uncore_emrr_mask.lo); - wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_emrr_base); - wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_emrr_mask); -} - static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, struct smm_relocation_params *relo_params) @@ -174,7 +165,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, /* Make appropriate changes to the save state map. */ update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); - /* Write EMRR and SMRR MSRs based on indicated support. */ + /* Write SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); if (mtrr_cap.lo & SMRR_SUPPORTED) write_smrr(relo_params); @@ -184,18 +175,9 @@ static void fill_in_relocation_params(struct smm_relocation_params *params) { uintptr_t tseg_base; size_t tseg_size; - u32 emrr_base; - u32 emrr_size; - int phys_bits; /* All range registers are aligned to 4KiB */ const u32 rmask = ~((1 << 12) - 1); - /* - * Some of the range registers are dependent on the number of physical - * address bits supported. - */ - phys_bits = cpuid_eax(0x80000008) & 0xff; - smm_region(&tseg_base, &tseg_size); smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); @@ -204,27 +186,6 @@ static void fill_in_relocation_params(struct smm_relocation_params *params) params->smrr_base.hi = 0; params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; params->smrr_mask.hi = 0; - - /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */ - emrr_base = (params->ied_base + (2 << 20)) & rmask; - emrr_size = params->ied_size - (2 << 20); - - /* - * EMRR has 46 bits of valid address aligned to 4KiB. It's dependent - * on the number of physical address bits supported. - */ - params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK; - params->emrr_base.hi = 0; - params->emrr_mask.lo = (~(emrr_size - 1) & rmask) - | MTRR_PHYS_MASK_VALID; - params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1; - - /* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */ - params->uncore_emrr_base.lo = emrr_base; - params->uncore_emrr_base.hi = 0; - params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) | - MTRR_PHYS_MASK_VALID; - params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1; } static void setup_ied_area(struct smm_relocation_params *params) diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index c83e18dd1d..089dd5d572 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -19,87 +19,8 @@ #include #include #include - -#define KBLY_ICCMAX_SA VR_CFG_AMP(4.1) -#define KBLY_ICCMAX_CORE VR_CFG_AMP(24) -#define AMLY_ICCMAX_CORE VR_CFG_AMP(28) -#define KBLY_ICCMAX_GTS_GTUS VR_CFG_AMP(24) -#define KBLR_ICCMAX_SA_U42 VR_CFG_AMP(6) -#define KBLU_ICCMAX_SA_U22 VR_CFG_AMP(4.5) -#define KBLR_ICCMAX_CORE_U42 VR_CFG_AMP(64) -#define KBLU_ICCMAX_CORE_U22_PREMIUM VR_CFG_AMP(32) -#define KBLU_ICCMAX_CORE_U22_BASE VR_CFG_AMP(29) -#define KBLUR_ICCMAX_GTS_GTUS VR_CFG_AMP(31) - -enum kbl_sku { - KBL_Y_SKU, - KBL_R_SKU, - KBL_U_BASE_SKU, - KBL_U_PREMIUM_SKU, - AML_Y_SKU, -}; - -/* - * Iccmax table from Doc #559100 Section 7.2 DC Specifications, the - * Iccmax is the same among KBL-Y but KBL-U/R. - * Addendum for AML-Y #594883, IccMax for IA core is 28A. - * +----------------+-------------+---------------+------+-----+ - * | Domain/Setting | SA | IA | GTUS | GTS | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(KBL-U/R)| 6A(U42) | 64A(U42) | 31A | 31A | - * | | 4.5A(Others)| 29A(P/C) | | | - * | | | 32A(i3/i5) | | | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(KBL-Y) | 4.1A | 24A | 24A | 24A | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(AML-Y) | 4.1A | 28A | 24A | 24A | - * +----------------+-------------+---------------+------+-----+ - */ - -static const struct { - uint16_t icc_max[NUM_VR_DOMAINS]; -}sku_icc_max_mapping[] = { - [KBL_Y_SKU] = { - .icc_max = { - KBLY_ICCMAX_SA, - KBLY_ICCMAX_CORE, - KBLY_ICCMAX_GTS_GTUS, - KBLY_ICCMAX_GTS_GTUS - } - }, - [KBL_R_SKU] = { - .icc_max = { - KBLR_ICCMAX_SA_U42, - KBLR_ICCMAX_CORE_U42, - KBLUR_ICCMAX_GTS_GTUS, - KBLUR_ICCMAX_GTS_GTUS - } - }, - [KBL_U_BASE_SKU] = { - .icc_max = { - KBLU_ICCMAX_SA_U22, - KBLU_ICCMAX_CORE_U22_BASE, - KBLUR_ICCMAX_GTS_GTUS, - KBLUR_ICCMAX_GTS_GTUS - } - }, - [KBL_U_PREMIUM_SKU] = { - .icc_max = { - KBLU_ICCMAX_SA_U22, - KBLU_ICCMAX_CORE_U22_PREMIUM, - KBLUR_ICCMAX_GTS_GTUS, - KBLUR_ICCMAX_GTS_GTUS - } - }, - [AML_Y_SKU] = { - .icc_max = { - KBLY_ICCMAX_SA, - AMLY_ICCMAX_CORE, - KBLY_ICCMAX_GTS_GTUS, - KBLY_ICCMAX_GTS_GTUS - } - }, -}; +#include +#include /* Default values for domain configuration. PSI3 and PSI4 are disabled. */ static const struct vr_config default_configs[NUM_VR_DOMAINS] = { @@ -167,54 +88,212 @@ static const struct vr_config default_configs[NUM_VR_DOMAINS] = { }, }; -static uint16_t get_dev_id(struct device *dev) +static uint16_t get_sku_icc_max(int domain) { - return pci_read_config16(dev, PCI_DEVICE_ID); -} + const uint16_t tdp = cpu_get_power_max(); -static int get_kbl_sku(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - static int sku = -1; - uint16_t id; - - if (sku != -1) - return sku; - - id = get_dev_id(sa_dev); - if (id == PCI_DEVICE_ID_INTEL_KBL_U_R) - sku = KBL_R_SKU; - else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_Y) { - struct device *igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); - id = get_dev_id(igd_dev); - if (id == PCI_DEVICE_ID_INTEL_AML_GT2_ULX) - sku = AML_Y_SKU; + static uint16_t mch_id = 0, igd_id = 0, lpc_id = 0; + if (!mch_id) { + struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + mch_id = pci_read_config16(dev, PCI_DEVICE_ID); + } + if (!igd_id) { + struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); + if (dev) + igd_id = pci_read_config16(dev, PCI_DEVICE_ID); else - sku = KBL_Y_SKU; - } else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_U) { - id = get_dev_id(PCH_DEV_LPC); - if (id == PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22) - sku = KBL_U_BASE_SKU; - else - sku = KBL_U_PREMIUM_SKU; - } else - /* Not one of the skus with available Icc max mapping. */ - sku = -2; - return sku; + igd_id = 0xffff; + } + if (!lpc_id) { + struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); + lpc_id = pci_read_config16(dev, PCI_DEVICE_ID); + } + + /* + * Iccmax table from Doc #559100 Section 7.2 DC Specifications, the + * Iccmax is the same among KBL-Y but KBL-U/R. + * Addendum for AML-Y #594883, IccMax for IA core is 28A. + * KBL-S #335195, KBL-H #335190 + * +----------------+-------------+---------------+------+-----+ + * | Domain/Setting | SA | IA | GTUS | GTS | + * +----------------+-------------+---------------+------+-----+ + * | IccMax(KBL-S) | 11.1A | 100A | 45A | 45A | + * | | | ... | | | + * | | | 40A | | | + * +----------------+-------------+---------------+------+-----+ + * | IccMax(KBL-H) | 11.1A(45W) | 68A | 55A | 55A | + * | | 6.6A(Others)| 60A | | | + * +----------------+-------------+---------------+------+-----+ + * | IccMax(KBL-U/R)| 6A(U42) | 64A(U42) | 31A | 31A | + * | | 4.5A(Others)| 29A(P/C) | | | + * | | | 32A(i3/i5) | | | + * +----------------+-------------+---------------+------+-----+ + * | IccMax(KBL-Y) | 4.1A | 24A | 24A | 24A | + * +----------------+-------------+---------------+------+-----+ + * | IccMax(AML-Y) | 4.1A | 28A | 24A | 24A | + * +----------------+-------------+---------------+------+-----+ + */ + + switch (mch_id) { + case PCI_DEVICE_ID_INTEL_KBL_ID_S: { + uint16_t icc_max[NUM_VR_DOMAINS] = { + VR_CFG_AMP(11.1), + VR_CFG_AMP(40), + VR_CFG_AMP(45), + VR_CFG_AMP(45), + }; + if (tdp >= 54) + icc_max[VR_IA_CORE] = VR_CFG_AMP(58); + else if (tdp >= 51) + icc_max[VR_IA_CORE] = VR_CFG_AMP(45); + + return icc_max[domain]; + + } + case PCI_DEVICE_ID_INTEL_KBL_ID_DT_2: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_KBL_ID_DT: { + uint16_t icc_max[NUM_VR_DOMAINS] = { + VR_CFG_AMP(11.1), + VR_CFG_AMP(66), + VR_CFG_AMP(55), + VR_CFG_AMP(55), + }; + if (tdp >= 91) + icc_max[VR_IA_CORE] = VR_CFG_AMP(100); + else if (tdp >= 65) + icc_max[VR_IA_CORE] = VR_CFG_AMP(79); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_KBL_ID_H: { + uint16_t icc_max[NUM_VR_DOMAINS] = { + VR_CFG_AMP(6.6), + VR_CFG_AMP(60), + VR_CFG_AMP(55), + VR_CFG_AMP(55), + }; + if (tdp >= 45) { + icc_max[VR_SYSTEM_AGENT] = VR_CFG_AMP(11.1); + icc_max[VR_IA_CORE] = VR_CFG_AMP(68); + } + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_KBL_U_R: { + static const uint16_t icc_max[NUM_VR_DOMAINS] = { + VR_CFG_AMP(6), + VR_CFG_AMP(64), + VR_CFG_AMP(31), + VR_CFG_AMP(31), + }; + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_KBL_ID_Y: { + uint16_t icc_max[NUM_VR_DOMAINS] = { + VR_CFG_AMP(4.1), + VR_CFG_AMP(24), + VR_CFG_AMP(24), + VR_CFG_AMP(24), + }; + + if (igd_id == PCI_DEVICE_ID_INTEL_AML_GT2_ULX) + icc_max[VR_IA_CORE] = VR_CFG_AMP(28); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_KBL_ID_U: { + uint16_t icc_max[NUM_VR_DOMAINS] = { + VR_CFG_AMP(4.5), + VR_CFG_AMP(32), + VR_CFG_AMP(31), + VR_CFG_AMP(31), + }; + + if (igd_id == PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22) + icc_max[VR_IA_CORE] = VR_CFG_AMP(29); + + return icc_max[domain]; + } + default: + printk(BIOS_ERR, "ERROR: Unknown MCH in VR-config\n"); + } + return 0; } -static uint16_t get_sku_icc_max(int domain, uint16_t board_icc_max) +#if CONFIG(PLATFORM_USES_FSP2_0) +static uint16_t get_sku_ac_dc_loadline(const int domain) { - /* If board provided non-zero value, use it. */ - if (board_icc_max) - return board_icc_max; + static uint16_t mch_id = 0, igd_id = 0; + if (!mch_id) { + struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + mch_id = pci_read_config16(dev, PCI_DEVICE_ID); + } + if (!igd_id) { + struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); + if (dev) + igd_id = pci_read_config16(dev, PCI_DEVICE_ID); + else + igd_id = 0xffff; + } - /* Check if this SKU has a mapping table entry. */ - int sku_id = get_kbl_sku(); - if (sku_id < 0) - return 0; - return sku_icc_max_mapping[sku_id].icc_max[domain]; + switch (mch_id) { + case PCI_DEVICE_ID_INTEL_KBL_ID_S: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_KBL_ID_DT: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_KBL_ID_DT_2: { + static const uint16_t loadline[NUM_VR_DOMAINS] = { + VR_CFG_MOHMS(0), /* Not specified */ + VR_CFG_MOHMS(2.1), + VR_CFG_MOHMS(3.1), + VR_CFG_MOHMS(3.1), + }; + + return loadline[domain]; + } + case PCI_DEVICE_ID_INTEL_KBL_ID_H: { + static const uint16_t loadline[NUM_VR_DOMAINS] = { + VR_CFG_MOHMS(10), + VR_CFG_MOHMS(1.8), + VR_CFG_MOHMS(2.65), + VR_CFG_MOHMS(2.65), + }; + + return loadline[domain]; + } + case PCI_DEVICE_ID_INTEL_KBL_ID_Y: { + uint16_t loadline[NUM_VR_DOMAINS] = { + VR_CFG_MOHMS(18), + VR_CFG_MOHMS(5.9), + VR_CFG_MOHMS(5.7), + VR_CFG_MOHMS(5.7), + }; + + if (igd_id == PCI_DEVICE_ID_INTEL_AML_GT2_ULX) + loadline[VR_IA_CORE] = VR_CFG_MOHMS(4); + + return loadline[domain]; + } + case PCI_DEVICE_ID_INTEL_KBL_U_R: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_KBL_ID_U: { + uint16_t loadline[NUM_VR_DOMAINS] = { + VR_CFG_MOHMS(10.3), + VR_CFG_MOHMS(2.4), + VR_CFG_MOHMS(3.1), + VR_CFG_MOHMS(3.1), + }; + + if (igd_id == PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM_HDCP22) { + loadline[VR_GT_UNSLICED] = VR_CFG_MOHMS(6); + loadline[VR_GT_SLICED] = VR_CFG_MOHMS(6); + } + + return loadline[domain]; + } + default: + printk(BIOS_ERR, "ERROR: Unknown MCH in VR-config\n"); + } + return 0; } +#endif void fill_vr_domain_config(void *params, int domain, const struct vr_config *chip_cfg) @@ -239,11 +318,21 @@ void fill_vr_domain_config(void *params, vr_params->Psi4Enable[domain] = cfg->psi4enable; vr_params->ImonSlope[domain] = cfg->imon_slope; vr_params->ImonOffset[domain] = cfg->imon_offset; - vr_params->IccMax[domain] = get_sku_icc_max(domain, cfg->icc_max); + /* If board provided non-zero value, use it. */ + if (cfg->icc_max) + vr_params->IccMax[domain] = cfg->icc_max; + else + vr_params->IccMax[domain] = get_sku_icc_max(domain); vr_params->VrVoltageLimit[domain] = cfg->voltage_limit; #if CONFIG(PLATFORM_USES_FSP2_0) - vr_params->AcLoadline[domain] = cfg->ac_loadline; - vr_params->DcLoadline[domain] = cfg->dc_loadline; + if (cfg->ac_loadline) + vr_params->AcLoadline[domain] = cfg->ac_loadline; + else + vr_params->AcLoadline[domain] = get_sku_ac_dc_loadline(domain); + if (cfg->dc_loadline) + vr_params->DcLoadline[domain] = cfg->dc_loadline; + else + vr_params->DcLoadline[domain] = get_sku_ac_dc_loadline(domain); #endif } diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c new file mode 100644 index 0000000000..679bec8d75 --- /dev/null +++ b/src/soc/mediatek/common/dsi.c @@ -0,0 +1,418 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static unsigned int mtk_dsi_get_bits_per_pixel(u32 format) +{ + switch (format) { + case MIPI_DSI_FMT_RGB565: + return 16; + case MIPI_DSI_FMT_RGB666: + case MIPI_DSI_FMT_RGB666_PACKED: + return 18; + case MIPI_DSI_FMT_RGB888: + return 24; + } + printk(BIOS_WARNING, "%s: WARN: Unknown format %d, assuming 24 bpp\n", + __func__, format); + return 24; +} + +static int mtk_dsi_get_data_rate(u32 bits_per_pixel, u32 lanes, + const struct edid *edid) +{ + /* data_rate = pixel_clock * bits_per_pixel * mipi_ratio / lanes + * Note pixel_clock comes in kHz and returned data_rate is in Mbps. + * mipi_ratio is the clk coefficient to balance the pixel clk in MIPI + * for older platforms which do not have complete implementation in HFP. + * Newer platforms should just set that to 1.0 (100 / 100). + */ + int data_rate = (u64)edid->mode.pixel_clock * bits_per_pixel * + MTK_DSI_MIPI_RATIO_NUMERATOR / + (1000 * lanes * MTK_DSI_MIPI_RATIO_DENOMINATOR); + printk(BIOS_INFO, "DSI data_rate: %d Mbps\n", data_rate); + + if (data_rate < MTK_DSI_DATA_RATE_MIN_MHZ) { + printk(BIOS_ERR, "data rate (%dMbps) must be >=%dMbps. " + "Please check the pixel clock (%u), bits per pixel(%u), " + "mipi_ratio (%d%%) and number of lanes (%d)\n", + data_rate, MTK_DSI_DATA_RATE_MIN_MHZ, + edid->mode.pixel_clock, bits_per_pixel, + (100 * MTK_DSI_MIPI_RATIO_NUMERATOR / + MTK_DSI_MIPI_RATIO_DENOMINATOR), lanes); + return -1; + } + return data_rate; +} + +__weak void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing) +{ + /* Do nothing. */ +} + +static void mtk_dsi_phy_timing(int data_rate, struct mtk_phy_timing *phy_timing) +{ + u32 cycle_time, ui; + + ui = 1000 / data_rate + 0x01; + cycle_time = 8000 / data_rate + 0x01; + + memset(phy_timing, 0, sizeof(*phy_timing)); + + phy_timing->lpx = DIV_ROUND_UP(60, cycle_time); + phy_timing->da_hs_prepare = DIV_ROUND_UP((40 + 5 * ui), cycle_time); + phy_timing->da_hs_zero = DIV_ROUND_UP((110 + 6 * ui), cycle_time); + phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 80), cycle_time); + + phy_timing->ta_go = 4U * phy_timing->lpx; + phy_timing->ta_sure = 3U * phy_timing->lpx / 2U; + phy_timing->ta_get = 5U * phy_timing->lpx; + phy_timing->da_hs_exit = 2U * phy_timing->lpx; + + phy_timing->da_hs_sync = 1; + phy_timing->clk_hs_zero = DIV_ROUND_UP(0x150U, cycle_time); + phy_timing->clk_hs_trail = DIV_ROUND_UP(0x64U, cycle_time) + 0xaU; + + phy_timing->clk_hs_prepare = DIV_ROUND_UP(0x40U, cycle_time); + phy_timing->clk_hs_post = DIV_ROUND_UP(80U + 52U * ui, cycle_time); + phy_timing->clk_hs_exit = 2U * phy_timing->lpx; + + /* Allow board-specific tuning. */ + mtk_dsi_override_phy_timing(phy_timing); + + u32 timcon0, timcon1, timcon2, timcon3; + + timcon0 = phy_timing->lpx | phy_timing->da_hs_prepare << 8 | + phy_timing->da_hs_zero << 16 | phy_timing->da_hs_trail << 24; + timcon1 = phy_timing->ta_go | phy_timing->ta_sure << 8 | + phy_timing->ta_get << 16 | phy_timing->da_hs_exit << 24; + timcon2 = phy_timing->da_hs_sync << 8 | phy_timing->clk_hs_zero << 16 | + phy_timing->clk_hs_trail << 24; + timcon3 = phy_timing->clk_hs_prepare | phy_timing->clk_hs_post << 8 | + phy_timing->clk_hs_exit << 16; + + write32(&dsi0->dsi_phy_timecon0, timcon0); + write32(&dsi0->dsi_phy_timecon1, timcon1); + write32(&dsi0->dsi_phy_timecon2, timcon2); + write32(&dsi0->dsi_phy_timecon3, timcon3); +} + +static void mtk_dsi_clk_hs_mode_enable(void) +{ + setbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN); +} + +static void mtk_dsi_clk_hs_mode_disable(void) +{ + clrbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN); +} + +static void mtk_dsi_set_mode(u32 mode_flags) +{ + u32 tmp_reg1 = 0; + + if (mode_flags & MIPI_DSI_MODE_VIDEO) { + tmp_reg1 = SYNC_PULSE_MODE; + + if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) + tmp_reg1 = BURST_MODE; + + if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) + tmp_reg1 = SYNC_PULSE_MODE; + } + + write32(&dsi0->dsi_mode_ctrl, tmp_reg1); +} + +static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes) +{ + u32 tmp_reg = 0; + + switch (lanes) { + case 1: + tmp_reg = 1 << 2; + break; + case 2: + tmp_reg = 3 << 2; + break; + case 3: + tmp_reg = 7 << 2; + break; + case 4: + default: + tmp_reg = 0xf << 2; + break; + } + + tmp_reg |= (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; + tmp_reg |= (mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; + + write32(&dsi0->dsi_txrx_ctrl, tmp_reg); +} + +static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes, + const struct edid *edid, + const struct mtk_phy_timing *phy_timing) +{ + u32 hsync_active_byte; + u32 hbp_byte; + u32 hfp_byte; + u32 vbp_byte; + u32 vfp_byte; + u32 bytes_per_pixel; + u32 packet_fmt; + u32 hactive; + u32 data_phy_cycles; + + bytes_per_pixel = DIV_ROUND_UP(mtk_dsi_get_bits_per_pixel(format), 8); + vbp_byte = edid->mode.vbl - edid->mode.vso - edid->mode.vspw - + edid->mode.vborder; + vfp_byte = edid->mode.vso - edid->mode.vborder; + + write32(&dsi0->dsi_vsa_nl, edid->mode.vspw); + write32(&dsi0->dsi_vbp_nl, vbp_byte); + write32(&dsi0->dsi_vfp_nl, vfp_byte); + write32(&dsi0->dsi_vact_nl, edid->mode.va); + + unsigned int hspw = 0; + if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) + hspw = edid->mode.hspw; + + hbp_byte = (edid->mode.hbl - edid->mode.hso - hspw - edid->mode.hborder) + * bytes_per_pixel - 10; + hsync_active_byte = edid->mode.hspw * bytes_per_pixel - 10; + hfp_byte = (edid->mode.hso - edid->mode.hborder) * bytes_per_pixel; + + data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare + + phy_timing->da_hs_zero + phy_timing->da_hs_exit + 2; + + u32 delta = 12; + if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) + delta += 6; + + u32 d_phy = phy_timing->d_phy; + if (d_phy == 0) + d_phy = data_phy_cycles * lanes + delta; + if (hfp_byte > d_phy) + hfp_byte -= d_phy; + else + printk(BIOS_ERR, "HFP is not greater than d-phy, FPS < 60Hz " + "and the panel may not work properly.\n"); + + write32(&dsi0->dsi_hsa_wc, hsync_active_byte); + write32(&dsi0->dsi_hbp_wc, hbp_byte); + write32(&dsi0->dsi_hfp_wc, hfp_byte); + + switch (format) { + case MIPI_DSI_FMT_RGB888: + packet_fmt = PACKED_PS_24BIT_RGB888; + break; + case MIPI_DSI_FMT_RGB666: + packet_fmt = LOOSELY_PS_18BIT_RGB666; + break; + case MIPI_DSI_FMT_RGB666_PACKED: + packet_fmt = PACKED_PS_18BIT_RGB666; + break; + case MIPI_DSI_FMT_RGB565: + packet_fmt = PACKED_PS_16BIT_RGB565; + break; + default: + packet_fmt = PACKED_PS_24BIT_RGB888; + break; + } + + hactive = edid->mode.ha; + packet_fmt |= (hactive * bytes_per_pixel) & DSI_PS_WC; + + write32(&dsi0->dsi_psctrl, + PIXEL_STREAM_CUSTOM_HEADER << DSI_PSCON_CUSTOM_HEADER_SHIFT | + packet_fmt); + + /* Older systems like MT8173 do not support size_con. */ + if (MTK_DSI_HAVE_SIZE_CON) + write32(&dsi0->dsi_size_con, + edid->mode.va << DSI_SIZE_CON_HEIGHT_SHIFT | + hactive << DSI_SIZE_CON_WIDTH_SHIFT); +} + +static void mtk_dsi_start(void) +{ + write32(&dsi0->dsi_start, 0); + /* Only start master DSI */ + write32(&dsi0->dsi_start, 1); +} + +static bool mtk_dsi_is_read_command(u32 type) +{ + switch (type) { + case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: + case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: + case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: + case MIPI_DSI_DCS_READ: + return true; + } + return false; +} + +static void mtk_dsi_cmdq(const u8 *data, u8 len, u32 type) +{ + const u8 *tx_buf = data; + u32 config; + int i, j; + + if (!wait_ms(20, !(read32(&dsi0->dsi_intsta) & DSI_BUSY))) { + printk(BIOS_ERR, "%s: cannot get DSI ready for sending commands" + " after 20ms and the panel may not work properly.\n", + __func__); + return; + } + write32(&dsi0->dsi_intsta, 0); + + if (mtk_dsi_is_read_command(type)) + config = BTA; + else + config = (len > 2) ? LONG_PACKET : SHORT_PACKET; + + if (len <= 2) { + uint32_t val = (type << 8) | config; + for (i = 0; i < len; i++) + val |= tx_buf[i] << (i + 2) * 8; + write32(&dsi0->dsi_cmdq[0], val); + write32(&dsi0->dsi_cmdq_size, 1); + } else { + /* TODO(hungte) Replace by buffer_to_fifo32_prefix */ + write32(&dsi0->dsi_cmdq[0], (len << 16) | (type << 8) | config); + for (i = 0; i < len; i += 4) { + uint32_t val = 0; + for (j = 0; j < MIN(len - i, 4); j++) + val |= tx_buf[i + j] << j * 8; + write32(&dsi0->dsi_cmdq[i / 4 + 1], val); + } + write32(&dsi0->dsi_cmdq_size, 1 + DIV_ROUND_UP(len, 4)); + } + + mtk_dsi_start(); + + if (!wait_us(400, read32(&dsi0->dsi_intsta) & CMD_DONE_INT_FLAG)) { + printk(BIOS_ERR, "%s: failed sending DSI command, " + "panel may not work.\n", __func__); + return; + } +} + +static void mtk_dsi_send_init_commands(const u8 *buf) +{ + if (!buf) + return; + const struct lcm_init_command *init = (const void *)buf; + + /* + * The given commands should be in a buffer containing a packed array of + * lcm_init_command and each element may be in variable size so we have + * to parse and scan. + */ + + for (; init->cmd != LCM_END_CMD; init = (const void *)buf) { + /* + * For some commands like DELAY, the init->len should not be + * counted for buf. + */ + buf += sizeof(*init); + + u32 cmd = init->cmd, len = init->len; + u32 type; + + switch (cmd) { + case LCM_DELAY_CMD: + mdelay(len); + continue; + + case LCM_DCS_CMD: + switch (len) { + case 0: + return; + case 1: + type = MIPI_DSI_DCS_SHORT_WRITE; + break; + case 2: + type = MIPI_DSI_DCS_SHORT_WRITE_PARAM; + break; + default: + type = MIPI_DSI_DCS_LONG_WRITE; + break; + } + break; + + case LCM_GENERIC_CMD: + switch (len) { + case 0: + type = MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM; + break; + case 1: + type = MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM; + break; + case 2: + type = MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM; + break; + default: + type = MIPI_DSI_GENERIC_LONG_WRITE; + break; + } + break; + + default: + printk(BIOS_ERR, "%s: Unknown cmd: %d, " + "abort panel initialization.\n", __func__, cmd); + return; + + } + buf += len; + mtk_dsi_cmdq(init->data, len, type); + } +} + +int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid, + const u8 *init_commands) +{ + int data_rate; + u32 bits_per_pixel = mtk_dsi_get_bits_per_pixel(format); + + data_rate = mtk_dsi_get_data_rate(bits_per_pixel, lanes, edid); + if (data_rate < 0) + return -1; + + mtk_dsi_configure_mipi_tx(data_rate, lanes); + mtk_dsi_reset(); + struct mtk_phy_timing phy_timing; + mtk_dsi_phy_timing(data_rate, &phy_timing); + mtk_dsi_rxtx_control(mode_flags, lanes); + mtk_dsi_clk_hs_mode_disable(); + mtk_dsi_config_vdo_timing(mode_flags, format, lanes, edid, &phy_timing); + mtk_dsi_clk_hs_mode_enable(); + mtk_dsi_send_init_commands(init_commands); + mtk_dsi_set_mode(mode_flags); + mtk_dsi_start(); + + return 0; +} diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h new file mode 100644 index 0000000000..9a00d1d149 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/dsi_common.h @@ -0,0 +1,370 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_DSI_COMMON_H +#define SOC_MEDIATEK_DSI_COMMON_H + +#include +#include +#include + +enum mipi_dsi_pixel_format { + MIPI_DSI_FMT_RGB888, + MIPI_DSI_FMT_RGB666, + MIPI_DSI_FMT_RGB666_PACKED, + MIPI_DSI_FMT_RGB565 +}; + +/* video mode */ +enum { + MIPI_DSI_MODE_VIDEO = BIT(0), + /* video burst mode */ + MIPI_DSI_MODE_VIDEO_BURST = BIT(1), + /* video pulse mode */ + MIPI_DSI_MODE_VIDEO_SYNC_PULSE = BIT(2), + /* enable auto vertical count mode */ + MIPI_DSI_MODE_VIDEO_AUTO_VERT = BIT(3), + /* enable hsync-end packets in vsync-pulse and v-porch area */ + MIPI_DSI_MODE_VIDEO_HSE = BIT(4), + /* disable hfront-porch area */ + MIPI_DSI_MODE_VIDEO_HFP = BIT(5), + /* disable hback-porch area */ + MIPI_DSI_MODE_VIDEO_HBP = BIT(6), + /* disable hsync-active area */ + MIPI_DSI_MODE_VIDEO_HSA = BIT(7), + /* flush display FIFO on vsync pulse */ + MIPI_DSI_MODE_VSYNC_FLUSH = BIT(8), + /* disable EoT packets in HS mode */ + MIPI_DSI_MODE_EOT_PACKET = BIT(9), + /* device supports non-continuous clock behavior (DSI spec 5.6.1) */ + MIPI_DSI_CLOCK_NON_CONTINUOUS = BIT(10), + /* transmit data in low power */ + MIPI_DSI_MODE_LPM = BIT(11) +}; + +struct dsi_regs { + u32 dsi_start; + u8 reserved0[4]; + u32 dsi_inten; + u32 dsi_intsta; + u32 dsi_con_ctrl; + u32 dsi_mode_ctrl; + u32 dsi_txrx_ctrl; + u32 dsi_psctrl; + u32 dsi_vsa_nl; + u32 dsi_vbp_nl; + u32 dsi_vfp_nl; + u32 dsi_vact_nl; + u32 dsi_lfr_con; /* Available since MT8183 */ + u32 dsi_lfr_sta; /* Available since MT8183 */ + u32 dsi_size_con; /* Available since MT8183 */ + u32 dsi_vfp_early_stop; /* Available since MT8183 */ + u32 reserved1[4]; + u32 dsi_hsa_wc; + u32 dsi_hbp_wc; + u32 dsi_hfp_wc; + u32 dsi_bllp_wc; + u32 dsi_cmdq_size; + u32 dsi_hstx_cklp_wc; + u8 reserved2[156]; + u32 dsi_phy_lccon; + u32 dsi_phy_ld0con; + u8 reserved3[4]; + u32 dsi_phy_timecon0; + u32 dsi_phy_timecon1; + u32 dsi_phy_timecon2; + u32 dsi_phy_timecon3; + u8 reserved4[16]; + u32 dsi_vm_cmd_con; + u8 reserved5[92]; + u32 dsi_force_commit; /* Available since MT8183 */ + u8 reserved6[108]; + u32 dsi_cmdq[128]; +}; +static struct dsi_regs *const dsi0 = (void *)DSI0_BASE; + +check_member(dsi_regs, dsi_phy_lccon, 0x104); +check_member(dsi_regs, dsi_phy_timecon3, 0x11c); +check_member(dsi_regs, dsi_vm_cmd_con, 0x130); +check_member(dsi_regs, dsi_force_commit, 0x190); +check_member(dsi_regs, dsi_cmdq, 0x200); + +/* DSI_INTSTA */ +enum { + LPRX_RD_RDY_INT_FLAG = BIT(0), + CMD_DONE_INT_FLAG = BIT(1), + TE_RDY_INT_FLAG = BIT(2), + VM_DONE_INT_FLAG = BIT(3), + EXT_TE_RDY_INT_FLAG = BIT(4), + DSI_BUSY = BIT(31), +}; + +/* DSI_CON_CTRL */ +enum { + DSI_RESET = BIT(0), + DSI_EN = BIT(1), + DSI_DUAL = BIT(4), +}; + +/* DSI_MODE_CTRL */ +enum { + MODE = 3, + CMD_MODE = 0, + SYNC_PULSE_MODE = 1, + SYNC_EVENT_MODE = 2, + BURST_MODE = 3, + FRM_MODE = BIT(16), + MIX_MODE = BIT(17) +}; + +/* DSI_PSCTRL */ +enum { + DSI_PS_WC = 0x3fff, + DSI_PS_SEL = (3 << 16), + PACKED_PS_16BIT_RGB565 = (0 << 16), + LOOSELY_PS_18BIT_RGB666 = (1 << 16), + PACKED_PS_18BIT_RGB666 = (2 << 16), + PACKED_PS_24BIT_RGB888 = (3 << 16), + + DSI_PSCON_CUSTOM_HEADER_SHIFT = 26, +}; + +/* DSI_SIZE_CON */ +enum { + DSI_SIZE_CON_HEIGHT_SHIFT = 16, + DSI_SIZE_CON_WIDTH_SHIFT = 0, +}; + +/* DSI_CMDQ_SIZE */ +enum { + CMDQ_SIZE = 0x3f, +}; + +/* DSI_PHY_LCCON */ +enum { + LC_HS_TX_EN = BIT(0), + LC_ULPM_EN = BIT(1), + LC_WAKEUP_EN = BIT(2) +}; + +/*DSI_PHY_LD0CON */ +enum { + LD0_RM_TRIG_EN = BIT(0), + LD0_ULPM_EN = BIT(1), + LD0_WAKEUP_EN = BIT(2) +}; + +enum { + LPX = (0xff << 0), + HS_PRPR = (0xff << 8), + HS_ZERO = (0xff << 16), + HS_TRAIL = (0xff << 24) +}; + +enum { + TA_GO = (0xff << 0), + TA_SURE = (0xff << 8), + TA_GET = (0xff << 16), + DA_HS_EXIT = (0xff << 24) +}; + +enum { + CONT_DET = (0xff << 0), + CLK_ZERO = (0xf << 16), + CLK_TRAIL = (0xff << 24) +}; + +enum { + CLK_HS_PRPR = (0xff << 0), + CLK_HS_POST = (0xff << 8), + CLK_HS_EXIT = (0xf << 16) +}; + +/* DSI_VM_CMD_CON */ +enum { + VM_CMD_EN = BIT(0), + TS_VFP_EN = BIT(5), +}; + +/* DSI_CMDQ0 */ +enum { + CONFIG = (0xff << 0), + SHORT_PACKET = 0, + LONG_PACKET = 2, + BTA = BIT(2), + DATA_ID = (0xff << 8), + DATA_0 = (0xff << 16), + DATA_1 = (0xff << 24), +}; + +/* DSI_FORCE_COMMIT */ +enum { + DSI_FORCE_COMMIT_USE_MMSYS = BIT(0), + DSI_FORCE_COMMIT_ALWAYS = BIT(1), +}; + +/* MIPI DSI Processor-to-Peripheral transaction types */ +enum { + MIPI_DSI_V_SYNC_START = 0x01, + MIPI_DSI_V_SYNC_END = 0x11, + MIPI_DSI_H_SYNC_START = 0x21, + MIPI_DSI_H_SYNC_END = 0x31, + + MIPI_DSI_COLOR_MODE_OFF = 0x02, + MIPI_DSI_COLOR_MODE_ON = 0x12, + MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22, + MIPI_DSI_TURN_ON_PERIPHERAL = 0x32, + + MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03, + MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13, + MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23, + + MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04, + MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14, + MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24, + + MIPI_DSI_DCS_SHORT_WRITE = 0x05, + MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15, + + MIPI_DSI_DCS_READ = 0x06, + + MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, + + MIPI_DSI_END_OF_TRANSMISSION = 0x08, + + MIPI_DSI_NULL_PACKET = 0x09, + MIPI_DSI_BLANKING_PACKET = 0x19, + MIPI_DSI_GENERIC_LONG_WRITE = 0x29, + MIPI_DSI_DCS_LONG_WRITE = 0x39, + + MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c, + + MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d, + MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d, + + MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e, + MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e, + MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e, + MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e, +}; + +/* MIPI DSI Peripheral-to-Processor transaction types */ +enum { + MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02, + MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08, + MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11, + MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12, + MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a, + MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c, + MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21, + MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22, +}; + +/* MIPI DCS commands */ +enum { + MIPI_DCS_NOP = 0x00, + MIPI_DCS_SOFT_RESET = 0x01, + MIPI_DCS_GET_DISPLAY_ID = 0x04, + MIPI_DCS_GET_RED_CHANNEL = 0x06, + MIPI_DCS_GET_GREEN_CHANNEL = 0x07, + MIPI_DCS_GET_BLUE_CHANNEL = 0x08, + MIPI_DCS_GET_DISPLAY_STATUS = 0x09, + MIPI_DCS_GET_POWER_MODE = 0x0A, + MIPI_DCS_GET_ADDRESS_MODE = 0x0B, + MIPI_DCS_GET_PIXEL_FORMAT = 0x0C, + MIPI_DCS_GET_DISPLAY_MODE = 0x0D, + MIPI_DCS_GET_SIGNAL_MODE = 0x0E, + MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F, + MIPI_DCS_ENTER_SLEEP_MODE = 0x10, + MIPI_DCS_EXIT_SLEEP_MODE = 0x11, + MIPI_DCS_ENTER_PARTIAL_MODE = 0x12, + MIPI_DCS_ENTER_NORMAL_MODE = 0x13, + MIPI_DCS_EXIT_INVERT_MODE = 0x20, + MIPI_DCS_ENTER_INVERT_MODE = 0x21, + MIPI_DCS_SET_GAMMA_CURVE = 0x26, + MIPI_DCS_SET_DISPLAY_OFF = 0x28, + MIPI_DCS_SET_DISPLAY_ON = 0x29, + MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A, + MIPI_DCS_SET_PAGE_ADDRESS = 0x2B, + MIPI_DCS_WRITE_MEMORY_START = 0x2C, + MIPI_DCS_WRITE_LUT = 0x2D, + MIPI_DCS_READ_MEMORY_START = 0x2E, + MIPI_DCS_SET_PARTIAL_AREA = 0x30, + MIPI_DCS_SET_SCROLL_AREA = 0x33, + MIPI_DCS_SET_TEAR_OFF = 0x34, + MIPI_DCS_SET_TEAR_ON = 0x35, + MIPI_DCS_SET_ADDRESS_MODE = 0x36, + MIPI_DCS_SET_SCROLL_START = 0x37, + MIPI_DCS_EXIT_IDLE_MODE = 0x38, + MIPI_DCS_ENTER_IDLE_MODE = 0x39, + MIPI_DCS_SET_PIXEL_FORMAT = 0x3A, + MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C, + MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E, + MIPI_DCS_SET_TEAR_SCANLINE = 0x44, + MIPI_DCS_GET_SCANLINE = 0x45, + MIPI_DCS_READ_DDB_START = 0xA1, + MIPI_DCS_READ_DDB_CONTINUE = 0xA8, +}; + +struct mtk_phy_timing { + u8 lpx; + u8 da_hs_prepare; + u8 da_hs_zero; + u8 da_hs_trail; + + u8 ta_go; + u8 ta_sure; + u8 ta_get; + u8 da_hs_exit; + + u8 da_hs_sync; + u8 clk_hs_zero; + u8 clk_hs_trail; + + u8 clk_hs_prepare; + u8 clk_hs_post; + u8 clk_hs_exit; + + u32 d_phy; +}; + +/* Definitions for cmd in lcm_init_command */ +#define LCM_END_CMD 0 +#define LCM_DELAY_CMD 1 +#define LCM_GENERIC_CMD 2 +#define LCM_DCS_CMD 3 + +struct lcm_init_command { + u8 cmd; + u8 len; + u8 data[]; +}; + +/* Functions that each SOC should provide. */ +void mtk_dsi_reset(void); +void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes); + +/* Functions as weak no-ops that can be overridden. */ +void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing); + +/* Public API provided in common/dsi.c */ +int mtk_dsi_bpp_from_format(u32 format); +int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid, + const u8 *init_commands); + +#endif /* SOC_MEDIATEK_DSI_COMMON_H */ diff --git a/src/soc/mediatek/common/include/soc/spi_common.h b/src/soc/mediatek/common/include/soc/spi_common.h index 81a9098180..1ecb94dab0 100644 --- a/src/soc/mediatek/common/include/soc/spi_common.h +++ b/src/soc/mediatek/common/include/soc/spi_common.h @@ -16,6 +16,7 @@ #ifndef MTK_COMMON_SPI_H #define MTK_COMMON_SPI_H +#include #include enum { @@ -77,6 +78,7 @@ struct mtk_spi_bus { struct mtk_spi_regs *regs; int initialized; int state; + gpio_t cs_gpio; }; extern const struct spi_ctrlr spi_ctrlr; diff --git a/src/soc/mediatek/common/include/soc/usb_common.h b/src/soc/mediatek/common/include/soc/usb_common.h index 8a36c6a66b..22704e77b5 100644 --- a/src/soc/mediatek/common/include/soc/usb_common.h +++ b/src/soc/mediatek/common/include/soc/usb_common.h @@ -70,6 +70,8 @@ struct ssusb_ippc_regs { #define PA6_RG_U2_ISO_EN (0x1 << 31) #define PA6_RG_U2_BC11_SW_EN (0x1 << 23) #define PA6_RG_U2_OTG_VBUSCMP_EN (0x1 << 20) +#define PA6_RG_U2_DISCTH (0xf << 4) +#define PA6_RG_U2_DISCTH_VAL(x) ((0xf & (x)) << 4) #define PA6_RG_U2_SQTH (0xf << 0) #define PA6_RG_U2_SQTH_VAL(x) ((0xf & (x)) << 0) diff --git a/src/soc/mediatek/common/spi.c b/src/soc/mediatek/common/spi.c index 40ab9b7002..2a668fe349 100644 --- a/src/soc/mediatek/common/spi.c +++ b/src/soc/mediatek/common/spi.c @@ -17,6 +17,8 @@ #include #include #include +#include +#include #include #include #include @@ -87,6 +89,8 @@ void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select, clrsetbits_le32(®s->spi_pad_macro_sel_reg, SPI_PAD_SEL_MASK, pad_select); + + gpio_output(slave->cs_gpio, 1); } static void mtk_spi_dump_data(const char *name, const uint8_t *data, int size) @@ -109,6 +113,8 @@ static int spi_ctrlr_claim_bus(const struct spi_slave *slave) setbits_le32(®s->spi_cmd_reg, 1 << SPI_CMD_PAUSE_EN_SHIFT); mtk_slave->state = MTK_SPI_IDLE; + gpio_output(mtk_slave->cs_gpio, 0); + return 0; } @@ -243,6 +249,8 @@ static void spi_ctrlr_release_bus(const struct spi_slave *slave) clrbits_le32(®s->spi_cmd_reg, SPI_CMD_PAUSE_EN); spi_sw_reset(regs); mtk_slave->state = MTK_SPI_IDLE; + + gpio_output(mtk_slave->cs_gpio, 1); } static int spi_ctrlr_setup(const struct spi_slave *slave) diff --git a/src/soc/mediatek/common/uart.c b/src/soc/mediatek/common/uart.c index 8905c55528..0d4add8fca 100644 --- a/src/soc/mediatek/common/uart.c +++ b/src/soc/mediatek/common/uart.c @@ -172,17 +172,16 @@ void uart_tx_flush(int idx) mtk_uart_tx_flush(); } -#ifndef __PRE_RAM__ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = UART0_BASE; - serial.input_hertz = UART_HZ; serial.baud = get_uart_baudrate(); serial.regwidth = 4; + serial.input_hertz = UART_HZ; + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } -#endif diff --git a/src/soc/mediatek/common/usb.c b/src/soc/mediatek/common/usb.c index dcb93073b7..328bf66e0f 100644 --- a/src/soc/mediatek/common/usb.c +++ b/src/soc/mediatek/common/usb.c @@ -76,6 +76,10 @@ static void phy_index_power_on(int index) /* Set USB 2.0 slew rate value */ clrsetbits_le32(&phy->u2phy.usbphyacr5, PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4)); + + /* Set USB 2.0 disconnect threshold */ + clrsetbits_le32(&phy->u2phy.usbphyacr6, + PA6_RG_U2_DISCTH, PA6_RG_U2_DISCTH_VAL(15)); } static void u3phy_power_on(void) diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 510fbf0cc5..8632affc7e 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -83,9 +83,7 @@ ramstage-y += ../common/rtc.c rtc.c ramstage-y += ../common/usb.c usb.c ramstage-y += ../common/ddp.c ddp.c -ramstage-y += dsi.c - -ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c +ramstage-y += ../common/dsi.c dsi.c BL31_MAKEARGS += PLAT=mt8173 diff --git a/src/soc/mediatek/mt8173/dsi.c b/src/soc/mediatek/mt8173/dsi.c index 5b96a582b7..b6ff0bc51f 100644 --- a/src/soc/mediatek/mt8173/dsi.c +++ b/src/soc/mediatek/mt8173/dsi.c @@ -13,21 +13,19 @@ * GNU General Public License for more details. */ +#include #include #include #include -#include #include #include -static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes, - const struct edid *edid) +void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes) { u32 txdiv0, txdiv1; u64 pcw; u32 reg; - u32 bit_per_pixel; - int i, data_rate, mipi_tx_rate; + int i; reg = read32(&mipi_tx0->dsi_bg_con); @@ -53,31 +51,6 @@ static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes, clrbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); - switch (format) { - case MIPI_DSI_FMT_RGB565: - bit_per_pixel = 16; - break; - case MIPI_DSI_FMT_RGB666: - case MIPI_DSI_FMT_RGB666_PACKED: - bit_per_pixel = 18; - break; - case MIPI_DSI_FMT_RGB888: - default: - bit_per_pixel = 24; - break; - } - - /** - * data_rate = (pixel_clock / 1000) * bit_per_pixel * mipi_ratio / lane_num - * pixel_clock unit is Khz, data_rata unit is MHz, so need divide 1000. - * mipi_ratio is mipi clk coefficient for balance the pixel clk in mipi. - * we set mipi_ratio is 1.02. - * lane_num - */ - data_rate = edid->mode.pixel_clock * 102 * bit_per_pixel / - (lanes * 1000 * 100); - mipi_tx_rate = data_rate; - if (data_rate > 500) { txdiv0 = 0; txdiv1 = 0; @@ -90,14 +63,11 @@ static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes, } else if (data_rate >= 62) { txdiv0 = 2; txdiv1 = 1; - } else if (data_rate >= 50) { + } else { + /* MIN = 50 */ + assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ); txdiv0 = 2; txdiv1 = 2; - } else { - printk(BIOS_ERR, "data rate (%u) must be >=50. Please check " - "pixel clock (%u), bpp (%u), and number of lanes (%u)\n", - data_rate, edid->mode.pixel_clock, bit_per_pixel, lanes); - return -1; } clrsetbits_le32(&mipi_tx0->dsi_pll_con0, @@ -129,184 +99,31 @@ static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes, clrbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN); clrbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN); - - return mipi_tx_rate; } -static void mtk_dsi_phy_timconfig(u32 data_rate) -{ - u32 timcon0, timcon1, timcon2, timcon3; - u32 cycle_time, ui, lpx; - - ui = 1000 / data_rate + 0x01; - cycle_time = 8000 / data_rate + 0x01; - lpx = 5; - - timcon0 = (8 << 24) | (0xa << 16) | (0x6 << 8) | lpx; - timcon1 = (7 << 24) | (5 * lpx << 16) | ((3 * lpx) / 2) << 8 | - (4 * lpx); - timcon2 = ((DIV_ROUND_UP(0x64, cycle_time) + 0xa) << 24) | - (DIV_ROUND_UP(0x150, cycle_time) << 16); - timcon3 = (2 * lpx) << 16 | - DIV_ROUND_UP(80 + 52 * ui, cycle_time) << 8 | - DIV_ROUND_UP(0x40, cycle_time); - - write32(&dsi0->dsi_phy_timecon0, timcon0); - write32(&dsi0->dsi_phy_timecon1, timcon1); - write32(&dsi0->dsi_phy_timecon2, timcon2); - write32(&dsi0->dsi_phy_timecon3, timcon3); -} - -static void mtk_dsi_reset(void) +void mtk_dsi_reset(void) { setbits_le32(&dsi0->dsi_con_ctrl, 3); clrbits_le32(&dsi0->dsi_con_ctrl, 1); } -static void mtk_dsi_clk_hs_mode_enable(void) +void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing) { - setbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN); -} + int lpx = 5; + timing->lpx = lpx; + timing->da_hs_prepare = 6; + timing->da_hs_zero = 10; + timing->da_hs_trail = 8; -static void mtk_dsi_clk_hs_mode_disable(void) -{ - clrbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN); -} + timing->ta_go = 4 * lpx; + timing->ta_sure = 3 * lpx / 2; + timing->ta_get = 5 * lpx; + timing->da_hs_exit = 7; -static void mtk_dsi_set_mode(u32 mode_flags) -{ - u32 tmp_reg1 = 0; + timing->da_hs_sync = 0; + timing->clk_hs_exit = 2 * lpx; - if (mode_flags & MIPI_DSI_MODE_VIDEO) { - tmp_reg1 = SYNC_PULSE_MODE; - - if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) - tmp_reg1 = BURST_MODE; - - if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) - tmp_reg1 = SYNC_PULSE_MODE; - } - - write32(&dsi0->dsi_mode_ctrl, tmp_reg1); -} - -static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes) -{ - u32 tmp_reg = 0; - - switch (lanes) { - case 1: - tmp_reg = 1 << 2; - break; - case 2: - tmp_reg = 3 << 2; - break; - case 3: - tmp_reg = 7 << 2; - break; - case 4: - default: - tmp_reg = 0xf << 2; - break; - } - - tmp_reg |= (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; - tmp_reg |= (mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; - - write32(&dsi0->dsi_txrx_ctrl, tmp_reg); -} - -static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, - const struct edid *edid) -{ - u32 hsync_active_byte; - u32 hbp_byte; - u32 hfp_byte; - u32 vbp_byte; - u32 vfp_byte; - u32 bpp; - u32 packet_fmt; - u32 hactive; - - if (format == MIPI_DSI_FMT_RGB565) - bpp = 2; - else - bpp = 3; - - vbp_byte = edid->mode.vbl - edid->mode.vso - edid->mode.vspw - - edid->mode.vborder; - vfp_byte = edid->mode.vso - edid->mode.vborder; - - write32(&dsi0->dsi_vsa_nl, edid->mode.vspw); - write32(&dsi0->dsi_vbp_nl, vbp_byte); - write32(&dsi0->dsi_vfp_nl, vfp_byte); - write32(&dsi0->dsi_vact_nl, edid->mode.va); - - if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) - hbp_byte = (edid->mode.hbl - edid->mode.hso - edid->mode.hspw - - edid->mode.hborder) * bpp - 10; - else - hbp_byte = (edid->mode.hbl - edid->mode.hso - - edid->mode.hborder) * bpp - 10; - - hsync_active_byte = edid->mode.hspw * bpp - 10; - hfp_byte = (edid->mode.hso - edid->mode.hborder) * bpp - 12; - - write32(&dsi0->dsi_hsa_wc, hsync_active_byte); - write32(&dsi0->dsi_hbp_wc, hbp_byte); - write32(&dsi0->dsi_hfp_wc, hfp_byte); - - switch (format) { - case MIPI_DSI_FMT_RGB888: - packet_fmt = PACKED_PS_24BIT_RGB888; - break; - case MIPI_DSI_FMT_RGB666: - packet_fmt = LOOSELY_PS_18BIT_RGB666; - break; - case MIPI_DSI_FMT_RGB666_PACKED: - packet_fmt = PACKED_PS_18BIT_RGB666; - break; - case MIPI_DSI_FMT_RGB565: - packet_fmt = PACKED_PS_16BIT_RGB565; - break; - default: - packet_fmt = PACKED_PS_24BIT_RGB888; - break; - } - - hactive = edid->mode.ha; - packet_fmt |= (hactive * bpp) & DSI_PS_WC; - - write32(&dsi0->dsi_psctrl, packet_fmt); -} - -static void mtk_dsi_start(void) -{ - write32(&dsi0->dsi_start, 0); - /* Only start master DSI */ - write32(&dsi0->dsi_start, 1); -} - -int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid) -{ - int data_rate; - - data_rate = mtk_dsi_phy_clk_setting(format, lanes, edid); - - if (data_rate < 0) - return -1; - - mtk_dsi_reset(); - mtk_dsi_phy_timconfig(data_rate); - mtk_dsi_rxtx_control(mode_flags, lanes); - mtk_dsi_clk_hs_mode_disable(); - mtk_dsi_config_vdo_timing(mode_flags, format, edid); - mtk_dsi_set_mode(mode_flags); - mtk_dsi_clk_hs_mode_enable(); - - mtk_dsi_start(); - - return 0; + timing->d_phy = 12; } void mtk_dsi_pin_drv_ctrl(void) diff --git a/src/soc/mediatek/mt8173/include/soc/dsi.h b/src/soc/mediatek/mt8173/include/soc/dsi.h index 967ed4d27e..e7c1d28b1f 100644 --- a/src/soc/mediatek/mt8173/include/soc/dsi.h +++ b/src/soc/mediatek/mt8173/include/soc/dsi.h @@ -16,183 +16,16 @@ #ifndef _DSI_REG_H_ #define _DSI_REG_H_ -#include -#include +#include -enum mipi_dsi_pixel_format { - MIPI_DSI_FMT_RGB888, - MIPI_DSI_FMT_RGB666, - MIPI_DSI_FMT_RGB666_PACKED, - MIPI_DSI_FMT_RGB565 -}; +/* DSI features */ +#define MTK_DSI_MIPI_RATIO_NUMERATOR 102 +#define MTK_DSI_MIPI_RATIO_DENOMINATOR 100 +#define MTK_DSI_DATA_RATE_MIN_MHZ 50 +#define MTK_DSI_HAVE_SIZE_CON 0 +#define PIXEL_STREAM_CUSTOM_HEADER 0 -/* video mode */ -enum { - MIPI_DSI_MODE_VIDEO = BIT(0), - /* video burst mode */ - MIPI_DSI_MODE_VIDEO_BURST = BIT(1), - /* video pulse mode */ - MIPI_DSI_MODE_VIDEO_SYNC_PULSE = BIT(2), - /* enable auto vertical count mode */ - MIPI_DSI_MODE_VIDEO_AUTO_VERT = BIT(3), - /* enable hsync-end packets in vsync-pulse and v-porch area */ - MIPI_DSI_MODE_VIDEO_HSE = BIT(4), - /* disable hfront-porch area */ - MIPI_DSI_MODE_VIDEO_HFP = BIT(5), - /* disable hback-porch area */ - MIPI_DSI_MODE_VIDEO_HBP = BIT(6), - /* disable hsync-active area */ - MIPI_DSI_MODE_VIDEO_HSA = BIT(7), - /* flush display FIFO on vsync pulse */ - MIPI_DSI_MODE_VSYNC_FLUSH = BIT(8), - /* disable EoT packets in HS mode */ - MIPI_DSI_MODE_EOT_PACKET = BIT(9), - /* device supports non-continuous clock behavior (DSI spec 5.6.1) */ - MIPI_DSI_CLOCK_NON_CONTINUOUS = BIT(10), - /* transmit data in low power */ - MIPI_DSI_MODE_LPM = BIT(11) -}; - -struct dsi_regs { - u32 dsi_start; - u8 reserved0[4]; - u32 dsi_inten; - u32 dsi_intsta; - u32 dsi_con_ctrl; - u32 dsi_mode_ctrl; - u32 dsi_txrx_ctrl; - u32 dsi_psctrl; - u32 dsi_vsa_nl; - u32 dsi_vbp_nl; - u32 dsi_vfp_nl; - u32 dsi_vact_nl; - u8 reserved1[32]; - u32 dsi_hsa_wc; - u32 dsi_hbp_wc; - u32 dsi_hfp_wc; - u32 dsi_bllp_wc; - u32 dsi_cmdq_size; - u32 dsi_hstx_cklp_wc; - u8 reserved2[156]; - u32 dsi_phy_lccon; - u32 dsi_phy_ld0con; - u8 reserved3[4]; - u32 dsi_phy_timecon0; - u32 dsi_phy_timecon1; - u32 dsi_phy_timecon2; - u32 dsi_phy_timecon3; - u8 reserved4[16]; - u32 dsi_vm_cmd_con; - u8 reserved5[204]; - u32 dsi_cmdq0; -}; - -check_member(dsi_regs, dsi_phy_lccon, 0x104); -check_member(dsi_regs, dsi_phy_timecon3, 0x11c); -check_member(dsi_regs, dsi_vm_cmd_con, 0x130); -check_member(dsi_regs, dsi_cmdq0, 0x200); -static struct dsi_regs *const dsi0 = (void *)DSI0_BASE; -static struct dsi_regs *const dsi1 = (void *)DSI1_BASE; - -/* DSI_INTSTA */ -enum { - LPRX_RD_RDY_INT_FLAG = BIT(0), - CMD_DONE_INT_FLAG = BIT(1), - TE_RDY_INT_FLAG = BIT(2), - VM_DONE_INT_FLAG = BIT(3), - EXT_TE_RDY_INT_FLAG = BIT(4), - DSI_BUSY = BIT(31), -}; - -/* DSI_CON_CTRL */ -enum { - DSI_RESET = BIT(0), - DSI_EN = BIT(1), - DSI_DUAL = BIT(4), -}; - -/* DSI_MODE_CTRL */ -enum { - MODE = 3, - CMD_MODE = 0, - SYNC_PULSE_MODE = 1, - SYNC_EVENT_MODE = 2, - BURST_MODE = 3, - FRM_MODE = BIT(16), - MIX_MODE = BIT(17) -}; - -/* DSI_PSCTRL */ -enum { - DSI_PS_WC = 0x3fff, - DSI_PS_SEL = (3 << 16), - PACKED_PS_16BIT_RGB565 = (0 << 16), - LOOSELY_PS_18BIT_RGB666 = (1 << 16), - PACKED_PS_18BIT_RGB666 = (2 << 16), - PACKED_PS_24BIT_RGB888 = (3 << 16) -}; - -/* DSI_CMDQ_SIZE */ -enum { - CMDQ_SIZE = 0x3f, -}; - -/* DSI_PHY_LCCON */ -enum { - LC_HS_TX_EN = BIT(0), - LC_ULPM_EN = BIT(1), - LC_WAKEUP_EN = BIT(2) -}; - -/*DSI_PHY_LD0CON */ -enum { - LD0_RM_TRIG_EN = BIT(0), - LD0_ULPM_EN = BIT(1), - LD0_WAKEUP_EN = BIT(2) -}; - -enum { - LPX = (0xff << 0), - HS_PRPR = (0xff << 8), - HS_ZERO = (0xff << 16), - HS_TRAIL = (0xff << 24) -}; - -enum { - TA_GO = (0xff << 0), - TA_SURE = (0xff << 8), - TA_GET = (0xff << 16), - DA_HS_EXIT = (0xff << 24) -}; - -enum { - CONT_DET = (0xff << 0), - CLK_ZERO = (0xf << 16), - CLK_TRAIL = (0xff << 24) -}; - -enum { - CLK_HS_PRPR = (0xff << 0), - CLK_HS_POST = (0xff << 8), - CLK_HS_EXIT = (0xf << 16) -}; - -/* DSI_VM_CMD_CON */ -enum { - VM_CMD_EN = BIT(0), - TS_VFP_EN = BIT(5), -}; - -/* DSI_CMDQ0 */ -enum { - CONFIG = (0xff << 0), - SHORT_PACKET = 0, - LONG_PACKET = 2, - BTA = BIT(2), - DATA_ID = (0xff << 8), - DATA_0 = (0xff << 16), - DATA_1 = (0xff << 24), -}; +/* MIPITX is SOC specific and cannot live in common. */ /* MIPITX_REG */ struct mipi_tx_regs { @@ -336,114 +169,7 @@ enum { RG_DA_LVDSTX_PWR_ON = BIT(9) }; -/* MIPI DSI Processor-to-Peripheral transaction types */ -enum { - MIPI_DSI_V_SYNC_START = 0x01, - MIPI_DSI_V_SYNC_END = 0x11, - MIPI_DSI_H_SYNC_START = 0x21, - MIPI_DSI_H_SYNC_END = 0x31, - - MIPI_DSI_COLOR_MODE_OFF = 0x02, - MIPI_DSI_COLOR_MODE_ON = 0x12, - MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22, - MIPI_DSI_TURN_ON_PERIPHERAL = 0x32, - - MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03, - MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13, - MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23, - - MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04, - MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14, - MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24, - - MIPI_DSI_DCS_SHORT_WRITE = 0x05, - MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15, - - MIPI_DSI_DCS_READ = 0x06, - - MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, - - MIPI_DSI_END_OF_TRANSMISSION = 0x08, - - MIPI_DSI_NULL_PACKET = 0x09, - MIPI_DSI_BLANKING_PACKET = 0x19, - MIPI_DSI_GENERIC_LONG_WRITE = 0x29, - MIPI_DSI_DCS_LONG_WRITE = 0x39, - - MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c, - - MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d, - MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d, - - MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e, - MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e, - MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e, - MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e, -}; - -/* MIPI DSI Peripheral-to-Processor transaction types */ -enum { - MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02, - MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08, - MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11, - MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12, - MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a, - MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c, - MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21, - MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22, -}; - -/* MIPI DCS commands */ -enum { - MIPI_DCS_NOP = 0x00, - MIPI_DCS_SOFT_RESET = 0x01, - MIPI_DCS_GET_DISPLAY_ID = 0x04, - MIPI_DCS_GET_RED_CHANNEL = 0x06, - MIPI_DCS_GET_GREEN_CHANNEL = 0x07, - MIPI_DCS_GET_BLUE_CHANNEL = 0x08, - MIPI_DCS_GET_DISPLAY_STATUS = 0x09, - MIPI_DCS_GET_POWER_MODE = 0x0A, - MIPI_DCS_GET_ADDRESS_MODE = 0x0B, - MIPI_DCS_GET_PIXEL_FORMAT = 0x0C, - MIPI_DCS_GET_DISPLAY_MODE = 0x0D, - MIPI_DCS_GET_SIGNAL_MODE = 0x0E, - MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F, - MIPI_DCS_ENTER_SLEEP_MODE = 0x10, - MIPI_DCS_EXIT_SLEEP_MODE = 0x11, - MIPI_DCS_ENTER_PARTIAL_MODE = 0x12, - MIPI_DCS_ENTER_NORMAL_MODE = 0x13, - MIPI_DCS_EXIT_INVERT_MODE = 0x20, - MIPI_DCS_ENTER_INVERT_MODE = 0x21, - MIPI_DCS_SET_GAMMA_CURVE = 0x26, - MIPI_DCS_SET_DISPLAY_OFF = 0x28, - MIPI_DCS_SET_DISPLAY_ON = 0x29, - MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A, - MIPI_DCS_SET_PAGE_ADDRESS = 0x2B, - MIPI_DCS_WRITE_MEMORY_START = 0x2C, - MIPI_DCS_WRITE_LUT = 0x2D, - MIPI_DCS_READ_MEMORY_START = 0x2E, - MIPI_DCS_SET_PARTIAL_AREA = 0x30, - MIPI_DCS_SET_SCROLL_AREA = 0x33, - MIPI_DCS_SET_TEAR_OFF = 0x34, - MIPI_DCS_SET_TEAR_ON = 0x35, - MIPI_DCS_SET_ADDRESS_MODE = 0x36, - MIPI_DCS_SET_SCROLL_START = 0x37, - MIPI_DCS_EXIT_IDLE_MODE = 0x38, - MIPI_DCS_ENTER_IDLE_MODE = 0x39, - MIPI_DCS_SET_PIXEL_FORMAT = 0x3A, - MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C, - MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E, - MIPI_DCS_SET_TEAR_SCANLINE = 0x44, - MIPI_DCS_GET_SCANLINE = 0x45, - MIPI_DCS_READ_DDB_START = 0xA1, - MIPI_DCS_READ_DDB_CONTINUE = 0xA8, -}; - -int mtk_dsi_init(u32 mode_flags, enum mipi_dsi_pixel_format format, u32 lanes, - const struct edid *edid); +/* SOC specific functions */ void mtk_dsi_pin_drv_ctrl(void); #endif diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index d0094418b8..cf2ffa264b 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -24,6 +24,7 @@ struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = { { .regs = (void *)SPI_BASE, + .cs_gpio = GPIO(MSDC2_CMD), } }; @@ -35,7 +36,7 @@ void mtk_spi_set_gpio_pinmux(unsigned int bus, gpio_set_mode(GPIO(MSDC2_DAT2), PAD_MSDC2_DAT2_FUNC_SPI_CK_1); gpio_set_mode(GPIO(MSDC2_DAT3), PAD_MSDC2_DAT3_FUNC_SPI_MI_1); gpio_set_mode(GPIO(MSDC2_CLK), PAD_MSDC2_CLK_FUNC_SPI_MO_1); - gpio_set_mode(GPIO(MSDC2_CMD), PAD_MSDC2_CMD_FUNC_SPI_CS_1); + gpio_set_mode(GPIO(MSDC2_CMD), 0); } void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, diff --git a/src/soc/mediatek/mt8183/Kconfig b/src/soc/mediatek/mt8183/Kconfig index c60cdea38d..5ded0d3801 100644 --- a/src/soc/mediatek/mt8183/Kconfig +++ b/src/soc/mediatek/mt8183/Kconfig @@ -15,6 +15,7 @@ config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE config DEBUG_DRAM bool "Output verbose DRAM related debug messages" @@ -22,6 +23,13 @@ config DEBUG_DRAM help This option enables additional DRAM related debug messages. +config MT8183_DRAM_EMCP + bool + default n + help + The eMCP platform should select this option to run at different DRAM + frequencies. + config MEMORY_TEST bool default y diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 45276835af..b6c3a33819 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -46,6 +46,7 @@ romstage-y += ../common/wdt.c ramstage-y += auxadc.c ramstage-y += ../common/cbmem.c emi.c ramstage-y += ../common/ddp.c ddp.c +ramstage-y += ../common/dsi.c dsi.c ramstage-y += ../common/gpio.c gpio.c ramstage-y += ../common/i2c.c i2c.c ramstage-y += ../common/mmu_operations.c mmu_operations.c @@ -66,6 +67,8 @@ sspm.bin-file := 3rdparty/blobs/soc/mediatek/mt8183/sspm.bin sspm.bin-type := raw sspm.bin-compression := $(CBFS_COMPRESS_FLAG) +BL31_MAKEARGS += PLAT=mt8183 + CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index 09bec0108e..b8491d3360 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -13,1086 +13,1710 @@ * GNU General Public License for more details. */ +#include #include #include #include #include #include #include +#include +#include -struct reg_init_value { - u32 *addr; - u32 value; +enum { + CKE_FIXOFF = 0, + CKE_FIXON, + CKE_DYNAMIC }; -static struct reg_init_value dramc_init_sequence[] = { - {&mt8183_infracfg->dramc_wbr, 0x00000000}, - {&ch[0].ao.refctrl0, 0x20712000}, - {&ch[1].ao.refctrl0, 0x20712000}, - {&ch[0].ao.ckectrl, 0x00100480}, - {&ch[1].ao.ckectrl, 0x00100480}, - {&ch[0].phy.ckmux_sel, 0x00000003}, - {&ch[1].phy.ckmux_sel, 0x00000003}, - {&mt8183_infracfg->dramc_wbr, 0x0000001f}, - {&ch[0].phy.misc_cg_ctrl0, 0x00000101}, - {&ch[0].phy.misc_ctrl0, 0x38010000}, - {&ch[0].phy.misc_spm_ctrl1, 0x00000000}, - {&ch[0].phy.misc_spm_ctrl2, 0x00000000}, - {&ch[0].phy.misc_spm_ctrl0, 0x00000000}, - {&ch[0].phy.misc_cg_ctrl2, 0x006003bf}, - {&ch[0].phy.misc_cg_ctrl4, 0x333f3f00}, - {&ch[0].phy.shu[0].pll[1], 0x0000001f}, - {&ch[0].phy.shu[0].b[0].dq[7], 0x00000010}, - {&ch[0].phy.shu[0].b[1].dq[7], 0x00000000}, - {&ch[0].phy.shu[0].pll[4], 0xe57800ff}, - {&ch[0].phy.shu[0].pll[6], 0xe57800ff}, - {&ch[0].phy.shu[0].pll[14], 0x00000000}, - {&ch[0].phy.shu[0].pll20, 0x00000000}, - {&ch[0].phy.ca_cmd[2], 0x00000000}, - {&ch[0].phy.b[0].dq[2], 0x00000000}, - {&ch[0].phy.b[1].dq[2], 0x00000000}, - {&ch[0].phy.b[0].dq[9], 0x10000000}, - {&ch[0].phy.b[1].dq[9], 0x10000000}, - {&ch[0].phy.ca_cmd[10], 0x00000000}, - {&ch[0].phy.b0_rxdvs[0], 0x10000022}, - {&ch[0].phy.b1_rxdvs[0], 0x10000022}, - {&ch[0].phy.b0_rxdvs[0], 0x10000222}, - {&ch[0].phy.b1_rxdvs[0], 0x10000222}, - {&ch[0].phy.r[0].b[0].rxdvs[2], 0x20000000}, - {&ch[0].phy.r[1].b[0].rxdvs[2], 0x20000000}, - {&ch[0].phy.shu[0].b[0].dq[5], 0x0030000e}, - {&ch[0].phy.r[0].b[0].rxdvs[1], 0x00020002}, - {&ch[0].phy.r[0].b[0].rxdvs[2], 0xb0800000}, - {&ch[0].phy.r[1].b[0].rxdvs[1], 0x00020002}, - {&ch[0].phy.r[1].b[0].rxdvs[2], 0xb0800000}, - {&ch[0].phy.r[0].b[1].rxdvs[2], 0x20000000}, - {&ch[0].phy.r[1].b[1].rxdvs[2], 0x20000000}, - {&ch[0].phy.shu[0].b[1].dq[5], 0x0030000e}, - {&ch[0].phy.r[0].b[1].rxdvs[1], 0x00020002}, - {&ch[0].phy.r[0].b[1].rxdvs[2], 0xb0800000}, - {&ch[0].phy.r[1].b[1].rxdvs[1], 0x00020002}, - {&ch[0].phy.r[1].b[1].rxdvs[2], 0xb0800000}, - {&ch[0].phy.b0_rxdvs[0], 0x00000222}, - {&ch[0].phy.b1_rxdvs[0], 0x00000222}, - {&ch[0].phy.b[0].dq[9], 0x10000001}, - {&ch[0].phy.shu[0].rk[0].b[0].dq[7], 0x001f1f00}, - {&ch[0].phy.shu[0].rk[1].b[0].dq[7], 0x001f1f00}, - {&ch[0].phy.b[0].dq[4], 0x00001010}, - {&ch[0].phy.b[0].dq[5], 0x00110e10}, - {&ch[0].phy.b[0].dq[6], 0x010310c0}, - {&ch[0].phy.b[0].dq[5], 0x02110e00}, - {&ch[0].phy.b[1].dq[9], 0x10000001}, - {&ch[0].phy.shu[0].rk[0].b[1].dq[7], 0x001f1f00}, - {&ch[0].phy.shu[0].rk[1].b[1].dq[7], 0x001f1f00}, - {&ch[0].phy.b[1].dq[4], 0x00001010}, - {&ch[0].phy.b[1].dq[5], 0x00110e10}, - {&ch[0].phy.b[1].dq[6], 0x010310c0}, - {&ch[0].phy.b[1].dq[5], 0x02110e00}, - {&ch[0].phy.ca_cmd[3], 0x0000008c}, - {&ch[0].phy.ca_cmd[6], 0x00020000}, - {&ch[0].phy.pll3, 0x00000011}, - {&ch[0].phy.b[0].dq[3], 0x00000008}, - {&ch[0].phy.b[1].dq[3], 0x00000008}, - {&ch[0].phy.shu[0].pll[8], 0x00040000}, - {&ch[0].phy.shu[0].pll[9], 0x00000000}, - {&ch[0].phy.shu[0].pll[11], 0x00000000}, - {&ch[0].phy.shu[0].pll[10], 0x00040000}, - {&ch[0].phy.pll4, 0x000c0000}, - {&ch[0].phy.shu[0].pll[0], 0x00000003}, - {&ch[0].phy.ca_dll_fine_tune[1], 0x00200000}, - {&ch[0].phy.b[0].dq[3], 0x0000040e}, - {&ch[0].phy.b[1].dq[3], 0x0000040e}, - {&mt8183_infracfg->dramc_wbr, 0x00000000}, - {&ch[0].phy.shu[0].ca_dll[0], 0x00666009}, - {&ch[1].phy.shu[0].ca_dll[0], 0x00666009}, - {&mt8183_infracfg->dramc_wbr, 0x0000001f}, - {&ch[0].phy.shu[0].b[0].dll[0], 0xc0778608}, - {&ch[0].phy.shu[0].b[1].dll[0], 0xc0778608}, - {&ch[0].phy.shu[0].ca_cmd[5], 0x00000000}, - {&ch[0].phy.shu[0].ca_cmd[0], 0x00104010}, - {&mt8183_infracfg->dramc_wbr, 0x00000000}, - {&ch[0].phy.shu[0].ca_cmd[6], 0x000000c0}, - {&ch[1].phy.shu[0].ca_cmd[6], 0x00000040}, - {&mt8183_infracfg->dramc_wbr, 0x0000001f}, - {&ch[0].phy.shu[0].b[0].dq[6], 0x00000040}, - {&ch[0].phy.shu[0].b[1].dq[6], 0x00000040}, - {&mt8183_infracfg->dramc_wbr, 0x00000000}, - {&ch[0].phy.misc_shu_opt, 0x00050909}, - {&ch[1].phy.misc_shu_opt, 0x00090909}, - {&ch[0].phy.shu[0].ca_dll[1], 0x00090004}, - {&ch[1].phy.shu[0].ca_dll[1], 0x00090001}, - {&mt8183_infracfg->dramc_wbr, 0x0000001f}, - {&ch[0].phy.shu[0].b[0].dll[1], 0x00000001}, - {&ch[0].phy.shu[0].b[1].dll[1], 0x00000001}, - {&ch[0].phy.pll2, 0x00000000}, - {&ch[0].phy.misc_cg_ctrl0, 0x0000000f}, - {&mt8183_infracfg->dramc_wbr, 0x00000000}, - {&ch[0].phy.shu[0].ca_cmd[6], 0x000604c0}, - {&ch[1].phy.shu[0].ca_cmd[6], 0x00060440}, - {&ch[0].phy.shu[0].ca_dll[1], 0x0004e104}, - {&ch[0].phy.shu[0].b[0].dq[6], 0x00060440}, - {&ch[0].phy.shu[0].b[0].dll[1], 0x00022401}, - {&ch[0].phy.shu[0].b[1].dq[6], 0x00060440}, - {&ch[0].phy.shu[0].b[1].dll[1], 0x00022401}, - {&ch[1].phy.shu[0].ca_dll[1], 0x0004e101}, - {&ch[1].phy.shu[0].b[0].dq[6], 0x00060440}, - {&ch[1].phy.shu[0].b[0].dll[1], 0x00022401}, - {&ch[1].phy.shu[0].b[1].dq[6], 0x00060440}, - {&ch[1].phy.shu[0].b[1].dll[1], 0x00022401}, - {&ch[0].phy.shu[0].pll[4], 0xe5780000}, - {&ch[0].phy.shu[0].pll[6], 0xe5780000}, - {&ch[0].phy.misc_shu_opt, 0x00050909}, - {&ch[0].phy.ckmux_sel, 0x00000003}, - {&ch[0].phy.shu[0].ca_cmd[0], 0x00144010}, - {&ch[0].ao.dvfsdll, 0x00000000}, - {&ch[0].phy.shu[0].ca_dll[0], 0x00698619}, - {&ch[0].phy.shu[0].ca_dll[1], 0x0004e104}, - {&ch[0].phy.shu[0].ca_cmd[6], 0x000604c0}, - {&ch[0].phy.b[0].dq[7], 0x00000055}, - {&ch[0].phy.b[1].dq[7], 0x00000055}, - {&ch[0].phy.ca_cmd[7], 0x00000055}, - {&ch[0].phy.ca_cmd[2], 0x00200000}, - {&ch[0].phy.misc_cg_ctrl0, 0x0000000f}, - {&ch[0].phy.shu[0].b[0].dq[6], 0x00060440}, - {&ch[0].phy.shu[0].b[1].dq[6], 0x00060440}, - {&ch[0].phy.shu[0].ca_cmd[6], 0x000604c0}, - {&ch[0].phy.pll4, 0x000c0000}, - {&ch[0].phy.pll1, 0x00000000}, - {&ch[0].phy.pll2, 0x00000000}, - {&ch[0].phy.ca_dll_fine_tune[2], 0x00000000}, - {&ch[0].phy.b[0].dll_fine_tune[2], 0x00000000}, - {&ch[0].phy.b[1].dll_fine_tune[2], 0x00000000}, - {&ch[0].phy.b[0].dll_fine_tune[2], 0x880aec00}, - {&ch[0].phy.b[1].dll_fine_tune[2], 0x880aec00}, - {&ch[0].phy.ca_dll_fine_tune[2], 0x880bac00}, - {&ch[0].phy.ca_dll_fine_tune[0], 0x00000000}, - {&ch[0].phy.b[0].dll_fine_tune[0], 0x00000000}, - {&ch[0].phy.b[1].dll_fine_tune[0], 0x00000000}, - {&ch[0].phy.shu[0].pll[8], 0x00040000}, - {&ch[0].phy.shu[0].pll[10], 0x00040000}, - {&ch[0].phy.shu[0].pll[5], 0x7b000002}, - {&ch[0].phy.shu[0].pll[7], 0x7b000002}, - {&ch[0].phy.ca_dll_fine_tune[0], 0x00000002}, - {&ch[0].phy.b[0].dll_fine_tune[0], 0x00000002}, - {&ch[0].phy.b[1].dll_fine_tune[0], 0x00000002}, - {&ch[0].phy.ca_dll_fine_tune[1], 0x00200000}, - {&ch[0].phy.b[0].dll_fine_tune[1], 0x00000000}, - {&ch[0].phy.b[1].dll_fine_tune[1], 0x00000000}, - {&ch[0].phy.shu[0].b[0].dq[6], 0x02860440}, - {&ch[0].phy.shu[0].b[1].dq[6], 0x02860440}, - {&ch[0].phy.shu[0].ca_cmd[6], 0x028604c0}, - {&ch[0].phy.ca_dll_fine_tune[0], 0x0000000a}, - {&ch[0].phy.b[0].dll_fine_tune[0], 0x0000000a}, - {&ch[0].phy.b[1].dll_fine_tune[0], 0x0000000a}, - {&ch[0].phy.pll1, 0x80000000}, - {&ch[0].phy.pll2, 0x80000000}, - {&ch[0].phy.pll4, 0x004d0000}, - {&ch[0].phy.shu[0].b[0].dq[6], 0x06860440}, - {&ch[0].phy.shu[0].b[1].dq[6], 0x06860440}, - {&ch[0].phy.shu[0].ca_cmd[6], 0x068604c0}, - {&ch[0].phy.ca_dll_fine_tune[3], 0x000ba000}, - {&ch[0].phy.b[0].dll_fine_tune[3], 0x0002e800}, - {&ch[0].phy.b[1].dll_fine_tune[3], 0x0002e800}, - {&ch[0].phy.ca_dll_fine_tune[2], 0x00000800}, - {&ch[0].phy.b[0].dll_fine_tune[2], 0x00000800}, - {&ch[0].phy.b[1].dll_fine_tune[2], 0x00000800}, - {&ch[0].phy.ca_dll_fine_tune[2], 0x00000800}, - {&ch[0].phy.b[0].dll_fine_tune[2], 0x00000000}, - {&ch[0].phy.b[1].dll_fine_tune[2], 0x00000000}, - {&ch[0].phy.misc_cg_ctrl0, 0x0000001f}, - {&ch[0].phy.ca_dll_fine_tune[2], 0x00000801}, - {&ch[0].phy.b[0].dll_fine_tune[2], 0x00000001}, - {&ch[0].phy.b[1].dll_fine_tune[2], 0x00000001}, - {&ch[0].phy.ca_cmd[2], 0x00000000}, - {&ch[0].phy.b[0].dq[7], 0x00000040}, - {&ch[0].phy.b[1].dq[7], 0x00000040}, - {&ch[0].phy.ca_cmd[7], 0x00000040}, - {&ch[0].ao.ckectrl, 0x00100400}, - {&ch[1].ao.ckectrl, 0x00100400}, - {&ch[0].phy.shu[0].pll[5], 0x7b000003}, - {&ch[0].phy.shu[0].pll[7], 0x7b000003}, - {&ch[0].phy.shu[0].pll[14], 0x00000002}, - {&ch[0].phy.shu[0].pll20, 0x00000002}, - {&ch[0].phy.shu[0].pll[14], 0x02080002}, - {&ch[0].phy.shu[0].pll20, 0x02080002}, - {&ch[0].phy.shu[0].pll[15], 0x0c030000}, - {&ch[0].phy.shu[0].pll21, 0x0c030000}, - {&ch[1].phy.shu[0].pll[4], 0x00000000}, - {&ch[1].phy.shu[0].pll[6], 0x00000000}, - {&ch[1].phy.misc_shu_opt, 0x00090909}, - {&ch[1].phy.ckmux_sel, 0x00000003}, - {&ch[1].phy.shu[0].ca_cmd[0], 0x00144010}, - {&ch[1].ao.dvfsdll, 0x00000000}, - {&ch[1].phy.shu[0].ca_dll[0], 0xc0778609}, - {&ch[1].phy.shu[0].ca_dll[1], 0x0004e101}, - {&ch[1].phy.shu[0].ca_cmd[6], 0x00060440}, - {&ch[1].phy.b[0].dq[7], 0x00000055}, - {&ch[1].phy.b[1].dq[7], 0x00000055}, - {&ch[1].phy.ca_cmd[7], 0x00000055}, - {&ch[1].phy.ca_cmd[2], 0x00200000}, - {&ch[1].phy.misc_cg_ctrl0, 0x0000000f}, - {&ch[1].phy.shu[0].b[0].dq[6], 0x00060440}, - {&ch[1].phy.shu[0].b[1].dq[6], 0x00060440}, - {&ch[1].phy.shu[0].ca_cmd[6], 0x00060440}, - {&ch[1].phy.pll4, 0x00000000}, - {&ch[1].phy.pll1, 0x00000000}, - {&ch[1].phy.pll2, 0x00000000}, - {&ch[1].phy.ca_dll_fine_tune[2], 0x00000000}, - {&ch[1].phy.b[0].dll_fine_tune[2], 0x00000000}, - {&ch[1].phy.b[1].dll_fine_tune[2], 0x00000000}, - {&ch[1].phy.b[0].dll_fine_tune[2], 0x880aec00}, - {&ch[1].phy.b[1].dll_fine_tune[2], 0x880aec00}, - {&ch[1].phy.ca_dll_fine_tune[2], 0x880bac00}, - {&ch[1].phy.ca_dll_fine_tune[0], 0x00000000}, - {&ch[1].phy.b[0].dll_fine_tune[0], 0x00000000}, - {&ch[1].phy.b[1].dll_fine_tune[0], 0x00000000}, - {&ch[1].phy.shu[0].pll[8], 0x00040000}, - {&ch[1].phy.shu[0].pll[10], 0x00040000}, - {&ch[1].phy.shu[0].pll[5], 0x7b000000}, - {&ch[1].phy.shu[0].pll[7], 0x7b000000}, - {&ch[1].phy.ca_dll_fine_tune[0], 0x00000002}, - {&ch[1].phy.b[0].dll_fine_tune[0], 0x00000002}, - {&ch[1].phy.b[1].dll_fine_tune[0], 0x00000002}, - {&ch[1].phy.ca_dll_fine_tune[1], 0x00200000}, - {&ch[1].phy.b[0].dll_fine_tune[1], 0x00000000}, - {&ch[1].phy.b[1].dll_fine_tune[1], 0x00000000}, - {&ch[1].phy.shu[0].b[0].dq[6], 0x02860440}, - {&ch[1].phy.shu[0].b[1].dq[6], 0x02860440}, - {&ch[1].phy.shu[0].ca_cmd[6], 0x02860440}, - {&ch[1].phy.ca_dll_fine_tune[0], 0x0000000a}, - {&ch[1].phy.b[0].dll_fine_tune[0], 0x0000000a}, - {&ch[1].phy.b[1].dll_fine_tune[0], 0x0000000a}, - {&ch[1].phy.pll1, 0x80000000}, - {&ch[1].phy.pll2, 0x80000000}, - {&ch[1].phy.pll4, 0x00410000}, - {&ch[1].phy.shu[0].b[0].dq[6], 0x06860440}, - {&ch[1].phy.shu[0].b[1].dq[6], 0x06860440}, - {&ch[1].phy.shu[0].ca_cmd[6], 0x06860440}, - {&ch[1].phy.ca_dll_fine_tune[3], 0x0003a000}, - {&ch[1].phy.b[0].dll_fine_tune[3], 0x0002e800}, - {&ch[1].phy.b[1].dll_fine_tune[3], 0x0002e800}, - {&ch[1].phy.ca_dll_fine_tune[2], 0x00000800}, - {&ch[1].phy.b[0].dll_fine_tune[2], 0x00000800}, - {&ch[1].phy.b[1].dll_fine_tune[2], 0x00000800}, - {&ch[1].phy.ca_dll_fine_tune[2], 0x00000800}, - {&ch[1].phy.b[0].dll_fine_tune[2], 0x00000000}, - {&ch[1].phy.b[1].dll_fine_tune[2], 0x00000000}, - {&ch[1].phy.misc_cg_ctrl0, 0x0000001f}, - {&ch[1].phy.ca_dll_fine_tune[2], 0x00000801}, - {&ch[1].phy.b[0].dll_fine_tune[2], 0x00000001}, - {&ch[1].phy.b[1].dll_fine_tune[2], 0x00000001}, - {&ch[1].phy.ca_cmd[2], 0x00000000}, - {&ch[1].phy.b[0].dq[7], 0x00000040}, - {&ch[1].phy.b[1].dq[7], 0x00000040}, - {&ch[1].phy.ca_cmd[7], 0x00000040}, - {&ch[0].ao.ckectrl, 0x00100400}, - {&ch[1].ao.ckectrl, 0x00100400}, - {&ch[1].phy.shu[0].pll[5], 0x00000001}, - {&ch[1].phy.shu[0].pll[7], 0x00000001}, - {&ch[1].phy.shu[0].pll[14], 0x00000002}, - {&ch[1].phy.shu[0].pll20, 0x00000002}, - {&ch[1].phy.shu[0].pll[14], 0x02080000}, - {&ch[1].phy.shu[0].pll20, 0x02080000}, - {&ch[1].phy.shu[0].pll[15], 0x0c030000}, - {&ch[1].phy.shu[0].pll21, 0x0c030000}, - {&mt8183_infracfg->dramc_wbr, 0x0000001f}, - {&ch[0].ao.drsctrl, 0x20080000}, - {&ch[0].ao.ckectrl, 0x08100400}, - {&ch[0].ao.dramctrl, 0x30822201}, - {&ch[0].ao.spcmdctrl, 0x200007d2}, - {&ch[0].phy.b[0].dq[9], 0x10000011}, - {&ch[0].phy.b[1].dq[9], 0x10000011}, - {&ch[0].ao.shu[0].rk[1].dqsien, 0x0f0f0f0f}, - {&ch[0].ao.stbcal1, 0x00014310}, - {&ch[0].ao.shu[0].dqsg_retry, 0x80200608}, - {&ch[0].ao.shu[0].drving[0], 0x14a5294a}, - {&ch[0].ao.shu[0].drving[1], 0x14a5294a}, - {&ch[0].ao.shu[0].drving[2], 0x14a5294a}, - {&ch[0].ao.shu[0].drving[3], 0x14a5294a}, - {&ch[0].ao.shuctrl2, 0x0001d00a}, - {&ch[0].ao.dvfsdll, 0x00000001}, - {&ch[0].ao.ddrconf0, 0x04109000}, - {&ch[0].ao.stbcal2, 0x70000010}, - {&ch[0].ao.stbcal2, 0x50000010}, - {&ch[0].ao.clkar, 0x020c0000}, - {&ch[0].phy.b[0].dq[9], 0x10100011}, - {&ch[0].phy.b[1].dq[9], 0x10100011}, - {&ch[0].phy.ca_cmd[10], 0x00000000}, - {&ch[0].phy.misc_ctrl0, 0xb901020f}, - {&ch[0].phy.misc_ctrl1, 0x8100908c}, - {&ch[1].phy.misc_ctrl1, 0x8100908c}, - {&ch[0].phy.b0_rxdvs[0], 0x01000222}, - {&ch[0].phy.b1_rxdvs[0], 0x01000222}, - {&ch[0].phy.ca_rxdvs0, 0x00000000}, - {&ch[0].phy.ca_cmd[7], 0x00000000}, - {&ch[0].phy.b[0].dq[7], 0x00000000}, - {&ch[0].phy.b[1].dq[7], 0x00000000}, - {&ch[0].ao.shu[0].conf[0], 0xa10810bf}, - {&ch[0].ao.shu[0].odtctrl, 0xc0010003}, - {&ch[0].phy.shu[0].b[0].dq[7], 0x00008010}, - {&ch[0].phy.shu[0].b[1].dq[7], 0x00008000}, - {&ch[0].ao.refctrl0, 0x25712000}, - {&ch[0].ao.shu[0].selph_ca1, 0x00000000}, - {&ch[0].ao.shu[0].selph_ca2, 0x00070000}, - {&ch[0].ao.shu[0].selph_ca3, 0x00000000}, - {&ch[0].ao.shu[0].selph_ca4, 0x00000000}, - {&ch[0].ao.shu[0].selph_ca5, 0x11111011}, - {&ch[0].ao.shu[0].selph_dqs0, 0x33333333}, - {&ch[0].ao.shu[0].selph_dqs1, 0x11114444}, - {&ch[0].ao.shu[0].rk[0].selph_dq[0], 0x33333333}, - {&ch[0].ao.shu[0].rk[0].selph_dq[1], 0x33333333}, - {&ch[0].ao.shu[0].rk[0].selph_dq[2], 0x11113333}, - {&ch[0].ao.shu[0].rk[0].selph_dq[3], 0x11113333}, - {&ch[0].ao.shu[0].rk[1].selph_dq[0], 0x33333333}, - {&ch[0].ao.shu[0].rk[1].selph_dq[1], 0x33333333}, - {&ch[0].ao.shu[0].rk[1].selph_dq[2], 0x11113333}, - {&ch[0].ao.shu[0].rk[1].selph_dq[3], 0x11113333}, - {&ch[0].phy.shu[0].rk[0].b[0].dq[7], 0x001a1a00}, - {&ch[0].phy.shu[0].rk[1].b[0].dq[7], 0x00141400}, - {&ch[0].phy.shu[0].rk[0].b[1].dq[7], 0x001a1a00}, - {&ch[0].phy.shu[0].rk[1].b[1].dq[7], 0x00141400}, - {&ch[0].phy.b[0].dq[9], 0x10100031}, - {&ch[0].phy.b[0].dq[6], 0x010350c0}, - {&ch[0].phy.b[1].dq[9], 0x10100031}, - {&ch[0].phy.b[1].dq[6], 0x010350c0}, - {&ch[0].ao.stbcal, 0xf0100000}, - {&ch[0].ao.srefctrl, 0x08400000}, - {&ch[0].ao.shu[0].ckectrl, 0x33210000}, - {&ch[0].ao.shu[0].pipe, 0xc0000000}, - {&ch[0].ao.ckectrl, 0x88102400}, - {&ch[0].ao.rkcfg, 0x00731004}, - {&ch[0].ao.shu[0].conf[2], 0x9007000f}, - {&ch[0].ao.spcmdctrl, 0x240007d2}, - {&ch[0].ao.shuctrl1, 0x00000040}, - {&ch[0].ao.shuctrl, 0x0001c110}, - {&ch[0].ao.refctrl1, 0x30000700}, - {&ch[0].ao.refratre_filter, 0x6543b321}, - {&ch[0].ao.dramctrl, 0x30822001}, - {&ch[0].ao.misctl0, 0x81080000}, - {&ch[0].ao.perfctl0, 0x00024f13}, - {&ch[0].ao.arbctl, 0x00000080}, - {&ch[0].ao.padctrl, 0x00000009}, - {&ch[0].ao.dramc_pd_ctrl, 0x80000106}, - {&ch[0].ao.clkctrl, 0x3000000c}, - {&ch[0].ao.refctrl0, 0x25714001}, - {&ch[0].ao.shu[0].rankctl, 0x64400000}, - {&ch[0].ao.shu[0].rk[0].dqsien, 0x00001919}, - {&ch[0].ao.shu[0].rk[1].dqsien, 0x00001b1b}, - {&ch[0].ao.dramctrl, 0x308a2001}, - {&ch[0].ao.zqcs, 0x00000a56}, - {&ch[0].ao.shu[0].conf[3], 0x00ff0000}, - {&ch[0].ao.refctrl0, 0x65714001}, - {&ch[0].ao.srefctrl, 0x48400000}, - {&ch[0].ao.mpc_option, 0x00020000}, - {&ch[0].ao.dramc_pd_ctrl, 0xc0000106}, - {&ch[0].ao.dramc_pd_ctrl, 0xc0000107}, - {&ch[0].ao.eyescan, 0x00010000}, - {&ch[0].ao.stbcal1, 0x00014f10}, - {&ch[0].ao.test2_3, 0x12000480}, - {&ch[0].ao.rstmask, 0x57000000}, - {&ch[0].ao.rstmask, 0x17000000}, - {&ch[0].ao.hw_mrr_fun, 0x00000068}, - {&ch[0].ao.perfctl0, 0x000a4f13}, - {&ch[0].ao.rstmask, 0x07000000}, - {&ch[0].ao.rkcfg, 0x00731804}, - {&ch[0].ao.spcmdctrl, 0x340007d2}, - {&ch[0].ao.eyescan, 0x00010004}, - {&ch[0].ao.dramctrl, 0x308a2000}, - {&ch[0].ao.mpc_option, 0x00020000}, - {&ch[0].ao.shu[0].wodt, 0xa0000000}, - {&ch[0].phy.shu[0].b[0].dq[7], 0x00008090}, - {&ch[0].phy.shu[0].b[1].dq[7], 0x00008080}, - {&ch[0].ao.shu[0].rankctl, 0x64400000}, - {&ch[0].ao.shu[0].rk[0].selph_dq[0], 0x33333322}, - {&ch[0].ao.shu[0].rk[0].selph_dq[1], 0x33333322}, - {&ch[0].ao.shu[0].rk[1].selph_dq[0], 0x33333322}, - {&ch[0].ao.shu[0].rk[1].selph_dq[1], 0x33333322}, - {&ch[0].ao.stbcal1, 0x00034f10}, - {&ch[0].ao.stbcal1, 0x00014f10}, - {&ch[0].ao.stbcal, 0xfc100001}, - {&ch[0].ao.stbcal1, 0x00014f50}, - {&ch[0].ao.shu[0].dqsg, 0x02009800}, - {&ch[0].phy.misc_ctrl0, 0xb9010200}, - {&ch[0].ao.shu[0].stbcal, 0x00000100}, - {&ch[0].ao.stbcal, 0xfc120001}, - {&ch[0].phy.shu[0].b[0].dq[7], 0x00008090}, - {&ch[0].phy.shu[0].b[1].dq[7], 0x00008080}, - {&ch[0].ao.shu[0].stbcal, 0x00000110}, - {&ch[0].ao.shu[0].stbcal, 0x00000112}, - {&ch[0].ao.refctrl1, 0x30000721}, - {&ch[0].ao.dqsoscr, 0x098e0080}, - {&ch[0].ao.rstmask, 0x00000000}, - {&ch[0].ao.rkcfg, 0x00731814}, - {&ch[0].ao.shu[0].rankctl, 0x64300000}, - {&ch[0].ao.shu[0].wodt, 0x20000000}, - {&ch[0].ao.shu[0].rk[0].fine_tune, 0x1a1a1a1a}, - {&ch[0].ao.shu[0].rk[1].fine_tune, 0x14141414}, - {&ch[0].ao.shu[0].rk[0].selph_dq[2], 0x33333333}, - {&ch[0].ao.shu[0].rk[0].selph_dq[3], 0x33333333}, - {&ch[0].ao.shu[0].rk[1].selph_dq[2], 0x33333333}, - {&ch[0].ao.shu[0].rk[1].selph_dq[3], 0x33333333}, - {&ch[0].ao.shu[0].dqsg_retry, 0x8120050c}, - {&ch[0].phy.shu[0].b[0].dq[7], 0x00008090}, - {&ch[0].phy.shu[0].b[1].dq[7], 0x00008080}, - {&ch[0].ao.shu[0].dqs2dq_tx, 0x00000000}, - {&ch[0].ao.shu[0].odtctrl, 0xc0010003}, - {&ch[0].phy.shu[0].b[0].dq[7], 0x00008090}, - {&ch[0].phy.shu[0].b[1].dq[7], 0x00008080}, - {&ch[0].phy.r[0].b[0].rxdvs[2], 0x20000000}, - {&ch[0].phy.r[1].b[0].rxdvs[2], 0x20000000}, - {&ch[0].phy.r[0].b[1].rxdvs[2], 0x20000000}, - {&ch[0].phy.r[1].b[1].rxdvs[2], 0x20000000}, - {&ch[0].phy.shu[0].ca_cmd[7], 0x00000000}, - {&ch[0].phy.ca_cmd[3], 0x0000048c}, - {&ch[0].phy.ca_cmd[10], 0x00000020}, - {&ch[0].phy.ca_cmd[6], 0x00024000}, - {&ch[0].phy.b[0].dq[3], 0x000004ee}, - {&ch[0].phy.b[1].dq[3], 0x000004ee}, - {&ch[0].phy.ca_cmd[3], 0x000004ac}, - {&ch[0].phy.b[0].dq[3], 0x000004ec}, - {&ch[0].phy.b[1].dq[3], 0x000004ec}, - {&ch[0].phy.b[0].dq[5], 0x82110e00}, - {&ch[0].phy.b[1].dq[5], 0x82110e00}, - {&ch[0].phy.ca_cmd[5], 0x80000808}, - {&ch[0].phy.ca_cmd[6], 0x00034000}, - {&ch[0].phy.misc_imp_ctrl0, 0x00000020}, - {&ch[0].phy.b[0].dq[6], 0x010352c0}, - {&ch[0].phy.b[1].dq[6], 0x010352c0}, - {&ch[0].phy.ca_cmd[6], 0x00034200}, - {&ch[0].phy.b[0].dq[6], 0x010352c1}, - {&ch[0].phy.b[1].dq[6], 0x010352c1}, - {&ch[0].phy.ca_cmd[6], 0x00034201}, - {&ch[0].phy.ca_cmd[6], 0x00034241}, - {&ch[0].phy.b[0].dq[6], 0x010352c9}, - {&ch[0].phy.b[1].dq[6], 0x010352c9}, - {&ch[0].phy.ca_cmd[6], 0x00034249}, - {&ch[0].phy.b[0].dq[6], 0x010352e9}, - {&ch[0].phy.b[1].dq[6], 0x010352e9}, - {&ch[0].phy.ca_cmd[6], 0x00034269}, - {&ch[0].phy.shu[0].b[0].dq[5], 0x0030000e}, - {&ch[0].phy.b[0].dq[5], 0x82110e00}, - {&ch[0].phy.shu[0].b[1].dq[5], 0x0030000e}, - {&ch[0].phy.b[1].dq[5], 0x82110e00}, - {&ch[0].phy.b[0].dq[8], 0x00000007}, - {&ch[0].phy.b[1].dq[8], 0x00000007}, - {&ch[0].phy.ca_cmd[9], 0x00010007}, - {&ch[0].ao.stbcal1, 0x00014f70}, - {&ch[0].ao.stbcal, 0xfc120001}, - {&ch[0].phy.b[0].dq[6], 0x010392e9}, - {&ch[0].phy.b[0].dq[9], 0x10100031}, - {&ch[0].phy.b[0].dq[9], 0x10100020}, - {&ch[0].phy.b[0].dq[9], 0x10100031}, - {&ch[0].phy.b[1].dq[6], 0x010392e9}, - {&ch[0].phy.b[1].dq[9], 0x10100031}, - {&ch[0].phy.b[1].dq[9], 0x10100020}, - {&ch[0].phy.b[1].dq[9], 0x10100031}, - {&ch[1].phy.b[0].dq[8], 0x00000007}, - {&ch[1].phy.b[1].dq[8], 0x00000007}, - {&ch[1].phy.ca_cmd[9], 0x00010007}, - {&ch[1].ao.stbcal1, 0x00014f70}, - {&ch[1].ao.stbcal, 0xfc120001}, - {&ch[1].phy.b[0].dq[6], 0x010392e9}, - {&ch[1].phy.b[0].dq[9], 0x10100031}, - {&ch[1].phy.b[0].dq[9], 0x10100020}, - {&ch[1].phy.b[0].dq[9], 0x10100031}, - {&ch[1].phy.b[1].dq[6], 0x010392e9}, - {&ch[1].phy.b[1].dq[9], 0x10100031}, - {&ch[1].phy.b[1].dq[9], 0x10100020}, - {&ch[1].phy.b[1].dq[9], 0x10100031}, - {&ch[0].phy.ca_cmd[8], 0x00080a0a}, - {&ch[0].phy.ca_cmd[8], 0x00080a0a}, - {&ch[0].ao.shu[0].misc, 0x0000f132}, - {&ch[0].ao.shu[0].dqsg, 0x02a19800}, - {&ch[0].phy.shu[0].b[0].dq[5], 0x0030000e}, - {&ch[0].phy.shu[0].b[1].dq[5], 0x0030000e}, - {&ch[0].phy.shu[0].ca_cmd[5], 0x00000000}, - {&mt8183_infracfg->dramc_wbr, 0x00000000}, - {&ch[0].phy.shu[0].b[0].dq[6], 0x06860440}, - {&ch[0].phy.shu[0].b[1].dq[6], 0x06860440}, - {&ch[0].phy.shu[0].ca_cmd[6], 0x068604c0}, - {&ch[1].phy.shu[0].b[0].dq[6], 0x06860440}, - {&ch[1].phy.shu[0].b[1].dq[6], 0x06860440}, - {&ch[1].phy.shu[0].ca_cmd[6], 0x06860440}, - {&mt8183_infracfg->dramc_wbr, 0x0000001f}, - {&ch[0].ao.shu[0].impcal1, 0x81080004}, - {&ch[0].ao.srefctrl, 0x4840f000}, - {&ch[0].ao.pre_tdqsck[0], 0x00020000}, - {&ch[0].ao.shu[0].misc, 0x0000f132}, - {&ch[0].phy.shu[0].b[0].dq[8], 0xffc07fff}, - {&ch[0].phy.shu[0].b[1].dq[8], 0xffc07fff}, - {&ch[0].phy.shu[0].ca_cmd[8], 0xffc07fff}, - {&ch[0].phy.misc_ctrl3, 0x15351135}, - {&ch[0].phy.shu[0].b[0].dq[7], 0x00008090}, - {&ch[0].phy.shu[0].b[1].dq[7], 0x00008080}, - {&ch[0].ao.clkar, 0x020cffff}, - {&ch[0].ao.shu[0].dqsg_retry, 0x8120050c}, - {&ch[0].ao.write_lev, 0x00080000}, - {&ch[0].ao.dummy_rd, 0x01000000}, - {&ch[0].ao.stbcal2, 0x50000010}, - {&ch[0].ao.eyescan, 0x00010704}, - {&ch[0].ao.shu[0].odtctrl, 0xc001000f}, - {&ch[0].phy.shu[0].b[0].dll[0], 0xc0778609}, - {&ch[0].phy.shu[0].b[1].dll[0], 0xc0778609}, - {&ch[0].phy.ca_dll_fine_tune[1], 0x00200000}, - {&ch[0].ao.perfctl0, 0x040acf13}, - {&ch[0].ao.srefctrl, 0x4840f000}, - {&ch[0].ao.shuctrl1, 0x0000001a}, - {&ch[0].phy.b[0].dq[6], 0x010392e9}, - {&ch[0].phy.b[1].dq[6], 0x010392e9}, - {&ch[0].phy.ca_cmd[6], 0x000352e9}, - {&ch[0].ao.stbcal2, 0x50010010}, - {&ch[0].phy.shu[0].b[0].dq[7], 0x13008090}, - {&ch[0].phy.shu[0].b[1].dq[7], 0x13008080}, - {&ch[0].ao.shu[0].rodtenstb, 0x00000000}, - {&ch[0].ao.shu[0].dqsg, 0x02a19800}, - {&ch[0].ao.shu[0].rk[0].dqscal, 0x00000000}, - {&ch[0].ao.shu[0].rk[1].dqscal, 0x00000000}, - {&ch[0].ao.shu[0].stbcal, 0x00000112}, - {&ch[1].ao.shu[0].dqsg, 0x02a19800}, - {&ch[1].ao.shu[0].rk[0].dqscal, 0x00000000}, - {&ch[1].ao.shu[0].rk[1].dqscal, 0x00000000}, - {&ch[1].ao.shu[0].stbcal, 0x00000112}, - {&ch[0].phy.b[0].dq[9], 0x10100431}, - {&ch[0].phy.b[1].dq[9], 0x10100431}, - {&ch[0].phy.ca_cmd[10], 0x00000020}, - {&ch[0].phy.shu[0].b[0].dq[8], 0xffc07fff}, - {&ch[0].phy.shu[0].b[1].dq[8], 0xffc07fff}, - {&ch[0].phy.shu[0].b[0].dll[1], 0x00022401}, - {&ch[0].phy.shu[0].b[1].dll[1], 0x00022401}, - {&ch[0].ao.shu[0].odtctrl, 0xc001000f}, - {&ch[0].phy.shu[0].b[0].dq[7], 0x13008090}, - {&ch[0].phy.shu[0].b[1].dq[7], 0x13008080}, - {&ch[0].ao.drsctrl, 0x20080000}, - {&ch[0].ao.refctrl0, 0x75714001}, - {&ch[0].ao.zqcs, 0x00080a56}, - {&ch[0].ao.dummy_rd, 0x0d000000}, - {&ch[0].ao.shuctrl2, 0x0001d10a}, - {&ch[0].ao.shuctrl3, 0x0b80000d}, - {&ch[0].phy.misc_ctrl3, 0x1d351135}, - {&ch[0].phy.b[0].dll_fine_tune[1], 0x00300000}, - {&ch[0].phy.b[1].dll_fine_tune[1], 0x00300000}, - {&ch[0].phy.ca_dll_fine_tune[1], 0x00300000}, - {&ch[0].phy.misc_ctrl0, 0xb1010200}, - {&ch[0].phy.misc_rxdvs[2], 0x00000101}, - {&ch[0].ao.clkctrl, 0x3000008c}, - {&ch[0].ao.refctrl1, 0x300007a1}, - {&ch[0].ao.shuctrl, 0x0c01c1d0}, - {&ch[0].ao.shuctrl2, 0x8001dd0a}, - {&ch[0].ao.stbcal2, 0x50010000}, - {&ch[0].ao.pre_tdqsck[0], 0x00020000}, - {&ch[0].ao.ckectrl, 0x88502400}, - {&ch[0].phy.ca_tx_mck, 0xa94011c0}, - {&ch[0].ao.ckectrl, 0x88d02400}, - {&ch[0].ao.shu[0].rodtenstb, 0x00000000}, - {&ch[0].ao.test2_4, 0x0080110d}, - {&ch[0].ao.shu[0].conf[3], 0x00ff0005}, - {&ch[0].ao.refctrl0, 0x75774001}, - {&ch[0].ao.shuctrl2, 0x8301dd0a}, - {&ch[0].ao.refctrl0, 0x75774001}, - {&ch[0].ao.dramctrl, 0x348a2000}, - {&ch[0].ao.dummy_rd, 0x0d426810}, - {&ch[0].ao.test2_4, 0x4080110d}, - {&ch[0].ao.dramctrl, 0x348a2000}, - {&mt8183_infracfg->dramc_wbr, 0x00000000}, - {&ch[0].ao.shuctrl, 0x0c03c1d0}, - {&ch[0].ao.shuctrl2, 0x8301dd0a}, - {&ch[1].ao.shuctrl, 0x0c01c1f0}, - {&ch[1].ao.shuctrl2, 0x8301cd0a}, - - /* dramc duty calibration */ - {&ch[0].phy.shu[0].rk[0].ca_cmd[1], 0x00000000}, - {&ch[0].phy.shu[0].rk[0].ca_cmd[0], 0x00000000}, - {&ch[0].phy.shu[0].rk[1].ca_cmd[1], 0x00000000}, - {&ch[0].phy.shu[0].rk[1].ca_cmd[0], 0x00000000}, - {&ch[0].phy.shu[0].ca_cmd[3], 0x00000400}, - {&ch[0].phy.shu[0].rk[0].b[0].dq[1], 0x00110000}, - {&ch[0].phy.shu[0].rk[0].b[1].dq[1], 0x00110000}, - {&ch[0].phy.shu[0].rk[1].b[0].dq[1], 0x00110000}, - {&ch[0].phy.shu[0].rk[1].b[1].dq[1], 0x00110000}, - {&ch[0].phy.shu[0].b[0].dll[1], 0x00022601}, - {&ch[1].phy.shu[0].rk[0].ca_cmd[1], 0x00000000}, - {&ch[1].phy.shu[0].rk[0].ca_cmd[0], 0x00000000}, - {&ch[1].phy.shu[0].rk[1].ca_cmd[1], 0x00000000}, - {&ch[1].phy.shu[0].rk[1].ca_cmd[0], 0x00000000}, - {&ch[1].phy.shu[0].ca_cmd[3], 0x00000400}, - {&ch[1].phy.shu[0].rk[0].b[0].dq[1], 0x22000000}, - {&ch[1].phy.shu[0].rk[0].b[1].dq[1], 0x22000000}, - {&ch[1].phy.shu[0].rk[1].b[0].dq[1], 0x22000000}, - {&ch[1].phy.shu[0].rk[1].b[1].dq[1], 0x22000000}, - {&ch[1].phy.shu[0].b[0].dll[1], 0x00022501}, - - /* update the ac timing */ - {&ch[0].ao.shu[0].actim[0], 0x06020c07}, - {&ch[0].ao.shu[0].actim[1], 0x10080501}, - {&ch[0].ao.shu[0].actim[2], 0x07070201}, - {&ch[0].ao.shu[0].actim[3], 0x6164002c}, - {&ch[0].ao.shu[0].actim[4], 0x22650077}, - {&ch[0].ao.shu[0].actim[5], 0x0a000c0b}, - {&ch[0].ao.shu[0].actim_xrt, 0x05030609}, - {&ch[0].ao.shu[0].ac_time_05t, 0x000106e1}, - {&ch[0].ao.catraining1, 0x0b000000}, - {&ch[0].ao.shu[0].rk[0].dqsctl, 0x00000004}, - {&ch[0].ao.shu[0].rk[1].dqsctl, 0x00000004}, - {&ch[0].ao.shu[0].odtctrl, 0xc001004f}, - {&ch[0].ao.shu[0].conf[1], 0x34000d0f}, - {&ch[0].ao.shu[0].conf[2], 0x9007640f}, - {&ch[0].ao.shu[0].scintv, 0x4e39eb36}, - {&ch[0].ao.shu[0].ckectrl, 0x33210000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - {&ch[0].ao.shu[0].rankctl, 0x64300003}, - {&ch[0].ao.shu[0].rankctl, 0x64301203}, - {&ch[1].ao.shu[0].actim[0], 0x06020c07}, - {&ch[1].ao.shu[0].actim[1], 0x10080501}, - {&ch[1].ao.shu[0].actim[2], 0x07070201}, - {&ch[1].ao.shu[0].actim[3], 0x6164002c}, - {&ch[1].ao.shu[0].actim[4], 0x22650077}, - {&ch[1].ao.shu[0].actim[5], 0x0a000c0b}, - {&ch[1].ao.shu[0].actim_xrt, 0x05030609}, - {&ch[1].ao.shu[0].ac_time_05t, 0x000106e1}, - {&ch[1].ao.catraining1, 0x0b000000}, - {&ch[1].ao.shu[0].rk[0].dqsctl, 0x00000004}, - {&ch[1].ao.shu[0].rk[1].dqsctl, 0x00000004}, - {&ch[1].ao.shu[0].odtctrl, 0xc001004f}, - {&ch[1].ao.shu[0].conf[1], 0x34000d0f}, - {&ch[1].ao.shu[0].conf[2], 0x9007640f}, - {&ch[1].ao.shu[0].scintv, 0x4e39eb36}, - {&ch[1].ao.shu[0].ckectrl, 0x33210000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.shu[0].rankctl, 0x64300003}, - {&ch[1].ao.shu[0].rankctl, 0x64301203}, - {&ch[0].ao.arbctl, 0x00000c80}, - {&ch[0].ao.rstmask, 0x00000000}, - {&ch[0].ao.arbctl, 0x00000c80}, -}; - -static struct reg_init_value dramc_mode_reg_init_sequence[] = { - /* dramc power on sequence */ - {&ch[0].phy.misc_ctrl1, 0x8100908c}, - {&ch[1].phy.misc_ctrl1, 0x8100908c}, - {&ch[0].ao.ckectrl, 0x88d02480}, - {&ch[1].ao.ckectrl, 0x88d02480}, - {&ch[0].phy.misc_ctrl1, 0x8100b08c}, - {&ch[1].phy.misc_ctrl1, 0x8100b08c}, - {&ch[0].ao.dramc_pd_ctrl, 0xc4000107}, - {&ch[1].ao.dramc_pd_ctrl, 0xc4000107}, - {&ch[0].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[0].ao.mrs, 0x00000000}, - - /* CH0 dramc ZQ Calibration */ - {&ch[0].ao.dramc_pd_ctrl, 0xc4000107}, - {&ch[0].ao.ckectrl, 0x88d02440}, - {&ch[0].ao.mrs, 0x00000000}, - {&ch[0].ao.mpc_option, 0x00020000}, - {&ch[0].ao.spcmd, 0x00000040}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.mrs, 0x00000000}, - {&ch[0].ao.dramc_pd_ctrl, 0xc4000107}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR13 */ - {&ch[0].ao.mrs, 0x00000d18}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR12 */ - {&ch[0].ao.mrs, 0x00000c5d}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR1 */ - {&ch[0].ao.mrs, 0x00000156}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR2 */ - {&ch[0].ao.mrs, 0x0000020b}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR11 */ - {&ch[0].ao.mrs, 0x00000b00}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR22 */ - {&ch[0].ao.mrs, 0x00001638}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR14 */ - {&ch[0].ao.mrs, 0x00000e5d}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR3 */ - {&ch[0].ao.mrs, 0x00000330}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR13 */ - {&ch[0].ao.mrs, 0x00000d58}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR12 */ - {&ch[0].ao.mrs, 0x00000c5d}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR1 */ - {&ch[0].ao.mrs, 0x00000156}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR2 */ - {&ch[0].ao.mrs, 0x0000022d}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR11 */ - {&ch[0].ao.mrs, 0x00000b23}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR22 */ - {&ch[0].ao.mrs, 0x00001634}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR14 */ - {&ch[0].ao.mrs, 0x00000e10}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR3 */ - {&ch[0].ao.mrs, 0x00000330}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* dramc ZQ Calibration */ - {&ch[0].ao.mrs, 0x01000330}, - {&ch[0].ao.dramc_pd_ctrl, 0xc4000107}, - {&ch[0].ao.ckectrl, 0x88d02440}, - {&ch[0].ao.mrs, 0x11000330}, - {&ch[0].ao.mpc_option, 0x00020000}, - {&ch[0].ao.spcmd, 0x00000040}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.mrs, 0x01000330}, - {&ch[0].ao.dramc_pd_ctrl, 0xc4000107}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR13 */ - {&ch[0].ao.mrs, 0x01000d18}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR12 */ - {&ch[0].ao.mrs, 0x01000c5d}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR1 */ - {&ch[0].ao.mrs, 0x01000156}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR2 */ - {&ch[0].ao.mrs, 0x0100020b}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR11 */ - {&ch[0].ao.mrs, 0x01000b00}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR22 */ - {&ch[0].ao.mrs, 0x01001638}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR14 */ - {&ch[0].ao.mrs, 0x01000e5d}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR3 */ - {&ch[0].ao.mrs, 0x01000330}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR13 */ - {&ch[0].ao.mrs, 0x01000d58}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR12 */ - {&ch[0].ao.mrs, 0x01000c5d}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR1 */ - {&ch[0].ao.mrs, 0x01000156}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR2 */ - {&ch[0].ao.mrs, 0x0100022d}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR11 */ - {&ch[0].ao.mrs, 0x01000b23}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR22 */ - {&ch[0].ao.mrs, 0x01001634}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR14 */ - {&ch[0].ao.mrs, 0x01000e10}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR3 */ - {&ch[0].ao.mrs, 0x01000330}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR13 */ - {&ch[0].ao.mrs, 0x00000330}, - {&ch[0].ao.ckectrl, 0x88d02440}, - {&ch[0].ao.mrs, 0x00000dd8}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - - /* MR13 */ - {&ch[0].ao.mrs, 0x01000dd8}, - {&ch[0].ao.ckectrl, 0x88d02440}, - {&ch[0].ao.mrs, 0x01000dd8}, - {&ch[0].ao.spcmd, 0x00000001}, - {&ch[0].ao.spcmd, 0x00000000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - {&ch[0].ao.mrs, 0x01000dd8}, - - {&ch[0].ao.shu[0].hwset_mr13, 0x00d8000d}, - {&ch[0].ao.shu[0].hwset_vrcg, 0x00d8000d}, - {&ch[0].ao.shu[0].hwset_mr2, 0x002d0002}, - - /* CH1 dramc ZQ Calibration */ - {&ch[1].ao.mrs, 0x00000000}, - {&ch[1].ao.dramc_pd_ctrl, 0xc4000107}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x00000000}, - {&ch[1].ao.mpc_option, 0x00020000}, - {&ch[1].ao.spcmd, 0x00000040}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.mrs, 0x00000000}, - {&ch[1].ao.dramc_pd_ctrl, 0xc4000107}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x00000d18}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x00000c5d}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x00000156}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x0000020b}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x00000b00}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x00001638}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x00000e5d}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x00000330}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x00000d58}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x00000c5d}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x00000156}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x0000022d}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x00000b23}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x00001634}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x00000e10}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x00000330}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x01000330}, - {&ch[1].ao.dramc_pd_ctrl, 0xc4000107}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x11000330}, - {&ch[1].ao.mpc_option, 0x00020000}, - {&ch[1].ao.spcmd, 0x00000040}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.mrs, 0x01000330}, - {&ch[1].ao.dramc_pd_ctrl, 0xc4000107}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x01000d18}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x01000c5d}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x01000156}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x0100020b}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x01000b00}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x01001638}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x01000e5d}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x01000330}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x01000d58}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x01000c5d}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x01000156}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x0100022d}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x01000b23}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x01001634}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x01000e10}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x01000330}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x00000330}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x00000dd8}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x01000dd8}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x01000dd8}, - {&ch[1].ao.spcmd, 0x00000001}, - {&ch[1].ao.spcmd, 0x00000000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.mrs, 0x01000dd8}, - {&ch[1].ao.shu[0].hwset_mr13, 0x00d8000d}, - {&ch[1].ao.shu[0].hwset_vrcg, 0x00d8000d}, - {&ch[1].ao.shu[0].hwset_mr2, 0x002d0002}, - {&ch[0].ao.mrs, 0x00000dd8}, - {&ch[1].ao.mrs, 0x00000dd8}, -}; - -void dramc_init(void) +static void cke_fix_onoff(int option, u8 chn) { - for (int i = 0; i < ARRAY_SIZE(dramc_init_sequence); i++) - write32(dramc_init_sequence[i].addr, - dramc_init_sequence[i].value); + u8 on = 0, off = 0; - for (int i = 0; i < ARRAY_SIZE(dramc_mode_reg_init_sequence); i++) { - write32(dramc_mode_reg_init_sequence[i].addr, - dramc_mode_reg_init_sequence[i].value); - udelay(2); + /* if CKE is dynamic, set both CKE fix On and Off as 0 */ + if (option != CKE_DYNAMIC) { + on = option; + off = (1 - option); + } + + clrsetbits_le32(&ch[chn].ao.ckectrl, + (0x1 << 6) | (0x1 << 7), (on << 6) | (off << 7)); +} + +static void ddr_phy_pll_setting(u8 chn, u8 freq_group) +{ + u8 cap_sel, mid_cap_sel; + u8 vth_sel = 0x2; + u8 ca_dll_mode[2]; + u32 sdm_pcw, delta; + + switch (freq_group) { + case LP4X_DDR1600: + mid_cap_sel = 0x0; + cap_sel = 0x3; + sdm_pcw = 0x7b00; + delta = 0; + break; + case LP4X_DDR2400: + mid_cap_sel = 0x3; + cap_sel = 0x0; + sdm_pcw = 0x5c00; + delta = 0; + break; + case LP4X_DDR3200: + mid_cap_sel = 0x2; + cap_sel = 0x0; + sdm_pcw = 0x7b00; + delta = 0xC03; + break; + case LP4X_DDR3600: + mid_cap_sel = 0x1; + cap_sel = 0x0; + sdm_pcw = 0x8a00; + delta = 0xD96; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + + if (freq_group == LP4X_DDR1600) + ca_dll_mode[CHANNEL_A] = DLL_SLAVE; + else + ca_dll_mode[CHANNEL_A] = DLL_MASTER; + ca_dll_mode[CHANNEL_B] = DLL_SLAVE; + + clrbits_le32(&ch[chn].phy.shu[0].pll[4], 0xFFFF); + clrbits_le32(&ch[chn].phy.shu[0].pll[6], 0xFFFF); + setbits_le32(&ch[chn].phy.misc_shu_opt, (chn + 1) << 18); + clrsetbits_le32(&ch[chn].phy.ckmux_sel, 0x3 << 18 | 0x3 << 16, 0x0); + clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[0], 0x3 << 18, 0x1 << 18); + + if (ca_dll_mode[chn] == DLL_SLAVE) + clrsetbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 1, 0x1 << 1); + else + clrsetbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 1, 0x0 << 1); + + bool is_master = (ca_dll_mode[chn] == DLL_MASTER); + u8 phdet_out = is_master ? 0x0 : 0x1; + u8 phdet_in = is_master ? 0x0 : 0x1; + u8 gain = is_master ? 0x6 : 0x7; + u8 idle_cnt = is_master ? 0x9 : 0x7; + u8 fast_psjp = is_master ? 0x1 : 0x0; + + clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[0], + (0x1 << 31) | (0x1 << 30) | (0xf << 20) | (0xf << 16) | + (0xf << 12) | (0x1 << 10) | (0x1 << 9) | (0x1 << 4), + (phdet_out << 31) | (phdet_in << 30) | + (gain << 20) | (idle_cnt << 16) | + (0x8 << 12) | + (0x1 << 10) | (0x1 << 9) | (fast_psjp << 4)); + + u8 pd_ck_sel = is_master ? 0x1 : 0x0; + u8 fastpj_ck_sel = is_master ? 0x0 : 0x1; + + clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[1], + (0x1 << 2) | (0x1 << 0), + (pd_ck_sel << 2) | (fastpj_ck_sel << 0)); + + clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], + 0x1 << 7, + (is_master ? 0x1 : 0x0) << 7); + + struct reg_value regs_bak[] = { + {&ch[chn].phy.b[0].dq[7]}, + {&ch[chn].phy.b[1].dq[7]}, + {&ch[chn].phy.ca_cmd[7]}, + }; + + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + regs_bak[i].value = read32(regs_bak[i].addr); + + for (size_t b = 0; b < 2; b++) { + setbits_le32(&ch[chn].phy.b[b].dq[7], + 0x1 << 6 | 0x1 << 4 | 0x1 << 2 | 0x1 << 0); + } + setbits_le32(&ch[chn].phy.ca_cmd[7], 0x1 << 6 | 0x1 << 4 | 0x1 << 2 | 0x1 << 0); + setbits_le32(&ch[chn].phy.ca_cmd[2], 0x1 << 21); + + /* 26M */ + clrsetbits_le32(&ch[chn].phy.misc_cg_ctrl0, 0x3 << 4, 0x0 << 4); + + /* MID FINE_TUNE */ + clrbits_le32(&ch[chn].phy.shu[0].b[0].dq[6], (0x1 << 26) | (0x1 << 27)); + clrbits_le32(&ch[chn].phy.shu[0].b[1].dq[6], (0x1 << 26) | (0x1 << 27)); + clrbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], (0x1 << 26) | (0x1 << 27)); + clrbits_le32(&ch[chn].phy.pll4, (0x1 << 16) | (0x1 << 22)); + + /* PLL */ + clrbits_le32(&ch[chn].phy.pll1, 0x1 << 31); + clrbits_le32(&ch[chn].phy.pll2, 0x1 << 31); + + /* DLL */ + clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[2], 0x1 << 0); + clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2], 0x1 << 0); + clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[2], 0x1 << 0); + setbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2], + (0x1 << 10) | (0x1 << 11) | (0x1 << 13) | (0x1 << 14) | + (0x1 << 15) | (0x1 << 17) | (0x1 << 19) | (0x1 << 27) | (0x1 << 31)); + setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[2], + (0x1 << 10) | (0x1 << 11) | (0x1 << 13) | (0x1 << 14) | + (0x1 << 15) | (0x1 << 17) | (0x1 << 19) | (0x1 << 27) | (0x1 << 31)); + setbits_le32(&ch[chn].phy.ca_dll_fine_tune[2], + (0x1 << 10) | (0x1 << 11) | (0x1 << 13) | (0x1 << 15) | + (0x1 << 16) | (0x1 << 17) | (0x1 << 19) | (0x1 << 27) | (0x1 << 31)); + + /* RESETB */ + clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[0], 0x1 << 3); + clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[0], 0x1 << 3); + clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[0], 0x1 << 3); + + udelay(1); + + /* MPLL 52M */ + clrsetbits_le32(&ch[chn].phy.shu[0].pll[8], + (0x7 << 0) | (0x3 << 18), (0x0 << 0) | (0x1 << 18)); + clrsetbits_le32(&ch[chn].phy.shu[0].pll[10], + (0x7 << 0) | (0x3 << 18), (0x0 << 0) | (0x1 << 18)); + clrsetbits_le32(&ch[chn].phy.shu[0].pll[5], + (0xffff << 16) | 0x1 << 0, sdm_pcw << 16); + clrsetbits_le32(&ch[chn].phy.shu[0].pll[7], + (0xffff << 16) | 0x1 << 0, sdm_pcw << 16); + + setbits_le32(&ch[chn].phy.ca_dll_fine_tune[0], 0x1 << 1); + setbits_le32(&ch[chn].phy.b[0].dll_fine_tune[0], 0x1 << 1); + setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[0], 0x1 << 1); + + clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[1], 0x1 << 11); + clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[1], 0x1 << 19); + clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[1], 0x1 << 19); + + clrsetbits_le32(&ch[chn].phy.shu[0].b[0].dq[6], + (0x3 << 22) | (0x3 << 24) | (0x3 << 28), + (mid_cap_sel << 22) | (vth_sel << 24) | (cap_sel << 28)); + clrsetbits_le32(&ch[chn].phy.shu[0].b[1].dq[6], + (0x3 << 22) | (0x3 << 24) | (0x3 << 28), + (mid_cap_sel << 22) | (vth_sel << 24) | (cap_sel << 28)); + clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], + (0x3 << 22) | (0x3 << 24) | (0x3 << 28), + (mid_cap_sel << 22) | (vth_sel << 24) | (cap_sel << 28)); + + /* RESETB */ + setbits_le32(&ch[chn].phy.ca_dll_fine_tune[0], 0x1 << 3); + setbits_le32(&ch[chn].phy.b[0].dll_fine_tune[0], 0x1 << 3); + setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[0], 0x1 << 3); + udelay(1); + + /* PLL EN */ + setbits_le32(&ch[chn].phy.pll1, 0x1 << 31); + setbits_le32(&ch[chn].phy.pll2, 0x1 << 31); + udelay(100); + + /* MIDPI Init 1 */ + setbits_le32(&ch[chn].phy.pll4, (0x1 << 16) | (0x1 << 22)); + udelay(1); + + /* MIDPI Init 2 */ + u8 midpi_en; + u8 midpi_ckdiv4_en; + + if (freq_group > LP4X_DDR1600) { + midpi_en = 0x1; + midpi_ckdiv4_en = 0x0; + } else { + midpi_en = 0x0; + midpi_ckdiv4_en = 0x1; + } + + u32 dq6_clear = (0x1 << 26) | (0x1 << 27); + u32 dq6_set = (midpi_en << 26) | (midpi_ckdiv4_en << 27); + + clrsetbits_le32(&ch[chn].phy.shu[0].b[0].dq[6], dq6_clear, dq6_set); + clrsetbits_le32(&ch[chn].phy.shu[0].b[1].dq[6], dq6_clear, dq6_set); + clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], dq6_clear, dq6_set); + + udelay(1); + clrsetbits_le32(&ch[chn].phy.ca_dll_fine_tune[3], 0x1 << 19, + (0x1 << 13) | (0x1 << 15) | (0x1 << 16) | (0x1 << 17) | + ((chn ? 0 : 1) << 19)); + setbits_le32(&ch[chn].phy.b[0].dll_fine_tune[3], + (0x1 << 11) | (0x1 << 13) | (0x1 << 14) | (0x1 << 15) | + (0x1 << 17)); + setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[3], + (0x1 << 11) | (0x1 << 13) | (0x1 << 14) | (0x1 << 15) | + (0x1 << 17)); + clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[2], + (0x1 << 10) | (0x1 << 13) | + (0x1 << 15) | (0x1 << 16) | (0x1 << 17) | + (0x1 << 19) | (0x1 << 27) | (0x1 << 31)); + + clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2], + (0x1 << 10) | (0x1 << 13) | (0x1 << 14) | + (0x1 << 15) | (0x1 << 17) | + (0x1 << 19) | (0x1 << 27) | (0x1 << 31)); + clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[2], + (0x1 << 10) | (0x1 << 13) | + (0x1 << 14) | (0x1 << 15) | (0x1 << 17) | + (0x1 << 19) | (0x1 << 27) | (0x1 << 31)); + + setbits_le32(&ch[chn].phy.ca_dll_fine_tune[2], 0x1 << 11); + clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2], 0x1 << 11); + clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[2], 0x1 << 11); + udelay(2); + + setbits_le32(&ch[chn].phy.misc_cg_ctrl0, 0x1 << 4); + udelay(1); + + /* DLL */ + setbits_le32(&ch[chn].phy.ca_dll_fine_tune[2], 0x1 << 0); + udelay(1); + setbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2], 0x1 << 0); + setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[2], 0x1 << 0); + udelay(1); + + clrbits_le32(&ch[chn].phy.ca_cmd[2], 0x1 << 21); + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + write32(regs_bak[i].addr, regs_bak[i].value); + + cke_fix_onoff(CKE_DYNAMIC, CHANNEL_A); + cke_fix_onoff(CKE_DYNAMIC, CHANNEL_B); + + if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600) { + setbits_le32(&ch[chn].phy.shu[0].pll[5], 0x1 << 0); + setbits_le32(&ch[chn].phy.shu[0].pll[7], 0x1 << 0); + setbits_le32(&ch[chn].phy.shu[0].pll[14], 0x1 << 1); + setbits_le32(&ch[chn].phy.shu[0].pll20, 0x1 << 1); + clrsetbits_le32(&ch[chn].phy.shu[0].pll[14], + 0xffff << 16, 0x0208 << 16); + clrsetbits_le32(&ch[chn].phy.shu[0].pll20, + 0xffff << 16, 0x0208 << 16); + clrsetbits_le32(&ch[chn].phy.shu[0].pll[15], + 0xffffffff << 0, delta << 16); + clrsetbits_le32(&ch[chn].phy.shu[0].pll21, + 0xffffffff << 0, delta << 16); } } + +static void dramc_gating_mode(u8 mode) +{ + u8 vref_sel = 0, burst = 0; + + if (mode) { + vref_sel = 2; + burst = 1; + } + + for (u8 b = 0; b < 2; b++) { + clrsetbits_le32(&ch[0].phy.b[b].dq[6], 0x3 << 14, vref_sel << 14); + setbits_le32(&ch[0].phy.b[b].dq[9], 0x1 << 5); + } + + clrsetbits_le32(&ch[0].ao.stbcal1, 0x1 << 5, burst << 5); + setbits_le32(&ch[0].ao.stbcal, 0x1 << 30); + + for (u8 b = 0; b < 2; b++) { + clrbits_le32(&ch[0].phy.b[b].dq[9], (0x1 << 4) | (0x1 << 0)); + udelay(1); + setbits_le32(&ch[0].phy.b[b].dq[9], (0x1 << 4) | (0x1 << 0)); + } +} + +static void update_initial_settings(u8 freq_group) +{ + u8 chn = 0, operate_fsp = get_freq_fsq(freq_group); + u16 rx_vref = 0x16; + + if (operate_fsp == FSP_1) + rx_vref = 0xb; + + if (operate_fsp == FSP_1) { + setbits_le32(&ch[0].ao.shu[0].odtctrl, 0x1 << 0); + setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); + setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); + } else { + clrbits_le32(&ch[0].ao.shu[0].odtctrl, 0x1 << 0); + clrbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); + clrbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); + } + + for (size_t b = 0; b < 2; b++) + for (size_t r = 0; r < 2; r++) + clrbits_le32(&ch[0].phy.r[r].b[b].rxdvs[2], + (0x1 << 23) | (0x1 << 28) | (0x3 << 30)); + clrbits_le32(&ch[0].phy.shu[0].ca_cmd[7], 0xf << 0); + + setbits_le32(&ch[0].phy.ca_cmd[3], 0x1 << 10); + setbits_le32(&ch[0].phy.ca_cmd[10], 0x1 << 5); + clrsetbits_le32(&ch[0].phy.ca_cmd[6], 0x3 << 14, 0x1 << 14); + setbits_le32(&ch[0].phy.b[0].dq[3], 0x7 << 5); + setbits_le32(&ch[0].phy.b[1].dq[3], 0x7 << 5); + setbits_le32(&ch[0].phy.ca_cmd[3], (0x1 << 5) | (0x1 << 7)); + clrbits_le32(&ch[0].phy.b[0].dq[3], 0x1 << 1); + clrbits_le32(&ch[0].phy.b[1].dq[3], 0x1 << 1); + setbits_le32(&ch[0].phy.b[0].dq[5], 0x1 << 31); + setbits_le32(&ch[0].phy.b[1].dq[5], 0x1 << 31); + setbits_le32(&ch[0].phy.ca_cmd[5], 0x1 << 31); + + clrsetbits_le32(&ch[0].phy.ca_cmd[6], 0xf << 16, 0x3 << 16); + clrsetbits_le32(&ch[0].phy.misc_imp_ctrl0, (0x1 << 5) | (0x1 << 6), + (0x1 << 5) | (0x0 << 6)); + setbits_le32(&ch[0].phy.b[0].dq[6], 0x1 << 9); + setbits_le32(&ch[0].phy.b[1].dq[6], 0x1 << 9); + setbits_le32(&ch[0].phy.ca_cmd[6], 0x1 << 9); + clrsetbits_le32(&ch[0].phy.b[0].dq[6], 0x3 << 0, 0x1 << 0); + clrsetbits_le32(&ch[0].phy.b[1].dq[6], 0x1 << 0, 0x1 << 0); + clrsetbits_le32(&ch[0].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0); + + setbits_le32(&ch[0].phy.ca_cmd[6], 0x1 << 6); + setbits_le32(&ch[0].phy.b[0].dq[6], 0x1 << 3); + setbits_le32(&ch[0].phy.b[1].dq[6], 0x1 << 3); + setbits_le32(&ch[0].phy.ca_cmd[6], 0x1 << 3); + setbits_le32(&ch[0].phy.b[0].dq[6], 0x1 << 5); + setbits_le32(&ch[0].phy.b[1].dq[6], 0x1 << 5); + setbits_le32(&ch[0].phy.ca_cmd[6], 0x1 << 5); + + for (u8 b = 0; b < 2; b++) { + clrsetbits_le32(&ch[0].phy.shu[0].b[b].dq[5], 0x3f << 0, rx_vref << 0); + clrsetbits_le32(&ch[0].phy.b[b].dq[5], 0x3f << 8, rx_vref << 8); + } + + for (chn = 0; chn < CHANNEL_MAX; chn++) { + setbits_le32(&ch[chn].phy.b[0].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); + setbits_le32(&ch[chn].phy.b[1].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); + setbits_le32(&ch[chn].phy.ca_cmd[9], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); + } + dramc_gating_mode(1); + + setbits_le32(&ch[0].phy.ca_cmd[8], 0x1 << 19); + clrbits_le32(&ch[0].phy.ca_cmd[8], 0x1 << 18); + clrsetbits_le32(&ch[0].ao.shu[0].misc, 0xf << 0, 0x2 << 0); + clrsetbits_le32(&ch[0].ao.shu[0].dqsg, (0x3f << 20) | (0x1 << 16), + (0x2a << 20) | (0x1 << 16)); + + clrbits_le32(&ch[0].phy.shu[0].b[0].dq[5], 0x3f << 8); + clrbits_le32(&ch[0].phy.shu[0].b[1].dq[5], 0x3f << 8); + clrbits_le32(&ch[0].phy.shu[0].ca_cmd[5], 0x3f << 8); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (chn = 0; chn < CHANNEL_MAX; chn++) { + clrbits_le32(&ch[chn].phy.shu[0].b[0].dq[6], 0x3f << 0); + clrbits_le32(&ch[chn].phy.shu[0].b[1].dq[6], 0x3f << 0); + clrbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], 0x3f << 0); + } + dramc_set_broadcast(DRAMC_BROADCAST_ON); + + /* IMP Tracking Init Settings */ + clrsetbits_le32(&ch[0].ao.shu[0].impcal1, + (0x7 << 0) | (0x7 << 17) | (0xff << 20) | (0xf << 28), + (0x4 << 0) | (0x4 << 17) | (0x10 << 20) | (0x8 << 28)); + + setbits_le32(&ch[0].ao.srefctrl, 0xf << 12); + setbits_le32(&ch[0].ao.pre_tdqsck[0], 0x1 << 17); + setbits_le32(&ch[0].ao.shu[0].misc, 0xf << 12); + clrsetbits_le32(&ch[0].phy.shu[0].b[0].dq[8], + (0xffff << 0) | (0x1 << 15) | (0x3ff << 22), + (0x7fff << 0) | (0x0 << 15) | (0x3ff << 22)); + clrsetbits_le32(&ch[0].phy.shu[0].b[1].dq[8], + (0xffff << 0) | (0x1 << 15) | (0x3ff << 22), + (0x7fff << 0) | (0x0 << 15) | (0x3ff << 22)); + clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[8], + (0xffff << 0) | (0x1 << 15) | (0x3ff << 22), + (0x7fff << 0) | (0x0 << 15) | (0x3ff << 22)); + setbits_le32(&ch[0].phy.misc_ctrl3, 0x1 << 26); + clrbits_le32(&ch[0].phy.shu[0].b[0].dq[7], (0xf << 8) | (0x1 << 12) | (0x1 << 13)); + clrbits_le32(&ch[0].phy.shu[0].b[1].dq[7], (0xf << 8) | (0x1 << 12) | (0x1 << 13)); + clrsetbits_le32(&ch[0].ao.clkar, (0xffff << 0) | (0x1 << 15), + (0x7fff << 0) | (0x1 << 15)); + + clrbits_le32(&ch[0].ao.shu[0].dqsg_retry, 0x1 << 29); + clrbits_le32(&ch[0].ao.write_lev, 0x1 << 2); + setbits_le32(&ch[0].ao.dummy_rd, 0x1 << 24); + clrbits_le32(&ch[0].ao.stbcal2, (0x1 << 0) | (0x1 << 1)); + setbits_le32(&ch[0].ao.eyescan, (0x1 << 8) | (0x1 << 9) | (0x1 << 10)); + setbits_le32(&ch[0].ao.shu[0].odtctrl, (0x1 << 2) | (0x1 << 3)); + + setbits_le32(&ch[0].phy.shu[0].b[0].dll[0], 0x1 << 0); + setbits_le32(&ch[0].phy.shu[0].b[1].dll[0], 0x1 << 0); + setbits_le32(&ch[0].phy.ca_dll_fine_tune[1], 0x1 << 21); + + setbits_le32(&ch[0].ao.perfctl0, (0x1 << 15) | (0x1 << 19) | (0x1 << 26)); + setbits_le32(&ch[0].ao.srefctrl, 0x1 << 22); + clrsetbits_le32(&ch[0].ao.shuctrl1, 0xff << 0, 0x1a << 0); + setbits_le32(&ch[0].phy.b[0].dq[6], (0x1 << 7) | (0x1 << 12)); + setbits_le32(&ch[0].phy.b[1].dq[6], (0x1 << 7) | (0x1 << 12)); + setbits_le32(&ch[0].phy.ca_cmd[6], (0x1 << 7) | (0x1 << 12)); + setbits_le32(&ch[0].ao.stbcal2, 0x1 << 16); + clrsetbits_le32(&ch[0].phy.shu[0].b[0].dq[7], + (0x7 << 29) | (0x1 << 28) | (0x7 << 25) | (0x1 << 24), + (0x0 << 29) | (0x1 << 28) | (0x1 << 25) | (0x1 << 24)); + clrsetbits_le32(&ch[0].phy.shu[0].b[1].dq[7], + (0x7 << 29) | (0x1 << 28) | (0x7 << 25) | (0x1 << 24), + (0x0 << 29) | (0x1 << 28) | (0x1 << 25) | (0x1 << 24)); + + /* Disable RODT tracking */ + clrbits_le32(&ch[0].ao.shu[0].rodtenstb, 0x1 << 0); + + /* Rx Gating tracking settings */ + clrsetbits_le32(&ch[0].ao.shu[0].dqsg, + (0x1 << 11) | (0xf << 12), (0x1 << 11) | (0x9 << 12)); + clrbits_le32(&ch[0].ao.shu[0].rk[0].dqscal, (0x1 << 7) | (0x1 << 15)); + clrbits_le32(&ch[0].ao.shu[0].rk[1].dqscal, (0x1 << 7) | (0x1 << 15)); + clrsetbits_le32(&ch[0].ao.shu[0].stbcal, + (0x7 << 4) | (0x1 << 8), (0x1 << 4) | (0x1 << 8)); + + clrsetbits_le32(&ch[0].phy.b[0].dq[9], 0xff << 8, 0x4 << 8); + clrsetbits_le32(&ch[0].phy.b[1].dq[9], 0xff << 8, 0x4 << 8); + clrbits_le32(&ch[0].phy.ca_cmd[10], 0xff << 8); + + setbits_le32(&ch[0].phy.shu[0].b[0].dq[8], 0x1 << 24); + setbits_le32(&ch[0].phy.shu[0].b[1].dq[8], 0x1 << 24); + + /* Enable WDQS */ + clrsetbits_le32(&ch[0].phy.shu[0].b[0].dll[1], + (0x1 << 10) | (0x1 << 16) | (0x1 << 17), + (0x1 << 10) | (!operate_fsp << 16) | (0x1 << 17)); + clrsetbits_le32(&ch[0].phy.shu[0].b[1].dll[1], + (0x1 << 10) | (0x1 << 16) | (0x1 << 17), + (0x1 << 10) | (!operate_fsp << 16) | (0x1 << 17)); + setbits_le32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0) | (0x1 << 30) | (0x1 << 31)); + setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); + setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); + setbits_le32(&ch[0].ao.drsctrl, 0x1 << 19); + setbits_le32(&ch[0].ao.refctrl0, 0x1 << 28); + setbits_le32(&ch[0].ao.zqcs, 0x1 << 19); + setbits_le32(&ch[0].ao.dummy_rd, 0x3 << 26); + setbits_le32(&ch[0].ao.shuctrl2, 0x1 << 8); + clrsetbits_le32(&ch[0].ao.shuctrl3, 0xff << 24, 0xb << 24); + setbits_le32(&ch[0].phy.misc_ctrl3, 0x1 << 27); + setbits_le32(&ch[0].phy.b[0].dll_fine_tune[1], 0x3 << 20); + setbits_le32(&ch[0].phy.b[1].dll_fine_tune[1], 0x3 << 20); + setbits_le32(&ch[0].phy.ca_dll_fine_tune[1], 0x1 << 20); + clrbits_le32(&ch[0].phy.misc_ctrl0, 0x1 << 27); + setbits_le32(&ch[0].phy.misc_rxdvs[2], 0x1 << 8); + setbits_le32(&ch[0].ao.clkctrl, 0x1 << 7); + setbits_le32(&ch[0].ao.refctrl1, 0x1 << 7); + clrsetbits_le32(&ch[0].ao.shuctrl, (0x1 << 2) | (0x3 << 6) | (0x3 << 26), + (0x0 << 2) | (0x3 << 6) | (0x3 << 26)); + setbits_le32(&ch[0].ao.shuctrl2, (0x1 << 31) | (0x3 << 10)); + clrbits_le32(&ch[0].ao.stbcal2, 0xf << 4); + clrbits_le32(&ch[0].ao.pre_tdqsck[0], 0x3 << 19); + + setbits_le32(&ch[0].ao.ckectrl, 0x1 << 22); + clrsetbits_le32(&ch[0].phy.ca_tx_mck, (0x1 << 31) | (0x1f << 21) | (0x1f << 26), + (0x1 << 31) | (0xa << 21) | (0xa << 26)); + + setbits_le32(&ch[0].ao.ckectrl, 0x1 << 23); + + /* Gating error problem happened in M17 + * has been solved by setting this RG as 0 */ + clrbits_le32(&ch[0].ao.shu[0].rodtenstb, 0x1 << 31); + +} + +static void dramc_power_on_sequence(void) +{ + for (size_t chn = 0; chn < CHANNEL_MAX; chn++) + clrbits_le32(&ch[chn].phy.misc_ctrl1, 0x1 << 13); + + dramc_cke_fix_onoff(CHANNEL_A, false, true); + dramc_cke_fix_onoff(CHANNEL_B, false, true); + + udelay(200); + for (size_t chn = 0; chn < CHANNEL_MAX; chn++) + setbits_le32(&ch[chn].phy.misc_ctrl1, 0x1 << 13); + + for (size_t chn = 0; chn < CHANNEL_MAX; chn++) + setbits_le32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26); + + udelay(2000); + dramc_cke_fix_onoff(CHANNEL_A, true, false); + dramc_cke_fix_onoff(CHANNEL_B, true, false); + udelay(2); +} + +static void ddr_phy_reserved_rg_setting(u8 freq_group) +{ + u32 hyst_sel = 0, midpi_cap_sel = 0, lp3_sel = 0; + + if (get_freq_fsq(freq_group) == FSP_0) { + hyst_sel = 1; + midpi_cap_sel = 1; + } + + if (freq_group == LP4X_DDR1600) + lp3_sel = 1; + + /* fine tune */ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], 0xFFFF << 6, + (0x1 << 6) | ((!chn) << 7) | (hyst_sel << 8) | + (midpi_cap_sel << 9) | (0x1 << 10) | (0x3 << 17) | (lp3_sel << 20)); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[1], + (0xf << 9) | (0x1f << 16) | (0x7ff << 21), + (0x1 << 8) | (0x7 << 13) | (0x4 << 16)); + + for (u8 b = 0; b < 2; b++) { + clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dq[6], + (0x1f << 6) | (0x3f << 11) | (0x7 << 19), + (0x1 << 6) | (hyst_sel << 8) | (midpi_cap_sel << 9) + | (0x1 << 10) | (0x3 << 17) | (lp3_sel << 20)); + + clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dll[1], + (0x3 << 8) | (0x3 << 11) | (0x7 << 14) | (0x3fff << 18), + (0x1 << 10) | (0x1 << 13) | (0x1 << 17)); + } + } +} + +static void dramc_duty_set_clk_delay(u8 chn, s8 clkDelay) +{ + u8 dly, dlyb, revb0, revb1; + + dly = (clkDelay < 0) ? -clkDelay : 0; + dlyb = (clkDelay < 0) ? 0 : clkDelay; + revb0 = dly ? 1 : 0; + revb1 = dlyb ? 1 : 0; + + for (u8 r = 0; r < RANK_MAX; r++) { + clrsetbits_le32(&ch[chn].phy.shu[0].rk[r].ca_cmd[1], + (0xf << 24) | (0xf << 28), (dly << 24) | (dly << 28)); + clrsetbits_le32(&ch[chn].phy.shu[0].rk[r].ca_cmd[0], + (0xf << 24) | (0xf << 28), (dlyb << 24) | (dlyb << 28)); + } + clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[3], + (0x3 << 8), (revb0 << 8) | (revb1 << 9)); +} + +static void dramc_duty_set_dqs_delay(u8 chn, const s8 *s_dqsDelay) +{ + u8 dly, dlyb, revb0, revb1; + s8 dqsDelay; + + for (u8 r = 0; r < RANK_MAX; r++) + for (u8 dqs = 0; dqs < DQS_NUMBER; dqs++) { + dqsDelay = s_dqsDelay[dqs]; + + dly = (dqsDelay < 0) ? -dqsDelay : 0; + dlyb = (dqsDelay < 0) ? 0 : dqsDelay; + revb0 = dly ? 1 : 0; + revb1 = dlyb ? 1 : 0; + clrsetbits_le32(&ch[chn].phy.shu[0].rk[r].b[dqs].dq[1], + (0xf << 24) | (0xf << 28) | (0xf << 16) | (0xf << 20), + (dly << 24) | (dly << 28) | (dlyb << 16) | (dlyb << 20)); + } + clrsetbits_le32(&ch[chn].phy.shu[0].b[0].dll[1], + 0x3 << 8, (revb0 << 8) | (revb1 << 9)); +} + +static void dramc_duty_calibration(const struct sdram_params *params, u8 freq_group) +{ + s8 clkDelay[CHANNEL_MAX] = {0x0}; + s8 dqsDelay[CHANNEL_MAX][DQS_NUMBER] = {0x0}; + + switch (freq_group) { + case LP4X_DDR1600: + clkDelay[CHANNEL_A] = 2; + clkDelay[CHANNEL_B] = 1; + dqsDelay[CHANNEL_A][0] = 0; + dqsDelay[CHANNEL_A][1] = 0; + dqsDelay[CHANNEL_B][0] = -1; + dqsDelay[CHANNEL_B][1] = 0; + break; + case LP4X_DDR2400: + clkDelay[CHANNEL_A] = clkDelay[CHANNEL_B] = 0; + dqsDelay[CHANNEL_A][0] = 0; + dqsDelay[CHANNEL_A][1] = -2; + dqsDelay[CHANNEL_B][0] = 0; + dqsDelay[CHANNEL_B][1] = -2; + break; + case LP4X_DDR3200: + clkDelay[CHANNEL_A] = clkDelay[CHANNEL_B] = 1; + dqsDelay[CHANNEL_A][0] = 1; + dqsDelay[CHANNEL_A][1] = -2; + dqsDelay[CHANNEL_B][0] = 1; + dqsDelay[CHANNEL_B][1] = -2; + break; + case LP4X_DDR3600: + clkDelay[CHANNEL_A] = 2; + clkDelay[CHANNEL_B] = 1; + dqsDelay[CHANNEL_A][0] = 0; + dqsDelay[CHANNEL_A][1] = 0; + dqsDelay[CHANNEL_B][0] = -1; + dqsDelay[CHANNEL_B][1] = 0; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + dramc_duty_set_clk_delay(chn, clkDelay[chn]); + dramc_duty_set_dqs_delay(chn, dqsDelay[chn]); + } +} + +static u8 dramc_zq_calibration(u8 chn, u8 rank) +{ + const u32 TIMEOUT_US = 100; + + struct reg_value regs_bak[] = { + {&ch[chn].ao.mrs, 0x0}, + {&ch[chn].ao.dramc_pd_ctrl, 0x0}, + {&ch[chn].ao.ckectrl, 0x0}, + }; + + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + regs_bak[i].value = read32(regs_bak[i].addr); + + setbits_le32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26); + dramc_cke_fix_onoff(chn, true, false); + + clrsetbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK, rank << MRS_MRSRK_SHIFT); + setbits_le32(&ch[chn].ao.mpc_option, 0x1 << MPC_OPTION_MPCRKEN_SHIFT); + setbits_le32(&ch[chn].ao.spcmd, 0x1 << SPCMD_ZQCEN_SHIFT); + + if (!wait_us(TIMEOUT_US, read32(&ch[chn].nao.spcmdresp) & 0x1 << 4)) { + dramc_dbg("ZQCAL Start fail (time out)\n"); + return 1; + } + + clrbits_le32(&ch[chn].ao.spcmd, 0x1 << SPCMD_ZQCEN_SHIFT); + + udelay(1); + setbits_le32(&ch[chn].ao.spcmd, 0x1 << SPCMD_ZQLATEN_SHIFT); + + if (!wait_us(TIMEOUT_US, read32(&ch[chn].nao.spcmdresp) & 0x1 << 6)) { + dramc_dbg("ZQCAL Latch fail (time out)\n"); + return 1; + } + + clrbits_le32(&ch[chn].ao.spcmd, 0x1 << SPCMD_ZQLATEN_SHIFT); + udelay(1); + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + write32(regs_bak[i].addr, regs_bak[i].value); + + return 0; +} + +u8 MR01Value[FSP_MAX] = {0x26, 0x56}; +u8 MR13Value = (1 << 4) | (1 << 3); +static void dramc_mode_reg_init(u8 freq_group) +{ + u8 MR02Value[FSP_MAX] = {0x12, 0x12}; + u8 MR03Value = 0x30; + u8 MR11Value[FSP_MAX] = {0x0, 0x23}; + u8 MR12Value[CHANNEL_MAX][RANK_MAX][FSP_MAX] = { + {{0x5d, 0x5d}, {0x5d, 0x5d} }, {{0x5d, 0x5d}, {0x5d, 0x5d} }, + }; + u8 MR14Value[CHANNEL_MAX][RANK_MAX][FSP_MAX] = { + {{0x5d, 0x10}, {0x5d, 0x10} }, {{0x5d, 0x10}, {0x5d, 0x10} }, + }; + + u8 MR22Value[FSP_MAX] = {0x38, 0x34}; + + MR01Value[FSP_0] &= 0x8F; + MR01Value[FSP_1] &= 0x8F; + + if (freq_group == LP4X_DDR1600) { + MR02Value[0] = 0x12; + MR02Value[1] = 0x00; + + MR01Value[FSP_0] |= (0x5 << 4); + MR01Value[FSP_1] |= (0x5 << 4); + } else if (freq_group == LP4X_DDR2400) { + MR02Value[0] = 0x24; + MR02Value[1] = 0x2d; + + MR01Value[FSP_0] |= (0x5 << 4); + MR01Value[FSP_1] |= (0x5 << 4); + } else if (freq_group == LP4X_DDR3200) { + MR02Value[0] = 0x12; + MR02Value[1] = 0x2d; + + MR01Value[FSP_0] |= (0x5 << 4); + MR01Value[FSP_1] |= (0x5 << 4); + } else if (freq_group == LP4X_DDR3600) { + MR02Value[0] = 0x1A; + MR02Value[1] = 0x36; + + MR01Value[FSP_0] |= (0x6 << 4); + MR01Value[FSP_1] |= (0x6 << 4); + } + + u8 operate_fsp = get_freq_fsq(freq_group); + dramc_dbg("%s operate_fsp:%d, freq:%d\n", __func__, operate_fsp, freq_group); + + u8 chn, rank; + u32 broadcast_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + dramc_power_on_sequence(); + + for (chn = 0; chn < CHANNEL_MAX; chn++) { + for (rank = 0; rank < 2; rank++) { + clrsetbits_le32(&ch[chn].ao.mrs, 0x3 << 24, rank << 24); + + dramc_zq_calibration(chn, rank); + + for (uint32_t fsp = FSP_0; fsp < FSP_MAX; fsp++) { + dramc_dbg("chn:%d,rank:%d,fsp%d\n", chn, rank, fsp); + + if (fsp == FSP_0) + MR13Value = (1 << 4) | (1 << 3); + else + MR13Value |= 0x40; + dramc_mode_reg_write(chn, 0xd, MR13Value); + dramc_mode_reg_write(chn, 0xc, + MR12Value[chn][rank][fsp]); + dramc_mode_reg_write(chn, 0x1, MR01Value[fsp]); + dramc_mode_reg_write(chn, 0x2, MR02Value[fsp]); + dramc_mode_reg_write(chn, 0xb, MR11Value[fsp]); + + dramc_mode_reg_write(chn, 0x16, MR22Value[fsp]); + dramc_mode_reg_write(chn, 0xe, + MR14Value[chn][rank][fsp]); + + /* MR3 set write-DBI and read-DBI */ + dramc_mode_reg_write(chn, 0x3, MR03Value); + } + + if (operate_fsp == FSP_0) + MR13Value &= 0x3f; + else + MR13Value |= 0xc0; + dramc_mode_reg_write(chn, 0xd, MR13Value); + } + + clrsetbits_le32(&ch[chn].ao.shu[0].hwset_mr13, + (0x1fff << 0) | (0xff << 16), + (13 << 0) | ((MR13Value | (0x1 << 3)) << 16)); + clrsetbits_le32(&ch[chn].ao.shu[0].hwset_vrcg, + (0x1fff << 0) | (0xff << 16), + (13 << 0) | ((MR13Value | (0x1 << 3)) << 16)); + clrsetbits_le32(&ch[chn].ao.shu[0].hwset_mr2, + (0x1fff << 0) | (0xff << 16), + (2 << 0) | (MR02Value[operate_fsp] << 16)); + } + + clrsetbits_le32(&ch[0].ao.mrs, 0x3 << 24, RANK_0 << 24); + clrsetbits_le32(&ch[1].ao.mrs, 0x3 << 24, RANK_0 << 24); + dramc_set_broadcast(broadcast_bak); +} + +static void auto_refresh_cke_off(void) +{ + u32 broadcast_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + setbits_le32(&ch[chn].ao.refctrl0, 0x1 << 29); + + udelay(3); + cke_fix_onoff(CKE_FIXOFF, CHANNEL_A); + cke_fix_onoff(CKE_FIXOFF, CHANNEL_B); + + dramc_set_broadcast(broadcast_bak); +} + +static void dramc_setting_DDR1600(void) +{ + clrsetbits_le32(&ch[0].ao.shu[0].rankctl, + (0xf << 20) | (0xf << 24) | (0xf << 28), + (0x0 << 20) | (0x0 << 24) | (0x2 << 28)); + clrbits_le32(&ch[0].ao.shu[0].ckectrl, 0x3 << 24); + clrbits_le32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0) | (0x3 << 30)); + + clrbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); + clrbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); + + clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_1600); + clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_1600); + clrsetbits_le32(&ch[0].ao.shu[0].wodt, (0x1 << 29) | (0x1 << 31), + (0x0 << 29) | (0x1 << 31)); + clrsetbits_le32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0, 0x4 << 0); + + for (size_t rank = 0; rank < 2; rank++) { + int value = ((rank == 0) ? 0x1a : 0x1e); + clrbits_le32(&ch[0].ao.shu[0].rk[rank].dqsien, (0x7f << 0) | (0x7f << 8)); + clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].fine_tune, + (0x3f << 0) | (0x3f << 8) | (0x3f << 16) | (0x3f << 24), + (value << 0) | (value << 8) | (value << 16) | (value << 24)); + + clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[0], + (0x7 << 8) | (0x7 << 12) | + (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28), + (0x2 << 8) | (0x2 << 12) | + (0x1 << 16) | (0x1 << 20) | (0x1 << 24) | (0x1 << 28)); + clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[1], + (0x7 << 8) | (0x7 << 12) | + (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28), + (0x2 << 8) | (0x2 << 12) | + (0x1 << 16) | (0x1 << 20) | (0x1 << 24) | (0x1 << 28)); + clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], + 0x77777777, + (0x1 << 0) | (0x1 << 4) | (0x1 << 8) | (0x1 << 12) | + (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28)); + clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], + 0x77777777, + (0x1 << 0) | (0x1 << 4) | (0x1 << 8) | (0x1 << 12) | + (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28)); + } + + clrsetbits_le32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8), + (0x0 << 2) | (0x3 << 8)); + clrsetbits_le32(&ch[0].phy.b[0].dq[5], 0x7 << 20, 0x4 << 20); + + clrsetbits_le32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), + (0x2 << 4) | (0x0 << 7) | (0x0 << 13)); + clrsetbits_le32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x4 << 20); + clrbits_le32(&ch[0].phy.b[0].dq[7], (0x1 << 7) | (0x1 << 13)); + + for (size_t r = 0; r < 2; r++) { + int value = ((r == 0) ? 0x1a : 0x26); + for (size_t b = 0; b < 2; b++) + clrsetbits_le32(&ch[0].phy.shu[0].rk[r].b[b].dq[7], + (0x3f << 8) | (0x3f << 16), + (value << 8) | (value << 16)); + } +} + +static void dramc_setting_DDR2400(void) +{ + clrsetbits_le32(&ch[0].ao.shu[0].rankctl, + (0xf << 20) | (0xf << 24) | (0xf << 28), + (0x2 << 20) | (0x2 << 24) | (0x4 << 28)); + clrsetbits_le32(&ch[0].ao.shu[0].ckectrl, 0x3 << 24, 0x3 << 24); + setbits_le32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0) | (0x1 << 30) | (0x1 << 31)); + + setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); + setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); + + clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_2400); + clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_2400); + clrsetbits_le32(&ch[0].ao.shu[0].wodt, + (0x1 << 29) | (0x1 << 31), (0x1 << 29) | (0x0 << 31)); + clrsetbits_le32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0, 0x7 << 0); + + for (size_t rank = 0; rank < 2; rank++) { + int value = ((rank == 0) ? 0x19 : 0x1f); + clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].dqsien, + (0x7f << 0) | (0x7f << 8), (value << 0) | (value << 8)); + clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].fine_tune, + (0x3f << 0) | (0x3f << 8) | (0x3f << 16) | (0x3f << 24), + (0x14 << 0) | (0x14 << 8) | (0x14 << 16) | (0x14 << 24)); + + clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[0], + (0x7 << 8) | (0x7 << 12) | + (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28), + (0x3 << 8) | (0x3 << 12) | + (0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28)); + clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[1], + (0x7 << 8) | (0x7 << 12) | + (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28), + (0x3 << 8) | (0x3 << 12) | + (0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28)); + clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], + 0x77777777, + (0x2 << 0) | (0x2 << 4) | (0x2 << 8) | (0x2 << 12) | + (0x0 << 16) | (0x0 << 20) | (0x0 << 24) | (0x0 << 28)); + clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], + 0x77777777, + (0x2 << 0) | (0x2 << 4) | (0x2 << 8) | (0x2 << 12) | + (0x0 << 16) | (0x0 << 20) | (0x0 << 24) | (0x0 << 28)); + } + + clrsetbits_le32(&ch[0].ao.shu[0].dqsg_retry, + (0x1 << 2) | (0xf << 8), (0x1 << 2) | (0x4 << 8)); + clrsetbits_le32(&ch[0].phy.b[0].dq[5], 0x7 << 20, 0x3 << 20); + clrsetbits_le32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), + (0x1 << 4) | (0x1 << 7) | (0x1 << 13)); + clrsetbits_le32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x3 << 20); + clrsetbits_le32(&ch[0].phy.b[0].dq[7], + (0x1 << 7) | (0x1 << 13), (0x1 << 7) | (0x1 << 13)); + + for (size_t r = 0; r < 2; r++) { + for (size_t b = 0; b < 2; b++) + clrsetbits_le32(&ch[0].phy.shu[0].rk[r].b[b].dq[7], + (0x3f << 8) | (0x3f << 16), (0x14 << 8) | (0x14 << 16)); + } +} + +static void dramc_setting_DDR3600(void) +{ + clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_3600); + clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_3600); +} + +static void dramc_setting(const struct sdram_params *params, u8 freq_group) +{ + u8 chn; + + auto_refresh_cke_off(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + + for (chn = 0; chn < CHANNEL_MAX; chn++) + setbits_le32(&ch[chn].phy.ckmux_sel, (0x1 << 0) | (0x1 << 1)); + + dramc_set_broadcast(DRAMC_BROADCAST_ON); + + setbits_le32(&ch[0].phy.misc_cg_ctrl0, 0x1 << 0); + + /* 26M */ + clrbits_le32(&ch[0].phy.misc_cg_ctrl0, 0x3 << 4); + clrbits_le32(&ch[0].phy.misc_ctrl0, 0x1 << 17); + + clrbits_le32(&ch[0].phy.misc_spm_ctrl1, 0xf << 0); + write32(&ch[0].phy.misc_spm_ctrl2, 0x0); + write32(&ch[0].phy.misc_spm_ctrl0, 0x0); + write32(&ch[0].phy.misc_cg_ctrl2, 0x6003bf); + write32(&ch[0].phy.misc_cg_ctrl4, 0x333f3f00); + setbits_le32(&ch[0].phy.shu[0].pll[1], (0x1 << 4) | (0x7 << 1)); + clrsetbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x3f << 0, 0x10 << 0); + clrbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x0f << 0); + + for (size_t b = 0; b <= 2; b += 2) + clrsetbits_le32(&ch[0].phy.shu[0].pll[4 + b], + (0x3 << 18) | (0x3 << 24) | (0x3 << 26), + (0x2 << 18) | (0x1 << 24) | (0x1 << 26)); + + clrbits_le32(&ch[0].phy.shu[0].pll[14], 0x1 << 1); + clrbits_le32(&ch[0].phy.shu[0].pll20, 0x1 << 1); + clrbits_le32(&ch[0].phy.ca_cmd[2], (0x3 << 16) | (0x3 << 20)); + for (size_t b = 0; b < 2; b++) + clrbits_le32(&ch[0].phy.b[b].dq[2], (0x3 << 16) | (0x3 << 20)); + for (size_t b = 0; b < 2; b++) + clrsetbits_le32(&ch[0].phy.b[b].dq[9], 0x7 << 28, 0x1 << 28); + clrbits_le32(&ch[0].phy.ca_cmd[10], 0x7 << 28); + + setbits_le32(&ch[0].phy.b0_rxdvs[0], 0x1 << 28); + setbits_le32(&ch[0].phy.b1_rxdvs[0], 0x1 << 28); + setbits_le32(&ch[0].phy.b0_rxdvs[0], 0x1 << 9); + setbits_le32(&ch[0].phy.b1_rxdvs[0], 0x1 << 9); + + for (size_t b = 0; b < 2; b++) { + for (size_t r = 0; r < 2; r++) + setbits_le32(&ch[0].phy.r[r].b[b].rxdvs[2], 0x1 << 29); + clrsetbits_le32(&ch[0].phy.shu[0].b[b].dq[5], 0x7 << 20, 0x3 << 20); + + for (size_t r = 0; r < 2; r++) { + clrsetbits_le32(&ch[0].phy.r[r].b[b].rxdvs[1], + (0xffff << 0) | (0xffff << 16), (0x2 << 0) | (0x2 << 16)); + clrsetbits_le32(&ch[0].phy.r[r].b[b].rxdvs[2], + (0x1 << 23) | (0x1 << 28) | (0x3 << 30), + (0x1 << 23) | (0x1 << 28) | (0x2 << 30)); + } + } + + clrbits_le32(&ch[0].phy.b0_rxdvs[0], 0x1 << 28); + clrbits_le32(&ch[0].phy.b1_rxdvs[0], 0x1 << 28); + + for (size_t b = 0; b < 2; b++) { + setbits_le32(&ch[0].phy.b[b].dq[9], 0x1 << 0); + for (size_t r = 0; r < 2; r++) + clrsetbits_le32(&ch[0].phy.shu[0].rk[r].b[b].dq[7], + (0x3f << 8) | (0x3f << 16), (0x1f << 8) | (0x1f << 16)); + + clrsetbits_le32(&ch[0].phy.b[b].dq[4], + (0x7f << 0) | (0x7f << 8), (0x10 << 0) | (0x10 << 8)); + clrsetbits_le32(&ch[0].phy.b[b].dq[5], + (0xff << 0) | (0x3f << 8) | (0x1 << 16) | (0xf << 20) | (0x1 << 24), + (0x10 << 0) | (0xe << 8) | (0x1 << 16) | (0x1 << 20) | (0x0 << 24)); + clrsetbits_le32(&ch[0].phy.b[b].dq[6], + (0x1 << 4) | (0x1 << 7) | (0x1 << 12) | (0x3 << 14) | + (0xf << 16) | (0x1 << 24), + (0x0 << 4) | (0x1 << 7) | (0x1 << 12) | (0x0 << 14) | + (0x3 << 16) | (0x1 << 24)); + clrsetbits_le32(&ch[0].phy.b[b].dq[5], + (0xff << 0) | (0x1 << 25), (0x0 << 0) | (0x1 << 25)); + } + + setbits_le32(&ch[0].phy.ca_cmd[3], (0x3 << 2) | (0x1 << 7)); + clrsetbits_le32(&ch[0].phy.ca_cmd[6], (0x1 << 6) | (0x3 << 14) | (0x1 << 16), + (0x0 << 6) | (0x0 << 14) | (0x0 << 16)); + + clrbits_le32(&ch[0].phy.pll3, 0x1 < 0); + setbits_le32(&ch[0].phy.b[0].dq[3], 0x1 << 3); + setbits_le32(&ch[0].phy.b[1].dq[3], 0x1 << 3); + + udelay(1); + clrsetbits_le32(&ch[0].phy.shu[0].pll[8], + (0x7 << 0) | (0x3 << 18), (0x0 << 0) | (0x1 << 18)); + + udelay(1); + clrbits_le32(&ch[0].phy.shu[0].pll[9], + (0x3 << 8) | (0x1 << 12) | (0x3 << 14) | (0x1 << 16)); + clrbits_le32(&ch[0].phy.shu[0].pll[11], + (0x3 << 8) | (0x1 << 12) | (0x3 << 14) | (0x1 << 16)); + udelay(1); + + clrsetbits_le32(&ch[0].phy.shu[0].pll[10], + (0x7 << 0) | (0x3 << 18), (0x0 << 0) | (0x1 << 18)); + udelay(1); + + /* PLL EN */ + /* MID FINE_TUNE Init 1 */ + clrsetbits_le32(&ch[0].phy.pll4, (0x3 << 18) | (0x1 << 21), 0x3 << 18); + + udelay(1); + clrsetbits_le32(&ch[0].phy.shu[0].pll[0], 0xffff << 0, 0x3 << 0); + + udelay(1); + setbits_le32(&ch[0].phy.ca_dll_fine_tune[1], 0x1 << 21); + + for (size_t b = 0; b < 2; b++) + setbits_le32(&ch[0].phy.b[b].dq[3], (0x3 << 1) | (0x1 << 10)); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + setbits_le32(&ch[0].phy.shu[0].ca_dll[0], 0x1 << 0); + setbits_le32(&ch[1].phy.shu[0].ca_dll[0], 0x1 << 0); + dramc_set_broadcast(DRAMC_BROADCAST_ON); + + for (size_t b = 0; b < 2; b++) + clrsetbits_le32(&ch[0].phy.shu[0].b[b].dll[0], + (0x1 << 4) | (0x3 << 9) | (0xf << 12) | + (0xf << 16) | (0xf << 20) | (0x1 << 30), + (0x0 << 4) | (0x3 << 9) | (0x8 << 12) | + (0x7 << 16) | (0x7 << 20) | (0x1 << 30)); + + clrbits_le32(&ch[0].phy.shu[0].ca_cmd[5], 0x3f << 0); + clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[0], + (0x1 << 4) | (0x7 << 12) | (0x1 << 20), + (0x1 << 4) | (0x4 << 12) | (0x1 << 20)); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[6], 0xffff << 6, 0x3 << 6); + clrsetbits_le32(&ch[1].phy.shu[0].ca_cmd[6], 0xffff << 6, 0x1 << 6); + dramc_set_broadcast(DRAMC_BROADCAST_ON); + + for (size_t b = 0; b < 2; b++) + clrsetbits_le32(&ch[0].phy.shu[0].b[b].dq[6], 0xffff << 6, 0x1 << 6); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (size_t chan = 0; chan < 2; chan++) + clrsetbits_le32(&ch[chan].phy.misc_shu_opt, + (0x1 << 0) | (0x3 << 2) | (0x1 << 8) | + (0x3 << 10) | (0x1 << 16) | (0x3 << 18), + (0x1 << 0) | (0x2 << 2) | (0x1 << 8) | + (0x2 << 10) | (0x1 << 16) | ((0x1+chan) << 18)); + + udelay(9); + clrsetbits_le32(&ch[0].phy.shu[0].ca_dll[1], (0x1 << 0) | (0x1 << 2), 0x1 << 2); + clrsetbits_le32(&ch[1].phy.shu[0].ca_dll[1], (0x1 << 0) | (0x1 << 2), 0x1 << 0); + dramc_set_broadcast(DRAMC_BROADCAST_ON); + + for (size_t b = 0; b < 2; b++) { + clrsetbits_le32(&ch[0].phy.shu[0].b[b].dll[1], + (0x1 << 0) | (0x1 << 2), (0x1 << 0) | (0x0 << 2)); + } + udelay(1); + + clrbits_le32(&ch[0].phy.pll2, 0x1 << 31); + clrsetbits_le32(&ch[0].phy.misc_cg_ctrl0, 0xffffffff, 0xF); + udelay(1); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + ddr_phy_reserved_rg_setting(freq_group); + for (chn = 0; chn < CHANNEL_MAX; chn++) + ddr_phy_pll_setting(chn, freq_group); + + dramc_set_broadcast(DRAMC_BROADCAST_ON); + setbits_le32(&ch[0].ao.drsctrl, 0x1 << 29); + + /* Set Run time MRR CKE fix to 1 in tMRRI old mode + * to avoid no ACK from precharge all */ + setbits_le32(&ch[0].ao.ckectrl, 0x1 << 27); + clrsetbits_le32(&ch[0].ao.dramctrl, + (0x1 << 15) | (0x1 << 17) | (0x1 << 23), + (0x0 << 15) | (0x1 << 17) | (0x1 << 23)); + setbits_le32(&ch[0].ao.spcmdctrl, (0x1 << 1) | (0x1 << 8) | (0x1 << 9) | (0x1 << 10)); + setbits_le32(&ch[0].phy.b[0].dq[9], 0x1 << 4); + setbits_le32(&ch[0].phy.b[1].dq[9], 0x1 << 4); + + clrsetbits_le32(&ch[0].ao.shu[0].rk[1].dqsien, + (0x7f << 0) | (0x7f << 8) | (0x7f << 16) | (0x7f << 24), + (0xf << 0) | (0xf << 8) | (0xf << 16) | (0xf << 24)); + clrsetbits_le32(&ch[0].ao.stbcal1, + (0x1 << 4) | (0x1 << 8) | (0x1 << 12), (0x1 << 4) | (0x1 << 8)); + clrsetbits_le32(&ch[0].ao.shu[0].dqsg_retry, + (0x1 << 3) | (0xf << 8) | (0x1 << 21) | (0x1 << 31), + (0x1 << 3) | (0x6 << 8) | (0x1 << 21) | (0x1 << 31)); + + for (size_t i = 0; i < 4; i++) { + clrsetbits_le32(&ch[0].ao.shu[0].drving[i], + (0x1f << 0) | (0x1f << 5) | (0x1f << 10) | + (0x1f << 15) | (0x1f << 20) | (0x1f << 25), + (0xa << 0) | (0xa << 5) | (0xa << 10) | + (0xa << 15) | (0xa << 20) | (0xa << 25)); + } + + clrsetbits_le32(&ch[0].ao.shuctrl2, + (0x3f << 0) | (0x1 << 12) | (0x1 << 14) | + (0x1 << 15) | (0xff << 16) | (0x1 << 24), + (0xa << 0) | (0x1 << 12) | (0x1 << 14) | + (0x1 << 15) | (0x1 << 16) | (0x0 << 24)); + setbits_le32(&ch[0].ao.dvfsdll, 0x1 << 0); + setbits_le32(&ch[0].ao.ddrconf0, + (0x1 << 12) | (0x1 << 15) | (0x1 << 20) | (0x1 << 26)); + setbits_le32(&ch[0].ao.stbcal2, (0x1 << 4) | (0x7 << 28)); + clrbits_le32(&ch[0].ao.stbcal2, 0x1 << 29); + setbits_le32(&ch[0].ao.clkar, 0x1 << 19); + + for (size_t b = 0; b < 2; b++) + clrsetbits_le32(&ch[0].phy.b[b].dq[9], 0x7 << 20, 0x1 << 20); + clrsetbits_le32(&ch[0].phy.ca_cmd[10], 0x7 << 20, 0x0 << 20); + setbits_le32(&ch[0].phy.misc_ctrl0, + (0xf << 0) | (0x1 << 9) | (0x1 << 24) | (0x1 << 31)); + + for (chn = 0; chn < CHANNEL_MAX; chn++) + setbits_le32(&ch[chn].phy.misc_ctrl1, + (0x1 << 2) | (0x1 << 3) | (0x1 << 15) | (0x1 << 24)); + clrsetbits_le32(&ch[0].phy.b0_rxdvs[0], 0x1 << 24, 0x1 << 24); + clrsetbits_le32(&ch[0].phy.b1_rxdvs[0], 0x1 << 24, 0x1 << 24); + clrsetbits_le32(&ch[0].phy.ca_rxdvs0, 0x1 << 24, 0x0 << 24); + clrbits_le32(&ch[0].phy.ca_cmd[7], (0x1 << 4) | (0x1 << 6)); + clrbits_le32(&ch[0].phy.b[0].dq[7], 0x1 << 6); + clrbits_le32(&ch[0].phy.b[1].dq[7], 0x1 << 6); + + clrsetbits_le32(&ch[0].ao.shu[0].conf[0], + (0x3f << 0) | (0x1 << 7) | (0xf << 12) | (0x1 << 24) | + (0x1 << 29) | (0x3 << 30), + (0x3f << 0) | (0x1 << 7) | (0x1 << 12) | (0x1 << 24) | + (0x1 << 29) | (0x2 << 30)); + clrsetbits_le32(&ch[0].ao.shu[0].odtctrl, + (0x1 << 0) | (0x1 << 1) | (0x7f << 16) | (0x1 << 30) | (0x1 << 31), + (0x1 << 0) | (0x1 << 1) | (0x1 << 16) | (0x1 << 30) | (0x1 << 31)); + setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); + setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); + + clrsetbits_le32(&ch[0].ao.refctrl0, 0xf << 24, 0x5 << 24); + clrbits_le32(&ch[0].ao.shu[0].selph_ca1, + (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) | + (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28)); + clrsetbits_le32(&ch[0].ao.shu[0].selph_ca2, + (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 16) | (0x7 << 24), + (0x0 << 0) | (0x0 << 4) | (0x0 << 8) | (0x7 << 16) | (0x0 << 24)); + clrbits_le32(&ch[0].ao.shu[0].selph_ca3, + (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) | + (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28)); + clrbits_le32(&ch[0].ao.shu[0].selph_ca4, + (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) | + (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28)); + clrbits_le32(&ch[0].ao.shu[0].selph_ca5, 0x7 << 8); + clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0); + clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1); + + for (size_t rank = 0; rank < 2; rank++) { + clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[0], + 0x77777777, + (0x3 << 0) | (0x3 << 4) | (0x3 << 8) | (0x3 << 12) | + (0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28)); + clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[1], + 0x77777777, + (0x3 << 0) | (0x3 << 4) | (0x3 << 8) | (0x3 << 12) | + (0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28)); + clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], + 0x77777777, + (0x6 << 0) | (0x6 << 4) | (0x6 << 8) | (0x6 << 12) | + (0x2 << 16) | (0x2 << 20) | (0x2 << 24) | (0x2 << 28)); + clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], + 0x77777777, + (0x6 << 0) | (0x6 << 4) | (0x6 << 8) | (0x6 << 12) | + (0x2 << 16) | (0x2 << 20) | (0x2 << 24) | (0x2 << 28)); + } + + for (int b = 0; b < 2; b++) { + clrsetbits_le32(&ch[0].phy.shu[0].rk[0].b[b].dq[7], + (0x3f << 8) | (0x3f << 16), (0x1a << 8) | (0x1a << 16)); + clrsetbits_le32(&ch[0].phy.shu[0].rk[1].b[b].dq[7], + (0x3f << 8) | (0x3f << 16), (0x14 << 8) | (0x14 << 16)); + } + udelay(1); + + for (size_t b = 0; b < 2; b++) { + setbits_le32(&ch[0].phy.b[b].dq[9], 0x1 << 5); + clrsetbits_le32(&ch[0].phy.b[b].dq[6], 0x3 << 14, 0x1 << 14); + } + setbits_le32(&ch[0].ao.stbcal, 0x1 << 31); + clrsetbits_le32(&ch[0].ao.srefctrl, (0xf << 24) | (0x1 << 30), 0x8 << 24); + clrsetbits_le32(&ch[0].ao.shu[0].ckectrl, + (0x3 << 24) | (0x3 << 28), (0x3 << 24) | (0x3 << 28)); + setbits_le32(&ch[0].ao.shu[0].pipe, (0x1 << 30) | (0x1 << 31)); + setbits_le32(&ch[0].ao.ckectrl, (0x1 << 13) | (0x1 << 31)); + setbits_le32(&ch[0].ao.rkcfg, 0x1 << 2); + clrsetbits_le32(&ch[0].ao.shu[0].conf[2], + (0x7 << 16) | (0x1 << 28), (0x7 << 16) | (0x1 << 28)); + clrsetbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 26, 0x1 << 26); + clrsetbits_le32(&ch[0].ao.shuctrl1, 0xff << 0, 0x40 << 0); + + setbits_le32(&ch[0].ao.shuctrl, 0x1 << 16); + clrbits_le32(&ch[0].ao.refctrl1, (0x1 << 1) | (0x1 << 2) | (0x1 << 3) | (0x1 << 6)); + clrsetbits_le32(&ch[0].ao.refratre_filter, (0x1 << 15) | (0x1 << 23), + (0x1 << 15) | (0x0 << 23)); + clrbits_le32(&ch[0].ao.dramctrl, 0x1 << 9); + setbits_le32(&ch[0].ao.misctl0, (0x1 << 19) | (0x1 << 24) | (0x1 << 31)); + setbits_le32(&ch[0].ao.perfctl0, + (0x1 << 0) | (0x1 << 1) | (0x1 << 4) | (0x1 << 8) | + (0x1 << 9) | (0x1 << 10) | (0x1 << 11) | (0x1 << 14) | (0x1 << 17)); + clrsetbits_le32(&ch[0].ao.arbctl, 0xff << 0, 0x80 << 0); + clrsetbits_le32(&ch[0].ao.padctrl, (0x3 << 0) | (0x1 << 3), (0x1 << 0) | (0x1 << 3)); + setbits_le32(&ch[0].ao.dramc_pd_ctrl, 0x1 << 8); + setbits_le32(&ch[0].ao.clkctrl, 0x1 << 29); + clrsetbits_le32(&ch[0].ao.refctrl0, (0x1 << 0) | (0x7 << 12), (0x1 << 0) | (0x4 << 12)); + clrsetbits_le32(&ch[0].ao.shu[0].rankctl, (0xf << 20) | (0xf << 24) | (0xf << 28), + (0x4 << 20) | (0x4 << 24) | (0x6 << 28)); + udelay(2); + + clrsetbits_le32(&ch[0].ao.shu[0].rk[0].dqsien, + (0x7f << 0) | (0x7f << 8), (0x19 << 0) | (0x19 << 8)); + clrsetbits_le32(&ch[0].ao.shu[0].rk[1].dqsien, + (0x7f << 0) | (0x7f << 8) | (0x7f << 16) | (0x7f << 24), + (0x1b << 0) | (0x1b << 8) | (0x0 << 16) | (0x0 << 24)); + + setbits_le32(&ch[0].ao.dramctrl, 0x1 << 19); + clrsetbits_le32(&ch[0].ao.zqcs, 0xff << 0, 0x56 << 0); + udelay(1); + + clrsetbits_le32(&ch[0].ao.shu[0].conf[3], 0x1ff << 16, 0xff << 16); + setbits_le32(&ch[0].ao.refctrl0, 0x1 << 30); + setbits_le32(&ch[0].ao.srefctrl, 0x1 << 30); + setbits_le32(&ch[0].ao.mpc_option, 0x1 << 17); + setbits_le32(&ch[0].ao.dramc_pd_ctrl, 0x1 << 30); + setbits_le32(&ch[0].ao.dramc_pd_ctrl, 0x1 << 0); + clrsetbits_le32(&ch[0].ao.eyescan, (0x1 << 1) | (0xf << 16), (0x0 << 1) | (0x1 << 16)); + setbits_le32(&ch[0].ao.stbcal1, (0x1 << 10) | (0x1 << 11)); + clrsetbits_le32(&ch[0].ao.test2_3, + (0x1 << 7) | (0x7 << 8) | (0x1 << 28), + (0x1 << 7) | (0x4 << 8) | (0x1 << 28)); + clrbits_le32(&ch[0].ao.rstmask, 0x1 << 29); + clrbits_le32(&ch[0].ao.rstmask, 0x1 << 30); + + udelay(1); + clrsetbits_le32(&ch[0].ao.hw_mrr_fun, (0xf << 0) | (0xf << 4), (0x8 << 0) | (0x6 << 4)); + + clrsetbits_le32(&ch[0].ao.perfctl0, + (0x1 << 18) | (0x1 << 19), (0x0 << 18) | (0x1 << 19)); + clrbits_le32(&ch[0].ao.rstmask, 0x1 << 28); + setbits_le32(&ch[0].ao.rkcfg, 0x1 << 11); + setbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 28); + setbits_le32(&ch[0].ao.eyescan, 0x1 << 2); + + clrbits_le32(&ch[0].ao.dramctrl, 0x1 << 0); + setbits_le32(&ch[0].ao.mpc_option, 0x1 << 17); + setbits_le32(&ch[0].ao.shu[0].wodt, 0x1 << 29); + setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 7); + setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 7); + clrsetbits_le32(&ch[0].ao.shu[0].rankctl, 0xf << 20, 0x4 << 20); + + for (size_t r = 0; r < 2; r++) { + clrsetbits_le32(&ch[0].ao.shu[0].rk[r].selph_dq[0], + (0x7 << 0) | (0x7 << 4), (0x2 << 0) | (0x2 << 4)); + clrsetbits_le32(&ch[0].ao.shu[0].rk[r].selph_dq[1], + (0x7 << 0) | (0x7 << 4), (0x2 << 0) | (0x2 << 4)); + } + udelay(5); + + clrsetbits_le32(&ch[0].ao.stbcal1, 0xffff << 16, 0x3 << 16); + clrsetbits_le32(&ch[0].ao.stbcal1, 0xffff << 16, 0x1 << 16); + clrsetbits_le32(&ch[0].ao.stbcal, + (0x1 << 0) | (0x1 << 22) | (0x1 << 24) | (0x1 << 26) | (0x1 << 27), + (0x1 << 0) | (0x0 << 22) | (0x0 << 24) | (0x1 << 26) | (0x1 << 27)); + setbits_le32(&ch[0].ao.stbcal1, 0x1 << 6); + clrsetbits_le32(&ch[0].ao.shu[0].dqsg, + (0x1 << 11) | (0xf << 12), (0x1 << 11) | (0x9 << 12)); + clrbits_le32(&ch[0].phy.misc_ctrl0, 0xf << 0); + setbits_le32(&ch[0].ao.shu[0].stbcal, 0x1 << 8); + setbits_le32(&ch[0].ao.stbcal, 0x1 << 17); + clrbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 14); + clrbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 14); + clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x7 << 4, 0x1 << 4); + + if (freq_group == LP4X_DDR1600) + clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, (0x0 << 0)); + else + clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, 0x2 << 0); + setbits_le32(&ch[0].ao.refctrl1, (0x1 << 0) | (0x1 << 5)); + setbits_le32(&ch[0].ao.dqsoscr, (0x1 << 23) | (0x1 << 27)); + clrbits_le32(&ch[0].ao.rstmask, (0x1 << 24) | (0x1 << 25) | (0x1 << 26)); + clrsetbits_le32(&ch[0].ao.rkcfg, 0x7 << 4, 0x1 << 4); + udelay(12); + + clrsetbits_le32(&ch[0].ao.shu[0].rankctl, + (0xf << 24) | (0xf << 28), (0x4 << 24) | 0x6 << 28); + clrbits_le32(&ch[0].ao.shu[0].wodt, 0x1 << 31); + clrsetbits_le32(&ch[0].ao.shu[0].rk[0].fine_tune, + (0x3f << 0) | (0x3f << 8) | (0x3f << 16) | (0x3f << 24), + (0x1a << 0) | (0x1a << 8) | (0x1a << 16) | (0x1a << 24)); + clrsetbits_le32(&ch[0].ao.shu[0].rk[1].fine_tune, + (0x3f << 0) | (0x3f << 8) | (0x3f << 16) | (0x3f << 24), + (0x14 << 0) | (0x14 << 8) | (0x14 << 16) | (0x14 << 24)); + for (u8 rank = 0; rank < 2; rank++) { + clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], + (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28), + (0x4 << 16) | (0x4 << 20) | (0x4 << 24) | (0x4 << 28)); + clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], + (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28), + (0x4 << 16) | (0x4 << 20) | (0x4 << 24) | (0x4 << 28)); + } + clrsetbits_le32(&ch[0].ao.shu[0].dqsg_retry, + (0x1 << 2) | (0xf << 8) | (0x1 << 14) | (0x3 << 24), + (0x1 << 2) | (0x5 << 8) | (0x0 << 14) | (0x1 << 24)); + setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], (0x1 << 12) | (0x1 << 13)); + setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 12) | (0x1 << 13)); + clrbits_le32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0); + + switch (freq_group) { + case LP4X_DDR1600: + dramc_setting_DDR1600(); + break; + case LP4X_DDR2400: + dramc_setting_DDR2400(); + break; + case LP4X_DDR3200: + /* Do nothing */ + break; + case LP4X_DDR3600: + dramc_setting_DDR3600(); + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + break; + } + + update_initial_settings(freq_group); + dramc_sw_impedance_save_reg(freq_group); + + clrbits_le32(&ch[0].ao.test2_4, 0x1 << 17); + clrsetbits_le32(&ch[0].ao.shu[0].conf[3], 0x1ff << 0, 0x5 << 0); + udelay(1); + + setbits_le32(&ch[0].ao.refctrl0, (0x1 << 17) | (0x1 << 18)); + setbits_le32(&ch[0].ao.shuctrl2, (0x1 << 24) | (0x1 << 25)); + setbits_le32(&ch[0].ao.refctrl0, 0x1 << 29); + setbits_le32(&ch[0].ao.dramctrl, 0x1 << 26); + clrsetbits_le32(&ch[0].ao.dummy_rd, + (0x1 << 4) | (0x1 << 11) | (0x1 << 13) | + (0x1 << 14) | (0x3 << 16) | (0x1 << 22), + (0x1 << 4) | (0x1 << 11) | (0x1 << 13) | + (0x1 << 14) | (0x2 << 16) | (0x1 << 22)); + clrsetbits_le32(&ch[0].ao.test2_4, 0x7 << 28, 0x4 << 28); + clrbits_le32(&ch[0].ao.dramctrl, 0x1 << 0); + udelay(1); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + clrsetbits_le32(&ch[0].ao.shuctrl, (0x1 << 5) | (0x1 << 17), (0x0 << 5) | (0x1 << 17)); + setbits_le32(&ch[0].ao.shuctrl2, 0x1 << 12); + clrsetbits_le32(&ch[1].ao.shuctrl, (0x1 << 5) | (0x1 << 17), (0x1 << 5) | (0x0 << 17)); + clrbits_le32(&ch[1].ao.shuctrl2, 0x1 << 12); +} + +struct ac_time { + u8 dqsinctl; + u8 datlat; + u8 trcd; + u8 trrd; + u8 twr; + u8 twtr; + u8 trc; + u8 tras; + u8 trp; + u8 trpab; + u8 tfaw; + u8 trtw_odt_on; + u8 trtp; + u8 txp; + u8 refcnt; + u8 trfc; + u8 trfcpb; + u8 tzqcs; + u8 refcnt_fr_clk; + u8 txrefcnt; + u8 tmrr2w_odt_on; + u8 twtpd; + u8 trtpd; + u8 xrtw2w; + u8 xrtw2r; + u8 xrtr2w; + u8 xrtr2r; + u8 twtr_05T; + u8 trtw_odt_on_05T; + u8 twtpd_05T; + u8 trtpd_05T; + u8 tfaw_05T; + u8 trrd_05T; + u8 twr_05T; + u8 tras_05T; + u8 trpab_05T; + u8 trp_05T; + u8 trcd_05T; + u8 trtp_05T; + u8 txp_05T; + u8 trfc_05T; + u8 trfcpb_05T; + u8 trc_05T; + u8 r_dmcatrain_intv; + u8 r_dmmrw_intv; + u8 r_dmfspchg_prdcnt; + u8 ckeprd; + u8 ckelckcnt; + u8 zqlat2; +}; + +static const struct ac_time ac_timing_tbl[LP4X_DDRFREQ_MAX] = { + /* LP4x-1600, 800MHz, RDBI_OFF, normal mode */ + [LP4X_DDR1600] = { + .tras = 0, .tras_05T = 0, + .trp = 2, .trp_05T = 0, + .trpab = 0, .trpab_05T = 1, + .trc = 4, .trc_05T = 0, + .trfc = 44, .trfc_05T = 0, + .trfcpb = 16, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 1, .trtp_05T = 1, + .trcd = 3, .trcd_05T = 0, + .twr = 7, .twr_05T = 1, + .twtr = 4, .twtr_05T = 1, + .trrd = 0, .trrd_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .trtw_odt_on = 4, .trtw_odt_on_05T = 0, + .refcnt = 48, + .refcnt_fr_clk = 101, + .txrefcnt = 62, + .tzqcs = 16, + .xrtw2w = 5, + .xrtw2r = 3, + .xrtr2w = 3, + .xrtr2r = 8, + .r_dmcatrain_intv = 8, + .r_dmmrw_intv = 0xf, + .r_dmfspchg_prdcnt = 50, + .trtpd = 6, .trtpd_05T = 0, + .twtpd = 6, .twtpd_05T = 0, + .tmrr2w_odt_on = 5, + .ckeprd = 1, + .ckelckcnt = 0, + .zqlat2 = 6, + .dqsinctl = 1, .datlat = 10, + }, + /* LP4x-2400, 1200MHz, RDBI_OFF, normal mode */ + [LP4X_DDR2400] = { + .tras = 4, .tras_05T = 1, + .trp = 3, .trp_05T = 1, + .trpab = 1, .trpab_05T = 0, + .trc = 10, .trc_05T = 0, + .trfc = 72, .trfc_05T = 0, + .trfcpb = 30, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 1, + .trtp = 1, .trtp_05T = 0, + .trcd = 4, .trcd_05T = 1, + .twr = 10, .twr_05T = 1, + .twtr = 6, .twtr_05T = 1, + .trrd = 1, .trrd_05T = 0, + .tfaw = 3, .tfaw_05T = 0, + .trtw_odt_on = 7, .trtw_odt_on_05T = 0, + .refcnt = 73, + .refcnt_fr_clk = 101, + .txrefcnt = 91, + .tzqcs = 25, + .xrtw2w = 5, + .xrtw2r = 3, + .xrtr2w = 6, + .xrtr2r = 8, + .r_dmcatrain_intv = 9, + .r_dmmrw_intv = 0xf, + .r_dmfspchg_prdcnt = 75, + .trtpd = 9, .trtpd_05T = 0, + .twtpd = 9, .twtpd_05T = 0, + .tmrr2w_odt_on = 8, + .ckeprd = 2, + .ckelckcnt = 0, + .zqlat2 = 9, + .dqsinctl = 3, .datlat = 13, + }, + /* LP4x-3200, 1600MHz, RDBI_OFF, normal mode */ + [LP4X_DDR3200] = { + .tras = 8, .tras_05T = 1, + .trp = 5, .trp_05T = 1, + .trpab = 1, .trpab_05T = 0, + .trc = 16, .trc_05T = 1, + .trfc = 100, .trfc_05T = 0, + .trfcpb = 44, .trfcpb_05T = 0, + .txp = 1, .txp_05T = 0, + .trtp = 2, .trtp_05T = 1, + .trcd = 6, .trcd_05T = 1, + .twr = 12, .twr_05T = 1, + .twtr = 7, .twtr_05T = 0, + .trrd = 2, .trrd_05T = 0, + .tfaw = 7, .tfaw_05T = 0, + .trtw_odt_on = 7, .trtw_odt_on_05T = 0, + .refcnt = 97, + .refcnt_fr_clk = 101, + .txrefcnt = 119, + .tzqcs = 34, + .xrtw2w = 5, + .xrtw2r = 3, + .xrtr2w = 6, + .xrtr2r = 9, + .r_dmcatrain_intv = 11, + .r_dmmrw_intv = 0xf, + .r_dmfspchg_prdcnt = 100, + .trtpd = 11, .trtpd_05T = 0, + .twtpd = 12, .twtpd_05T = 1, + .tmrr2w_odt_on = 10, + .ckeprd = 2, + .ckelckcnt = 0, + .zqlat2 = 12, + .dqsinctl = 4, .datlat = 15, + }, + /* LP4x-3600, 1800MHz, RDBI_OFF, normal mode */ + [LP4X_DDR3600] = { + .tras = 11, .tras_05T = 1, + .trp = 6, .trp_05T = 1, + .trpab = 1, .trpab_05T = 1, + .trc = 20, .trc_05T = 1, + .trfc = 118, .trfc_05T = 1, + .trfcpb = 53, .trfcpb_05T = 1, + .txp = 1, .txp_05T = 1, + .trtp = 2, .trtp_05T = 0, + .trcd = 7, .trcd_05T = 1, + .twr = 14, .twr_05T = 1, + .twtr = 8, .twtr_05T = 0, + .trrd = 3, .trrd_05T = 0, + .tfaw = 10, .tfaw_05T = 0, + .trtw_odt_on = 8, .trtw_odt_on_05T = 0, + .refcnt = 113, + .refcnt_fr_clk = 101, + .txrefcnt = 138, + .tzqcs = 40, + .xrtw2w = 5, + .xrtw2r = 3, + .xrtr2w = 7, + .xrtr2r = 9, + .r_dmcatrain_intv = 13, + .r_dmmrw_intv = 0xf, + .r_dmfspchg_prdcnt = 117, + .trtpd = 12, .trtpd_05T = 0, + .twtpd = 13, .twtpd_05T = 0, + .tmrr2w_odt_on = 11, + .ckeprd = 3, + .ckelckcnt = 0, + .zqlat2 = 14, + .dqsinctl = 6, .datlat = 18, + }, +}; + +static void ddr_update_ac_timing(u8 freq_group) +{ + struct ac_time ac_t; + u32 temp, r2w_odt_onoff = ODT_ON; + u8 new_datlat; + u8 root = 0, tx_rank_inctl = 0, tx_dly = 0; + u8 trtw = 0, trtw_05t = 0, tmrr2w = 0; + + memcpy(&ac_t, &ac_timing_tbl[freq_group], sizeof(struct ac_time)); + new_datlat = ac_timing_tbl[freq_group].datlat - 2; + + if (freq_group == LP4X_DDR1600) { + root = 0; tx_rank_inctl = 0; tx_dly = 1; + } else { + root = (freq_group == LP4X_DDR3600) ? 1 : 0; + tx_rank_inctl = 1; tx_dly = 2; + } + + if (r2w_odt_onoff == ODT_ON) { + trtw = ac_t.trtw_odt_on; + trtw_05t = ac_t.trtw_odt_on_05T; + tmrr2w = ac_t.tmrr2w_odt_on; + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + clrsetbits_le32(&ch[chn].ao.shu[0].actim[0], + (0xf << 24) | (0x7 << 16) | (0x1f << 8) | (0xf << 0), + (ac_t.trcd << 24) | (ac_t.trrd << 16) | + (ac_t.twr << 8) | (ac_t.twtr << 0)); + clrsetbits_le32(&ch[chn].ao.shu[0].actim[1], + (0x1f << 24) | (0xf << 16) | (0xf << 8) | (0x7 << 0), + (ac_t.trc << 24) | (ac_t.tras << 16) | + (ac_t.trp << 8) | (ac_t.trpab << 0)); + clrsetbits_le32(&ch[chn].ao.shu[0].actim[2], + (0x1f << 24) | (0xf << 16) | (0x7 << 8) | (0x7 << 0), + (ac_t.tfaw << 24) | (trtw << 16) | + (ac_t.trtp << 8) | (ac_t.txp << 0)); + clrsetbits_le32(&ch[chn].ao.shu[0].actim[3], + (0xff << 16) | (0xff << 24) | (0xff << 0), + (ac_t.trfc << 16) | (ac_t.refcnt << 24) | (ac_t.trfcpb << 0)); + clrsetbits_le32(&ch[chn].ao.shu[0].actim[4], + (0xff << 24) | (0xff << 16) | (0x3ff << 0), + (ac_t.tzqcs << 24) | (ac_t.refcnt_fr_clk << 16) | + (ac_t.txrefcnt << 0)); + clrsetbits_le32(&ch[chn].ao.shu[0].actim[5], + (0xf << 24) | (0x1f << 8) | (0x1f << 0), + (tmrr2w << 24) | (ac_t.twtpd << 8) | (ac_t.trtpd << 0)); + clrsetbits_le32(&ch[chn].ao.shu[0].actim_xrt, + (0xf << 24) | (0x7 << 16) | (0xf << 8) | (0x1f << 0), + (ac_t.xrtw2w << 24) | (ac_t.xrtw2r << 16) | + (ac_t.xrtr2w << 8) | (ac_t.xrtr2r << 0)); + clrsetbits_le32(&ch[chn].ao.shu[0].ac_time_05t, + (0x1 << 25) | (0x0 << 24) | (0x1 << 16) | (0x0 << 15) | + (0x1 << 13) | (0x1 << 12) | (0x1 << 10) | (0x1 << 9) | + (0x1 << 8) | (0x1 << 7) | (0x1 << 6) | (0x1 << 5) | + (0x1 << 4) | (0x1 << 2) | (0x1 << 1) | (0x1 << 0), + (ac_t.twtr_05T << 25) | (trtw_05t << 24) | + (ac_t.twtpd_05T << 16) | (ac_t.trtpd_05T << 15) | + (ac_t.tfaw_05T << 13) | (ac_t.trrd_05T << 12) | + (ac_t.twr_05T << 10) | (ac_t.tras_05T << 9) | + (ac_t.trpab_05T << 8) | (ac_t.trp_05T << 7) | + (ac_t.trcd_05T << 6) | (ac_t.trtp_05T << 5) | + (ac_t.txp_05T << 4) | (ac_t.trfc_05T << 2) | + (ac_t.trfcpb_05T << 1) | (ac_t.trc_05T << 0)); + clrsetbits_le32(&ch[chn].ao.catraining1, (0xff << 24) | (0xf << 20), + (ac_t.r_dmcatrain_intv << 24) | (0x0 << 20)); + + /* DQSINCTL related */ + clrsetbits_le32(&ch[chn].ao.shu[0].rk[0].dqsctl, 0xf << 0, + ac_t.dqsinctl << 0); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[1].dqsctl, 0xf << 0, + ac_t.dqsinctl << 0); + clrsetbits_le32(&ch[chn].ao.shu[0].odtctrl, 0xf << 4, + ac_t.dqsinctl << 4); + + /* DATLAT related, tREFBW */ + clrsetbits_le32(&ch[chn].ao.shu[0].conf[1], + (0x1f << 0) | (0x1f << 8) | (0x1f << 26) | (0x3ff << 16), + (ac_t.datlat << 0) | (new_datlat << 8) | + (new_datlat << 26) | (0x0 << 16)); + clrsetbits_le32(&ch[chn].ao.shu[0].conf[2], + (0xff << 8), ac_t.r_dmfspchg_prdcnt << 8); + clrsetbits_le32(&ch[chn].ao.shu[0].scintv, (0x1f << 13) | (0x1f << 6), + (ac_t.r_dmmrw_intv << 13) | (ac_t.zqlat2 << 6)); + + /* CKEPRD - CKE pulse width */ + clrsetbits_le32(&ch[chn].ao.shu[0].ckectrl, 0x7 << 20, ac_t.ckeprd << 20); + + /* CKELCKCNT: Valid clock requirement after CKE input low */ + clrsetbits_le32(&ch[chn].ao.ckectrl, 0x7 << 24, ac_t.ckelckcnt << 24); + + temp = ((read32(&ch[chn].ao.shu[0].rankctl) & 0x00f00000) >> 20) & 0xf; + clrsetbits_le32(&ch[chn].ao.shu[0].rankctl, 0xf << 0, temp << 0); + + clrsetbits_le32(&ch[chn].ao.shu[0].rankctl, + (0xf << 16) | (0xf << 12) | (0xf << 8), + (root << 16) | (tx_rank_inctl << 12) | (tx_dly << 8)); + } + + u8 dram_cbt_mode = 0; + clrsetbits_le32(&ch[0].ao.arbctl, 0x7 << 10, 0x3 << 10); + clrsetbits_le32(&ch[0].ao.rstmask, 0x3 << 13, dram_cbt_mode); + clrsetbits_le32(&ch[0].ao.arbctl, 0x1 << 13, dram_cbt_mode); +} + +void dramc_init(const struct sdram_params *params, u8 freq_group) +{ + dramc_setting(params, freq_group); + + dramc_duty_calibration(params, freq_group); + + dramc_mode_reg_init(freq_group); + ddr_update_ac_timing(freq_group); +} diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index cdba2af2df..a194d7a3dd 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -20,11 +20,21 @@ #include #include +static u32 impedance[2][4]; + +u8 get_freq_fsq(u8 freq) +{ + if (freq == LP4X_DDR1600 || freq == LP4X_DDR2400) + return FSP_0; + else + return FSP_1; +} + static void dramc_sw_imp_cal_vref_sel(u8 term_option, u8 impcal_stage) { u8 vref_sel = 0; - if (term_option == 1) + if (term_option == ODT_ON) vref_sel = IMP_LP4X_TERM_VREF_SEL; else { switch (impcal_stage) { @@ -43,14 +53,114 @@ static void dramc_sw_imp_cal_vref_sel(u8 term_option, u8 impcal_stage) clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0x3f << 8, vref_sel << 8); } -void dramc_sw_impedance(const struct sdram_params *params) +void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term) { - u8 term = 0, ca_term = ODT_OFF, dq_term = ODT_ON; + u32 broadcast_bak, impcal_bak, imp_cal_result; + u32 DRVP_result = 0xff, ODTN_result = 0xff, DRVN_result = 0x9; + + broadcast_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + + clrbits_le32(&ch[0].phy.misc_spm_ctrl1, 0xf << 0); + write32(&ch[0].phy.misc_spm_ctrl2, 0x0); + write32(&ch[0].phy.misc_spm_ctrl0, 0x0); + clrbits_le32(&ch[0].ao.impcal, 0x1 << 31); + + impcal_bak = read32(&ch[0].ao.impcal); + dramc_sw_imp_cal_vref_sel(term, IMPCAL_STAGE_DRVP); + clrbits_le32(&ch[0].phy.misc_imp_ctrl1, 0x1 << 6); + clrsetbits_le32(&ch[0].ao.impcal, 0x1 << 21, 0x3 << 24); + clrsetbits_le32(&ch[0].phy.misc_imp_ctrl0, 0x7 << 4, 0x3 << 4); + udelay(1); + + dramc_show("K DRVP\n"); + setbits_le32(&ch[0].ao.impcal, 0x1 << 23); + setbits_le32(&ch[0].ao.impcal, 0x1 << 22); + clrbits_le32(&ch[0].ao.impcal, 0x1 << 21); + clrbits_le32(&ch[0].ao.shu[0].impcal1, 0x1f << 4 | 0x1f << 11); + clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0xff << 0, 0x3); + + for (u8 impx_drv = 0; impx_drv < 32; impx_drv++) { + impx_drv = (impx_drv == 16) ? 29 : impx_drv; + + clrsetbits_le32(&ch[0].ao.shu[0].impcal1, + 0x1f << 4, impx_drv << 4); + udelay(1); + imp_cal_result = (read32(&ch[0].phy_nao.misc_phy_rgs_cmd) >> + 24) & 0x1; + dramc_show("1. OCD DRVP=%d CALOUT=%d\n", + impx_drv, imp_cal_result); + + if (imp_cal_result == 1 && DRVP_result == 0xff) { + DRVP_result = impx_drv; + dramc_show("1. OCD DRVP calibration OK! DRVP=%d\n", + DRVP_result); + break; + } + } + + dramc_show("K ODTN\n"); + dramc_sw_imp_cal_vref_sel(term, IMPCAL_STAGE_DRVN); + clrbits_le32(&ch[0].ao.impcal, 0x1 << 22); + if (term == ODT_ON) + setbits_le32(&ch[0].ao.impcal, 0x1 << 21); + clrsetbits_le32(&ch[0].ao.shu[0].impcal1, 0x1f << 4 | 0x1f << 11, + DRVP_result << 4 | 0x1f << 11); + clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0xff << 0, 0x3); + + for (u8 impx_drv = 0; impx_drv < 32; impx_drv++) { + impx_drv = (impx_drv == 16) ? 29 : impx_drv; + + clrsetbits_le32(&ch[0].ao.shu[0].impcal1, + 0x1f << 11, impx_drv << 11); + udelay(1); + imp_cal_result = (read32(&ch[0].phy_nao.misc_phy_rgs_cmd) >> + 24) & 0x1; + dramc_show("3. OCD ODTN=%d CALOUT=%d\n", + impx_drv, imp_cal_result); + + if (imp_cal_result == 0 && ODTN_result == 0xff) { + ODTN_result = impx_drv; + dramc_show("3. OCD ODTN calibration OK! ODTN=%d\n", + ODTN_result); + break; + } + } + + write32(&ch[0].ao.impcal, impcal_bak); + + dramc_show("term:%d, DRVP=%d, DRVN=%d, ODTN=%d\n", + term, DRVP_result, DRVN_result, ODTN_result); + if (term == ODT_OFF) { + impedance[term][0] = DRVP_result; + impedance[term][1] = ODTN_result; + impedance[term][2] = 0; + impedance[term][3] = 15; + } else { + impedance[term][0] = (DRVP_result <= 3) ? + (DRVP_result * 3) : DRVP_result; + impedance[term][1] = (DRVN_result <= 3) ? + (DRVN_result * 3) : DRVN_result; + impedance[term][2] = 0; + impedance[term][3] = (ODTN_result <= 3) ? + (ODTN_result * 3) : ODTN_result; + } + dramc_sw_imp_cal_vref_sel(term, IMPCAL_STAGE_TRACKING); + + dramc_set_broadcast(broadcast_bak); +} + +void dramc_sw_impedance_save_reg(u8 freq_group) +{ + u8 ca_term = ODT_OFF, dq_term = ODT_ON; u32 sw_impedance[2][4] = {0}; - for (term = 0; term < 2; term++) + if (get_freq_fsq(freq_group) == FSP_0) + dq_term = ODT_OFF; + + for (u8 term = 0; term < 2; term++) for (u8 i = 0; i < 4; i++) - sw_impedance[term][i] = params->impedance[term][i]; + sw_impedance[term][i] = impedance[term][i]; sw_impedance[ODT_OFF][2] = sw_impedance[ODT_ON][2]; sw_impedance[ODT_OFF][3] = sw_impedance[ODT_ON][3]; @@ -63,7 +173,7 @@ void dramc_sw_impedance(const struct sdram_params *params) (sw_impedance[dq_term][0] << 5) | (sw_impedance[dq_term][1] << 0)); clrsetbits_le32(&ch[0].ao.shu[0].drving[1], - (0x1f << 25)|(0x1f << 20) | (1 << 31), + (0x1f << 25) | (0x1f << 20) | (1 << 31), (sw_impedance[dq_term][0] << 25) | (sw_impedance[dq_term][1] << 20) | (!dq_term << 31)); clrsetbits_le32(&ch[0].ao.shu[0].drving[2], (0x1f << 5) | (0x1f << 0), @@ -113,7 +223,7 @@ void dramc_sw_impedance(const struct sdram_params *params) static void transfer_pll_to_spm_control(void) { - u8 shu_lev = (read32(&ch[0].ao.shustatus) & 0x00000006) >> 1; + u8 shu_lev = (read32(&ch[0].ao.shustatus) >> 1) & 0x3; clrsetbits_le32(&mtk_spm->poweron_config_set, (0xffff << 16) | (0x1 << 0), @@ -154,6 +264,7 @@ static void dramc_rx_input_delay_tracking(u8 chn) for (size_t r = 0; r < 2; r++) for (size_t b = 0; b < 2; b++) { + clrbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[2], 1 << 29); clrsetbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[7], (0x3f << 0) | (0x3f << 8) | (0x7f << 16) | (0x7f << 24), @@ -176,7 +287,6 @@ static void dramc_rx_input_delay_tracking(u8 chn) clrsetbits_le32(&ch[chn].phy.b1_rxdvs[0], (0x1 << 29) | (0xf << 4) | (0x1 << 0), (0x1 << 29) | (0x0 << 4) | (0x1 << 0)); - clrbits_le32(&ch[chn].phy.ca_cmd[10], (0x7 << 28) | (0x7 << 24)); for (u8 b = 0; b < 2; b++) { clrsetbits_le32(&ch[chn].phy.b[b].dq[9], @@ -184,6 +294,7 @@ static void dramc_rx_input_delay_tracking(u8 chn) (0x1 << 28) | (0x0 << 24)); setbits_le32(&ch[chn].phy.b[b].dq[5], 0x1 << 31); } + clrbits_le32(&ch[chn].phy.ca_cmd[10], (0x7 << 28) | (0x7 << 24)); setbits_le32(&ch[chn].phy.b0_rxdvs[0], (0x1 << 28) | (0x1 << 31)); setbits_le32(&ch[chn].phy.b1_rxdvs[0], (0x1 << 28) | (0x1 << 31)); @@ -236,16 +347,12 @@ static void dramc_impedance_tracking_enable(void) setbits_le32(&ch[chn].ao.impcal, 0x1 << 19); } setbits_le32(&ch[0].ao.impcal, 0x1 << 14); - setbits_le32(&ch[1].ao.refctrl0, 0x1 << 2); for (size_t chn = 0; chn < CHANNEL_MAX; chn++) - setbits_le32(&ch[chn].ao.refctrl0, 0x1 << 3); + setbits_le32(&ch[chn].ao.refctrl0, (0x1 << 2) | (0x1 << 3)); } static void dramc_phy_low_power_enable(void) { - u32 broadcast_bak = dramc_get_broadcast(); - dramc_set_broadcast(DRAMC_BROADCAST_OFF); - for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { for (size_t b = 0; b < 2; b++) { clrbits_le32(&ch[chn].phy.b[b].dll_fine_tune[2], @@ -257,8 +364,6 @@ static void dramc_phy_low_power_enable(void) } write32(&ch[0].phy.ca_dll_fine_tune[3], 0xba000); write32(&ch[1].phy.ca_dll_fine_tune[3], 0x3a000); - - dramc_set_broadcast(broadcast_bak); } static void dramc_dummy_read_for_tracking_enable(u8 chn) @@ -274,8 +379,8 @@ static void dramc_dummy_read_for_tracking_enable(u8 chn) for (size_t r = 0; r < 2; r++) { clrsetbits_le32(&ch[chn].ao.rk[r].dummy_rd_adr, (0x1ffff << 0) | (0x7ff << 17) | (0xf << 28), - (0x7fff << 0) | (0x3f0 << 17)); - setbits_le32(&ch[chn].ao.rk[r].dummy_rd_bk, 0x7 << 0); + (0xffff << 0) | (0x3f0 << 17)); + clrbits_le32(&ch[chn].ao.rk[r].dummy_rd_bk, 0x7 << 0); } clrbits_le32(&ch[chn].ao.dummy_rd, 0x1 << 25 | 0x1 << 20); @@ -323,7 +428,7 @@ void dramc_runtime_config(void) clrbits_le32(&ch[1].ao.refctrl0, 0x1 << 29); transfer_pll_to_spm_control(); - setbits_le32(&mtk_spm->spm_power_on_val0, 0x3 << 25); + setbits_le32(&mtk_spm->spm_power_on_val0, 0x1 << 25); /* RX_TRACKING: ON */ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 05f793ec4b..fcc3b14a1e 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -23,24 +24,23 @@ enum { RX_VREF_BEGIN = 0, - RX_VREF_END = 12, + RX_VREF_END = 31, RX_VREF_STEP = 1, - TX_VREF_BEGIN = 8, - TX_VREF_END = 18, + TX_VREF_BEGIN = 0, + TX_VREF_END = 50, TX_VREF_STEP = 2, }; enum { FIRST_DQ_DELAY = 0, - FIRST_DQS_DELAY = -16, + FIRST_DQS_DELAY = -48, MAX_DQDLY_TAPS = 16, MAX_RX_DQDLY_TAPS = 63, }; -enum { - GATING_START = 26, - GATING_END = GATING_START + 24, -}; +#define WRITE_LEVELING_MOVD_DQS 1 +#define TEST2_1_CAL 0x55000000 +#define TEST2_2_CAL 0xaa000400 enum CAL_TYPE { RX_WIN_RD_DQC = 0, @@ -55,21 +55,19 @@ enum RX_TYPE { RX_DQS, }; -struct dqdqs_perbit_dly { - struct perbit_dly { - s16 first; - s16 last; - s16 best_first; - s16 best_last; - s16 best; - } dqdly, dqsdly; +struct win_perbit_dly { + s16 first_pass; + s16 last_pass; + s16 best_first; + s16 best_last; + s16 best_dqdly; + s16 win_center; }; struct vref_perbit_dly { - u8 vref; - u16 max_win; - u16 min_win; - struct dqdqs_perbit_dly perbit_dly[DQ_DATA_WIDTH]; + u8 best_vref; + u16 max_win_sum; + struct win_perbit_dly perbit_dly[DQ_DATA_WIDTH]; }; struct tx_dly_tune { @@ -86,6 +84,9 @@ struct per_byte_dly { u16 final_dly; }; +extern u8 MR01Value[FSP_MAX]; +extern u8 MR13Value; + static void dramc_auto_refresh_switch(u8 chn, bool option) { clrsetbits_le32(&ch[chn].ao.refctrl0, 1 << REFCTRL0_REFDIS_SHIFT, @@ -102,13 +103,13 @@ static void dramc_auto_refresh_switch(u8 chn, bool option) } } -static void dramc_cke_fix_onoff(u8 chn, bool fix_on, bool fix_off) +void dramc_cke_fix_onoff(u8 chn, bool cke_on, bool cke_off) { clrsetbits_le32(&ch[chn].ao.ckectrl, (0x1 << 6) | (0x1 << 7), - ((fix_on ? 1 : 0) << 6) | ((fix_off ? 1 : 0) << 7)); + ((cke_on ? 1 : 0) << 6) | ((cke_off ? 1 : 0) << 7)); } -static void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value) +void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value) { u32 ckectrl_bak = read32(&ch[chn].ao.ckectrl); @@ -124,13 +125,15 @@ static void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value) ; clrbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_MRWEN_SHIFT); - setbits_le32(&ch[chn].ao.ckectrl, ckectrl_bak); + write32(&ch[chn].ao.ckectrl, ckectrl_bak); + dramc_dbg("Write MR%d =0x%x\n", mr_idx, value); } static void dramc_mode_reg_write_by_rank(u8 chn, u8 rank, u8 mr_idx, u8 value) { u32 mrs_back = read32(&ch[chn].ao.mrs) & MRS_MRSRK_MASK; + dramc_dbg("Mode reg write rank%d MR%d = 0x%x\n", rank, mr_idx, value); clrsetbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK, rank << MRS_MRSRK_SHIFT); @@ -138,26 +141,113 @@ static void dramc_mode_reg_write_by_rank(u8 chn, u8 rank, clrsetbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK, mrs_back); } -static void dramc_write_leveling(u8 chn, u8 rank, +static void move_dramc_delay(u32 *reg_0, u32 *reg_1, u8 shift, s8 shift_coarse_tune) +{ + s32 sum; + u32 tmp_0p5t, tmp_2t; + + tmp_0p5t = ((read32(reg_0) >> shift) & DQ_DIV_MASK) & + ~(1 << DQ_DIV_SHIFT); + tmp_2t = (read32(reg_1) >> shift) & DQ_DIV_MASK; + + sum = (tmp_2t << DQ_DIV_SHIFT) + tmp_0p5t + shift_coarse_tune; + + if (sum < 0) { + tmp_0p5t = 0; + tmp_2t = 0; + } else { + tmp_2t = sum >> DQ_DIV_SHIFT; + tmp_0p5t = sum - (tmp_2t << DQ_DIV_SHIFT); + } + + clrsetbits_le32(reg_0, DQ_DIV_MASK << shift, tmp_0p5t << shift); + clrsetbits_le32(reg_1, DQ_DIV_MASK << shift, tmp_2t << shift); +} + +static void move_dramc_tx_dqs(u8 chn, u8 byte, s8 shift_coarse_tune) +{ + move_dramc_delay(&ch[chn].ao.shu[0].selph_dqs1, + &ch[chn].ao.shu[0].selph_dqs0, byte * 4, shift_coarse_tune); +} + +static void move_dramc_tx_dqs_oen(u8 chn, u8 byte, + s8 shift_coarse_tune) +{ + move_dramc_delay(&ch[chn].ao.shu[0].selph_dqs1, + &ch[chn].ao.shu[0].selph_dqs0, byte * 4 + OEN_SHIFT, shift_coarse_tune); +} + +static void move_dramc_tx_dq(u8 chn, u8 rank, u8 byte, s8 shift_coarse_tune) +{ + /* DQM0 */ + move_dramc_delay(&ch[chn].ao.shu[0].rk[rank].selph_dq[3], + &ch[chn].ao.shu[0].rk[rank].selph_dq[1], byte * 4, shift_coarse_tune); + + /* DQ0 */ + move_dramc_delay(&ch[chn].ao.shu[0].rk[rank].selph_dq[2], + &ch[chn].ao.shu[0].rk[rank].selph_dq[0], byte * 4, shift_coarse_tune); +} + +static void move_dramc_tx_dq_oen(u8 chn, u8 rank, + u8 byte, s8 shift_coarse_tune) +{ + /* DQM_OEN_0 */ + move_dramc_delay(&ch[chn].ao.shu[0].rk[rank].selph_dq[3], + &ch[chn].ao.shu[0].rk[rank].selph_dq[1], + byte * 4 + OEN_SHIFT, shift_coarse_tune); + + /* DQ_OEN_0 */ + move_dramc_delay(&ch[chn].ao.shu[0].rk[rank].selph_dq[2], + &ch[chn].ao.shu[0].rk[rank].selph_dq[0], + byte * 4 + OEN_SHIFT, shift_coarse_tune); +} + +static void write_leveling_move_dqs_instead_of_clk(u8 chn) +{ + dramc_dbg("%s do ch:%d k\n", __func__, chn); + for (u8 byte = 0; byte < DQS_NUMBER; byte++) { + move_dramc_tx_dqs(chn, byte, -WRITE_LEVELING_MOVD_DQS); + move_dramc_tx_dqs_oen(chn, byte, -WRITE_LEVELING_MOVD_DQS); + + for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { + move_dramc_tx_dq(chn, rk, byte, -WRITE_LEVELING_MOVD_DQS); + move_dramc_tx_dq_oen(chn, rk, byte, -WRITE_LEVELING_MOVD_DQS); + } + } +} + +static void dramc_write_leveling(u8 chn, u8 rank, u8 freq_group, const u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]) { + dramc_auto_refresh_switch(chn, false); + + if (rank == RANK_0 && (freq_group == LP4X_DDR3600 || + freq_group == LP4X_DDR1600 || + freq_group == LP4X_DDR2400)) + write_leveling_move_dqs_instead_of_clk(chn); + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CLK_MASK, 0); - for (size_t i = 0; i < DQS_NUMBER; i++) { - s32 wrlevel_dq_delay = wr_level[chn][rank][i] + 0x10; - assert(wrlevel_dq_delay < 0x40); + for (size_t byte = 0; byte < DQS_NUMBER; byte++) { + u32 wrlevel_dq_delay = wr_level[chn][rank][byte] + 0x10; + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[7], + FINE_TUNE_PBYTE_MASK, + wr_level[chn][rank][byte] << FINE_TUNE_PBYTE_SHIFT); + if (wrlevel_dq_delay >= 0x40) { + wrlevel_dq_delay -= 0x40; + move_dramc_tx_dq(chn, rank, byte, 2); + move_dramc_tx_dq_oen(chn, rank, byte, 2); + } - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[i].dq[7], - FINE_TUNE_PBYTE_MASK | FINE_TUNE_DQM_MASK | - FINE_TUNE_DQ_MASK, - (wr_level[chn][rank][i] << FINE_TUNE_PBYTE_SHIFT) | + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[7], + FINE_TUNE_DQM_MASK | FINE_TUNE_DQ_MASK, (wrlevel_dq_delay << FINE_TUNE_DQM_SHIFT) | (wrlevel_dq_delay << FINE_TUNE_DQ_SHIFT)); } } -static void dramc_cmd_bus_training(u8 chn, u8 rank, +static void dramc_cmd_bus_training(u8 chn, u8 rank, u8 freq_group, const struct sdram_params *params) { u32 cbt_cs, mr12_value; @@ -209,9 +299,6 @@ static void dramc_phy_dcm_2_channel(u8 chn, bool en) void dramc_enable_phy_dcm(bool en) { - u32 broadcast_bak = dramc_get_broadcast(); - dramc_set_broadcast(DRAMC_BROADCAST_OFF); - for (size_t chn = 0; chn < CHANNEL_MAX ; chn++) { clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[1], 0x1 << 20); clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[1], 0x1 << 20); @@ -254,7 +341,6 @@ void dramc_enable_phy_dcm(bool en) dramc_phy_dcm_2_channel(chn, en); } - dramc_set_broadcast(broadcast_bak); } static void dramc_reset_delay_chain_before_calibration(void) @@ -290,7 +376,7 @@ static void dramc_rx_input_delay_tracking_init_by_freq(u8 chn) clrbits_le32(&shu->b[1].dq[7], (0x1 << 12) | (0x1 << 13)); } -void dramc_apply_config_before_calibration(void) +void dramc_apply_config_before_calibration(u8 freq_group) { dramc_enable_phy_dcm(false); dramc_reset_delay_chain_before_calibration(); @@ -331,7 +417,10 @@ void dramc_apply_config_before_calibration(void) clrsetbits_le32(&ch[chn].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0); setbits_le32(&ch[chn].ao.dummy_rd, 0x1 << 25); setbits_le32(&ch[chn].ao.drsctrl, 0x1 << 0); - clrbits_le32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); + if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600) + clrbits_le32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); + else + setbits_le32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); dramc_rx_input_delay_tracking_init_by_freq(chn); } @@ -346,8 +435,9 @@ void dramc_apply_config_before_calibration(void) static void dramc_set_mr13_vrcg_to_Normal(u8 chn) { + MR13Value &= ~(0x1 << 3); for (u8 rank = 0; rank < RANK_MAX; rank++) - dramc_mode_reg_write_by_rank(chn, rank, 13, 0xd0); + dramc_mode_reg_write_by_rank(chn, rank, 13, MR13Value); for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) clrbits_le32(&ch[chn].ao.shu[shu].hwset_vrcg, 0x1 << 19); @@ -356,7 +446,7 @@ static void dramc_set_mr13_vrcg_to_Normal(u8 chn) void dramc_apply_config_after_calibration(void) { for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { - setbits_le32(&ch[chn].phy.misc_cg_ctrl4, 0x11400000); + write32(&ch[chn].phy.misc_cg_ctrl4, 0x11400000); clrbits_le32(&ch[chn].ao.refctrl1, 0x1 << 7); clrbits_le32(&ch[chn].ao.shuctrl, 0x1 << 2); clrbits_le32(&ch[chn].phy.ca_cmd[6], 0x1 << 6); @@ -370,7 +460,8 @@ void dramc_apply_config_after_calibration(void) setbits_le32(&ch[chn].phy.ca_cmd[6], 0x1 << 5); clrbits_le32(&ch[chn].ao.impcal, 0x3 << 24); - clrbits_le32(&ch[chn].phy.misc_imp_ctrl0, 0x7); + clrbits_le32(&ch[chn].phy.misc_imp_ctrl0, 0x4); + clrbits_le32(&ch[chn].phy.misc_cg_ctrl0, 0xf); clrbits_le32(&ch[chn].phy.misc_ctrl0, 0x1 << 31); clrbits_le32(&ch[chn].phy.misc_ctrl1, 0x1 << 25); @@ -405,12 +496,33 @@ static void dramc_set_rank_engine2(u8 chn, u8 rank) rank << TEST2_4_TESTAGENTRK_SHIFT); } -static void dramc_engine2_init(u8 chn, u8 rank, u32 size, bool test_pat) +static void dramc_engine2_setpat(u8 chn, bool test_pat) { - const u32 pat0 = 0x55; - const u32 pat1 = 0xaa; - const u32 addr = 0; + clrbits_le32(&ch[chn].ao.test2_4, + (0x1 << TEST2_4_TEST_REQ_LEN1_SHIFT) | + (0x1 << TEST2_4_TESTXTALKPAT_SHIFT) | + (0x1 << TEST2_4_TESTAUDMODE_SHIFT) | + (0x1 << TEST2_4_TESTAUDBITINV_SHIFT)); + if (!test_pat) { + setbits_le32(&ch[chn].ao.perfctl0, 1 << PERFCTL0_RWOFOEN_SHIFT); + + clrsetbits_le32(&ch[chn].ao.test2_4, + (0x1 << TEST2_4_TESTSSOPAT_SHIFT) | + (0x1 << TEST2_4_TESTSSOXTALKPAT_SHIFT), + (0x1 << TEST2_4_TESTXTALKPAT_SHIFT)); + } else { + clrsetbits_le32(&ch[chn].ao.test2_4, + TEST2_4_TESTAUDINIT_MASK | TEST2_4_TESTAUDINC_MASK, + (0x11 << 8) | (0xd << 0) | (0x1 << 14)); + } + clrsetbits_le32(&ch[chn].ao.test2_3, + (0x1 << TEST2_3_TESTAUDPAT_SHIFT) | TEST2_3_TESTCNT_MASK, + (test_pat ? 1 : 0) << TEST2_3_TESTAUDPAT_SHIFT); +} + +static void dramc_engine2_init(u8 chn, u8 rank, u32 t2_1, u32 t2_2, bool test_pat) +{ dramc_set_rank_engine2(chn, rank); clrbits_le32(&ch[chn].ao.dummy_rd, @@ -420,55 +532,50 @@ static void dramc_engine2_init(u8 chn, u8 rank, u32 size, bool test_pat) (0x1 << DUMMY_RD_SREF_DMYRD_EN_SHIFT) | (0x1 << DUMMY_RD_DMY_RD_DBG_SHIFT) | (0x1 << DUMMY_RD_DMY_WR_DBG_SHIFT)); - clrbits_le32(&ch[chn].nao.testchip_dma1, - 0x1 << TESTCHIP_DMA1_DMA_LP4MATAB_OPT_SHIFT); + clrbits_le32(&ch[chn].nao.testchip_dma1, 0x1 << 12); clrbits_le32(&ch[chn].ao.test2_3, (0x1 << TEST2_3_TEST2W_SHIFT) | (0x1 << TEST2_3_TEST2R_SHIFT) | (0x1 << TEST2_3_TEST1_SHIFT)); clrsetbits_le32(&ch[chn].ao.test2_0, TEST2_0_PAT0_MASK | TEST2_0_PAT1_MASK, - (pat0 << TEST2_0_PAT0_SHIFT) | - (pat1 << TEST2_0_PAT1_SHIFT)); - write32(&ch[chn].ao.test2_1, (addr << 4) & 0x00ffffff); - write32(&ch[chn].ao.test2_2, (size << 4) & 0x00ffffff); + ((t2_1 >> 24) << TEST2_0_PAT0_SHIFT) | + ((t2_2 >> 24) << TEST2_0_PAT1_SHIFT)); + clrsetbits_le32(&ch[chn].ao.test2_1, 0xfffffff0, (t2_1 & 0x00ffffff) << 4); + clrsetbits_le32(&ch[chn].ao.test2_2, 0xfffffff0, (t2_2 & 0x00ffffff) << 4); - clrsetbits_le32(&ch[chn].ao.test2_4, - (0x1 << TEST2_4_TESTAUDMODE_SHIFT) | - (0x1 << TEST2_4_TESTAUDBITINV_SHIFT) | - (0x1 << TEST2_4_TESTXTALKPAT_SHIFT), - ((!test_pat ? 1 : 0) << TEST2_4_TESTXTALKPAT_SHIFT) | - ((test_pat ? 1 : 0) << TEST2_4_TESTAUDMODE_SHIFT) | - ((test_pat ? 1 : 0) << TEST2_4_TESTAUDBITINV_SHIFT)); - - if (!test_pat) { - clrbits_le32(&ch[chn].ao.test2_4, - (0x1 << TEST2_4_TEST_REQ_LEN1_SHIFT) | - (0x1 << TEST2_4_TESTSSOPAT_SHIFT) | - (0x1 << TEST2_4_TESTSSOXTALKPAT_SHIFT)); - setbits_le32(&ch[chn].ao.perfctl0, - 0x1 << PERFCTL0_RWOFOEN_SHIFT); - } else { - clrsetbits_le32(&ch[chn].ao.test2_4, - TEST2_4_TESTAUDINIT_MASK | TEST2_4_TESTAUDINC_MASK, - (0x11 << TEST2_4_TESTAUDINIT_SHIFT) | - (0xd << TEST2_4_TESTAUDINC_SHIFT)); - } - clrsetbits_le32(&ch[chn].ao.test2_3, - TEST2_3_TESTCNT_MASK | (0x1 << TEST2_3_TESTAUDPAT_SHIFT), - (test_pat ? 1 : 0) << TEST2_3_TESTAUDPAT_SHIFT); + dramc_engine2_setpat(chn, test_pat); } -static void dramc_engine2_check_complete(u8 chn) +static void dramc_engine2_check_complete(u8 chn, u8 status) { + u32 loop = 0; /* In some case test engine finished but the complete signal late come, * system will wait very long time. Hence, we set a timeout here. * After system receive complete signal or wait until time out * it will return, the caller will check compare result to verify * whether engine success. */ - if (!wait_us(10000, read32(&ch[chn].nao.testrpt) & 0x1)) - dramc_dbg("MEASURE_A timeout\n"); + while (wait_us(100, read32(&ch[chn].nao.testrpt) & status) != status) { + if (loop++ > 100) + dramc_dbg("MEASURE_A timeout\n"); + } +} + +static void dramc_engine2_compare(u8 chn, enum dram_te_op wr) +{ + u8 rank_status = ((read32(&ch[chn].ao.test2_3) & 0xf) == 1) ? 3 : 1; + + if (wr == TE_OP_WRITE_READ_CHECK) { + dramc_engine2_check_complete(chn, rank_status); + + clrbits_le32(&ch[chn].ao.test2_3, (0x1 << TEST2_3_TEST2W_SHIFT) | + (0x1 << TEST2_3_TEST2R_SHIFT) | (0x1 << TEST2_3_TEST1_SHIFT)); + udelay(1); + setbits_le32(&ch[chn].ao.test2_3, 0x1 << TEST2_3_TEST2W_SHIFT); + } + + dramc_engine2_check_complete(chn, rank_status); } static u32 dramc_engine2_run(u8 chn, enum dram_te_op wr) @@ -478,26 +585,17 @@ static u32 dramc_engine2_run(u8 chn, enum dram_te_op wr) if (wr == TE_OP_READ_CHECK) { clrbits_le32(&ch[chn].ao.test2_4, 0x1 << TEST2_4_TESTAUDMODE_SHIFT); + + clrsetbits_le32(&ch[chn].ao.test2_3, + (0x1 << TEST2_3_TEST2W_SHIFT) | (0x1 << TEST2_3_TEST2R_SHIFT) | + (0x1 << TEST2_3_TEST1_SHIFT), 0x1 << TEST2_3_TEST2R_SHIFT); } else if (wr == TE_OP_WRITE_READ_CHECK) { clrsetbits_le32(&ch[chn].ao.test2_3, - (0x1 << TEST2_3_TEST2R_SHIFT) | - (0x1 << TEST2_3_TEST1_SHIFT), - 0x1 << TEST2_3_TEST2W_SHIFT); - - dramc_engine2_check_complete(chn); - clrbits_le32(&ch[chn].ao.test2_3, - (0x1 << TEST2_3_TEST2W_SHIFT) | - (0x1 << TEST2_3_TEST2R_SHIFT) | - (0x1 << TEST2_3_TEST1_SHIFT)); - udelay(1); + (0x1 << TEST2_3_TEST2W_SHIFT) | (0x1 << TEST2_3_TEST2R_SHIFT) | + (0x1 << TEST2_3_TEST1_SHIFT), 0x1 << TEST2_3_TEST2W_SHIFT); } - /* Do read test */ - clrsetbits_le32(&ch[chn].ao.test2_3, - (0x1 << TEST2_3_TEST2W_SHIFT) | (0x1 << TEST2_3_TEST1_SHIFT), - 0x1 << TEST2_3_TEST2R_SHIFT); - - dramc_engine2_check_complete(chn); + dramc_engine2_compare(chn, wr); udelay(1); result = read32(&ch[chn].nao.cmp_err); @@ -514,55 +612,84 @@ static void dramc_engine2_end(u8 chn) clrbits_le32(&ch[chn].ao.test2_4, 0x1 << 17); } -static void dramc_find_gating_window(u32 result_r, u32 result_f, u32 *debug_cnt, - u8 dly_coarse_large, u8 dly_coarse_0p5t, u8 *pass_begin, - u8 *pass_count, u8 *dly_fine_xt, u32 *coarse_tune, u8 *dqs_high) +static bool dramc_find_gating_window(u32 result_r, u32 result_f, u32 *debug_cnt, + u8 dly_coarse_large, u8 dly_coarse_0p5t, u8 *pass_begin, u8 *pass_count, + u8 *pass_count_1, u8 *dly_fine_xt, u8 *dqs_high, u8 *dqs_done) { - u16 debug_cnt_perbyte; - u8 pass_count_1[DQS_NUMBER]; + bool find_tune = false; + u16 debug_cnt_perbyte, current_pass = 0, pass_byte_cnt = 0; for (u8 dqs = 0; dqs < DQS_NUMBER; dqs++) { u8 dqs_result_r = (u8) ((result_r >> (8 * dqs)) & 0xff); u8 dqs_result_f = (u8) ((result_f >> (8 * dqs)) & 0xff); - debug_cnt_perbyte = (u16) debug_cnt[dqs]; - if (dqs_result_r != 0 || dqs_result_f != 0 || - debug_cnt_perbyte != GATING_GOLDEND_DQSCNT) + if (pass_byte_cnt & (1 << dqs)) continue; + current_pass = 0; - if (pass_begin[dqs] == 0) { - pass_begin[dqs] = 1; - pass_count_1[dqs] = 0; - dramc_dbg("[Byte %d]First pass (%d, %d, %d)\n", - dqs, dly_coarse_large, - dly_coarse_0p5t, *dly_fine_xt); - } + debug_cnt_perbyte = (u16) debug_cnt[dqs]; + if (dqs_result_r == 0 && dqs_result_f == 0 && + debug_cnt_perbyte == GATING_GOLDEND_DQSCNT) + current_pass = 1; - if (pass_begin[dqs] == 1) - pass_count_1[dqs]++; + if (current_pass) { + if (pass_begin[dqs] == 0) { + pass_begin[dqs] = 1; + pass_count_1[dqs] = 0; + dramc_dbg("[Byte %d]First pass (%d, %d, %d)\n", + dqs, dly_coarse_large, dly_coarse_0p5t, *dly_fine_xt); + } - if (pass_begin[dqs] == 1 && - pass_count_1[dqs] * DQS_GW_FINE_STEP > DQS_GW_FINE_END) - dqs_high[dqs] = 0; + if (pass_begin[dqs] == 1) + pass_count_1[dqs]++; - if (pass_count_1[0] * DQS_GW_FINE_STEP > DQS_GW_FINE_END && - pass_count_1[1] * DQS_GW_FINE_STEP > DQS_GW_FINE_END) { - dramc_dbg("All bytes gating window > 1 coarse_tune," - " Early break\n"); - *dly_fine_xt = DQS_GW_FINE_END; - *coarse_tune = GATING_END; + if (pass_begin[dqs] == 1 && + pass_count_1[dqs] * DQS_GW_FINE_STEP > DQS_GW_FINE_END) { + dqs_high[dqs] = 0; + dqs_done[dqs] = 1; + } + + if (pass_count_1[0] * DQS_GW_FINE_STEP > DQS_GW_FINE_END && + pass_count_1[1] * DQS_GW_FINE_STEP > DQS_GW_FINE_END) { + dramc_dbg("All bytes gating window > 1 coarse_tune, Early break\n"); + *dly_fine_xt = DQS_GW_FINE_END; + find_tune = true; + } + } else { + if (pass_begin[dqs] != 1) + continue; + + dramc_dbg("[Byte %d] pass_begin[dqs]:%d, pass_count[dqs]:%d,pass_count_1:%d\n", + dqs, pass_begin[dqs], pass_count[dqs], pass_count_1[dqs]); + + pass_begin[dqs] = 0; + if (pass_count_1[dqs] > pass_count[dqs]) { + pass_count[dqs] = pass_count_1[dqs]; + if (pass_count_1[dqs] * DQS_GW_FINE_STEP > 32 && + pass_count_1[dqs] * DQS_GW_FINE_STEP < 96) + pass_byte_cnt |= (1 << dqs); + if (pass_byte_cnt == 3) { + *dly_fine_xt = DQS_GW_FINE_END; + find_tune = true; + } + } } } + + return find_tune; } static void dramc_find_dly_tune(u8 chn, u8 dly_coarse_large, u8 dly_coarse_0p5t, u8 dly_fine_xt, u8 *dqs_high, u8 *dly_coarse_large_cnt, - u8 *dly_coarse_0p5t_cnt, u8 *dly_fine_tune_cnt, u8 *dqs_trans) + u8 *dly_coarse_0p5t_cnt, u8 *dly_fine_tune_cnt, u8 *dqs_trans, u8 *dqs_done) { for (size_t dqs = 0; dqs < DQS_NUMBER; dqs++) { u32 dqs_cnt = read32(&ch[chn].phy_nao.misc_phy_stben_b[dqs]); dqs_cnt = (dqs_cnt >> 16) & 3; + if (dqs_done[dqs] == 1) + continue; + if (dqs_cnt == 3) dqs_high[dqs]++; @@ -578,9 +705,16 @@ static void dramc_find_dly_tune(u8 chn, u8 dly_coarse_large, u8 dly_coarse_0p5t, break; case 2: case 1: + if (dqs_trans[dqs] == 1) + dramc_dbg("[Byte %ld] Lead/lag falling Transition" + " (%d, %d, %d)\n", + dqs, dly_coarse_large_cnt[dqs], + dly_coarse_0p5t_cnt[dqs], dly_fine_tune_cnt[dqs]); dqs_trans[dqs]++; break; case 0: + dramc_dbg("[Byte %ld] Lead/lag Transition tap number (%d)\n", + dqs, dqs_trans[dqs]); dqs_high[dqs] = 0; break; } @@ -610,20 +744,23 @@ static void dramc_set_gating_mode(u8 chn, bool mode) burst = 1; } - clrsetbits_le32(&ch[chn].ao.stbcal1, 0x1 << 5, burst << 5); - setbits_le32(&ch[chn].ao.stbcal, 0x1 << 30); - for (size_t b = 0; b < 2; b++) { clrsetbits_le32(&ch[chn].phy.b[b].dq[6], 0x3 << 14, vref << 14); setbits_le32(&ch[chn].phy.b[b].dq[9], 0x1 << 5); - clrbits_le32(&ch[chn].phy.b[b].dq[9], (0x1 << 4) | (0x1 << 0)); - setbits_le32(&ch[chn].phy.b[b].dq[9], (0x1 << 4) | (0x1 << 0)); } + + clrsetbits_le32(&ch[chn].ao.stbcal1, 0x1 << 5, burst << 5); + setbits_le32(&ch[chn].ao.stbcal, 0x1 << 30); + + clrbits_le32(&ch[chn].phy.b[0].dq[9], (0x1 << 4) | (0x1 << 0)); + clrbits_le32(&ch[chn].phy.b[1].dq[9], (0x1 << 4) | (0x1 << 0)); + udelay(1); + setbits_le32(&ch[chn].phy.b[1].dq[9], (0x1 << 4) | (0x1 << 0)); + setbits_le32(&ch[chn].phy.b[0].dq[9], (0x1 << 4) | (0x1 << 0)); } static void dramc_rx_dqs_gating_cal_pre(u8 chn, u8 rank) { - dramc_rx_dqs_isi_pulse_cg_switch(chn, false); clrbits_le32(&ch[chn].ao.refctrl0, 1 << REFCTRL0_PBREFEN_SHIFT); dramc_hw_gating_onoff(chn, false); @@ -645,8 +782,7 @@ static void dramc_rx_dqs_gating_cal_pre(u8 chn, u8 rank) static void dramc_write_dqs_gating_result(u8 chn, u8 rank, u8 *best_coarse_tune2t, u8 *best_coarse_tune0p5t, - u8 *best_coarse_tune2t_p1, u8 *best_coarse_tune0p5t_p1, - u8 *best_fine_tune) + u8 *best_coarse_tune2t_p1, u8 *best_coarse_tune0p5t_p1) { u8 best_coarse_rodt[DQS_NUMBER], best_coarse_0p5t_rodt[DQS_NUMBER]; u8 best_coarse_rodt_p1[DQS_NUMBER]; @@ -654,24 +790,14 @@ static void dramc_write_dqs_gating_result(u8 chn, u8 rank, dramc_rx_dqs_isi_pulse_cg_switch(chn, true); - write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, - ((u32) best_coarse_tune2t[0] << - SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_SHIFT) | - ((u32) best_coarse_tune2t[1] << - SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_SHIFT) | - ((u32) best_coarse_tune2t_p1[0] << - SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_SHIFT) | - ((u32) best_coarse_tune2t_p1[1] << - SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1_SHIFT)); - write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1, - ((u32) best_coarse_tune0p5t[0] << - SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_SHIFT) | - ((u32) best_coarse_tune0p5t[1] << - SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_SHIFT) | - ((u32) best_coarse_tune0p5t_p1[0] << - SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1_SHIFT) | - ((u32) best_coarse_tune0p5t_p1[1] << - SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1_SHIFT)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, + 0x77777777, + (best_coarse_tune2t[0] << 0) | (best_coarse_tune2t[1] << 8) | + (best_coarse_tune2t_p1[0] << 4) | (best_coarse_tune2t_p1[1] << 12)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1, + 0x77777777, + (best_coarse_tune0p5t[0] << 0) | (best_coarse_tune0p5t[1] << 8) | + (best_coarse_tune0p5t_p1[0] << 4) | (best_coarse_tune0p5t_p1[1] << 12)); for (size_t dqs = 0; dqs < DQS_NUMBER; dqs++) { u8 tmp_value = (best_coarse_tune2t[dqs] << 3) @@ -703,45 +829,31 @@ static void dramc_write_dqs_gating_result(u8 chn, u8 rank, } } - write32(&ch[chn].ao.shu[0].rk[rank].selph_odten0, - ((u32) best_coarse_rodt[0] << - SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_SHIFT) | - ((u32) best_coarse_rodt[1] << - SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_SHIFT) | - ((u32) best_coarse_rodt_p1[0] << - SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1_SHIFT) | - ((u32) best_coarse_rodt_p1[1] << - SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1_SHIFT)); - write32(&ch[chn].ao.shu[0].rk[rank].selph_odten1, - ((u32) best_coarse_0p5t_rodt[0] << - SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_SHIFT) | - ((u32) best_coarse_0p5t_rodt[1] << - SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_SHIFT) | - ((u32) best_coarse_0p5t_rodt_p1[0] << - SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_P1_SHIFT) | - ((u32) best_coarse_0p5t_rodt_p1[1] << - SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_P1_SHIFT)); - - write32(&ch[chn].ao.shu[0].rk[rank].dqsien, - best_fine_tune[0] | (best_fine_tune[1] << 8)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten0, + 0x77777777, + (best_coarse_rodt[0] << 0) | (best_coarse_rodt[1] << 8) | + (best_coarse_rodt_p1[0] << 4) | (best_coarse_rodt_p1[1] << 12)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten1, + 0x77777777, + (best_coarse_0p5t_rodt[0] << 0) | (best_coarse_0p5t_rodt[1] << 8) | + (best_coarse_0p5t_rodt_p1[0] << 4) | (best_coarse_0p5t_rodt_p1[1] << 12)); } -static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank) +static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank, u8 freq_group, + const struct sdram_params *params) { - u8 dqs; - const u8 mr1_value = 0x56; - u8 pass_begin[DQS_NUMBER] = {0}, pass_count[DQS_NUMBER] = {0}; + u8 dqs, fsp, freqDiv = 4; + u8 pass_begin[DQS_NUMBER] = {0}, pass_count[DQS_NUMBER] = {0}, + pass_count_1[DQS_NUMBER] = {0}, dqs_done[DQS_NUMBER] = {0}; u8 min_coarse_tune2t[DQS_NUMBER], min_coarse_tune0p5t[DQS_NUMBER], min_fine_tune[DQS_NUMBER]; u8 best_fine_tune[DQS_NUMBER], best_coarse_tune0p5t[DQS_NUMBER], best_coarse_tune2t[DQS_NUMBER]; - u8 best_coarse_tune0p5t_p1[DQS_NUMBER], - best_coarse_tune2t_p1[DQS_NUMBER]; + u8 best_coarse_tune0p5t_p1[DQS_NUMBER], best_coarse_tune2t_p1[DQS_NUMBER]; u8 dqs_high[DQS_NUMBER] = {0}, dqs_transition[DQS_NUMBER] = {0}; - u8 dly_coarse_large_cnt[DQS_NUMBER] = {0}, - dly_coarse_0p5t_cnt[DQS_NUMBER] = {0}, + u8 dly_coarse_large_cnt[DQS_NUMBER] = {0}, dly_coarse_0p5t_cnt[DQS_NUMBER] = {0}, dly_fine_tune_cnt[DQS_NUMBER] = {0}; - u32 coarse_start = GATING_START, coarse_end = GATING_END; + u32 coarse_start, coarse_end; u32 debug_cnt[DQS_NUMBER]; struct reg_value regs_bak[] = { @@ -756,23 +868,44 @@ static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank) for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) regs_bak[i].value = read32(regs_bak[i].addr); - dramc_mode_reg_write_by_rank(chn, rank, 0x1, mr1_value | 0x80); + fsp = get_freq_fsq(freq_group); + dramc_rx_dqs_isi_pulse_cg_switch(chn, false); + + MR01Value[fsp] |= 0x80; + dramc_mode_reg_write_by_rank(chn, rank, 0x1, MR01Value[fsp]); dramc_rx_dqs_gating_cal_pre(chn, rank); u32 dummy_rd_backup = read32(&ch[chn].ao.dummy_rd); - dramc_engine2_init(chn, rank, 0x23, true); + dramc_engine2_init(chn, rank, TEST2_1_CAL, 0xaa000023, true); + + switch (freq_group) { + case LP4X_DDR1600: + coarse_start = 18; + break; + case LP4X_DDR2400: + coarse_start = 25; + break; + case LP4X_DDR3200: + coarse_start = 25; + break; + case LP4X_DDR3600: + coarse_start = 21; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + coarse_end = coarse_start + 12; dramc_dbg("[Gating]\n"); - for (u32 coarse_tune = coarse_start; coarse_tune < coarse_end; - coarse_tune += DQS_GW_COARSE_STEP) { + for (u32 coarse_tune = coarse_start; coarse_tune < coarse_end; coarse_tune++) { u32 dly_coarse_large_rodt = 0, dly_coarse_0p5t_rodt = 0; u32 dly_coarse_large_rodt_p1 = 4, dly_coarse_0p5t_rodt_p1 = 4; + u8 dly_coarse_large = coarse_tune / RX_DQS_CTL_LOOP; u8 dly_coarse_0p5t = coarse_tune % RX_DQS_CTL_LOOP; - u32 dly_coarse_large_p1 = - (coarse_tune + DQS_GW_FREQ_DIV) / RX_DQS_CTL_LOOP; - u32 dly_coarse_0p5t_p1 = - (coarse_tune + DQS_GW_FREQ_DIV) % RX_DQS_CTL_LOOP; + u32 dly_coarse_large_p1 = (coarse_tune + freqDiv) / RX_DQS_CTL_LOOP; + u32 dly_coarse_0p5t_p1 = (coarse_tune + freqDiv) % RX_DQS_CTL_LOOP; u32 value = (dly_coarse_large << 3) + dly_coarse_0p5t; if (value >= 11) { @@ -787,49 +920,33 @@ static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank) value - (dly_coarse_large_rodt_p1 << 3); } - write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, - ((u32) dly_coarse_large << - SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_SHIFT) | - ((u32) dly_coarse_large << - SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_SHIFT) | - (dly_coarse_large_p1 << - SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_SHIFT) | - (dly_coarse_large_p1 << - SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1_SHIFT)); - write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1, - ((u32) dly_coarse_0p5t << - SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_SHIFT) | - ((u32) dly_coarse_0p5t << - SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_SHIFT) | - (dly_coarse_0p5t_p1 << - SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1_SHIFT) | - (dly_coarse_0p5t_p1 << - SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1_SHIFT)); - write32(&ch[chn].ao.shu[0].rk[rank].selph_odten0, - (dly_coarse_large_rodt << - SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_SHIFT) | - (dly_coarse_large_rodt << - SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_SHIFT) | - (dly_coarse_large_rodt_p1 << - SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1_SHIFT) | - (dly_coarse_large_rodt_p1 << - SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1_SHIFT)); - write32(&ch[chn].ao.shu[0].rk[rank].selph_odten1, - (dly_coarse_0p5t_rodt << - SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_SHIFT) | - (dly_coarse_0p5t_rodt << - SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_SHIFT) | - (dly_coarse_0p5t_rodt_p1 << - SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_P1_SHIFT) | - (dly_coarse_0p5t_rodt_p1 << - SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_P1_SHIFT)); - - for (u8 dly_fine_xt = DQS_GW_FINE_START; - dly_fine_xt < DQS_GW_FINE_END; - dly_fine_xt += DQS_GW_FINE_STEP) { + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, + 0x77777777, + (dly_coarse_large << 0) | (dly_coarse_large << 8) | + (dly_coarse_large << 16) | (dly_coarse_large << 24) | + (dly_coarse_large_p1 << 4) | (dly_coarse_large_p1 << 12) | + (dly_coarse_large_p1 << 20) | (dly_coarse_large_p1 << 28)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1, + 0x77777777, + (dly_coarse_0p5t << 0) | (dly_coarse_0p5t << 8) | + (dly_coarse_0p5t << 16) | (dly_coarse_0p5t << 24) | + (dly_coarse_0p5t_p1 << 4) | (dly_coarse_0p5t_p1 << 12) | + (dly_coarse_0p5t_p1 << 20) | (dly_coarse_0p5t_p1 << 28)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten0, + 0x77777777, + (dly_coarse_large_rodt << 0) | (dly_coarse_large_rodt << 8) | + (dly_coarse_large_rodt << 16) | (dly_coarse_large_rodt << 24) | + (dly_coarse_large_rodt_p1 << 4) | (dly_coarse_large_rodt_p1 << 12) | + (dly_coarse_large_rodt_p1 << 20) | (dly_coarse_large_rodt_p1 << 28)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten1, + 0x77777777, + (dly_coarse_0p5t_rodt << 0) | (dly_coarse_0p5t_rodt << 8) | + (dly_coarse_0p5t_rodt << 16) | (dly_coarse_0p5t_rodt << 24) | + (dly_coarse_0p5t_rodt_p1 << 4) | (dly_coarse_0p5t_rodt_p1 << 12) | + (dly_coarse_0p5t_rodt_p1 << 20) | (dly_coarse_0p5t_rodt_p1 << 28)); + for (u8 dly_fine_xt = 0; dly_fine_xt < DQS_GW_FINE_END; dly_fine_xt += 4) { dramc_set_gating_mode(chn, 0); - write32(&ch[chn].ao.shu[0].rk[rank].dqsien, dly_fine_xt | (dly_fine_xt << 8)); @@ -856,7 +973,7 @@ static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank) dramc_find_dly_tune(chn, dly_coarse_large, dly_coarse_0p5t, dly_fine_xt, dqs_high, dly_coarse_large_cnt, dly_coarse_0p5t_cnt, - dly_fine_tune_cnt, dqs_transition); + dly_fine_tune_cnt, dqs_transition, dqs_done); dramc_dbg("%d %d %d |", dly_coarse_large, dly_coarse_0p5t, dly_fine_xt); @@ -871,10 +988,10 @@ static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank) } dramc_dbg("\n"); - dramc_find_gating_window(result_r, result_f, debug_cnt, - dly_coarse_large, dly_coarse_0p5t, pass_begin, - pass_count, &dly_fine_xt, &coarse_tune, - dqs_high); + if (dramc_find_gating_window(result_r, result_f, debug_cnt, + dly_coarse_large, dly_coarse_0p5t, pass_begin, pass_count, + pass_count_1, &dly_fine_xt, dqs_high, dqs_done)) + coarse_tune = coarse_end; } } @@ -897,7 +1014,8 @@ static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank) tmp_offset = tmp_value / RX_DQS_CTL_LOOP; best_coarse_tune2t[dqs] = min_coarse_tune2t[dqs] + tmp_offset; - tmp_value = best_coarse_tune0p5t[dqs] + DQS_GW_FREQ_DIV; + + tmp_value = best_coarse_tune0p5t[dqs] + freqDiv; best_coarse_tune0p5t_p1[dqs] = tmp_value % RX_DQS_CTL_LOOP; tmp_offset = tmp_value / RX_DQS_CTL_LOOP; @@ -911,38 +1029,40 @@ static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank) best_coarse_tune0p5t[dqs], best_fine_tune[dqs]); for (dqs = 0; dqs < DQS_NUMBER; dqs++) - dramc_show("Best DQS%d coarse dly(2T, 0.5T, fine tune)" + dramc_show("Best DQS%d P1 dly(2T, 0.5T, fine tune)" " = (%d, %d, %d)\n", dqs, best_coarse_tune2t_p1[dqs], best_coarse_tune0p5t_p1[dqs], best_fine_tune[dqs]); for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) write32(regs_bak[i].addr, regs_bak[i].value); - dramc_mode_reg_write_by_rank(chn, rank, 0x1, mr1_value & 0x7f); + MR01Value[fsp] &= 0x7f; + dramc_mode_reg_write_by_rank(chn, rank, 0x1, MR01Value[fsp]); dramc_write_dqs_gating_result(chn, rank, best_coarse_tune2t, - best_coarse_tune0p5t, best_coarse_tune2t_p1, - best_coarse_tune0p5t_p1, best_fine_tune); + best_coarse_tune0p5t, best_coarse_tune2t_p1, best_coarse_tune0p5t_p1); + + write32(&ch[chn].ao.shu[0].rk[rank].dqsien, + best_fine_tune[0] | (best_fine_tune[1] << 8)); dram_phy_reset(chn); } -static void dramc_rd_dqc_init(u8 chn, u8 rank) +static void dramc_rx_rd_dqc_init(u8 chn, u8 rank) { const u8 *lpddr_phy_mapping = phy_mapping[chn]; u16 temp_value = 0; for (size_t b = 0; b < 2; b++) - clrbits_le32(&ch[chn].phy.shu[0].b[b].dq[7], - 0x1 << SHU1_BX_DQ7_R_DMDQMDBI_SHIFT); + clrbits_le32(&ch[chn].phy.shu[0].b[b].dq[7], 0x1 << 7); clrsetbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK, rank << MRS_MRSRK_SHIFT); setbits_le32(&ch[chn].ao.mpc_option, 0x1 << MPC_OPTION_MPCRKEN_SHIFT); - for (size_t i = 0; i < 16; i++) - temp_value |= ((0x5555 >> i) & 0x1) << lpddr_phy_mapping[i]; + for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) + temp_value |= ((0x5555 >> bit) & 0x1) << lpddr_phy_mapping[bit]; u16 mr15_golden_value = temp_value & 0xff; u16 mr20_golden_value = (temp_value >> 8) & 0xff; @@ -951,14 +1071,16 @@ static void dramc_rd_dqc_init(u8 chn, u8 rank) (mr15_golden_value << 8) | mr20_golden_value); } -static u32 dramc_rd_dqc_run(u8 chn) +static u32 dramc_rx_rd_dqc_run(u8 chn) { + u32 loop = 0; setbits_le32(&ch[chn].ao.spcmdctrl, 1 << SPCMDCTRL_RDDQCDIS_SHIFT); setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_RDDQCEN_SHIFT); - if (!wait_us(100, read32(&ch[chn].nao.spcmdresp) & - (0x1 << SPCMDRESP_RDDQC_RESPONSE_SHIFT))) - dramc_dbg("[RDDQC] resp fail (time out)\n"); + while (!wait_us(10, read32(&ch[chn].nao.spcmdresp) & (0x1 << 7))) { + if (loop++ > 10) + dramc_dbg("[RDDQC] resp fail (time out)\n"); + } u32 result = read32(&ch[chn].nao.rdqc_cmp); clrbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_RDDQCEN_SHIFT); @@ -967,25 +1089,22 @@ static u32 dramc_rd_dqc_run(u8 chn) return result; } -static void dramc_rd_dqc_end(u8 chn) +static void dramc_rx_rd_dqc_end(u8 chn) { clrbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK); } -static void dramc_rx_vref_enable(u8 chn) +static void dramc_rx_vref_pre_setting(u8 chn) { - setbits_le32(&ch[chn].phy.b[0].dq[5], - 0x1 << B0_DQ5_RG_RX_ARDQ_VREF_EN_B0_SHIFT); - setbits_le32(&ch[chn].phy.b[1].dq[5], - 0x1 << B1_DQ5_RG_RX_ARDQ_VREF_EN_B1_SHIFT); + setbits_le32(&ch[chn].phy.b[0].dq[5], 0x1 << 16); + setbits_le32(&ch[chn].phy.b[1].dq[5], 0x1 << 16); } -static void dramc_set_rx_vref(u8 chn, u8 value) +static void dramc_set_rx_vref(u8 chn, u8 vref) { for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dq[5], - SHU1_BX_DQ5_RG_RX_ARDQ_VREF_SEL_B0_MASK, - value << SHU1_BX_DQ5_RG_RX_ARDQ_VREF_SEL_B0_SHIFT); + clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dq[5], 0x3f, vref << 0); + dramc_dbg("set rx vref :%d\n", vref); } static void dramc_set_tx_vref(u8 chn, u8 rank, u8 value) @@ -1001,20 +1120,32 @@ static void dramc_set_vref(u8 chn, u8 rank, enum CAL_TYPE type, u8 vref) dramc_set_tx_vref(chn, rank, vref); } -static void dramc_transfer_dly_tune( - u8 chn, u32 dly, struct tx_dly_tune *dly_tune) +static void dramc_transfer_dly_tune(u8 chn, u32 dly, u32 adjust_center, + struct tx_dly_tune *dly_tune) { - u16 tmp_val; + u8 tune = 3, fine_tune = 0; + u16 tmp; - dly_tune->fine_tune = dly & (TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP - 1); + fine_tune = dly & (TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP - 1); + tmp = (dly / TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP) << 1; - tmp_val = (dly / TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP) << 1; - dly_tune->coarse_tune_small = tmp_val - ((tmp_val >> 3) << 3); - dly_tune->coarse_tune_large = tmp_val >> 3; + if (adjust_center) { + if (fine_tune < 10) { + fine_tune += TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP >> 1; + tmp--; + } else if (fine_tune > TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP - 10) { + fine_tune -= TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP >> 1; + tmp++; + } + } - tmp_val -= 4; - dly_tune->coarse_tune_small_oen = tmp_val - ((tmp_val >> 3) << 3); - dly_tune->coarse_tune_large_oen = tmp_val >> 3; + dly_tune->fine_tune = fine_tune; + dly_tune->coarse_tune_small = tmp - ((tmp >> tune) << tune); + dly_tune->coarse_tune_large = tmp >> tune; + + tmp -= 3; + dly_tune->coarse_tune_small_oen = tmp - ((tmp >> tune) << tune); + dly_tune->coarse_tune_large_oen = tmp >> tune; } static void dramc_set_rx_dly_factor(u8 chn, u8 rank, enum RX_TYPE type, u32 val) @@ -1024,9 +1155,9 @@ static void dramc_set_rx_dly_factor(u8 chn, u8 rank, enum RX_TYPE type, u32 val) switch (type) { case RX_DQ: tmp = (val << 24 | val << 16 | val << 8 | val); - for (size_t i = 2; i < 6; i++) { - write32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[i], tmp); - write32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[i], tmp); + for (size_t dq = 2; dq < 6; dq++) { + write32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[dq], tmp); + write32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[dq], tmp); } break; @@ -1049,79 +1180,105 @@ static void dramc_set_rx_dly_factor(u8 chn, u8 rank, enum RX_TYPE type, u32 val) clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[6], mask, tmp); break; + default: + dramc_show("error calibration type:%d\n", type); + break; } } -static void dramc_set_tx_dly_factor(u8 chn, u8 rank, - enum CAL_TYPE type, u32 val) +static void dramc_set_tx_dly_factor(u8 chn, u8 rk, + enum CAL_TYPE type, u8 *dq_small_reg, u32 dly) { struct tx_dly_tune dly_tune = {0}; - u32 coarse_tune_large = 0, coarse_tune_large_oen = 0; - u32 coarse_tune_small = 0, coarse_tune_small_oen = 0; + u32 dly_large = 0, dly_large_oen = 0, dly_small = 0, dly_small_oen = 0; + u32 adjust_center = 0; - dramc_transfer_dly_tune(chn, val, &dly_tune); + dramc_transfer_dly_tune(chn, dly, adjust_center, &dly_tune); for (u8 i = 0; i < 4; i++) { - coarse_tune_large += dly_tune.coarse_tune_large << (i * 4); - coarse_tune_large_oen += - dly_tune.coarse_tune_large_oen << (i * 4); - coarse_tune_small += dly_tune.coarse_tune_small << (i * 4); - coarse_tune_small_oen += - dly_tune.coarse_tune_small_oen << (i * 4); + dly_large += dly_tune.coarse_tune_large << (i * 4); + dly_large_oen += dly_tune.coarse_tune_large_oen << (i * 4); + dly_small += dly_tune.coarse_tune_small << (i * 4); + dly_small_oen += dly_tune.coarse_tune_small_oen << (i * 4); } + if (type == TX_WIN_DQ_DQM) dramc_dbg("%3d |%d %d %2d | [0]", - val, dly_tune.coarse_tune_large, - dly_tune.coarse_tune_small, dly_tune.fine_tune); + dly, dly_tune.coarse_tune_large, + dly_tune.coarse_tune_small, dly_tune.fine_tune); - if (type != TX_WIN_DQ_DQM && type != TX_WIN_DQ_ONLY) - return; + if (*dq_small_reg != dly_tune.coarse_tune_small) { + if (type == TX_WIN_DQ_DQM || type == TX_WIN_DQ_ONLY) { + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[0], + 0x77777777, dly_large | (dly_large_oen << 16)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[2], + 0x77777777, dly_small | (dly_small_oen << 16)); + } - write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[0], - (coarse_tune_large_oen << 16) | coarse_tune_large); - write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[2], - (coarse_tune_small_oen << 16) | coarse_tune_small); - for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[b].dq[7], - FINE_TUNE_DQ_MASK, dly_tune.fine_tune << 8); + if (type == TX_WIN_DQ_DQM) { + /* Large coarse_tune setting */ + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[1], + 0x77777777, dly_large | (dly_large_oen << 16)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[3], + 0x77777777, dly_small | (dly_small_oen << 16)); + } + } + *dq_small_reg = dly_tune.coarse_tune_small; - if (type == TX_WIN_DQ_DQM) { - /* Large coarse_tune setting */ - write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[1], - (coarse_tune_large_oen << 16) | coarse_tune_large); - write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[3], - (coarse_tune_small_oen << 16) | coarse_tune_small); - /* Fine_tune delay setting */ + if (type == TX_WIN_DQ_DQM || type == TX_WIN_DQ_ONLY) { for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[b].dq[7], + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rk].b[b].dq[7], + FINE_TUNE_DQ_MASK, dly_tune.fine_tune << 8); + } + if (type == TX_WIN_DQ_DQM) { + for (size_t b = 0; b < 2; b++) + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rk].b[b].dq[7], FINE_TUNE_DQM_MASK, dly_tune.fine_tune << 16); } } -static u32 dramc_get_smallest_dqs_dly( - u8 chn, u8 rank, const struct sdram_params *params) +static u32 dramc_get_smallest_dqs_dly(u8 chn, u8 rank, const struct sdram_params *params) { - u32 min_dly = 0xffff; + const u8 mck = 3; + u32 min_dly = 0xffff, virtual_delay = 0; + u32 tx_dly = read32(&ch[chn].ao.shu[0].selph_dqs0); + u32 dly = read32(&ch[chn].ao.shu[0].selph_dqs1); + u32 tmp; - for (size_t i = 0; i < DQS_NUMBER; i++) - min_dly = MIN(min_dly, params->wr_level[chn][rank][i]); + for (size_t dqs = 0; dqs < DQS_NUMBER; dqs++) { + tmp = ((tx_dly >> (dqs << 2) & 0x7) << mck) + + (dly >> (dqs << 2) & 0x7); + virtual_delay = (tmp << 5) + params->wr_level[chn][rank][dqs]; + min_dly = MIN(min_dly, virtual_delay); + } - return DQS_DELAY + min_dly + 40; + return min_dly; } static void dramc_get_dly_range(u8 chn, u8 rank, enum CAL_TYPE type, - u16 *pre_cal, s16 *begin, s16 *end, + u8 freq_group, u16 *pre_cal, s16 *begin, s16 *end, const struct sdram_params *params) { u16 pre_dq_dly; switch (type) { case RX_WIN_RD_DQC: - *begin = FIRST_DQS_DELAY; - *end = MAX_RX_DQDLY_TAPS; - break; - case RX_WIN_TEST_ENG: - *begin = FIRST_DQ_DELAY; + switch (freq_group) { + case LP4X_DDR1600: + *begin = -48; + break; + case LP4X_DDR2400: + *begin = -30; + break; + case LP4X_DDR3200: + case LP4X_DDR3600: + *begin = -26; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + *end = MAX_RX_DQDLY_TAPS; break; @@ -1136,394 +1293,401 @@ static void dramc_get_dly_range(u8 chn, u8 rank, enum CAL_TYPE type, *begin = pre_dq_dly; *end = *begin + 64; break; + default: + dramc_show("error calibration type:%d\n", type); + break; } } -static int dramc_check_dqdqs_win( - struct dqdqs_perbit_dly *p, s16 dly_pass, s16 last_step, - bool fail, bool is_dq) + +static int dramc_check_dqdqs_win(struct win_perbit_dly *perbit_dly, + s16 dly, s16 dly_end, bool fail_bit) { - s16 best_pass_win; - struct perbit_dly *dly = is_dq ? &p->dqdly : &p->dqsdly; + int pass_win = 0; - if (!fail && dly->first == -1) - dly->first = dly_pass; + if (perbit_dly->first_pass == PASS_RANGE_NA) { + if (!fail_bit) /* compare correct: pass */ + perbit_dly->first_pass = dly; + } else if (perbit_dly->last_pass == PASS_RANGE_NA) { + if (fail_bit) /* compare error: fail */ + perbit_dly->last_pass = dly - 1; + else if (dly == dly_end) + perbit_dly->last_pass = dly; - if (!fail && dly->last == -2 && dly_pass == last_step) - dly->last = dly_pass; - else if (fail && dly->first != -1 && dly->last == -2) - dly->last = dly_pass - 1; + if (perbit_dly->last_pass != PASS_RANGE_NA) { + pass_win = perbit_dly->last_pass - perbit_dly->first_pass; + int best_pass_win = perbit_dly->best_last - perbit_dly->best_first; + if (pass_win >= best_pass_win) { + perbit_dly->best_last = perbit_dly->last_pass; + perbit_dly->best_first = perbit_dly->first_pass; + } - if (dly->last == -2) - return 0; - - int pass_win = dly->last - dly->first; - best_pass_win = dly->best_last - dly->best_first; - if (pass_win > best_pass_win) { - dly->best_last = dly->last; - dly->best_first = dly->first; + /* Clear to find the next pass range if it has */ + perbit_dly->first_pass = PASS_RANGE_NA; + perbit_dly->last_pass = PASS_RANGE_NA; + } } - /* Clear to find the next pass range if it has */ - dly->first = -1; - dly->last = -2; return pass_win; } -static void dramc_set_vref_dly(struct vref_perbit_dly *vref_dly, - u8 vref, u32 win_size_sum, struct dqdqs_perbit_dly delay[]) +static void dramc_set_vref_dly(struct vref_perbit_dly *vref_dly, struct win_perbit_dly delay[]) { - struct dqdqs_perbit_dly *perbit_dly = vref_dly->perbit_dly; + struct win_perbit_dly *perbit_dly = vref_dly->perbit_dly; - vref_dly->max_win = win_size_sum; - vref_dly->vref = vref; - for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { - perbit_dly[bit].dqdly.best = delay[bit].dqdly.best; - perbit_dly[bit].dqdly.best_first = delay[bit].dqdly.best_first; - perbit_dly[bit].dqdly.best_last = delay[bit].dqdly.best_last; - perbit_dly[bit].dqsdly.best_first = - delay[bit].dqsdly.best_first; - perbit_dly[bit].dqsdly.best_last = delay[bit].dqsdly.best_last; + for (u8 bit = 0; bit < DQ_DATA_WIDTH; bit++) { + delay[bit].win_center = (delay[bit].best_first + delay[bit].best_last) >> 1; + + perbit_dly[bit].best_first = delay[bit].best_first; + perbit_dly[bit].best_last = delay[bit].best_last; + perbit_dly[bit].win_center = delay[bit].win_center; + perbit_dly[bit].best_dqdly = delay[bit].best_dqdly; } } static bool dramk_calc_best_vref(enum CAL_TYPE type, u8 vref, - struct vref_perbit_dly *vref_dly, - struct dqdqs_perbit_dly delay[]) + struct vref_perbit_dly *vref_dly, struct win_perbit_dly delay[], + u32 *win_min_max) { - u32 win_size; - u32 win_size_sum = 0; - static u32 min_win_size_vref; + u32 win_size, min_bit = 0xff, min_winsize = 0xffff, tmp_win_sum = 0; switch (type) { + case RX_WIN_RD_DQC: case RX_WIN_TEST_ENG: for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { - win_size_sum += delay[bit].dqdly.best_last - - delay[bit].dqdly.best_first + 1; - win_size_sum += delay[bit].dqsdly.best_last - - delay[bit].dqsdly.best_first + 1; + win_size = delay[bit].best_last - delay[bit].best_first; + + if (win_size < min_winsize) { + min_bit = bit; + min_winsize = win_size; + } + tmp_win_sum += win_size; } + dramc_dbg("type:%d vref:%d Min Bit=%d, min_winsize=%d, win sum:%d\n", + type, vref, min_bit, min_winsize, tmp_win_sum); - if (win_size_sum > vref_dly->max_win) - dramc_set_vref_dly(vref_dly, vref, win_size_sum, delay); + if (tmp_win_sum > vref_dly->max_win_sum) { + *win_min_max = min_winsize; + vref_dly->max_win_sum = tmp_win_sum; - if (win_size_sum < (vref_dly->max_win * 95 / 100)) + /* best vref */ + vref_dly->best_vref = vref; + } + dramc_dbg("type:%d vref:%d, win_sum_total:%d, tmp_win_sum:%d)\n", + type, vref, vref_dly->max_win_sum, tmp_win_sum); + dramc_set_vref_dly(vref_dly, delay); + + if (tmp_win_sum < vref_dly->max_win_sum * 95 / 100) { + dramc_dbg("type:%d best vref found[%d], early break! (%d < %d)\n", + type, vref_dly->best_vref, tmp_win_sum, + vref_dly->max_win_sum * 95 / 100); return true; + } break; - case TX_DQ_DQS_MOVE_DQ_ONLY: + case TX_WIN_DQ_ONLY: + case TX_WIN_DQ_DQM: for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { - win_size = delay[bit].dqdly.best_last - - delay[bit].dqdly.best_first + 1; - vref_dly->min_win = MIN(vref_dly->min_win, win_size); - win_size_sum += win_size; - } + win_size = delay[bit].best_last - delay[bit].best_first; - if (win_size_sum > vref_dly->max_win - && vref_dly->min_win >= min_win_size_vref) { - min_win_size_vref = vref_dly->min_win; - dramc_set_vref_dly(vref_dly, vref, win_size_sum, delay); + if (win_size < min_winsize) { + min_bit = bit; + min_winsize = win_size; + } + tmp_win_sum += win_size; + } + dramc_dbg("type:%d vref:%d Min Bit=%d, min_winsize=%d, win sum:%d\n", + type, vref, min_bit, min_winsize, tmp_win_sum); + + if (min_winsize > *win_min_max || + (min_winsize == *win_min_max && + tmp_win_sum > vref_dly->max_win_sum)) { + *win_min_max = min_winsize; + vref_dly->max_win_sum = tmp_win_sum; + + /* best vref */ + vref_dly->best_vref = vref; + } + dramc_dbg("type:%d vref:%d, win_sum_total:%d, tmp_win_sum:%d)\n", + type, vref, vref_dly->max_win_sum, tmp_win_sum); + dramc_set_vref_dly(vref_dly, delay); + + if (tmp_win_sum < vref_dly->max_win_sum * 95 / 100) { + dramc_dbg("type:%d best vref found[%d], early break! (%d < %d)\n", + type, vref_dly->best_vref, tmp_win_sum, + vref_dly->max_win_sum * 95 / 100); + return true; } break; + default: - dramc_set_vref_dly(vref_dly, vref, win_size_sum, delay); + dramc_show("error calibration type:%d\n", type); break; } return false; } -static void dramc_calc_tx_perbyte_dly( - struct dqdqs_perbit_dly *p, s16 *win, - struct per_byte_dly *byte_delay_prop) -{ - s16 win_center = (p->dqdly.best_first + p->dqdly.best_last) >> 1; - *win = win_center; - - if (win_center < byte_delay_prop->min_center) - byte_delay_prop->min_center = win_center; - if (win_center > byte_delay_prop->max_center) - byte_delay_prop->max_center = win_center; -} - -static void dramc_set_rx_dly(u8 chn, u8 rank, s32 dly) +static void dramc_set_rx_dqdqs_dly(u8 chn, u8 rank, s32 dly) { if (dly <= 0) { - /* Hold time calibration */ + /* Set DQS delay */ dramc_set_rx_dly_factor(chn, rank, RX_DQS, -dly); dram_phy_reset(chn); } else { /* Setup time calibration */ - dramc_set_rx_dly_factor(chn, rank, RX_DQS, 0); dramc_set_rx_dly_factor(chn, rank, RX_DQM, dly); dram_phy_reset(chn); dramc_set_rx_dly_factor(chn, rank, RX_DQ, dly); } } -static void dramc_set_tx_best_dly_factor(u8 chn, u8 rank_start, - struct per_byte_dly *tx_perbyte_dly, u16 dq_precal_result[]) +static void dramc_set_tx_best_dly_factor(u8 chn, u8 rank_start, u8 type, + struct per_byte_dly *tx_perbyte_dly, u16 *dq_precal_dly, + u8 use_delay_cell, u32 *byte_dly_cell) { - u32 coarse_tune_large = 0; - u32 coarse_tune_large_oen = 0; - u32 coarse_tune_small = 0; - u32 coarse_tune_small_oen = 0; + u32 dq_large = 0, dq_large_oen = 0, dq_small = 0, dq_small_oen = 0, adjust_center = 1; + u32 dqm_large = 0, dqm_large_oen = 0, dqm_small = 0, dqm_small_oen = 0; u16 dq_oen[DQS_NUMBER] = {0}, dqm_oen[DQS_NUMBER] = {0}; struct tx_dly_tune dqdly_tune[DQS_NUMBER] = {0}; struct tx_dly_tune dqmdly_tune[DQS_NUMBER] = {0}; for (size_t i = 0; i < DQS_NUMBER; i++) { dramc_transfer_dly_tune(chn, tx_perbyte_dly[i].final_dly, - &dqdly_tune[i]); - dramc_transfer_dly_tune(chn, dq_precal_result[i], - &dqmdly_tune[i]); + adjust_center, &dqdly_tune[i]); + dramc_transfer_dly_tune(chn, dq_precal_dly[i], + adjust_center, &dqmdly_tune[i]); - coarse_tune_large += dqdly_tune[i].coarse_tune_large << (i * 4); - coarse_tune_large_oen += - dqdly_tune[i].coarse_tune_large_oen << (i * 4); - coarse_tune_small += dqdly_tune[i].coarse_tune_small << (i * 4); - coarse_tune_small_oen += - dqdly_tune[i].coarse_tune_small_oen << (i * 4); + dq_large += dqdly_tune[i].coarse_tune_large << (i * 4); + dq_large_oen += dqdly_tune[i].coarse_tune_large_oen << (i * 4); + dq_small += dqdly_tune[i].coarse_tune_small << (i * 4); + dq_small_oen += dqdly_tune[i].coarse_tune_small_oen << (i * 4); + + dqm_large += dqmdly_tune[i].coarse_tune_large << (i * 4); + dqm_large_oen += dqmdly_tune[i].coarse_tune_large_oen << (i * 4); + dqm_small += dqmdly_tune[i].coarse_tune_small << (i * 4); + dqm_small_oen += dqmdly_tune[i].coarse_tune_small_oen << (i * 4); dq_oen[i] = (dqdly_tune[i].coarse_tune_large_oen << 3) + - (dqdly_tune[i].coarse_tune_small_oen << 5) + - dqdly_tune[i].fine_tune; + (dqdly_tune[i].coarse_tune_small_oen << 5) + dqdly_tune[i].fine_tune; dqm_oen[i] = (dqmdly_tune[i].coarse_tune_large_oen << 3) + - (dqmdly_tune[i].coarse_tune_small_oen << 5) + - dqmdly_tune[i].fine_tune; + (dqmdly_tune[i].coarse_tune_small_oen << 5) + + dqmdly_tune[i].fine_tune; } for (size_t rank = rank_start; rank < RANK_MAX; rank++) { - write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[0], - (coarse_tune_large_oen << 16) | coarse_tune_large); - write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[2], - (coarse_tune_small_oen << 16) | coarse_tune_small); - write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[1], - (coarse_tune_large_oen << 16) | coarse_tune_large); - write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[3], - (coarse_tune_small_oen << 16) | coarse_tune_small); - } + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[0], + 0x77777777, dq_large | (dq_large_oen << 16)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[2], + 0x77777777, dq_small | (dq_small_oen << 16)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[1], + 0x77777777, dqm_large | (dqm_large_oen << 16)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[3], + 0x77777777, dqm_small | (dqm_small_oen << 16)); - for (size_t rank = rank_start; rank < RANK_MAX; rank++) - for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[b].dq[7], + for (size_t byte = 0; byte < 2; byte++) + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[7], FINE_TUNE_DQ_MASK | FINE_TUNE_DQM_MASK, - (dqdly_tune[b].fine_tune << - FINE_TUNE_DQ_SHIFT) | - (dqmdly_tune[b].fine_tune << - FINE_TUNE_DQM_SHIFT)); + (dqdly_tune[byte].fine_tune << 8) | + (dqmdly_tune[byte].fine_tune << 16)); + if (use_delay_cell == 1) { + for (size_t byte = 0; byte < DQS_NUMBER; byte++) + write32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[0], + byte_dly_cell[byte]); + } + + if (type != TX_WIN_DQ_ONLY) + continue; + + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].fine_tune, 0x3f3f3f3f, + (dqdly_tune[0].fine_tune << 8) | (dqdly_tune[1].fine_tune << 0) | + (dqmdly_tune[0].fine_tune << 24) | (dqmdly_tune[1].fine_tune << 16)); + + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal1, 0x7ff | (0x7ff << 16), + (dqdly_tune[0].fine_tune << 0) | (dqdly_tune[1].fine_tune << 16)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal2, 0x7ff | (0x7ff << 16), + (dqdly_tune[0].fine_tune << 0) | (dqdly_tune[1].fine_tune << 16)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal5, 0x7ff | (0x7ff << 16), + (dqmdly_tune[0].fine_tune << 0) | (dqmdly_tune[1].fine_tune << 16)); + } } static void dramc_set_rx_best_dly_factor(u8 chn, u8 rank, - struct dqdqs_perbit_dly *dqdqs_perbit_dly, - u32 *max_dqsdly_byte, u32 *ave_dqm_dly) + struct win_perbit_dly *dly, s32 *dqsdly_byte, s32 *dqmdly_byte) { u32 value; - for (size_t i = 0; i < DQS_NUMBER; i++) { - value = (max_dqsdly_byte[i] << 24) | - (max_dqsdly_byte[i] << 16) | - (ave_dqm_dly[i] << 8) | (ave_dqm_dly[i] << 0); - write32(&ch[chn].phy.shu[0].rk[rank].b[i].dq[6], value); + /* set dqs delay, (dqm delay) */ + for (u8 byte = 0; byte < DQS_NUMBER; byte++) { + value = (dqsdly_byte[byte] << 24) | (dqsdly_byte[byte] << 16) | + (dqmdly_byte[byte] << 8) | (dqmdly_byte[byte] << 0); + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[6], 0x7f7f3f3f, value); } dram_phy_reset(chn); - for (size_t i = 0; i < DQ_DATA_WIDTH; i += 2) { - u32 byte = i / DQS_BIT_NUMBER; - u32 index = 2 + ((i % 8) * 2) / 4; - value = dqdqs_perbit_dly[i + 1].dqdly.best << 24 | - dqdqs_perbit_dly[i + 1].dqdly.best << 16 | - dqdqs_perbit_dly[i].dqdly.best << 8 | - dqdqs_perbit_dly[i].dqdly.best; - write32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[index], value); - } -} + /* set dq delay */ + for (u8 byte = 0; byte < DQS_NUMBER; byte++) { + for (u8 bit = 0; bit < DQS_BIT_NUMBER; bit += 2) { + u8 index = bit + byte * DQS_BIT_NUMBER; + u8 dq_num = 2 + bit / 2; + value = (dly[index + 1].best_dqdly << 24) | + (dly[index + 1].best_dqdly << 16) | + (dly[index].best_dqdly << 8) | (dly[index].best_dqdly << 0); -static bool dramc_calc_best_dly(u8 bit, - struct dqdqs_perbit_dly *p, u32 *p_max_byte) -{ - u8 fail = 0, hold, setup; - - hold = p->dqsdly.best_last - p->dqsdly.best_first + 1; - setup = p->dqdly.best_last - p->dqdly.best_first + 1; - - if (hold > setup) { - p->dqdly.best = 0; - p->dqsdly.best = (setup != 0) ? (hold - setup) / 2 : - (hold - setup) / 2 + p->dqsdly.best_first; - - if (p->dqsdly.best > *p_max_byte) - *p_max_byte = p->dqsdly.best; - - } else if (hold < setup) { - p->dqsdly.best = 0; - p->dqdly.best = (hold != 0) ? (setup - hold) / 2 : - (setup - hold) / 2 + p->dqdly.best_first; - - } else { /* Hold time == setup time */ - p->dqsdly.best = 0; - p->dqdly.best = 0; - - if (hold == 0) { - dramc_dbg("Error bit %d, setup = hold = 0\n", bit); - fail = 1; + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[dq_num], + 0x3f3f3f3f, value); } } - - dramc_dbg("bit#%d : dq =%d dqs=%d win=%d (%d, %d)\n", bit, setup, - hold, setup + hold, p->dqdly.best, p->dqsdly.best); - - return fail; } -static void dramc_set_dqdqs_dly(u8 chn, u8 rank, enum CAL_TYPE type, s32 dly) +static void dramc_set_dqdqs_dly(u8 chn, u8 rank, enum CAL_TYPE type, u8 *small_value, s32 dly) { - if ((type == RX_WIN_RD_DQC) || (type == RX_WIN_TEST_ENG)) - dramc_set_rx_dly(chn, rank, dly); + if (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) + dramc_set_rx_dqdqs_dly(chn, rank, dly); else - dramc_set_tx_dly_factor(chn, rank, type, dly); + dramc_set_tx_dly_factor(chn, rank, type, small_value, dly); } -static void dramc_set_tx_best_dly(u8 chn, u8 rank, - struct dqdqs_perbit_dly *tx_dly, u16 *tx_dq_precal_result, - const struct sdram_params *params) +static void dramc_set_tx_best_dly(u8 chn, u8 rank, bool bypass_tx, + struct win_perbit_dly *vref_dly, enum CAL_TYPE type, u8 freq_group, + u16 *tx_dq_precal_result, u16 dly_cell_unit, const struct sdram_params *params) { - s16 dq_win_center[DQ_DATA_WIDTH]; - u16 pi_diff; + int index, clock_rate; + u8 use_delay_cell; u32 byte_dly_cell[DQS_NUMBER] = {0}; - struct per_byte_dly tx_perbyte_dly[DQS_NUMBER]; - u16 dly_cell_unit = params->delay_cell_unit; - int index, bit; - u16 dq_delay_cell[DQ_DATA_WIDTH]; + struct per_byte_dly center_dly[DQS_NUMBER]; + u16 tune_diff, dq_delay_cell[DQ_DATA_WIDTH]; - for (size_t i = 0; i < DQS_NUMBER; i++) { - tx_perbyte_dly[i].min_center = 0xffff; - tx_perbyte_dly[i].max_center = 0; + switch (freq_group) { + case LP4X_DDR1600: + clock_rate = 800; + break; + case LP4X_DDR2400: + clock_rate = 1200; + break; + case LP4X_DDR3200: + clock_rate = 1600; + break; + case LP4X_DDR3600: + clock_rate = 1866; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; } - for (size_t i = 0; i < DQ_DATA_WIDTH; i++) { - index = i / DQS_BIT_NUMBER; - dramc_calc_tx_perbyte_dly(&tx_dly[i], - &dq_win_center[i], &tx_perbyte_dly[index]); - } + if (type == TX_WIN_DQ_ONLY && get_freq_fsq(freq_group) == FSP_1) + use_delay_cell = 1; + else + use_delay_cell = 0; - for (size_t i = 0; i < DQS_NUMBER; i++) { - tx_perbyte_dly[i].final_dly = tx_perbyte_dly[i].min_center; - tx_dq_precal_result[i] = (tx_perbyte_dly[i].max_center - + tx_perbyte_dly[i].min_center) >> 1; + for (u8 byte = 0; byte < DQS_NUMBER; byte++) { + center_dly[byte].min_center = 0xffff; + center_dly[byte].max_center = 0; - for (bit = 0; bit < DQS_BIT_NUMBER; bit++) { - pi_diff = dq_win_center[i * 8 + bit] - - tx_perbyte_dly[i].min_center; - dq_delay_cell[i * 8 + bit] = - ((pi_diff * 1000000) / (16 * 64)) - / dly_cell_unit; - byte_dly_cell[i] |= - (dq_delay_cell[i * 8 + bit] << (bit * 4)); + for (u8 bit = 0; bit < DQS_BIT_NUMBER; bit++) { + index = bit + 8 * byte; + if (vref_dly[index].win_center < center_dly[byte].min_center) + center_dly[byte].min_center = vref_dly[index].win_center; + if (vref_dly[index].win_center > center_dly[byte].max_center) + center_dly[byte].max_center = vref_dly[index].win_center; } - - write32(&ch[chn].phy.shu[0].rk[rank].b[i].dq[0], - byte_dly_cell[i]); + dramc_dbg("[channel %d] [rank %d] byte:%d, center_dly[byte].min_center:%d, center_dly[byte].max_center:%d\n", + chn, rank, byte, center_dly[byte].min_center, + center_dly[byte].max_center); } - dramc_set_tx_best_dly_factor(chn, rank, tx_perbyte_dly, - tx_dq_precal_result); + for (u8 byte = 0; byte < DQS_NUMBER; byte++) { + if (use_delay_cell == 0) { + center_dly[byte].final_dly = (center_dly[byte].min_center + + center_dly[byte].max_center) >> 1; + tx_dq_precal_result[byte] = center_dly[byte].final_dly; + } else { + center_dly[byte].final_dly = center_dly[byte].min_center; + tx_dq_precal_result[byte] = (center_dly[byte].min_center + + center_dly[byte].max_center) >> 1; + + for (u8 bit = 0; bit < DQS_BIT_NUMBER; bit++) { + index = bit + 8 * byte; + tune_diff = vref_dly[index].win_center - + center_dly[byte].min_center; + dq_delay_cell[index] = ((tune_diff * 100000000) / + (clock_rate / 2 * 64)) / dly_cell_unit; + byte_dly_cell[byte] |= (dq_delay_cell[index] << (bit * 4)); + } + } + } + + dramc_set_tx_best_dly_factor(chn, rank, type, center_dly, tx_dq_precal_result, + use_delay_cell, byte_dly_cell); } -static int dramc_set_rx_best_dly(u8 chn, u8 rank, - struct dqdqs_perbit_dly *rx_dly) +static int dramc_set_rx_best_dly(u8 chn, u8 rank, struct win_perbit_dly *perbit_dly) { - s16 dly; - bool fail = false; - u8 index, max_limit; - static u32 max_dqsdly_byte[DQS_NUMBER]; - static u32 ave_dqmdly_byte[DQS_NUMBER]; + u8 bit_first, bit_last; + u16 u2TmpDQMSum; + s32 dqsdly_byte[DQS_NUMBER] = {0x0}, dqm_dly_byte[DQS_NUMBER] = {0x0}; - for (size_t i = 0; i < DQS_NUMBER; i++) { - max_dqsdly_byte[i] = 0; - ave_dqmdly_byte[i] = 0; - } + for (u8 byte = 0; byte < DQS_NUMBER; byte++) { + u2TmpDQMSum = 0; - for (size_t i = 0; i < DQ_DATA_WIDTH; i++) { - index = i / DQS_BIT_NUMBER; - fail |= dramc_calc_best_dly(i, &rx_dly[i], - &max_dqsdly_byte[index]); - } + bit_first = DQS_BIT_NUMBER * byte; + bit_last = DQS_BIT_NUMBER * byte + DQS_BIT_NUMBER - 1; + dqsdly_byte[byte] = 64; - for (size_t i = 0; i < DQ_DATA_WIDTH; i++) { - index = i / DQS_BIT_NUMBER; - /* Set DQS to max for 8-bit */ - if (rx_dly[i].dqsdly.best < max_dqsdly_byte[index]) { - /* Delay DQ to compensate extra DQS delay */ - dly = max_dqsdly_byte[index] - rx_dly[i].dqsdly.best; - rx_dly[i].dqdly.best += dly; - max_limit = MAX_DQDLY_TAPS - 1; - if (rx_dly[i].dqdly.best > max_limit) - rx_dly[i].dqdly.best = max_limit; + for (u8 bit = bit_first; bit <= bit_last; bit++) { + if (perbit_dly[bit].win_center < dqsdly_byte[byte]) + dqsdly_byte[byte] = perbit_dly[bit].win_center; + } + dqsdly_byte[byte] = (dqsdly_byte[byte] > 0) ? 0 : -dqsdly_byte[byte]; + + for (u8 bit = bit_first; bit <= bit_last; bit++) { + perbit_dly[bit].best_dqdly = dqsdly_byte[byte] + + perbit_dly[bit].win_center; + u2TmpDQMSum += perbit_dly[bit].best_dqdly; } - ave_dqmdly_byte[index] += rx_dly[i].dqdly.best; - if ((i + 1) % DQS_BIT_NUMBER == 0) - ave_dqmdly_byte[index] /= DQS_BIT_NUMBER; + dqm_dly_byte[byte] = u2TmpDQMSum / DQS_BIT_NUMBER; } - if (fail) { - dramc_dbg("Fail on perbit_window_cal()\n"); - return -1; - } - - dramc_set_rx_best_dly_factor(chn, rank, rx_dly, max_dqsdly_byte, - ave_dqmdly_byte); + dramc_set_rx_best_dly_factor(chn, rank, perbit_dly, dqsdly_byte, dqm_dly_byte); return 0; } -static void dramc_get_vref_prop(u8 rank, enum CAL_TYPE type, +static void dramc_get_vref_prop(u8 rank, enum CAL_TYPE type, u8 fsp, u8 *vref_scan_en, u8 *vref_begin, u8 *vref_end) { if (type == RX_WIN_TEST_ENG && rank == RANK_0) { *vref_scan_en = 1; - *vref_begin = RX_VREF_BEGIN; - *vref_end = RX_VREF_END; + if (fsp == FSP_0) + *vref_begin = 0x18; + else + *vref_begin = 0; + *vref_end = RX_VREF_END; } else if (type == TX_WIN_DQ_ONLY) { *vref_scan_en = 1; - *vref_begin = TX_VREF_BEGIN; - *vref_end = TX_VREF_END; + if (fsp == FSP_0) { + *vref_begin = 27 - 5; + *vref_end = 27 + 5; + } else { + *vref_begin = TX_VREF_BEGIN; + *vref_end = TX_VREF_END; + } } else { *vref_scan_en = 0; + *vref_begin = 0; + *vref_end = 1; } } -static void dramc_engine2_setpat(u8 chn, bool test_pat) -{ - clrbits_le32(&ch[chn].ao.test2_4, - (0x1 << TEST2_4_TESTXTALKPAT_SHIFT) | - (0x1 << TEST2_4_TESTAUDMODE_SHIFT) | - (0x1 << TEST2_4_TESTAUDBITINV_SHIFT)); - - if (!test_pat) { - setbits_le32(&ch[chn].ao.perfctl0, 1 << PERFCTL0_RWOFOEN_SHIFT); - - clrbits_le32(&ch[chn].ao.test2_4, - (0x1 << TEST2_4_TEST_REQ_LEN1_SHIFT) | - (0x1 << TEST2_4_TESTSSOPAT_SHIFT) | - (0x1 << TEST2_4_TESTSSOXTALKPAT_SHIFT) | - (0x1 << TEST2_4_TESTXTALKPAT_SHIFT)); - } else { - clrsetbits_le32(&ch[chn].ao.test2_4, - TEST2_4_TESTAUDINIT_MASK | TEST2_4_TESTAUDINC_MASK, - (0x11 << 8) | (0xd << 0) | (0x1 << 14)); - } - clrsetbits_le32(&ch[chn].ao.test2_3, - (0x1 << TEST2_3_TESTAUDPAT_SHIFT) | TEST2_3_TESTCNT_MASK, - (test_pat ? 1 : 0) << TEST2_3_TESTAUDPAT_SHIFT); -} - static u32 dram_k_perbit(u8 chn, enum CAL_TYPE type) { u32 err_value; if (type == RX_WIN_RD_DQC) { - err_value = dramc_rd_dqc_run(chn); + err_value = dramc_rx_rd_dqc_run(chn); + } else if (type == RX_WIN_TEST_ENG) { + err_value = dramc_engine2_run(chn, TE_OP_WRITE_READ_CHECK); } else { dramc_engine2_setpat(chn, true); err_value = dramc_engine2_run(chn, TE_OP_WRITE_READ_CHECK); @@ -1533,149 +1697,146 @@ static u32 dram_k_perbit(u8 chn, enum CAL_TYPE type) return err_value; } -static u8 dramc_window_perbit_cal(u8 chn, u8 rank, +static u8 dramc_window_perbit_cal(u8 chn, u8 rank, u8 freq_group, enum CAL_TYPE type, const struct sdram_params *params) { - u8 vref = 0, vref_begin = 0, vref_end = 1, vref_step = 1; - u8 dly_step = 2, vref_scan_enable = 0; - s16 dly, dly_begin = 0, dly_end = 0, last_step; - s16 dly_pass; - u32 dummy_rd_backup = 0, err_value, finish_bit; + u8 vref = 0, vref_begin = 0, vref_end = 1, vref_step = 1, vref_use = 0; + u8 vref_scan_enable = 0, small_reg_value = 0xff; + s16 dly, dly_begin = 0, dly_end = 0, dly_step = 1; + u32 dummy_rd_bak_engine2 = 0, err_value, finish_bit, win_min_max = 0; static u16 dq_precal_result[DQS_NUMBER]; - static struct vref_perbit_dly vref_dly; - struct dqdqs_perbit_dly dq_perbit_dly[DQ_DATA_WIDTH]; + struct vref_perbit_dly vref_dly; + struct win_perbit_dly win_perbit[DQ_DATA_WIDTH]; + u16 dly_cell_unit = params->delay_cell_unit; - dramc_get_vref_prop(rank, type, + u8 fsp = get_freq_fsq(freq_group); + u8 vref_range = !fsp; + + dramc_get_vref_prop(rank, type, fsp, &vref_scan_enable, &vref_begin, &vref_end); - if (vref_scan_enable && type == RX_WIN_RD_DQC) - dramc_rx_vref_enable(chn); + dramc_get_dly_range(chn, rank, type, freq_group, dq_precal_result, + &dly_begin, &dly_end, params); - dramc_dbg("[channel %d] [rank %d] type:%d, vref_enable:%d\n", - chn, rank, type, vref_scan_enable); + if ((type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) && fsp == FSP_0) + dly_step = 2; - if ((type == TX_WIN_DQ_ONLY) || (type == TX_WIN_DQ_DQM)) { - for (size_t i = 0; i < 2; i++) { - write32(&ch[chn].phy.shu[0].rk[rank].b[i].dq[0], 0); - clrbits_le32(&ch[chn].phy.shu[0].rk[rank].b[i].dq[1], + dramc_dbg("[channel %d] [rank %d] type:%d, vref_enable:%d, vref range[%d:%d]\n", + chn, rank, type, vref_scan_enable, vref_begin, vref_end); + + if (type == TX_WIN_DQ_ONLY || type == TX_WIN_DQ_DQM) { + for (size_t byte = 0; byte < 2; byte++) { + write32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[0], 0); + clrbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[1], 0xf); } - setbits_le32(&ch[chn].phy.misc_ctrl1, - 0x1 << MISC_CTRL1_R_DMAR_FINE_TUNE_DQ_SW_SHIFT); - setbits_le32(&ch[chn].ao.dqsoscr, - 0x1 << DQSOSCR_AR_COARSE_TUNE_DQ_SW_SHIFT); - vref_step = 2; + setbits_le32(&ch[chn].phy.misc_ctrl1, 0x1 << 7); + setbits_le32(&ch[chn].ao.dqsoscr, 0x1 << 7); + if (fsp == FSP_1) + vref_step = 2; } if (type == RX_WIN_RD_DQC) { - dramc_rd_dqc_init(chn, rank); + dramc_rx_rd_dqc_init(chn, rank); } else { - dummy_rd_backup = read32(&ch[chn].ao.dummy_rd); - dramc_engine2_init(chn, rank, 0x400, false); + if (type == RX_WIN_TEST_ENG) + dramc_rx_vref_pre_setting(chn); + dummy_rd_bak_engine2 = read32(&ch[chn].ao.dummy_rd); + dramc_engine2_init(chn, rank, TEST2_1_CAL, TEST2_2_CAL, false); } - vref_dly.max_win = 0; - vref_dly.min_win = 0xffff; + vref_dly.max_win_sum = 0; for (vref = vref_begin; vref < vref_end; vref += vref_step) { - vref_dly.vref = vref; + small_reg_value = 0xff; finish_bit = 0; - for (size_t i = 0; i < DQ_DATA_WIDTH; i++) { - dq_perbit_dly[i].dqdly.first = -1; - dq_perbit_dly[i].dqdly.last = -2; - dq_perbit_dly[i].dqsdly.first = -1; - dq_perbit_dly[i].dqsdly.last = -2; - dq_perbit_dly[i].dqdly.best_first = -1; - dq_perbit_dly[i].dqdly.best_last = -2; - dq_perbit_dly[i].dqsdly.best_first = -1; - dq_perbit_dly[i].dqsdly.best_last = -2; + if (type == TX_WIN_DQ_ONLY) + vref_use = vref | (vref_range << 6); + else + vref_use = vref; + + for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { + win_perbit[bit].first_pass = PASS_RANGE_NA; + win_perbit[bit].last_pass = PASS_RANGE_NA; + win_perbit[bit].best_first = PASS_RANGE_NA; + win_perbit[bit].best_last = PASS_RANGE_NA; } if (vref_scan_enable) - dramc_set_vref(chn, rank, type, vref_dly.vref); + dramc_set_vref(chn, rank, type, vref_use); - if ((type == RX_WIN_RD_DQC) || (type == RX_WIN_TEST_ENG)) { + if (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) { dramc_set_rx_dly_factor(chn, rank, RX_DQM, FIRST_DQ_DELAY); dramc_set_rx_dly_factor(chn, rank, RX_DQ, FIRST_DQ_DELAY); } - dramc_get_dly_range(chn, rank, type, dq_precal_result, - &dly_begin, &dly_end, params); for (dly = dly_begin; dly < dly_end; dly += dly_step) { - dramc_set_dqdqs_dly(chn, rank, type, dly); + dramc_set_dqdqs_dly(chn, rank, type, &small_reg_value, dly); + err_value = dram_k_perbit(chn, type); - finish_bit = 0; if (!vref_scan_enable) dramc_dbg("%d ", dly); for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { - bool flag; - bool fail = (err_value & ((u32) 1 << bit)) != 0; + bool bit_fail = (err_value & ((u32) 1 << bit)) != 0; - if (dly < 0) { - dly_pass = -dly; - last_step = -FIRST_DQS_DELAY; - flag = false; - } else { - dly_pass = dly; - last_step = dly_end; - flag = true; - } - - /* pass window bigger than 7, - consider as real pass window */ - if (dramc_check_dqdqs_win(&(dq_perbit_dly[bit]), - dly_pass, last_step, - fail, flag) > 7) + /* pass window bigger than 7, consider as real pass window */ + if (dramc_check_dqdqs_win(&(win_perbit[bit]), + dly, dly_end, bit_fail) > 7) finish_bit |= (1 << bit); if (vref_scan_enable) continue; - dramc_dbg("%s", !fail ? "o" : "x"); + dramc_dbg("%s", bit_fail ? "x" : "o"); + if (bit % DQS_BIT_NUMBER == 7) + dramc_dbg(" "); } if (!vref_scan_enable) dramc_dbg(" [MSB]\n"); - if (finish_bit == ((1 << DQ_DATA_WIDTH) - 1)) { - dramc_dbg("all bits window found, break!\n"); + + if (finish_bit == 0xffff && (err_value & 0xffff) == 0xffff) { + dramc_dbg("all bits window found, early break! delay=0x%x\n", + dly); break; } } for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) - dramc_dbg("Dq[%zd] win(%d ~ %d)\n", bit, - dq_perbit_dly[bit].dqdly.best_first, - dq_perbit_dly[bit].dqdly.best_last); + dramc_dbg("Dq[%zd] win width (%d ~ %d) %d\n", bit, + win_perbit[bit].best_first, win_perbit[bit].best_last, + win_perbit[bit].best_last - win_perbit[bit].best_first); - if (dramk_calc_best_vref(type, vref, &vref_dly, dq_perbit_dly)) + if (dramk_calc_best_vref(type, vref_use, &vref_dly, win_perbit, &win_min_max)) break; - - if (finish_bit == ((1 << DQ_DATA_WIDTH) - 1)) { - dramc_dbg("all bits window found, break!\n"); - break; - } } if (type == RX_WIN_RD_DQC) { - dramc_rd_dqc_end(chn); + dramc_rx_rd_dqc_end(chn); } else { dramc_engine2_end(chn); - write32(&ch[chn].ao.dummy_rd, dummy_rd_backup); + write32(&ch[chn].ao.dummy_rd, dummy_rd_bak_engine2); } - if (vref_scan_enable) - dramc_set_vref(chn, rank, type, vref_dly.vref); + if (vref_scan_enable && type == RX_WIN_TEST_ENG) + dramc_set_vref(chn, rank, type, vref_dly.best_vref); - if ((type == RX_WIN_RD_DQC) || (type == RX_WIN_TEST_ENG)) + if (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) dramc_set_rx_best_dly(chn, rank, vref_dly.perbit_dly); else - dramc_set_tx_best_dly(chn, rank, vref_dly.perbit_dly, - dq_precal_result, params); + dramc_set_tx_best_dly(chn, rank, false, vref_dly.perbit_dly, type, + freq_group, dq_precal_result, dly_cell_unit, params); + + if (vref_scan_enable && type == TX_WIN_DQ_ONLY) + dramc_set_vref(chn, rank, type, vref_dly.best_vref); + return 0; } -static void dramc_dle_factor_handler(u8 chn, u8 val) +static void dramc_dle_factor_handler(u8 chn, u8 val, u8 freq_group) { + u8 start_ext2 = 0, start_ext3 = 0, last_ext2 = 0, last_ext3 = 0; + val = MAX(val, 2); clrsetbits_le32(&ch[chn].ao.shu[0].conf[1], SHU_CONF1_DATLAT_MASK | SHU_CONF1_DATLAT_DSEL_MASK | @@ -1683,94 +1844,106 @@ static void dramc_dle_factor_handler(u8 chn, u8 val) (val << SHU_CONF1_DATLAT_SHIFT) | ((val - 2) << SHU_CONF1_DATLAT_DSEL_SHIFT) | ((val - 2) << SHU_CONF1_DATLAT_DSEL_PHY_SHIFT)); + + if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600) + start_ext2 = 1; + + if (val >= 24) + last_ext2 = last_ext3 = 1; + else if (val >= 18) + last_ext2 = 1; + + clrsetbits_le32(&ch[chn].ao.shu[0].pipe, (0x1 << 31) | (0x1 << 30) | (0x1 << 29) | + (0x1 << 28) | (0x1 << 27) | (0x1 << 26), + (0x1 << 31) | (0x1 << 30) | (start_ext2 << 29) | + (last_ext2 << 28) | (start_ext3 << 27) | (last_ext3 << 26)); dram_phy_reset(chn); } -static u8 dramc_rx_datlat_cal(u8 chn, u8 rank) +static u8 dramc_rx_datlat_cal(u8 chn, u8 rank, u8 freq_group, const struct sdram_params *params) { - s32 datlat, first = -1, sum = 0, best_step; + u32 datlat, begin = 0, first = 0, sum = 0, best_step; + u32 datlat_start = 7; best_step = read32(&ch[chn].ao.shu[0].conf[1]) & SHU_CONF1_DATLAT_MASK; - dramc_dbg("[DATLAT] start. CH%d RK%d DATLAT Default: %2x\n", - chn, rank, best_step); + dramc_dbg("[DATLAT] start. CH%d RK%d DATLAT Default: 0x%x\n", + chn, rank, best_step); u32 dummy_rd_backup = read32(&ch[chn].ao.dummy_rd); - dramc_engine2_init(chn, rank, 0x400, false); + dramc_engine2_init(chn, rank, TEST2_1_CAL, TEST2_2_CAL, false); - for (datlat = 12; datlat < DATLAT_TAP_NUMBER; datlat++) { - dramc_dle_factor_handler(chn, datlat); + for (datlat = datlat_start; datlat < DATLAT_TAP_NUMBER; datlat++) { + dramc_dle_factor_handler(chn, datlat, freq_group); u32 err = dramc_engine2_run(chn, TE_OP_WRITE_READ_CHECK); - - if (err != 0 && first != -1) - break; - - if (sum >= 4) - break; - if (err == 0) { - if (first == -1) + if (begin == 0) { first = datlat; - sum++; + begin = 1; + } + if (begin == 1) { + sum++; + if (sum > 4) + break; + } + } else { + if (begin == 1) + begin = 0xff; } - dramc_dbg("Datlat=%2d, err_value=0x%8x, sum=%d\n", - datlat, err, sum); + dramc_dbg("Datlat=%2d, err_value=0x%4x, sum=%d\n", datlat, err, sum); } dramc_engine2_end(chn); write32(&ch[chn].ao.dummy_rd, dummy_rd_backup); - best_step = first + (sum >> 1); - dramc_dbg("First_step=%d, total pass=%d, best_step=%d\n", - first, sum, best_step); - assert(sum != 0); - dramc_dle_factor_handler(chn, best_step); + if (sum <= 3) + best_step = first + (sum >> 1); + else + best_step = first + 2; + dramc_dbg("First_step=%d, total pass=%d, best_step=%d\n", + begin, sum, best_step); - clrsetbits_le32(&ch[chn].ao.padctrl, PADCTRL_DQIENQKEND_MASK, + dramc_dle_factor_handler(chn, best_step, freq_group); + + clrsetbits_le32(&ch[chn].ao.padctrl, 0x3 | (0x1 << 3), (0x1 << PADCTRL_DQIENQKEND_SHIFT) | (0x1 << PADCTRL_DQIENLATEBEGIN_SHIFT)); return (u8) best_step; } -static void dramc_dual_rank_rx_datlat_cal(u8 chn, u8 datlat0, u8 datlat1) +static void dramc_dual_rank_rx_datlat_cal(u8 chn, u8 freq_group, u8 datlat0, u8 datlat1) { u8 final_datlat = MAX(datlat0, datlat1); - dramc_dle_factor_handler(chn, final_datlat); + dramc_dle_factor_handler(chn, final_datlat, freq_group); } -static void dramc_rx_dqs_gating_post_process(u8 chn) +static void dramc_rx_dqs_gating_post_process(u8 chn, u8 freq_group) { - u8 rank_rx_dvs, dqsinctl; - u32 read_dqsinctl, rankinctl_root, xrtr2r, reg_tx_dly_dqsgated_min = 3; + s8 dqsinctl; + u32 read_dqsinctl, rankinctl_root, reg_tx_dly_dqsgated_min = 3; u8 txdly_cal_min = 0xff, txdly_cal_max = 0, tx_dly_dqs_gated = 0; u32 best_coarse_tune2t[RANK_MAX][DQS_NUMBER]; u32 best_coarse_tune2t_p1[RANK_MAX][DQS_NUMBER]; - rank_rx_dvs = reg_tx_dly_dqsgated_min - 1; - - for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dq[7], - SHU1_BX_DQ7_R_DMRANKRXDVS_MASK, - rank_rx_dvs << SHU1_BX_DQ7_R_DMRANKRXDVS_SHIFT); + if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600) + reg_tx_dly_dqsgated_min = 2; + else + reg_tx_dly_dqsgated_min = 1; + /* get TXDLY_Cal_min and TXDLY_Cal_max value */ for (size_t rank = 0; rank < RANK_MAX; rank++) { u32 dqsg0 = read32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0); for (size_t dqs = 0; dqs < DQS_NUMBER; dqs++) { - best_coarse_tune2t[rank][dqs] = - (dqsg0 >> (dqs * 8)) & - SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_MASK; - best_coarse_tune2t_p1[rank][dqs] = - ((dqsg0 >> (dqs * 8)) & - SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_MASK) >> - SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_SHIFT; + best_coarse_tune2t[rank][dqs] = (dqsg0 >> (dqs * 8)) & 0x7; + best_coarse_tune2t_p1[rank][dqs] = (dqsg0 >> (dqs * 8 + 4)) & 0x7; dramc_dbg("Rank%zd best DQS%zd dly(2T,(P1)2T)=(%d, %d)\n", - rank, dqs, best_coarse_tune2t[rank][dqs], - best_coarse_tune2t_p1[rank][dqs]); + rank, dqs, best_coarse_tune2t[rank][dqs], + best_coarse_tune2t_p1[rank][dqs]); tx_dly_dqs_gated = best_coarse_tune2t[rank][dqs]; txdly_cal_min = MIN(txdly_cal_min, tx_dly_dqs_gated); @@ -1781,8 +1954,8 @@ static void dramc_rx_dqs_gating_post_process(u8 chn) } dqsinctl = reg_tx_dly_dqsgated_min - txdly_cal_min; - dramc_dbg("Dqsinctl:%d, tx_dly_dqsgated_min %d, txdly_cal_min %d\n", - dqsinctl, reg_tx_dly_dqsgated_min, txdly_cal_min); + dramc_dbg("Dqsinctl:%d, dqsgated_min %d, txdly_cal_min %d, txdly_cal_max %d\n", + dqsinctl, reg_tx_dly_dqsgated_min, txdly_cal_min, txdly_cal_max); if (dqsinctl != 0) { txdly_cal_min += dqsinctl; @@ -1795,13 +1968,13 @@ static void dramc_rx_dqs_gating_post_process(u8 chn) best_coarse_tune2t_p1[rank][dqs] += dqsinctl; dramc_dbg("Best DQS%zd dly(2T) = (%d)\n", - dqs, best_coarse_tune2t[rank][dqs]); + dqs, best_coarse_tune2t[rank][dqs]); dramc_dbg("Best DQS%zd P1 dly(2T) = (%d)\n", - dqs, - best_coarse_tune2t_p1[rank][dqs]); + dqs, best_coarse_tune2t_p1[rank][dqs]); } - write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, + 0x77777777, (best_coarse_tune2t[rank][0] << 0) | (best_coarse_tune2t[rank][1] << 8) | (best_coarse_tune2t_p1[rank][0] << 4) | @@ -1811,51 +1984,39 @@ static void dramc_rx_dqs_gating_post_process(u8 chn) read_dqsinctl = (read32(&ch[chn].ao.shu[0].rk[0].dqsctl) & SHURK_DQSCTL_DQSINCTL_MASK) - dqsinctl; - rankinctl_root = (read_dqsinctl >= 3) ? (read_dqsinctl - 3) : 0; + rankinctl_root = (read_dqsinctl >= 2) ? (read_dqsinctl - 2) : 0; - clrsetbits_le32(&ch[chn].ao.shu[0].rk[0].dqsctl, - SHURK_DQSCTL_DQSINCTL_MASK, - read_dqsinctl << SHURK_DQSCTL_DQSINCTL_SHIFT); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[1].dqsctl, - SHURK_DQSCTL_DQSINCTL_MASK, - read_dqsinctl << SHURK_DQSCTL_DQSINCTL_SHIFT); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[0].dqsctl, 0xf, read_dqsinctl << 0); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[1].dqsctl, 0xf, read_dqsinctl << 0); clrsetbits_le32(&ch[chn].ao.shu[0].rankctl, - SHU_RANKCTL_RANKINCTL_PHY_MASK | - SHU_RANKCTL_RANKINCTL_MASK | SHU_RANKCTL_RANKINCTL_ROOT1_MASK, - (read_dqsinctl << SHU_RANKCTL_RANKINCTL_PHY_SHIFT) | - (rankinctl_root << SHU_RANKCTL_RANKINCTL_SHIFT) | - (rankinctl_root << SHU_RANKCTL_RANKINCTL_ROOT1_SHIFT)); + (0xf << 28) | (0xf << 20) | (0xf << 24) | 0xf, + (read_dqsinctl << 28) | (rankinctl_root << 20) | + (rankinctl_root << 24) | rankinctl_root); - xrtr2r = MIN(8 + txdly_cal_max + 1, 12); - clrsetbits_le32(&ch[chn].ao.shu[0].actim_xrt, - SHU_ACTIM_XRT_XRTR2R_MASK, - xrtr2r << SHU_ACTIM_XRT_XRTR2R_SHIFT); - - dramc_dbg("Tx_dly_DQS gated check: min %d max %d, changeDQSINCTL=%d," - " DQSINCTL=%d, RANKINCTL=%d, XRTR2R=%d\n", - txdly_cal_min, txdly_cal_max, dqsinctl, - read_dqsinctl, rankinctl_root, xrtr2r); + u8 ROEN = read32(&ch[chn].ao.shu[0].odtctrl) & 0x1; + clrsetbits_le32(&ch[chn].ao.shu[0].rodtenstb, (0xffff << 8) | (0x3f << 2) | (0x1), + (0xff << 8) | (0x9 << 2) | ROEN); } -void dramc_calibrate_all_channels(const struct sdram_params *pams) +void dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group) { u8 rx_datlat[RANK_MAX] = {0}; for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { dramc_show("Start K ch:%d, rank:%d\n", chn, rk); dramc_auto_refresh_switch(chn, false); - dramc_cmd_bus_training(chn, rk, pams); - dramc_write_leveling(chn, rk, pams->wr_level); + dramc_cmd_bus_training(chn, rk, freq_group, pams); + dramc_write_leveling(chn, rk, freq_group, pams->wr_level); dramc_auto_refresh_switch(chn, true); - dramc_rx_dqs_gating_cal(chn, rk); - dramc_window_perbit_cal(chn, rk, RX_WIN_RD_DQC, pams); - dramc_window_perbit_cal(chn, rk, TX_WIN_DQ_DQM, pams); - dramc_window_perbit_cal(chn, rk, TX_WIN_DQ_ONLY, pams); - rx_datlat[rk] = dramc_rx_datlat_cal(chn, rk); - dramc_window_perbit_cal(chn, rk, RX_WIN_TEST_ENG, pams); + dramc_rx_dqs_gating_cal(chn, rk, freq_group, pams); + dramc_window_perbit_cal(chn, rk, freq_group, RX_WIN_RD_DQC, pams); + dramc_window_perbit_cal(chn, rk, freq_group, TX_WIN_DQ_DQM, pams); + dramc_window_perbit_cal(chn, rk, freq_group, TX_WIN_DQ_ONLY, pams); + rx_datlat[rk] = dramc_rx_datlat_cal(chn, rk, freq_group, pams); + dramc_window_perbit_cal(chn, rk, freq_group, RX_WIN_TEST_ENG, pams); } - dramc_rx_dqs_gating_post_process(chn); - dramc_dual_rank_rx_datlat_cal(chn, rx_datlat[0], rx_datlat[1]); + dramc_rx_dqs_gating_post_process(chn, freq_group); + dramc_dual_rank_rx_datlat_cal(chn, freq_group, rx_datlat[0], rx_datlat[1]); } } diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c new file mode 100644 index 0000000000..daa06caeae --- /dev/null +++ b/src/soc/mediatek/mt8183/dsi.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes) +{ + unsigned int txdiv, txdiv0, txdiv1; + u64 pcw; + + if (data_rate >= 2000) { + txdiv = 1; + txdiv0 = 0; + txdiv1 = 0; + } else if (data_rate >= 1000) { + txdiv = 2; + txdiv0 = 1; + txdiv1 = 0; + } else if (data_rate >= 500) { + txdiv = 4; + txdiv0 = 2; + txdiv1 = 0; + } else if (data_rate > 250) { + /* Be aware that 250 is a special case that must use txdiv=4. */ + txdiv = 8; + txdiv0 = 3; + txdiv1 = 0; + } else { + /* MIN = 125 */ + assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ); + txdiv = 16; + txdiv0 = 4; + txdiv1 = 0; + } + + clrbits_le32(&mipi_tx->pll_con4, BIT(11) | BIT(10)); + setbits_le32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_PWR_ON); + udelay(30); + clrbits_le32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_ISO_EN); + + pcw = (u64)data_rate * (1 << txdiv0) * (1 << txdiv1); + pcw <<= 24; + pcw /= CLK26M_HZ / MHz; + + write32(&mipi_tx->pll_con0, pcw); + clrsetbits_le32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8); + udelay(30); + setbits_le32(&mipi_tx->pll_con1, RG_DSI_PLL_EN); + + /* BG_LPF_EN / BG_CORE_EN */ + write32(&mipi_tx->lane_con, 0x3fff0180); + udelay(40); + write32(&mipi_tx->lane_con, 0x3fff00c0); + + /* Switch OFF each Lane */ + clrbits_le32(&mipi_tx->d0_sw_ctl_en, DSI_SW_CTL_EN); + clrbits_le32(&mipi_tx->d1_sw_ctl_en, DSI_SW_CTL_EN); + clrbits_le32(&mipi_tx->d2_sw_ctl_en, DSI_SW_CTL_EN); + clrbits_le32(&mipi_tx->d3_sw_ctl_en, DSI_SW_CTL_EN); + clrbits_le32(&mipi_tx->ck_sw_ctl_en, DSI_SW_CTL_EN); + + setbits_le32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN); +} + +void mtk_dsi_reset(void) +{ + write32(&dsi0->dsi_force_commit, + DSI_FORCE_COMMIT_USE_MMSYS | DSI_FORCE_COMMIT_ALWAYS); + write32(&dsi0->dsi_con_ctrl, 1); + write32(&dsi0->dsi_con_ctrl, 0); +} diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 937d06de37..8bd8a39a35 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -19,6 +19,25 @@ #include #include +static const u8 freq_shuffle[DRAM_DFS_SHUFFLE_MAX] = { + [DRAM_DFS_SHUFFLE_1] = LP4X_DDR3200, + [DRAM_DFS_SHUFFLE_2] = LP4X_DDR2400, + [DRAM_DFS_SHUFFLE_3] = LP4X_DDR1600, +}; + +static const u8 freq_shuffle_emcp[DRAM_DFS_SHUFFLE_MAX] = { + [DRAM_DFS_SHUFFLE_1] = LP4X_DDR3600, + [DRAM_DFS_SHUFFLE_2] = LP4X_DDR3200, + [DRAM_DFS_SHUFFLE_3] = LP4X_DDR1600, +}; + +u32 frequency_table[LP4X_DDRFREQ_MAX] = { + [LP4X_DDR1600] = 1600, + [LP4X_DDR2400] = 2400, + [LP4X_DDR3200] = 3200, + [LP4X_DDR3600] = 3600, +}; + struct emi_regs *emi_regs = (void *)EMI_BASE; const u8 phy_mapping[CHANNEL_MAX][16] = { [CHANNEL_A] = { @@ -32,6 +51,12 @@ const u8 phy_mapping[CHANNEL_MAX][16] = { } }; +struct optimize_ac_time { + u8 rfc; + u8 rfc_05t; + u16 tx_ref_cnt; +}; + void dramc_set_broadcast(u32 onoff) { write32(&mt8183_infracfg->dramc_wbr, onoff); @@ -268,27 +293,42 @@ static void dramc_init_pre_settings(void) setbits_le32(&ch[0].phy.misc_ctrl1, 0x1 << 31); } -static void dramc_ac_timing_optimize(void) +static void dramc_ac_timing_optimize(u8 freq_group) { + struct optimize_ac_time rf_cab_opt[LP4X_DDRFREQ_MAX] = { + [LP4X_DDR1600] = {.rfc = 44, .rfc_05t = 0, .tx_ref_cnt = 62}, + [LP4X_DDR2400] = {.rfc = 44, .rfc_05t = 0, .tx_ref_cnt = 62}, + [LP4X_DDR3200] = {.rfc = 100, .rfc_05t = 0, .tx_ref_cnt = 119}, + [LP4X_DDR3600] = {.rfc = 118, .rfc_05t = 1, .tx_ref_cnt = 138}, + }; + for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { clrsetbits_le32(&ch[chn].ao.shu[0].actim[3], - 0xff << 16, 0x64 << 16); - clrbits_le32(&ch[chn].ao.shu[0].ac_time_05t, 0x1 << 2); + 0xff << 16, rf_cab_opt[freq_group].rfc << 16); + clrbits_le32(&ch[chn].ao.shu[0].ac_time_05t, + rf_cab_opt[freq_group].rfc_05t << 2); clrsetbits_le32(&ch[chn].ao.shu[0].actim[4], - 0x3ff << 0, 0x77 << 0); + 0x3ff << 0, rf_cab_opt[freq_group].tx_ref_cnt << 0); } } -static void init_dram(const struct sdram_params *params) +static void dfs_init_for_calibration(const struct sdram_params *params, u8 freq_group) +{ + dramc_init(params, freq_group); + dramc_apply_config_before_calibration(freq_group); +} + +static void init_dram(const struct sdram_params *params, u8 freq_group) { global_option_init(params); emi_init(params); dramc_set_broadcast(DRAMC_BROADCAST_ON); dramc_init_pre_settings(); - dramc_sw_impedance(params); + dramc_sw_impedance_cal(params, ODT_OFF); + dramc_sw_impedance_cal(params, ODT_ON); - dramc_init(); + dfs_init_for_calibration(params, freq_group); emi_init2(params); } @@ -301,17 +341,32 @@ void enable_emi_dcm(void) clrbits_le32(&ch[chn].emi.chn_conb, 0xff << 24); } -static void do_calib(const struct sdram_params *params) +static void do_calib(const struct sdram_params *params, u8 freq_group) +{ + dramc_show("Start K freq group:%d\n", frequency_table[freq_group]); + dramc_calibrate_all_channels(params, freq_group); + dramc_ac_timing_optimize(freq_group); + dramc_show("%s K freq group:%d finish!\n", __func__, frequency_table[freq_group]); +} + +static void after_calib(void) { - dramc_apply_config_before_calibration(); - dramc_calibrate_all_channels(params); - dramc_ac_timing_optimize(); dramc_apply_config_after_calibration(); dramc_runtime_config(); } void mt_set_emi(const struct sdram_params *params) { - init_dram(params); - do_calib(params); + const u8 *freq_tbl; + u8 current_freqsel; + + if (CONFIG(MT8183_DRAM_EMCP)) + freq_tbl = freq_shuffle_emcp; + else + freq_tbl = freq_shuffle; + current_freqsel = freq_tbl[DRAM_DFS_SHUFFLE_1]; + + init_dram(params, current_freqsel); + do_calib(params, current_freqsel); + after_calib(); } diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index bb44f9bb45..c267a1473e 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -51,6 +51,7 @@ enum { IOCFG_RT_BASE = IO_PHYS + 0x01C50000, IOCFG_RM_BASE = IO_PHYS + 0x01D20000, IOCFG_RB_BASE = IO_PHYS + 0x01D30000, + MIPITX_BASE = IO_PHYS + 0x01E50000, IOCFG_LB_BASE = IO_PHYS + 0x01E70000, IOCFG_LM_BASE = IO_PHYS + 0x01E80000, IOCFG_BL_BASE = IO_PHYS + 0x01E90000, @@ -69,6 +70,7 @@ enum { DISP_AAL0_BASE = IO_PHYS + 0x04010000, DISP_GAMMA0_BASE = IO_PHYS + 0x04011000, DISP_DITHER0_BASE = IO_PHYS + 0x04012000, + DSI0_BASE = IO_PHYS + 0x04014000, DISP_MUTEX_BASE = IO_PHYS + 0x04016000, SMI_LARB0 = IO_PHYS + 0x04017000, SMI_BASE = IO_PHYS + 0x04019000, diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h index e699e80f8b..ef6eaf162c 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h @@ -16,7 +16,12 @@ #ifndef _DRAMC_COMMON_MT8183_H_ #define _DRAMC_COMMON_MT8183_H_ -#define DRAM_DFS_SHUFFLE_MAX 3 +enum { + DRAM_DFS_SHUFFLE_1 = 0, + DRAM_DFS_SHUFFLE_2, + DRAM_DFS_SHUFFLE_3, + DRAM_DFS_SHUFFLE_MAX +}; enum { CHANNEL_A = 0, diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index 23b5cf032c..1ce5f67470 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -50,16 +50,6 @@ enum { }; enum { - TX_DQ_DQS_MOVE_DQ_ONLY = 0, - TX_DQ_DQS_MOVE_DQM_ONLY, - TX_DQ_DQS_MOVE_DQ_DQM -}; - -enum { - MAX_CA_FINE_TUNE_DELAY = 63, - MAX_CS_FINE_TUNE_DELAY = 63, - MAX_CLK_FINE_TUNE_DELAY = 31, - CATRAINING_NUM = 6, PASS_RANGE_NA = 0x7fff }; @@ -76,17 +66,15 @@ enum { enum { DQS_GW_COARSE_STEP = 1, - DQS_GW_FINE_START = 0, DQS_GW_FINE_END = 32, DQS_GW_FINE_STEP = 4, - DQS_GW_FREQ_DIV = 4, RX_DQS_CTL_LOOP = 8, RX_DLY_DQSIENSTB_LOOP = 32 }; enum { - SAVE_VALUE, - RESTORE_VALUE + DLL_MASTER = 0, + DLL_SLAVE, }; struct reg_value { @@ -94,39 +82,39 @@ struct reg_value { u32 value; }; +#define _SELPH_DQS_BITS(l, h) ((l << 0) | (l << 4) | (l << 8) | (l << 12) | \ + (h << 16) | (h << 20) | (h << 24) | (h << 28)) + enum { DQ_DIV_SHIFT = 3, DQ_DIV_MASK = BIT(DQ_DIV_SHIFT) - 1, OEN_SHIFT = 16, - DQS_DELAY_2T = 3, - DQS_DELAY_0P5T = 4, - DQS_DELAY = ((DQS_DELAY_2T << DQ_DIV_SHIFT) + DQS_DELAY_0P5T) << 5, - - DQS_OEN_DELAY_2T = 3, - DQS_OEN_DELAY_0P5T = 1, - - SELPH_DQS0 = (DQS_DELAY_2T << 0) | (DQS_DELAY_2T << 4) | - (DQS_DELAY_2T << 8) | (DQS_DELAY_2T << 12) | - (DQS_OEN_DELAY_2T << 16) | (DQS_OEN_DELAY_2T << 20) | - (DQS_OEN_DELAY_2T << 24) | (DQS_OEN_DELAY_2T << 28), - - SELPH_DQS1 = (DQS_DELAY_0P5T << 0) | (DQS_DELAY_0P5T << 4) | - (DQS_DELAY_0P5T << 8) | (DQS_DELAY_0P5T << 12) | - (DQS_OEN_DELAY_0P5T << 16) | (DQS_OEN_DELAY_0P5T << 20) | - (DQS_OEN_DELAY_0P5T << 24) | (DQS_OEN_DELAY_0P5T << 28) + SELPH_DQS0 = _SELPH_DQS_BITS(0x3, 0x3), + SELPH_DQS1 = _SELPH_DQS_BITS(0x4, 0x1), + SELPH_DQS0_1600 = _SELPH_DQS_BITS(0x2, 0x1), + SELPH_DQS1_1600 = _SELPH_DQS_BITS(0x1, 0x6), + SELPH_DQS0_2400 = _SELPH_DQS_BITS(0x3, 0x2), + SELPH_DQS1_2400 = _SELPH_DQS_BITS(0x1, 0x6), + SELPH_DQS0_3600 = _SELPH_DQS_BITS(0x4, 0x3), + SELPH_DQS1_3600 = _SELPH_DQS_BITS(0x1, 0x6), }; void dramc_get_rank_size(u64 *dram_rank_size); void dramc_runtime_config(void); void dramc_set_broadcast(u32 onoff); u32 dramc_get_broadcast(void); -void dramc_init(void); -void dramc_sw_impedance(const struct sdram_params *params); -void dramc_apply_config_before_calibration(void); +u8 get_freq_fsq(u8 freq_group); +void dramc_init(const struct sdram_params *params, u8 freq_group); +void dramc_sw_impedance_save_reg(u8 freq_group); +void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term_option); +void dramc_apply_config_before_calibration(u8 freq_group); void dramc_apply_config_after_calibration(void); -void dramc_calibrate_all_channels(const struct sdram_params *params); +void dramc_calibrate_all_channels(const struct sdram_params *pams, + u8 freq_group); void dramc_hw_gating_onoff(u8 chn, bool onoff); void dramc_enable_phy_dcm(bool bEn); +void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value); +void dramc_cke_fix_onoff(u8 chn, bool fix_on, bool fix_off); #endif /* _DRAMC_PI_API_MT8183_H */ diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_register.h b/src/soc/mediatek/mt8183/include/soc/dramc_register.h index f0720a7272..fb8d7d78f9 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_register.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_register.h @@ -945,14 +945,11 @@ enum { }; enum { + MISC_STATUSA_SREF_STATE = 16, MISC_STATUSA_REFRESH_QUEUE_CNT_SHIFT = 24, MISC_STATUSA_REFRESH_QUEUE_CNT_MASK = 0x0f000000, }; -enum { - SPCMDRESP_RDDQC_RESPONSE_SHIFT = 7, -}; - enum { DDRCONF0_DM4TO1MODE_SHIFT = 22, DDRCONF0_RDATRST_SHIFT = 0, @@ -974,6 +971,8 @@ enum { }; enum { + MRS_MPCRK_SHIFT = 28, + MRS_MPCRK_MASK = 0x30000000, MRS_MRSRK_SHIFT = 24, MRS_MRSRK_MASK = 0x03000000, MRS_MRSMA_SHIFT = 8, @@ -986,6 +985,8 @@ enum { SPCMD_DQSGCNTRST_SHIFT = 9, SPCMD_DQSGCNTEN_SHIFT = 8, SPCMD_RDDQCEN_SHIFT = 7, + SPCMD_ZQLATEN_SHIFT = 6, + SPCMD_ZQCEN_SHIFT = 4, SPCMD_MRWEN_SHIFT = 0, }; diff --git a/src/soc/mediatek/mt8183/include/soc/dsi.h b/src/soc/mediatek/mt8183/include/soc/dsi.h new file mode 100644 index 0000000000..8813f94982 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/dsi.h @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_MT8183_DSI_H +#define SOC_MEDIATEK_MT8183_DSI_H + +#include + +/* DSI features */ +#define MTK_DSI_MIPI_RATIO_NUMERATOR 100 +#define MTK_DSI_MIPI_RATIO_DENOMINATOR 100 +#define MTK_DSI_DATA_RATE_MIN_MHZ 125 +#define MTK_DSI_HAVE_SIZE_CON 1 +#define PIXEL_STREAM_CUSTOM_HEADER 0xb + +/* MIPITX is SOC specific and cannot live in common. */ + +/* MIPITX_REG */ +struct mipi_tx_regs { + u32 reserved0[3]; + u32 lane_con; + u32 reserved1[6]; + u32 pll_pwr; + u32 pll_con0; + u32 pll_con1; + u32 pll_con2; + u32 pll_con3; + u32 pll_con4; + u32 reserved2[65]; + u32 d2_sw_ctl_en; + u32 reserved3[63]; + u32 d0_sw_ctl_en; + u32 reserved4[56]; + u32 ck_ckmode_en; + u32 reserved5[6]; + u32 ck_sw_ctl_en; + u32 reserved6[63]; + u32 d1_sw_ctl_en; + u32 reserved7[63]; + u32 d3_sw_ctl_en; +}; + +check_member(mipi_tx_regs, pll_con4, 0x3c); +check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544); +static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE; + +/* Register values */ +#define DSI_CK_CKMODE_EN BIT(0) +#define DSI_SW_CTL_EN BIT(0) +#define AD_DSI_PLL_SDM_PWR_ON BIT(0) +#define AD_DSI_PLL_SDM_ISO_EN BIT(1) + +#define RG_DSI_PLL_EN BIT(4) +#define RG_DSI_PLL_POSDIV (0x7 << 8) + +#endif diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index 2c04a50e9e..264d91869a 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -33,6 +33,14 @@ struct sdram_params { u16 delay_cell_unit; }; +enum { + LP4X_DDR1600, + LP4X_DDR2400, + LP4X_DDR3200, + LP4X_DDR3600, + LP4X_DDRFREQ_MAX, +}; + extern const u8 phy_mapping[CHANNEL_MAX][16]; int complex_mem_test(u8 *start, unsigned int len); diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld index 6a11a0ed8b..73c880afbf 100644 --- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld @@ -32,17 +32,16 @@ SECTIONS VBOOT2_TPM_LOG(0x00103000, 2K) PRERAM_CBMEM_CONSOLE(0x00103800, 14K) WATCHDOG_TOMBSTONE(0x00107000, 4) - PRERAM_CBFS_CACHE(0x00107004, 16K - 4) - TIMESTAMP(0x0010B000, 4K) - STACK(0x0010C000, 16K) - TTB(0x00110000, 28K) - DMA_COHERENT(0x00117000, 4K) + PRERAM_CBFS_CACHE(0x00107004, 48K - 4) + TIMESTAMP(0x00113000, 4K) + STACK(0x00114000, 16K) + TTB(0x00118000, 28K) + DMA_COHERENT(0x0011f000, 4K) SRAM_END(0x00120000) SRAM_L2C_START(0x00200000) - OVERLAP_DECOMPRESSOR_ROMSTAGE(0x000201000, 152K) - BOOTBLOCK(0x00227000, 89K) - VERSTAGE(0x0023E000, 114K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00201000, 188K) + BOOTBLOCK(0x00230000, 64K) SRAM_L2C_END(0x00280000) DRAM_START(0x40000000) diff --git a/src/soc/mediatek/mt8183/include/soc/mt6358.h b/src/soc/mediatek/mt8183/include/soc/mt6358.h index 277ee9aa35..19ab5e106e 100644 --- a/src/soc/mediatek/mt8183/include/soc/mt6358.h +++ b/src/soc/mediatek/mt8183/include/soc/mt6358.h @@ -40,5 +40,6 @@ struct pmic_setting { void mt6358_init(void); void pmic_set_power_hold(bool enable); void pmic_set_vsim2_cali(unsigned int vsim2_mv); +void pmic_init_scp_voltage(void); #endif /* __SOC_MEDIATEK_MT6358_H__ */ diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h index 5a61208eee..bf120e9387 100644 --- a/src/soc/mediatek/mt8183/include/soc/rtc.h +++ b/src/soc/mediatek/mt8183/include/soc/rtc.h @@ -147,6 +147,7 @@ enum { /* PMIC DCXO Register Definition */ enum { PMIC_RG_DCXO_CW00 = 0x0788, + PMIC_RG_DCXO_CW00_CLR = 0x078C, PMIC_RG_DCXO_CW02 = 0x0790, PMIC_RG_DCXO_CW07 = 0x079A, PMIC_RG_DCXO_CW09 = 0x079E, @@ -218,5 +219,6 @@ void rtc_bbpu_power_on(void); void rtc_osc_init(void); int rtc_init(u8 recover); void rtc_boot(void); +void mt6358_dcxo_disable_unused(void); #endif /* SOC_MEDIATEK_MT8183_RTC_H */ diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index 53d2a43803..fa928cbcf6 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -731,11 +731,40 @@ static struct pmic_setting lp_setting[] = { {0x1DA6, 0x0, 0x1, 3}, }; +static struct pmic_setting scp_setting[] = { + /* scp voltage initialization */ + /* [6:0]: RG_BUCK_VCORE_SSHUB_VOSEL */ + {0x14A6, 0x20, 0x7F, 0}, + /* [14:8]: RG_BUCK_VCORE_SSHUB_VOSEL_SLEEP */ + {0x14A6, 0x20, 0x7F, 8}, + /* [0:0]: RG_BUCK_VCORE_SSHUB_EN */ + {0x14A4, 0x1, 0x1, 0}, + /* [1:1]: RG_BUCK_VCORE_SSHUB_SLEEP_VOSEL_EN */ + {0x14A4, 0x0, 0x1, 1}, + /* [6:0]: RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL */ + {0x1BC6, 0x40, 0x7F, 0}, + /* [14:8]: RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SLEEP */ + {0x1BC6, 0x40, 0x7F, 8}, + /* [0:0]: RG_LDO_VSRAM_OTHERS_SSHUB_EN */ + {0x1BC4, 0x1, 0x1, 0}, + /* [1:1]: RG_LDO_VSRAM_OTHERS_SSHUB_SLEEP_VOSEL_EN */ + {0x1BC4, 0x0, 0x1, 1}, + /* [4:4]: RG_SRCVOLTEN_LP_EN */ + {0x134, 0x1, 0x1, 4}, +}; void pmic_set_power_hold(bool enable) { pwrap_write_field(PMIC_PWRHOLD, (enable) ? 1 : 0, 0x1, 0); } +void pmic_init_scp_voltage(void) +{ + for (size_t i = 0; i < ARRAY_SIZE(scp_setting); i++) + pwrap_write_field( + scp_setting[i].addr, scp_setting[i].val, + scp_setting[i].mask, scp_setting[i].shift); +} + void pmic_set_vsim2_cali(unsigned int vsim2_mv) { u16 vsim2_reg, cali_mv; diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index af30d1f90b..19b717cc82 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -177,7 +177,7 @@ static u16 rtc_eosc_cali(void) /* select 26M as target clock */ val = rtc_get_frequency_meter(middle, PMIC_FQMTR_CON0_FQM26M_CK, 0); - if ((val >= RTC_FQMTR_LOW_BASE) && (val <= RTC_FQMTR_HIGH_BASE)) + if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE) break; if (val > RTC_FQMTR_HIGH_BASE) right = middle; @@ -185,7 +185,7 @@ static u16 rtc_eosc_cali(void) left = middle; } - if ((val >= RTC_FQMTR_LOW_BASE) && (val <= RTC_FQMTR_HIGH_BASE)) + if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE) return middle; val = rtc_get_frequency_meter(left, PMIC_FQMTR_CON0_FQM26M_CK, 0); @@ -411,10 +411,9 @@ static void dcxo_init(void) rtc_write(PMIC_RG_DCXO_CW16, 0x9855); /* 26M enable control */ - /* Enable clock buffer XO_SOC */ - rtc_write(PMIC_RG_DCXO_CW00, 0x4005); + /* Enable clock buffer XO_SOC, XO_CEL */ + rtc_write(PMIC_RG_DCXO_CW00, 0x4805); rtc_write(PMIC_RG_DCXO_CW11, 0x8000); - rtc_write(PMIC_RG_DCXO_CW23, 0x0053); /* Load thermal coefficient */ rtc_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7); @@ -432,6 +431,14 @@ static void dcxo_init(void) mdelay(5); } +void mt6358_dcxo_disable_unused(void) +{ + /* Disable clock buffer XO_CEL */ + rtc_write(PMIC_RG_DCXO_CW00_CLR, 0x0800); + /* Mask bblpm */ + rtc_write(PMIC_RG_DCXO_CW23, 0x0053); +} + /* the rtc boot flow entry */ void rtc_boot(void) { diff --git a/src/soc/mediatek/mt8183/soc.c b/src/soc/mediatek/mt8183/soc.c index c9c2147cc8..21b2f811d6 100644 --- a/src/soc/mediatek/mt8183/soc.c +++ b/src/soc/mediatek/mt8183/soc.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -29,6 +30,7 @@ static void soc_init(struct device *dev) { mtk_mmu_disable_l2c_sram(); mtk_md_early_init(); + mt6358_dcxo_disable_unused(); sspm_init(); } diff --git a/src/soc/mediatek/mt8183/spi.c b/src/soc/mediatek/mt8183/spi.c index 982f6439ed..7672db7993 100644 --- a/src/soc/mediatek/mt8183/spi.c +++ b/src/soc/mediatek/mt8183/spi.c @@ -24,21 +24,27 @@ struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = { { .regs = (void *)SPI0_BASE, + .cs_gpio = GPIO(SPI_CSB), }, { .regs = (void *)SPI1_BASE, + .cs_gpio = GPIO(SPI1_CSB), }, { .regs = (void *)SPI2_BASE, + .cs_gpio = GPIO(EINT0), }, { .regs = (void *)SPI3_BASE, + .cs_gpio = GPIO(DPI_D9), }, { .regs = (void *)SPI4_BASE, + .cs_gpio = GPIO(DPI_D5), }, { .regs = (void *)SPI5_BASE, + .cs_gpio = GPIO(DPI_D1), } }; @@ -48,41 +54,42 @@ struct pad_func { }; #define PAD_FUNC(name, func) {PAD_##name##_ID, PAD_##name##_FUNC_##func} +#define PAD_FUNC_GPIO(name) {PAD_##name##_ID, 0} static const struct pad_func pad0_funcs[SPI_BUS_NUMBER][4] = { { PAD_FUNC(SPI_MI, SPI0_MI), - PAD_FUNC(SPI_CSB, SPI0_CSB), + PAD_FUNC_GPIO(SPI_CSB), PAD_FUNC(SPI_MO, SPI0_MO), PAD_FUNC(SPI_CLK, SPI0_CLK), }, { PAD_FUNC(SPI1_MI, SPI1_A_MI), - PAD_FUNC(SPI1_CSB, SPI1_A_CSB), + PAD_FUNC_GPIO(SPI1_CSB), PAD_FUNC(SPI1_MO, SPI1_A_MO), PAD_FUNC(SPI1_CLK, SPI1_A_CLK), }, { PAD_FUNC(KPCOL1, SPI2_MI), - PAD_FUNC(EINT0, SPI2_CSB), + PAD_FUNC_GPIO(EINT0), PAD_FUNC(EINT1, SPI2_MO), PAD_FUNC(EINT2, SPI2_CLK), }, { PAD_FUNC(DPI_D8, SPI3_MI), - PAD_FUNC(DPI_D9, SPI3_CSB), + PAD_FUNC_GPIO(DPI_D9), PAD_FUNC(DPI_D10, SPI3_MO), PAD_FUNC(DPI_D11, SPI3_CLK), }, { PAD_FUNC(DPI_D4, SPI4_MI), - PAD_FUNC(DPI_D5, SPI4_CSB), + PAD_FUNC_GPIO(DPI_D5), PAD_FUNC(DPI_D6, SPI4_MO), PAD_FUNC(DPI_D7, SPI4_CLK), }, { PAD_FUNC(DPI_D0, SPI5_MI), - PAD_FUNC(DPI_D1, SPI5_CSB), + PAD_FUNC_GPIO(DPI_D1), PAD_FUNC(DPI_D2, SPI5_MO), PAD_FUNC(DPI_D3, SPI5_CLK), } @@ -90,7 +97,7 @@ static const struct pad_func pad0_funcs[SPI_BUS_NUMBER][4] = { static const struct pad_func bus1_pad1_funcs[4] = { PAD_FUNC(EINT7, SPI1_B_MI), - PAD_FUNC(EINT8, SPI1_B_CSB), + PAD_FUNC_GPIO(EINT8), PAD_FUNC(EINT9, SPI1_B_MO), PAD_FUNC(EINT10, SPI1_B_CLK), }; diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h index a9061f8ce8..56332e433a 100644 --- a/src/soc/nvidia/tegra/dc.h +++ b/src/soc/nvidia/tegra/dc.h @@ -515,9 +515,7 @@ struct tegra_dc_mode { unsigned long READL(void *p); void WRITEL(unsigned long value, void *p); -#ifndef __PRE_RAM__ void display_startup(struct device *dev); -#endif void dp_init(void *_config); void dp_enable(void *_dp); unsigned int fb_base_mb(void); diff --git a/src/soc/nvidia/tegra124/dma.c b/src/soc/nvidia/tegra124/dma.c index 73d050f602..761bb6bce5 100644 --- a/src/soc/nvidia/tegra124/dma.c +++ b/src/soc/nvidia/tegra124/dma.c @@ -17,7 +17,7 @@ #include #include -#include +#include #include #include #include diff --git a/src/soc/nvidia/tegra124/include/soc/dma.h b/src/soc/nvidia/tegra124/include/soc/dma.h index 42c70275f5..3d6d209153 100644 --- a/src/soc/nvidia/tegra124/include/soc/dma.h +++ b/src/soc/nvidia/tegra124/include/soc/dma.h @@ -18,7 +18,7 @@ #ifndef __NVIDIA_TEGRA124_DMA_H__ #define __NVIDIA_TEGRA124_DMA_H__ -#include +#include #include /* diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 4bd0ab7d1a..2d6469cc3f 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c index c9514ac1fc..f5f72aff4b 100644 --- a/src/soc/nvidia/tegra124/uart.c +++ b/src/soc/nvidia/tegra124/uart.c @@ -128,7 +128,6 @@ void uart_tx_flush(int idx) tegra124_uart_tx_flush(uart_ptr); } -#ifndef __PRE_RAM__ void uart_fill_lb(void *data) { struct lb_serial serial; @@ -136,8 +135,9 @@ void uart_fill_lb(void *data) serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = get_uart_baudrate(); serial.regwidth = 4; + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } -#endif diff --git a/src/soc/nvidia/tegra210/arm_tf.c b/src/soc/nvidia/tegra210/arm_tf.c index 38bb8bfc9e..e0863d21e1 100644 --- a/src/soc/nvidia/tegra210/arm_tf.c +++ b/src/soc/nvidia/tegra210/arm_tf.c @@ -14,8 +14,8 @@ */ #include -#include #include +#include #include #include #include @@ -32,7 +32,7 @@ typedef struct bl31_plat_params { static bl31_plat_params_t t210_plat_params; -void *soc_get_bl31_plat_params(bl31_params_t *params) +void *soc_get_bl31_plat_params(void) { uintptr_t tz_base_mib; size_t tz_size_mib; diff --git a/src/soc/nvidia/tegra210/dma.c b/src/soc/nvidia/tegra210/dma.c index 03c5e6783e..75376d98f0 100644 --- a/src/soc/nvidia/tegra210/dma.c +++ b/src/soc/nvidia/tegra210/dma.c @@ -17,7 +17,7 @@ #include #include -#include +#include #include #include #include diff --git a/src/soc/nvidia/tegra210/include/soc/dma.h b/src/soc/nvidia/tegra210/include/soc/dma.h index 3cb94ce8d3..6d934191a4 100644 --- a/src/soc/nvidia/tegra210/include/soc/dma.h +++ b/src/soc/nvidia/tegra210/include/soc/dma.h @@ -17,7 +17,7 @@ #ifndef __NVIDIA_TEGRA210_DMA_H__ #define __NVIDIA_TEGRA210_DMA_H__ -#include +#include #include #include diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index 6ec8b641ab..5a065ba199 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/nvidia/tegra210/uart.c b/src/soc/nvidia/tegra210/uart.c index a91818c8c6..904aafa076 100644 --- a/src/soc/nvidia/tegra210/uart.c +++ b/src/soc/nvidia/tegra210/uart.c @@ -115,7 +115,6 @@ unsigned char uart_rx_byte(int idx) return tegra210_uart_rx_byte(); } -#ifndef __PRE_RAM__ void uart_fill_lb(void *data) { struct lb_serial serial; @@ -123,8 +122,9 @@ void uart_fill_lb(void *data) serial.baseaddr = CONFIG_CONSOLE_SERIAL_TEGRA210_UART_ADDRESS; serial.baud = get_uart_baudrate(); serial.regwidth = 4; + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } -#endif diff --git a/src/soc/qualcomm/ipq40xx/blobs_init.c b/src/soc/qualcomm/ipq40xx/blobs_init.c index 5cda9fc7fb..9d608fa93d 100644 --- a/src/soc/qualcomm/ipq40xx/blobs_init.c +++ b/src/soc/qualcomm/ipq40xx/blobs_init.c @@ -58,8 +58,6 @@ static void *load_ipq_blob(const char *file_name) return blob_mbn; } -#ifdef __PRE_RAM__ - #define DDR_VERSION() ((const char *)"private build") #define MAX_DDR_VERSION_SIZE 48 @@ -120,7 +118,6 @@ int initialize_dram(void) return 0; } -#else /* __PRE_RAM__ */ void start_tzbsp(void) { void *tzbsp = load_ipq_blob(CONFIG_TZ_MBN); @@ -133,4 +130,3 @@ void start_tzbsp(void) tz_init_wrapper(0, 0, tzbsp); } -#endif /* !__PRE_RAM__ */ diff --git a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld index a69b60bfb9..f1a7bc59d2 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld @@ -58,7 +58,7 @@ SECTIONS DRAM_START(0x80000000) SYMBOL(memlayout_cbmem_top, 0x87280000) - POSTRAM_CBFS_CACHE(0x87280000, 384K) - RAMSTAGE(0x872e0000, 128K) - DMA_COHERENT(0x87300000, 2M) + POSTRAM_CBFS_CACHE(0x87280000, 512K) + RAMSTAGE(0x87300000, 512K) + DMA_COHERENT(0x87400000, 2M) } diff --git a/src/soc/qualcomm/ipq40xx/lcc.c b/src/soc/qualcomm/ipq40xx/lcc.c index b2b4c4524f..9a6c9116ec 100644 --- a/src/soc/qualcomm/ipq40xx/lcc.c +++ b/src/soc/qualcomm/ipq40xx/lcc.c @@ -287,29 +287,21 @@ static int lcc_enable_mi2s(IpqLccClocks *bus) int audio_clock_config(unsigned frequency) { - IpqLccClocks *bus = malloc(sizeof(*bus)); + IpqLccClocks bus = { + .gcc_apcs_regs = (void *)(MSM_GCC_BASE + GCC_PLL_APCS_REG), + .lcc_pll0_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_PLL0_MODE_REG), + .lcc_ahbix_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_AHBIX_NS_REG), + .lcc_mi2s_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_MI2S_NS_REG), + .lcc_pll_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_PLL_PCLK_REG), + }; - if (!bus) { - printk(BIOS_ERR, "%s: failed to allocate bus structure\n", - __func__); + if (lcc_init_enable_pll0(&bus)) return 1; - } - - bus->gcc_apcs_regs = (void *)(MSM_GCC_BASE + GCC_PLL_APCS_REG); - bus->lcc_pll0_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_PLL0_MODE_REG); - bus->lcc_ahbix_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_AHBIX_NS_REG); - bus->lcc_mi2s_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_MI2S_NS_REG); - bus->lcc_pll_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_PLL_PCLK_REG); - - - if (lcc_init_enable_pll0(bus)) + if (lcc_init_enable_ahbix(&bus)) return 1; - if (lcc_init_enable_ahbix(bus)) + if (lcc_init_mi2s(&bus, frequency)) return 1; - if (lcc_init_mi2s(bus, frequency)) - return 1; - - if (lcc_enable_mi2s(bus)) + if (lcc_enable_mi2s(&bus)) return 1; return 0; diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c index eb3731b7f7..6e5bac624b 100644 --- a/src/soc/qualcomm/ipq40xx/uart.c +++ b/src/soc/qualcomm/ipq40xx/uart.c @@ -283,7 +283,6 @@ uint8_t uart_rx_byte(int idx) return byte; } -#ifndef __PRE_RAM__ /* TODO: Implement function */ void uart_fill_lb(void *data) { @@ -293,8 +292,9 @@ void uart_fill_lb(void *data) serial.baseaddr = (uint32_t)UART1_DM_BASE; serial.baud = get_uart_baudrate(); serial.regwidth = 1; - + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } -#endif diff --git a/src/soc/qualcomm/ipq806x/blobs_init.c b/src/soc/qualcomm/ipq806x/blobs_init.c index aa78f566e9..2da868b892 100644 --- a/src/soc/qualcomm/ipq806x/blobs_init.c +++ b/src/soc/qualcomm/ipq806x/blobs_init.c @@ -57,8 +57,6 @@ static void *load_ipq_blob(const char *file_name) return blob_mbn + 1; } -#ifdef __PRE_RAM__ - #define DDR_VERSION() ((const char *)0x2a03f600) #define MAX_DDR_VERSION_SIZE 48 @@ -89,8 +87,6 @@ int initialize_dram(void) return 0; } -#else /* __PRE_RAM__ */ - void start_tzbsp(void) { void *tzbsp = load_ipq_blob("tz.mbn"); @@ -152,4 +148,3 @@ void start_rpm(void) (rpm_version >> 16) & 0xff, rpm_version & 0xffff); } -#endif /* !__PRE_RAM__ */ diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index 66c31034fa..f3e7de5910 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -398,9 +398,7 @@ uint8_t uart_rx_byte(int idx) return byte; } -#ifndef __PRE_RAM__ /* TODO: Implement fuction */ void uart_fill_lb(void *data) { } -#endif diff --git a/src/soc/qualcomm/qcs405/uart.c b/src/soc/qualcomm/qcs405/uart.c index 4a4331220a..3e980887db 100644 --- a/src/soc/qualcomm/qcs405/uart.c +++ b/src/soc/qualcomm/qcs405/uart.c @@ -287,7 +287,6 @@ uint8_t uart_rx_byte(int idx) } #endif -#ifndef __PRE_RAM__ void uart_fill_lb(void *data) { struct lb_serial serial; @@ -296,8 +295,9 @@ void uart_fill_lb(void *data) serial.baseaddr = (uint64_t)UART2_DM_BASE; serial.baud = get_uart_baudrate(); serial.regwidth = 1; - + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } -#endif diff --git a/src/soc/rockchip/common/i2c.c b/src/soc/rockchip/common/i2c.c index e5f5a9a9bf..cd0ed9b94f 100644 --- a/src/soc/rockchip/common/i2c.c +++ b/src/soc/rockchip/common/i2c.c @@ -128,25 +128,21 @@ static int i2c_read(struct rk_i2c_regs *reg_addr, struct i2c_msg segment) uint8_t *data = segment.buf; int timeout = I2C_TIMEOUT_US; unsigned int bytes_remaining = segment.len; - unsigned int bytes_transferred = 0; - unsigned int words_transferred = 0; - unsigned int rxdata = 0; unsigned int con = 0; - unsigned int i, j; write32(®_addr->i2c_mrxaddr, I2C_8BIT | segment.slave << 1 | 1); write32(®_addr->i2c_mrxraddr, 0); con = I2C_MODE_TRX | I2C_EN | I2C_ACT2NAK; while (bytes_remaining) { - bytes_transferred = MIN(bytes_remaining, 32); - bytes_remaining -= bytes_transferred; + size_t size = MIN(bytes_remaining, 32); + bytes_remaining -= size; if (!bytes_remaining) con |= I2C_EN | I2C_NAK; - words_transferred = ALIGN_UP(bytes_transferred, 4) / 4; + i2c_info("I2C Read::%zu bytes\n", size); write32(®_addr->i2c_ipd, I2C_CLEANI); write32(®_addr->i2c_con, con); - write32(®_addr->i2c_mrxcnt, bytes_transferred); + write32(®_addr->i2c_mrxcnt, size); timeout = I2C_TIMEOUT_US; while (timeout--) { @@ -166,15 +162,8 @@ static int i2c_read(struct rk_i2c_regs *reg_addr, struct i2c_msg segment) return I2C_TIMEOUT; } - for (i = 0; i < words_transferred; i++) { - rxdata = read32(®_addr->rxdata[i]); - i2c_info("I2c Read::RXDATA[%d] = 0x%x\n", i, rxdata); - for (j = 0; j < 4; j++) { - if ((i * 4 + j) == bytes_transferred) - break; - *data++ = (rxdata >> (j * 8)) & 0xff; - } - } + buffer_from_fifo32(data, size, ®_addr->rxdata, 4, 4); + data += size; con = I2C_MODE_RX | I2C_EN | I2C_ACT2NAK; } return res; @@ -186,32 +175,22 @@ static int i2c_write(struct rk_i2c_regs *reg_addr, struct i2c_msg segment) uint8_t *data = segment.buf; int timeout = I2C_TIMEOUT_US; int bytes_remaining = segment.len + 1; - int bytes_transferred = 0; - int words_transferred = 0; - unsigned int i; - unsigned int j = 1; - u32 txdata = 0; - txdata |= (segment.slave << 1); + /* Prepend one byte for the slave address to the transfer. */ + u32 prefix = segment.slave << 1; + int prefsz = 1; + while (bytes_remaining) { - bytes_transferred = MIN(bytes_remaining, 32); - words_transferred = ALIGN_UP(bytes_transferred, 4) / 4; - for (i = 0; i < words_transferred; i++) { - do { - if ((i * 4 + j) == bytes_transferred) - break; - txdata |= (*data++) << (j * 8); - } while (++j < 4); - write32(®_addr->txdata[i], txdata); - j = 0; - i2c_info("I2c Write::TXDATA[%d] = 0x%x\n", i, txdata); - txdata = 0; - } + size_t size = MIN(bytes_remaining, 32); + buffer_to_fifo32_prefix(data, prefix, prefsz, size, + ®_addr->txdata, 4, 4); + data += size - prefsz; + i2c_info("I2C Write::%zu bytes\n", size); write32(®_addr->i2c_ipd, I2C_CLEANI); write32(®_addr->i2c_con, I2C_EN | I2C_MODE_TX | I2C_ACT2NAK); - write32(®_addr->i2c_mtxcnt, bytes_transferred); + write32(®_addr->i2c_mtxcnt, size); timeout = I2C_TIMEOUT_US; while (timeout--) { @@ -232,7 +211,9 @@ static int i2c_write(struct rk_i2c_regs *reg_addr, struct i2c_msg segment) return I2C_TIMEOUT; } - bytes_remaining -= bytes_transferred; + bytes_remaining -= size; + prefsz = 0; + prefix = 0; } return res; } diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c index 7bde4333ea..0307e24d35 100644 --- a/src/soc/rockchip/common/spi.c +++ b/src/soc/rockchip/common/spi.c @@ -221,23 +221,11 @@ static int do_xfer(struct rockchip_spi *regs, bool use_16bit, const void *dout, * sychronizing with the SPI clock which is pretty slow. */ if (*bytes_in && !(sr & SR_RF_EMPT)) { - int fifo = read32(®s->rxflr) & RXFLR_LEVEL_MASK; - int val; - - if (use_16bit) - xferred = fifo * 2; - else - xferred = fifo; + int w = use_16bit ? 2 : 1; + xferred = (read32(®s->rxflr) & RXFLR_LEVEL_MASK) * w; + buffer_from_fifo32(in_buf, xferred, ®s->rxdr, 0, w); *bytes_in -= xferred; - while (fifo-- > 0) { - val = read32(®s->rxdr); - if (use_16bit) { - *in_buf++ = val & 0xff; - *in_buf++ = (val >> 8) & 0xff; - } else { - *in_buf++ = val & 0xff; - } - } + in_buf += xferred; } min_xfer -= xferred; diff --git a/src/soc/rockchip/rk3288/crypto.c b/src/soc/rockchip/rk3288/crypto.c index c429258e10..00885bc11f 100644 --- a/src/soc/rockchip/rk3288/crypto.c +++ b/src/soc/rockchip/rk3288/crypto.c @@ -68,8 +68,8 @@ struct rk3288_crypto { } *crypto = (void *)CRYPTO_BASE; check_member(rk3288_crypto, trng_dout[7], 0x220); -int vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg, - uint32_t data_size) +vb2_error_t vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg, + uint32_t data_size) { if (hash_alg != VB2_HASH_SHA256) { printk(BIOS_INFO, "RK3288 doesn't support hash_alg %d!\n", @@ -94,7 +94,7 @@ int vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg, return VB2_SUCCESS; } -int vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size) +vb2_error_t vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size) { uint32_t intsts; @@ -115,7 +115,8 @@ int vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size) return VB2_SUCCESS; } -int vb2ex_hwcrypto_digest_finalize(uint8_t *digest, uint32_t digest_size) +vb2_error_t vb2ex_hwcrypto_digest_finalize(uint8_t *digest, + uint32_t digest_size) { uint32_t *dest = (uint32_t *)digest; uint32_t *src = crypto->hash_dout; diff --git a/src/soc/rockchip/rk3288/include/soc/timer.h b/src/soc/rockchip/rk3288/include/soc/timer.h index 04efeaf917..1d08fcc1e2 100644 --- a/src/soc/rockchip/rk3288/include/soc/timer.h +++ b/src/soc/rockchip/rk3288/include/soc/timer.h @@ -16,7 +16,7 @@ #ifndef __SOC_ROCKCHIP_RK3288_TIMER_H__ #define __SOC_ROCKCHIP_RK3288_TIMER_H__ -#include +#include #include #include #include diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc index 854eb84eed..3b66247868 100644 --- a/src/soc/rockchip/rk3399/Makefile.inc +++ b/src/soc/rockchip/rk3399/Makefile.inc @@ -76,7 +76,6 @@ ramstage-y += timer.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += ../common/vop.c ramstage-y += usb.c -ramstage-y += bl31_plat_params.c BL31_MAKEARGS += PLAT=rk3399 M0_CROSS_COMPILE="$(CROSS_COMPILE_arm)" ################################################################################ diff --git a/src/soc/rockchip/rk3399/bl31_plat_params.c b/src/soc/rockchip/rk3399/bl31_plat_params.c deleted file mode 100644 index 9c11552301..0000000000 --- a/src/soc/rockchip/rk3399/bl31_plat_params.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include - -static struct bl31_plat_param *plat_params; - -void register_bl31_param(struct bl31_plat_param *param) -{ - param->next = plat_params; - plat_params = param; -} - -void *soc_get_bl31_plat_params(bl31_params_t *bl31_params) -{ - static struct bl31_u64_param cbtable_param = { - .h = { .type = PARAM_COREBOOT_TABLE, }, - }; - if (!cbtable_param.value) { - cbtable_param.value = (uint64_t)cbmem_find(CBMEM_ID_CBTABLE); - if (cbtable_param.value) - register_bl31_param(&cbtable_param.h); - } - return plat_params; -} diff --git a/src/soc/rockchip/rk3399/include/soc/timer.h b/src/soc/rockchip/rk3399/include/soc/timer.h index 8513cfa5bc..46c69e6a2f 100644 --- a/src/soc/rockchip/rk3399/include/soc/timer.h +++ b/src/soc/rockchip/rk3399/include/soc/timer.h @@ -16,7 +16,7 @@ #ifndef __SOC_ROCKCHIP_RK3399_TIMER_H__ #define __SOC_ROCKCHIP_RK3399_TIMER_H__ -#include +#include #include #include diff --git a/src/soc/samsung/exynos5250/alternate_cbfs.c b/src/soc/samsung/exynos5250/alternate_cbfs.c index e431672579..c319019eb6 100644 --- a/src/soc/samsung/exynos5250/alternate_cbfs.c +++ b/src/soc/samsung/exynos5250/alternate_cbfs.c @@ -35,12 +35,14 @@ * should contain all available stages/payloads/etc. It is loaded when this * function is called a second time at the end of the romstage, and copied to * the romstage/ramstage CBFS cache in DRAM. It will reside there for the - * rest of the firmware's lifetime and all subsequent stages (which will not - * have __PRE_RAM__ defined) can just directly reference it there. + * rest of the firmware's lifetime and all subsequent stages can just directly + * reference it there. */ static int usb_cbfs_open(void) { -#ifdef __PRE_RAM__ + if (!ENV_ROMSTAGE_OR_BEFORE) + return 0; + static int first_run = 1; int (*irom_load_usb)(void) = *irom_load_image_from_usb_ptr; @@ -61,7 +63,6 @@ static int usb_cbfs_open(void) printk(BIOS_DEBUG, "USB A-A transfer successful, CBFS image should now" " be at %p\n", _cbfs_cache); first_run = 0; -#endif return 0; } @@ -75,7 +76,9 @@ static int usb_cbfs_open(void) */ static int sdmmc_cbfs_open(void) { -#ifdef __PRE_RAM__ + if (!ENV_ROMSTAGE_OR_BEFORE) + return 0; + /* * In the bootblock, we just copy the small part that fits in the buffer * and hope that it's enough (since the romstage is currently always the @@ -100,7 +103,6 @@ static int sdmmc_cbfs_open(void) printk(BIOS_DEBUG, "SDMMC read successful, CBFS image should now be" " at %p\n", _cbfs_cache); first_run = 0; -#endif return 0; } diff --git a/src/soc/samsung/exynos5250/uart.c b/src/soc/samsung/exynos5250/uart.c index 1b8e7859f1..cc851e5d3c 100644 --- a/src/soc/samsung/exynos5250/uart.c +++ b/src/soc/samsung/exynos5250/uart.c @@ -185,7 +185,6 @@ void uart_tx_flush(int idx) exynos5_uart_tx_flush(uart); } -#ifndef __PRE_RAM__ void uart_fill_lb(void *data) { struct lb_serial serial; @@ -193,8 +192,9 @@ void uart_fill_lb(void *data) serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = get_uart_baudrate(); serial.regwidth = 4; + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } -#endif diff --git a/src/soc/samsung/exynos5420/alternate_cbfs.c b/src/soc/samsung/exynos5420/alternate_cbfs.c index ba3f9a3c87..fabc9cff7d 100644 --- a/src/soc/samsung/exynos5420/alternate_cbfs.c +++ b/src/soc/samsung/exynos5420/alternate_cbfs.c @@ -36,12 +36,14 @@ * should contain all available stages/payloads/etc. It is loaded when this * function is called a second time at the end of the romstage, and copied to * the romstage/ramstage CBFS cache in DRAM. It will reside there for the - * rest of the firmware's lifetime and all subsequent stages (which will not - * have __PRE_RAM__ defined) can just directly reference it there. + * rest of the firmware's lifetime and all subsequent stages can just directly + * reference it there. */ static int usb_cbfs_open(void) { -#ifdef __PRE_RAM__ + if (!ENV_ROMSTAGE_OR_BEFORE) + return 0; + static int first_run = 1; int (*irom_load_usb)(void) = *irom_load_image_from_usb_ptr; @@ -65,7 +67,6 @@ static int usb_cbfs_open(void) printk(BIOS_DEBUG, "USB A-A transfer successful, CBFS image should now" " be at %p\n", _cbfs_cache); first_run = 0; -#endif return 0; } @@ -79,7 +80,9 @@ static int usb_cbfs_open(void) */ static int sdmmc_cbfs_open(void) { -#ifdef __PRE_RAM__ + if (!ENV_ROMSTAGE_OR_BEFORE) + return 0; + /* * In the bootblock, we just copy the small part that fits in the buffer * and hope that it's enough (since the romstage is currently always the @@ -107,7 +110,6 @@ static int sdmmc_cbfs_open(void) printk(BIOS_DEBUG, "SDMMC read successful, CBFS image should now be" " at %p\n", _cbfs_cache); first_run = 0; -#endif return 0; } diff --git a/src/soc/samsung/exynos5420/uart.c b/src/soc/samsung/exynos5420/uart.c index b2a0edd4e0..41fdd0d29c 100644 --- a/src/soc/samsung/exynos5420/uart.c +++ b/src/soc/samsung/exynos5420/uart.c @@ -176,7 +176,6 @@ void uart_tx_flush(int idx) /* Exynos5250 implements this too. */ } -#ifndef __PRE_RAM__ void uart_fill_lb(void *data) { struct lb_serial serial; @@ -190,4 +189,3 @@ void uart_fill_lb(void *data) lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } -#endif diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc index 4f62f3ed62..3c97c08191 100644 --- a/src/soc/sifive/fu540/Makefile.inc +++ b/src/soc/sifive/fu540/Makefile.inc @@ -15,13 +15,13 @@ ifeq ($(CONFIG_SOC_SIFIVE_FU540),y) bootblock-y += uart.c bootblock-y += clint.c -bootblock-y += media.c +bootblock-y += spi.c bootblock-y += bootblock.c bootblock-y += clock.c romstage-y += uart.c romstage-y += clint.c -romstage-y += media.c +romstage-y += spi.c romstage-y += sdram.c romstage-y += cbmem.c romstage-y += otp.c @@ -29,7 +29,7 @@ romstage-y += clock.c ramstage-y += uart.c ramstage-y += clint.c -ramstage-y += media.c +ramstage-y += spi.c ramstage-y += sdram.c ramstage-y += cbmem.c ramstage-y += otp.c diff --git a/src/soc/sifive/fu540/include/soc/spi.h b/src/soc/sifive/fu540/include/soc/spi.h new file mode 100644 index 0000000000..543f9b2035 --- /dev/null +++ b/src/soc/sifive/fu540/include/soc/spi.h @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_SIFIVE_HIFIVE_U_SPI_H__ +#define __SOC_SIFIVE_HIFIVE_U_SPI_H__ +#include + +/* Data Pins: MOSI MISO */ +#define FU540_SPI_PROTO_S 0 +/* Data Pins: DQ0 DQ1 */ +#define FU540_SPI_PROTO_D 1 +/* Data Pins: DQ0 DQ1 DQ2 DQ3 */ +#define FU540_SPI_PROTO_Q 2 + +/* send MSB first */ +#define FU540_SPI_ENDIAN_BIG 0 +/* send LSB first */ +#define FU540_SPI_ENDIAN_LITTLE 1 + +/* inactive state of SCK is logical 0 */ +#define FU540_SPI_PHA_LOW 0 +/* inactive state of SCK is logical 1 */ +#define FU540_SPI_PHA_HIGH 1 + +/* data is sampled on leading edge */ +#define FU540_SPI_POL_LEADING 0 +/* data is sampled on trailing edge */ +#define FU540_SPI_POL_TRAILING 1 + +struct fu540_spi_config { + /* speed of spi interface */ + unsigned int freq; + /* serial clock phase */ + unsigned int pha; + /* serial clock polarity */ + unsigned int pol; + unsigned int protocol; + unsigned int endianness; + /* up to 8bits */ + unsigned int bits_per_frame; +}; + +/* more detailed spi configuration */ +int fu540_spi_setup(unsigned int bus, unsigned int cs, struct spi_slave *slave, + struct fu540_spi_config *config); + +/* This structure is used to describe the read command of SPI FLASH. */ +struct fu540_spi_mmap_config { + /* enable sending of command */ + unsigned int cmd_en; + /* number of address bytes (0-4) */ + unsigned int addr_len; + /* number of dummy cycles */ + unsigned int pad_cnt; + /* protocol for transmitting command */ + unsigned int cmd_proto; + /* protocol for transmitting address and padding */ + unsigned int addr_proto; + /* protocol for receiving data bytes */ + unsigned int data_proto; + /* value of command byte */ + unsigned int cmd_code; + /* first 8 bits to transmit during dummy cycles */ + unsigned int pad_code; +}; + +int fu540_spi_mmap( + const struct spi_slave *slave, + const struct fu540_spi_mmap_config *config); + +#endif /* __SOC_SIFIVE_HIFIVE_U_SPI_H__ */ diff --git a/src/soc/sifive/fu540/spi.c b/src/soc/sifive/fu540/spi.c new file mode 100644 index 0000000000..6bf1700767 --- /dev/null +++ b/src/soc/sifive/fu540/spi.c @@ -0,0 +1,254 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * Copyright (C) 2019 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "spi_internal.h" + +static struct spi_ctrl *spictrls[] = { + (struct spi_ctrl *)FU540_QSPI0, + (struct spi_ctrl *)FU540_QSPI1, + (struct spi_ctrl *)FU540_QSPI2 +}; + + +/** + * Wait until SPI is ready for transmission and transmit byte. + */ +static void spi_tx(volatile struct spi_ctrl *spictrl, uint8_t in) +{ +#if __riscv_atomic + int32_t r; + do { + asm volatile ( + "amoor.w %0, %2, %1\n" + : "=r" (r), "+A" (spictrl->txdata.raw_bits) + : "r" (in) + ); + } while (r < 0); +#else + while ((int32_t) spictrl->txdata.raw_bits < 0) + ; + spictrl->txdata.data = in; +#endif +} + + +/** + * Wait until SPI receive queue has data and read byte. + */ +static uint8_t spi_rx(volatile struct spi_ctrl *spictrl) +{ + int32_t out; + while ((out = (int32_t) spictrl->rxdata.raw_bits) < 0) + ; + return (uint8_t) out; +} + +static int spi_xfer_(const struct spi_slave *slave, + const void *dout, size_t bytesout, + void *din, size_t bytesin) +{ + struct spi_ctrl *spictrl = spictrls[slave->bus]; + spi_reg_fmt fmt; + fmt.raw_bits = read32(&spictrl->fmt.raw_bits); + if (fmt.proto == FU540_SPI_PROTO_S) { + /* working in full-duplex mode + * receiving data needs to be triggered by sending data */ + while (bytesout || bytesin) { + uint8_t in, out = 0; + if (bytesout) { + out = *(uint8_t *)dout++; + bytesout--; + } + spi_tx(spictrl, out); + in = spi_rx(spictrl); + if (bytesin) { + *(uint8_t *)din++ = in; + bytesin--; + } + } + } else { + /* Working in half duplex + * send and receive can be done separately */ + if (dout && din) + return -1; + + if (dout) { + while (bytesout) { + spi_tx(spictrl, *(uint8_t *)dout++); + bytesout--; + } + } + + if (din) { + while (bytesin) { + *(uint8_t *)din++ = spi_rx(spictrl); + bytesin--; + } + } + } + return 0; +} + +static int spi_setup_(const struct spi_slave *slave) +{ + spi_reg_sckmode sckmode; + spi_reg_csmode csmode; + spi_reg_fmt fmt; + + if ((slave->bus > 2) || (slave->cs != 0)) + return -1; + + struct spi_ctrl *spictrl = spictrls[slave->bus]; + + write32(&spictrl->sckdiv, spi_min_clk_divisor(clock_get_tlclk_khz(), + 10000)); + + sckmode.raw_bits = 0; + sckmode.pha = FU540_SPI_PHA_LOW; + sckmode.pol = FU540_SPI_POL_LEADING; + write32(&spictrl->sckmode.raw_bits, sckmode.raw_bits); + + csmode.raw_bits = 0; + csmode.mode = FU540_SPI_CSMODE_AUTO; + write32(&spictrl->csmode.raw_bits, csmode.raw_bits); + + fmt.raw_bits = 0; + fmt.proto = FU540_SPI_PROTO_S; + fmt.endian = FU540_SPI_ENDIAN_BIG; + fmt.dir = 1; + fmt.len = 8; + write32(&spictrl->fmt.raw_bits, fmt.raw_bits); + + return 0; +} + +struct spi_ctrlr fu540_spi_ctrlr = { + .xfer = spi_xfer_, + .setup = spi_setup_, +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .bus_start = 0, + .bus_end = 2, + .ctrlr = &fu540_spi_ctrlr, + } +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); + +int fu540_spi_setup(unsigned int bus, unsigned int cs, + struct spi_slave *slave, + struct fu540_spi_config *config) +{ + spi_reg_sckmode sckmode; + spi_reg_csmode csmode; + spi_reg_fmt fmt; + + if ((bus > 2) || (cs != 0)) + return -1; + + if ((config->pha > 1) + || (config->pol > 1) + || (config->protocol > 2) + || (config->endianness > 1) + || (config->bits_per_frame > 8)) + return -1; + + slave->bus = bus; + slave->cs = cs; + slave->ctrlr = &fu540_spi_ctrlr; + + struct spi_ctrl *spictrl = spictrls[slave->bus]; + + write32(&spictrl->sckdiv, spi_min_clk_divisor(clock_get_tlclk_khz(), + config->freq / 1000)); + + sckmode.raw_bits = 0; + sckmode.pha = config->pha; + sckmode.pol = config->pol; + write32(&spictrl->sckmode.raw_bits, sckmode.raw_bits); + + csmode.raw_bits = 0; + csmode.mode = FU540_SPI_CSMODE_AUTO; + write32(&spictrl->csmode.raw_bits, csmode.raw_bits); + + fmt.raw_bits = 0; + fmt.proto = config->protocol; + fmt.endian = config->endianness; + fmt.dir = 1; + fmt.len = config->bits_per_frame; + write32(&spictrl->fmt.raw_bits, fmt.raw_bits); + + return 0; +} + +int fu540_spi_mmap( + const struct spi_slave *slave, + const struct fu540_spi_mmap_config *config) +{ + spi_reg_fctrl fctrl; + spi_reg_ffmt ffmt; + + if (slave->bus > 2) + return -1; + + if ((config->cmd_en > 1) + || (config->addr_len > 4) + || (config->pad_cnt > 15) + || (config->cmd_proto > 2) + || (config->addr_proto > 2) + || (config->data_proto > 2) + || (config->cmd_code > 255) + || (config->pad_code > 255)) + return -1; + + struct spi_ctrl *spictrl = spictrls[slave->bus]; + + /* disable direct memory-mapped spi flash mode */ + fctrl.raw_bits = 0; + fctrl.en = 0; + write32(&spictrl->fctrl.raw_bits, fctrl.raw_bits); + + /* reset spi flash chip */ + spi_tx(spictrl, 0x66); + spi_tx(spictrl, 0x99); + + /* Pass the information of the flash read operation to the spi + * controller */ + ffmt.raw_bits = 0; + ffmt.cmd_en = config->cmd_en; + ffmt.addr_len = config->addr_len; + ffmt.pad_cnt = config->pad_cnt; + ffmt.command_proto = config->cmd_proto; + ffmt.addr_proto = config->addr_proto; + ffmt.data_proto = config->data_proto; + ffmt.command_code = config->cmd_code; + ffmt.pad_code = config->pad_code; + write32(&spictrl->ffmt.raw_bits, ffmt.raw_bits); + + /* enable direct memory-mapped spi flash mode */ + fctrl.raw_bits = 0; + fctrl.en = 1; + write32(&spictrl->fctrl.raw_bits, fctrl.raw_bits); + + return 0; +} diff --git a/src/soc/sifive/fu540/spi_internal.h b/src/soc/sifive/fu540/spi_internal.h new file mode 100644 index 0000000000..97094c1d8c --- /dev/null +++ b/src/soc/sifive/fu540/spi_internal.h @@ -0,0 +1,242 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __SOC_SIFIVE_HIFIVE_U_SPI_INTERNAL_H__ +#define __SOC_SIFIVE_HIFIVE_U_SPI_INTERNAL_H__ + +#include + +#define _ASSERT_SIZEOF(type, size) _Static_assert( \ + sizeof(type) == (size), \ + #type " must be " #size " bytes wide") + +#define FU540_SPI_CSMODE_AUTO 0 +#define FU540_SPI_CSMODE_HOLD 2 +#define FU540_SPI_CSMODE_OFF 3 + +typedef union { + struct { + uint32_t pha : 1; + uint32_t pol : 1; + uint32_t reserved : 30; + }; + uint32_t raw_bits; +} spi_reg_sckmode; +_ASSERT_SIZEOF(spi_reg_sckmode, 4); + + +typedef union { + struct { + uint32_t mode : 2; + uint32_t reserved : 30; + }; + uint32_t raw_bits; +} spi_reg_csmode; +_ASSERT_SIZEOF(spi_reg_csmode, 4); + + +typedef union { + struct { + uint32_t cssck : 8; + uint32_t reserved0 : 8; + uint32_t sckcs : 8; + uint32_t reserved1 : 8; + }; + uint32_t raw_bits; +} spi_reg_delay0; +_ASSERT_SIZEOF(spi_reg_delay0, 4); + + +typedef union { + struct { + uint32_t intercs : 8; + uint32_t reserved0 : 8; + uint32_t interxfr : 8; + uint32_t reserved1 : 8; + }; + uint32_t raw_bits; +} spi_reg_delay1; +_ASSERT_SIZEOF(spi_reg_delay1, 4); + + +typedef union { + struct { + uint32_t proto : 2; + uint32_t endian : 1; + uint32_t dir : 1; + uint32_t reserved0 : 12; + uint32_t len : 4; + uint32_t reserved1 : 12; + }; + uint32_t raw_bits; +} spi_reg_fmt; +_ASSERT_SIZEOF(spi_reg_fmt, 4); + + +typedef union { + struct { + uint32_t data : 8; + uint32_t reserved : 23; + uint32_t full : 1; + }; + uint32_t raw_bits; +} spi_reg_txdata; +_ASSERT_SIZEOF(spi_reg_txdata, 4); + + +typedef union { + struct { + uint32_t data : 8; + uint32_t reserved : 23; + uint32_t empty : 1; + }; + uint32_t raw_bits; +} spi_reg_rxdata; +_ASSERT_SIZEOF(spi_reg_rxdata, 4); + + +typedef union { + struct { + uint32_t txmark : 3; + uint32_t reserved : 29; + }; + uint32_t raw_bits; +} spi_reg_txmark; +_ASSERT_SIZEOF(spi_reg_txmark, 4); + + +typedef union { + struct { + uint32_t rxmark : 3; + uint32_t reserved : 29; + }; + uint32_t raw_bits; +} spi_reg_rxmark; +_ASSERT_SIZEOF(spi_reg_rxmark, 4); + + +typedef union { + struct { + uint32_t en : 1; + uint32_t reserved : 31; + }; + uint32_t raw_bits; +} spi_reg_fctrl; +_ASSERT_SIZEOF(spi_reg_fctrl, 4); + + +typedef union { + struct { + uint32_t cmd_en : 1; + uint32_t addr_len : 3; + uint32_t pad_cnt : 4; + uint32_t command_proto : 2; + uint32_t addr_proto : 2; + uint32_t data_proto : 2; + uint32_t reserved : 2; + uint32_t command_code : 8; + uint32_t pad_code : 8; + }; + uint32_t raw_bits; +} spi_reg_ffmt; +_ASSERT_SIZEOF(spi_reg_ffmt, 4); + + +typedef union { + struct { + uint32_t txwm : 1; + uint32_t rxwm : 1; + uint32_t reserved : 30; + }; + uint32_t raw_bits; +} spi_reg_ie; +typedef spi_reg_ie spi_reg_ip; +_ASSERT_SIZEOF(spi_reg_ie, 4); +_ASSERT_SIZEOF(spi_reg_ip, 4); + +#undef _ASSERT_SIZEOF + + +/** + * SPI control register memory map. + * + * All functions take a pointer to a SPI device's control registers. + */ +struct spi_ctrl { + uint32_t sckdiv; + spi_reg_sckmode sckmode; + uint32_t reserved08; + uint32_t reserved0c; + + uint32_t csid; + uint32_t csdef; + spi_reg_csmode csmode; + uint32_t reserved1c; + + uint32_t reserved20; + uint32_t reserved24; + spi_reg_delay0 delay0; + spi_reg_delay1 delay1; + + uint32_t reserved30; + uint32_t reserved34; + uint32_t reserved38; + uint32_t reserved3c; + + spi_reg_fmt fmt; + uint32_t reserved44; + spi_reg_txdata txdata; + spi_reg_rxdata rxdata; + + spi_reg_txmark txmark; + spi_reg_rxmark rxmark; + uint32_t reserved58; + uint32_t reserved5c; + + spi_reg_fctrl fctrl; + spi_reg_ffmt ffmt; + uint32_t reserved68; + uint32_t reserved6c; + + spi_reg_ie ie; + spi_reg_ip ip; +}; + +/** + * Get smallest clock divisor that divides input_khz to a quotient less than or + * equal to max_target_khz; + */ +static inline unsigned int +spi_min_clk_divisor(unsigned int input_khz, unsigned int max_target_khz) +{ + // f_sck = f_in / (2 * (div + 1)) => div = (f_in / (2*f_sck)) - 1 + // + // The nearest integer solution for div requires rounding up as to not + // exceed max_target_khz. + // + // div = ceil(f_in / (2*f_sck)) - 1 + // = floor((f_in - 1 + 2*f_sck) / (2*f_sck)) - 1 + // + // This should not overflow as long as (f_in - 1 + 2*f_sck) does not + // exceed 2^32 - 1, which is unlikely since we represent frequencies + // in kHz. + unsigned int quotient = + (input_khz + 2 * max_target_khz - 1) / (2 * max_target_khz); + // Avoid underflow + if (quotient == 0) + return 0; + return quotient - 1; +} + +#endif /* __SOC_SIFIVE_HIFIVE_U_SPI_INTERNAL_H__ */ diff --git a/src/southbridge/amd/agesa/hudson/hda.c b/src/southbridge/amd/agesa/hudson/hda.c index 2368bb2d4f..725bb0b951 100644 --- a/src/southbridge/amd/agesa/hudson/hda.c +++ b/src/southbridge/amd/agesa/hudson/hda.c @@ -16,7 +16,6 @@ #include #include #include -#include #include "hudson.h" diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index bd49e8f05c..21a2129a5c 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -18,7 +18,6 @@ #define HUDSON_H #include -#include "chip.h" /* Power management index/data registers */ #define BIOSRAM_INDEX 0xcd4 @@ -62,14 +61,11 @@ static inline int hudson_ide_enable(void) return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3); } -#ifndef __SMM__ - void pm_write8(u8 reg, u8 value); u8 pm_read8(u8 reg); void pm_write16(u8 reg, u16 value); u16 pm_read16(u16 reg); -#ifdef __SIMPLE_DEVICE__ void hudson_lpc_port80(void); void hudson_pci_port80(void); void hudson_clk_output_48Mhz(void); @@ -77,10 +73,6 @@ void hudson_clk_output_48Mhz(void); int s3_save_nvram_early(u32 dword, int size, int nvram_pos); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); -#else void hudson_enable(struct device *dev); -#endif /* __PRE_RAM__ */ -#endif /* __SMM__ */ - #endif /* HUDSON_H */ diff --git a/src/southbridge/amd/agesa/hudson/ide.c b/src/southbridge/amd/agesa/hudson/ide.c index 66bb89b91f..aa2b66f8d5 100644 --- a/src/southbridge/amd/agesa/hudson/ide.c +++ b/src/southbridge/amd/agesa/hudson/ide.c @@ -16,7 +16,6 @@ #include #include #include -#include #include "hudson.h" static void ide_init(struct device *dev) diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c index 9ba07316e8..1d63c1e36a 100644 --- a/src/southbridge/amd/agesa/hudson/imc.c +++ b/src/southbridge/amd/agesa/hudson/imc.c @@ -54,7 +54,6 @@ void imc_reg_init(void) #endif } -#ifndef __PRE_RAM__ void enable_imc_thermal_zone(void) { AMD_CONFIG_PARAMS StdHeader; @@ -83,4 +82,3 @@ void enable_imc_thermal_zone(void) WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); // function number WaitForEcLDN9MailboxCmdAck(&StdHeader); } -#endif diff --git a/src/southbridge/amd/agesa/hudson/pci.c b/src/southbridge/amd/agesa/hudson/pci.c index 31371ce250..5564533b76 100644 --- a/src/southbridge/amd/agesa/hudson/pci.c +++ b/src/southbridge/amd/agesa/hudson/pci.c @@ -17,7 +17,6 @@ #include #include #include -#include #include "hudson.h" #include #include diff --git a/src/southbridge/amd/agesa/hudson/pcie.c b/src/southbridge/amd/agesa/hudson/pcie.c index c765fb6c77..9f7e84b6c8 100644 --- a/src/southbridge/amd/agesa/hudson/pcie.c +++ b/src/southbridge/amd/agesa/hudson/pcie.c @@ -16,7 +16,6 @@ #include #include #include -#include #include "hudson.h" static void pcie_init(struct device *dev) diff --git a/src/southbridge/amd/agesa/hudson/sd.c b/src/southbridge/amd/agesa/hudson/sd.c index cc9470e04b..25acf0cc1f 100644 --- a/src/southbridge/amd/agesa/hudson/sd.c +++ b/src/southbridge/amd/agesa/hudson/sd.c @@ -18,18 +18,19 @@ #include #include +#include "chip.h" #include "hudson.h" static void sd_init(struct device *dev) { - u32 stepping; + struct southbridge_amd_agesa_hudson_config *sd_chip = dev->chip_info; + u32 stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC); + u8 sd_mode = 0; - stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC); + if (sd_chip) + sd_mode = sd_chip->sd_mode; - struct southbridge_amd_agesa_hudson_config *sd_chip = - (struct southbridge_amd_agesa_hudson_config *)(dev->chip_info); - - if (sd_chip->sd_mode == 3) { /* SD 3.0 mode */ + if (sd_mode == 3) { /* SD 3.0 mode */ pci_write_config32(dev, 0xA4, 0x31FEC8B2); pci_write_config32(dev, 0xA8, 0x00002503); pci_write_config32(dev, 0xB0, 0x02180C19); diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c index 46eca33555..b5739f9e39 100644 --- a/src/southbridge/amd/agesa/hudson/sm.c +++ b/src/southbridge/amd/agesa/hudson/sm.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/src/southbridge/amd/agesa/hudson/smi.c b/src/southbridge/amd/agesa/hudson/smi.c index 4180795a73..f8196b4e65 100644 --- a/src/southbridge/amd/agesa/hudson/smi.c +++ b/src/southbridge/amd/agesa/hudson/smi.c @@ -18,9 +18,10 @@ * Utilities for SMM setup */ -#include "smi.h" - #include +#include + +#include "smi.h" void smm_setup_structures(void *gnvs, void *tcg, void *smi1) { diff --git a/src/southbridge/amd/agesa/hudson/smihandler.c b/src/southbridge/amd/agesa/hudson/smihandler.c index 1b9442b1b6..6ecb7462f0 100644 --- a/src/southbridge/amd/agesa/hudson/smihandler.c +++ b/src/southbridge/amd/agesa/hudson/smihandler.c @@ -120,7 +120,7 @@ static void process_smi_0x90(void) smi_write32(0x90, status); } -void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) +void southbridge_smi_handler(void) { const uint16_t smi_src = smi_read16(0x94); diff --git a/src/southbridge/amd/agesa/hudson/usb.c b/src/southbridge/amd/agesa/hudson/usb.c index ec305afe27..d6f38790f0 100644 --- a/src/southbridge/amd/agesa/hudson/usb.c +++ b/src/southbridge/amd/agesa/hudson/usb.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include "hudson.h" diff --git a/src/southbridge/amd/amd8111/ac97.c b/src/southbridge/amd/amd8111/ac97.c index 267c436ee9..d05f0be6d9 100644 --- a/src/southbridge/amd/amd8111/ac97.c +++ b/src/southbridge/amd/amd8111/ac97.c @@ -16,7 +16,6 @@ #include #include #include -#include #include "amd8111.h" static struct pci_operations lops_pci = { diff --git a/src/southbridge/amd/amd8111/amd8111.h b/src/southbridge/amd/amd8111/amd8111.h index a984143a17..447edf9b4c 100644 --- a/src/southbridge/amd/amd8111/amd8111.h +++ b/src/southbridge/amd/amd8111/amd8111.h @@ -14,14 +14,9 @@ #ifndef AMD8111_H #define AMD8111_H -#include "chip.h" +#include -#ifndef __SIMPLE_DEVICE__ void amd8111_enable(struct device *dev); -#endif - -#ifdef __PRE_RAM__ void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); -#endif #endif /* AMD8111_H */ diff --git a/src/southbridge/amd/amd8111/ide.c b/src/southbridge/amd/amd8111/ide.c index 420e28e157..49f9d154f8 100644 --- a/src/southbridge/amd/amd8111/ide.c +++ b/src/southbridge/amd/amd8111/ide.c @@ -17,6 +17,7 @@ #include #include #include "amd8111.h" +#include "chip.h" static void ide_init(struct device *dev) { diff --git a/src/southbridge/amd/amd8111/nic.c b/src/southbridge/amd/amd8111/nic.c index adf8af0d43..a4abd0360a 100644 --- a/src/southbridge/amd/amd8111/nic.c +++ b/src/southbridge/amd/amd8111/nic.c @@ -21,7 +21,7 @@ #include #include #include "amd8111.h" - +#include "chip.h" #define CMD3 0x54 diff --git a/src/southbridge/amd/amd8111/usb2.c b/src/southbridge/amd/amd8111/usb2.c index adb7db184c..b41c0bee66 100644 --- a/src/southbridge/amd/amd8111/usb2.c +++ b/src/southbridge/amd/amd8111/usb2.c @@ -18,7 +18,6 @@ #include #include #include -#include #include "amd8111.h" static void amd8111_usb2_enable(struct device *dev) diff --git a/src/southbridge/amd/cimx/sb800/fan.h b/src/southbridge/amd/cimx/sb800/fan.h index f31e48645e..3734da10a0 100644 --- a/src/southbridge/amd/cimx/sb800/fan.h +++ b/src/southbridge/amd/cimx/sb800/fan.h @@ -16,10 +16,10 @@ #ifndef _SB800_FAN_H_ #define _SB800_FAN_H_ -#ifndef __PRE_RAM__ +#include + void init_sb800_IMC_fans(struct device *dev); void init_sb800_MANUAL_fans(struct device *dev); -#endif /* Fan Register Definitions */ #define FAN_0_OFFSET 0x00 diff --git a/src/southbridge/amd/cimx/sb900/cfg.c b/src/southbridge/amd/cimx/sb900/cfg.c index 353d5771e0..2e4173fb92 100644 --- a/src/southbridge/amd/cimx/sb900/cfg.c +++ b/src/southbridge/amd/cimx/sb900/cfg.c @@ -243,15 +243,13 @@ void sb900_cimx_config(AMDSBCFG *sb_config) sb_config->PciClks = SB_PCI_CLOCK_RESERVED; sb_config->hwm.hwmEnable = 0x0; -#ifndef __PRE_RAM__ /* ramstage cimx config here */ - if (!sb_config->StdHeader.CALLBACK.CalloutPtr) { + if (ENV_RAMSTAGE && !sb_config->StdHeader.CALLBACK.CalloutPtr) { sb_config->StdHeader.CALLBACK.CalloutPtr = sb900_callout_entry; } //sb_config-> -#endif //!__PRE_RAM__ - printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n"); + printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n"); } void SbPowerOnInit_Config(AMDSBCFG *sb_config) diff --git a/src/southbridge/amd/common/amd_pci_util.c b/src/southbridge/amd/common/amd_pci_util.c index f10a459bfd..b6d6308710 100644 --- a/src/southbridge/amd/common/amd_pci_util.c +++ b/src/southbridge/amd/common/amd_pci_util.c @@ -22,8 +22,6 @@ #include "amd_pci_int_defs.h" #include "amd_pci_int_types.h" -#ifndef __PRE_RAM__ - const struct pirq_struct * pirq_data_ptr = NULL; u32 pirq_data_size = 0; const u8 *intr_data_ptr = NULL; @@ -195,4 +193,3 @@ void write_pci_cfg_irqs(void) } /* for (dev = all_devices) */ printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); } -#endif /* __PRE_RAM__ */ diff --git a/src/southbridge/amd/common/amd_pci_util.h b/src/southbridge/amd/common/amd_pci_util.h index 9a4695e29a..0a3ce23a84 100644 --- a/src/southbridge/amd/common/amd_pci_util.h +++ b/src/southbridge/amd/common/amd_pci_util.h @@ -23,8 +23,6 @@ #define PCI_INTR_INDEX 0xc00 #define PCI_INTR_DATA 0xc01 -#ifndef __PRE_RAM__ - struct pirq_struct { u8 devfn; u8 PIN[4]; /* PINA/B/C/D are index 0/1/2/3 */ @@ -39,6 +37,5 @@ u8 read_pci_int_idx(u8 index, int mode); void write_pci_int_idx(u8 index, int mode, u8 data); void write_pci_cfg_irqs(void); void write_pci_int_table (void); -#endif /* __PRE_RAM */ #endif /* AMD_PCI_UTIL_H */ diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index c8949b055c..4b4b138214 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -72,78 +72,43 @@ smm-y += smi_util.c # # EC ROM should be 64K aligned. +ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1) +else +HUDSON_FWM_POSITION=0xfff20000 +endif -## ifeq ($(CONFIG_HUDSON_PSP), y) -## -### 0 -## ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) FIRMWARE_TYPE= + +PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader.Bypass.sbin +#PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecovery.sbin +#PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs.sbin +#PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin +#TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert endif -## + ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) FIRMWARE_TYPE=CZ + +PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_CZ.sbin +PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_CZ.sbin +PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_CZ.csbin +PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspTrustlets_prod_CZ.cbin +TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/TrustletKey_prod_CZ.sbin +SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_CZ.sbin endif -###5 -PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key -###1 -ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) -PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader$(FIRMWARE_TYPE).Bypass.sbin -else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_$(FIRMWARE_TYPE).sbin -endif - -###3 -ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) -PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecovery$(FIRMWARE_TYPE).sbin -else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_$(FIRMWARE_TYPE).sbin -endif - -###2 -ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) -PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs$(FIRMWARE_TYPE).sbin -else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_$(FIRMWARE_TYPE).csbin -endif - -###4 -PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin - -###8 +#PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key +#PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE)_FN.sbin - -###95 SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin - -###9 -PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key - -###12 -ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) -PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin -else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspTrustlets_prod_$(FIRMWARE_TYPE).cbin -endif - -###13 -ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) -TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert -else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/TrustletKey_prod_$(FIRMWARE_TYPE).sbin -endif - -###18 -ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).sbin -endif +#PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key endif @@ -229,6 +194,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(OPT_2SMUFIRMWARE2_FN_FILE) \ $(OPT_2SMUSCS_FILE) \ --flashsize $(CONFIG_ROM_SIZE) \ + --location $(HUDSON_FWM_POSITION) \ --output $@ ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) diff --git a/src/southbridge/amd/pi/hudson/hda.c b/src/southbridge/amd/pi/hudson/hda.c index 9cdc1b4cd7..8bd54a8f62 100644 --- a/src/southbridge/amd/pi/hudson/hda.c +++ b/src/southbridge/amd/pi/hudson/hda.c @@ -16,7 +16,6 @@ #include #include #include -#include #include "hudson.h" diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 6afcc651e2..9511a6ad24 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -19,7 +19,6 @@ #include #include -#include "chip.h" /* Offsets from ACPI_MMIO_BASE * This is defined by AGESA, but we don't include AGESA headers to avoid @@ -170,14 +169,11 @@ static inline int hudson_ide_enable(void) return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3); } -#ifndef __SMM__ - void pm_write8(u8 reg, u8 value); u8 pm_read8(u8 reg); void pm_write16(u8 reg, u16 value); u16 pm_read16(u16 reg); -#ifdef __PRE_RAM__ void hudson_lpc_port80(void); void hudson_lpc_decode(void); void hudson_pci_port80(void); @@ -191,15 +187,9 @@ void lpc_wideio_16_window(uint16_t base); void hudson_tpm_decode_spi(void); int s3_save_nvram_early(u32 dword, int size, int nvram_pos); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); -#if CONFIG(HUDSON_UART) void configure_hudson_uart(void); -#endif -#else void hudson_enable(struct device *dev); void s3_resume_init_data(void *FchParams); -#endif /* __PRE_RAM__ */ -#endif /* __SMM__ */ - #endif /* HUDSON_H */ diff --git a/src/southbridge/amd/pi/hudson/ide.c b/src/southbridge/amd/pi/hudson/ide.c index 66bb89b91f..aa2b66f8d5 100644 --- a/src/southbridge/amd/pi/hudson/ide.c +++ b/src/southbridge/amd/pi/hudson/ide.c @@ -16,7 +16,6 @@ #include #include #include -#include #include "hudson.h" static void ide_init(struct device *dev) diff --git a/src/southbridge/amd/pi/hudson/imc.c b/src/southbridge/amd/pi/hudson/imc.c index 9ea8172af5..6a01a764cb 100644 --- a/src/southbridge/amd/pi/hudson/imc.c +++ b/src/southbridge/amd/pi/hudson/imc.c @@ -51,7 +51,6 @@ void imc_reg_init(void) pci_write_config8(PCI_DEV(0, 0x18, 0x3), 0x1E4, reg8); } -#ifndef __PRE_RAM__ void enable_imc_thermal_zone(void) { AMD_CONFIG_PARAMS StdHeader; @@ -80,4 +79,3 @@ void enable_imc_thermal_zone(void) WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); WaitForEcLDN9MailboxCmdAck(&StdHeader); } -#endif diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 5354a27822..02123a10b2 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -332,7 +332,11 @@ static void hudson_lpc_enable_resources(struct device *dev) unsigned long acpi_fill_mcfg(unsigned long current) { - /* Just a dummy */ + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, + CONFIG_MMCONF_BASE_ADDRESS, + 0, + 0, + CONFIG_MMCONF_BUS_NUMBER); return current; } diff --git a/src/southbridge/amd/pi/hudson/pci.c b/src/southbridge/amd/pi/hudson/pci.c index 35cd2a95fc..c8e51b1a19 100644 --- a/src/southbridge/amd/pi/hudson/pci.c +++ b/src/southbridge/amd/pi/hudson/pci.c @@ -17,7 +17,6 @@ #include #include #include -#include #include "hudson.h" #include #include diff --git a/src/southbridge/amd/pi/hudson/pcie.c b/src/southbridge/amd/pi/hudson/pcie.c index c765fb6c77..9f7e84b6c8 100644 --- a/src/southbridge/amd/pi/hudson/pcie.c +++ b/src/southbridge/amd/pi/hudson/pcie.c @@ -16,7 +16,6 @@ #include #include #include -#include #include "hudson.h" static void pcie_init(struct device *dev) diff --git a/src/southbridge/amd/pi/hudson/sd.c b/src/southbridge/amd/pi/hudson/sd.c index e4ace38f05..c22b988f53 100644 --- a/src/southbridge/amd/pi/hudson/sd.c +++ b/src/southbridge/amd/pi/hudson/sd.c @@ -18,18 +18,19 @@ #include #include +#include "chip.h" #include "hudson.h" static void sd_init(struct device *dev) { - u32 stepping; + struct southbridge_amd_pi_hudson_config *sd_chip = dev->chip_info; + u32 stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC); + u8 sd_mode = 0; - stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC); + if (sd_chip) + sd_mode = sd_chip->sd_mode; - struct southbridge_amd_pi_hudson_config *sd_chip = - (struct southbridge_amd_pi_hudson_config *)(dev->chip_info); - - if (sd_chip->sd_mode == 3) { /* SD 3.0 mode */ + if (sd_mode == 3) { /* SD 3.0 mode */ pci_write_config32(dev, 0xA4, 0x31FEC8B2); pci_write_config32(dev, 0xA8, 0x00002503); pci_write_config32(dev, 0xB0, 0x02180C19); diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c index 03875679b3..58f5113fa5 100644 --- a/src/southbridge/amd/pi/hudson/sm.c +++ b/src/southbridge/amd/pi/hudson/sm.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/src/southbridge/amd/pi/hudson/smi.c b/src/southbridge/amd/pi/hudson/smi.c index 4180795a73..f8196b4e65 100644 --- a/src/southbridge/amd/pi/hudson/smi.c +++ b/src/southbridge/amd/pi/hudson/smi.c @@ -18,9 +18,10 @@ * Utilities for SMM setup */ -#include "smi.h" - #include +#include + +#include "smi.h" void smm_setup_structures(void *gnvs, void *tcg, void *smi1) { diff --git a/src/southbridge/amd/pi/hudson/smihandler.c b/src/southbridge/amd/pi/hudson/smihandler.c index 1b9442b1b6..6ecb7462f0 100644 --- a/src/southbridge/amd/pi/hudson/smihandler.c +++ b/src/southbridge/amd/pi/hudson/smihandler.c @@ -120,7 +120,7 @@ static void process_smi_0x90(void) smi_write32(0x90, status); } -void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) +void southbridge_smi_handler(void) { const uint16_t smi_src = smi_read16(0x94); diff --git a/src/southbridge/amd/pi/hudson/usb.c b/src/southbridge/amd/pi/hudson/usb.c index f6d01062b0..2f50c3f713 100644 --- a/src/southbridge/amd/pi/hudson/usb.c +++ b/src/southbridge/amd/pi/hudson/usb.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include "hudson.h" diff --git a/src/southbridge/amd/sb700/ide.c b/src/southbridge/amd/sb700/ide.c index 0b11db3c86..070ee67d9c 100644 --- a/src/southbridge/amd/sb700/ide.c +++ b/src/southbridge/amd/sb700/ide.c @@ -22,6 +22,7 @@ #include #include "sb700.h" +#include "chip.h" static void ide_init(struct device *dev) { diff --git a/src/southbridge/amd/sb700/sb700.c b/src/southbridge/amd/sb700/sb700.c index 1836f34eb0..1eaf347dcc 100644 --- a/src/southbridge/amd/sb700/sb700.c +++ b/src/southbridge/amd/sb700/sb700.c @@ -22,6 +22,7 @@ #include #include #include "sb700.h" +#include "chip.h" static struct device *find_sm_dev(struct device *dev, u32 devfn) { diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h index 156522e579..4b863a0778 100644 --- a/src/southbridge/amd/sb700/sb700.h +++ b/src/southbridge/amd/sb700/sb700.h @@ -17,7 +17,8 @@ #ifndef SB700_H #define SB700_H -#include "chip.h" +#include +#include /* Power management index/data registers */ #define BIOSRAM_INDEX 0xcd4 @@ -37,14 +38,12 @@ #define ACPI_CPU_CONTROL (SB700_ACPI_IO_BASE + 0x08) /* 6 bytes */ #define ACPI_CPU_P_LVL2 (ACPI_CPU_CONTROL + 0x4) /* 1 byte */ -extern void pm_iowrite(u8 reg, u8 value); -extern u8 pm_ioread(u8 reg); -extern void pm2_iowrite(u8 reg, u8 value); -extern u8 pm2_ioread(u8 reg); -#ifndef __SIMPLE_DEVICE__ -extern void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, - u32 val); -#endif +void pm_iowrite(u8 reg, u8 value); +u8 pm_ioread(u8 reg); +void pm2_iowrite(u8 reg, u8 value); +u8 pm2_ioread(u8 reg); + +void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val); #define REV_SB700_A11 0x11 #define REV_SB700_A12 0x12 @@ -58,11 +57,7 @@ extern void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, * The differentiate is 0x28, isn't it? */ #define get_sb700_revision(sm_dev) (pci_read_config8((sm_dev), 0x08) - 0x28) -#ifndef __SIMPLE_DEVICE__ -void sb7xx_51xx_enable(struct device *dev); -#endif -#ifdef __PRE_RAM__ void sb7xx_51xx_lpc_port80(void); void sb7xx_51xx_pci_port80(void); void sb7xx_51xx_lpc_init(void); @@ -71,14 +66,12 @@ void sb7xx_51xx_disable_wideio(u8 wio_index); void sb7xx_51xx_early_setup(void); void sb7xx_51xx_before_pci_init(void); uint16_t sb7xx_51xx_decode_last_reset(void); -#else -#include -#include + + /* allow override in mainboard.c */ void sb7xx_51xx_setup_sata_phys(struct device *dev); void sb7xx_51xx_setup_sata_port_indication(void *sata_bar5); - -#endif +void sb7xx_51xx_enable(struct device *dev); void set_lpc_sticky_ctl(bool enable); @@ -86,4 +79,5 @@ int s3_save_nvram_early(u32 dword, int size, int nvram_pos); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn); + #endif /* SB700_H */ diff --git a/src/southbridge/amd/sb800/ide.c b/src/southbridge/amd/sb800/ide.c index fddb48c8d2..77e2f5ef1d 100644 --- a/src/southbridge/amd/sb800/ide.c +++ b/src/southbridge/amd/sb800/ide.c @@ -18,6 +18,7 @@ #include #include #include "sb800.h" +#include "chip.h" static void ide_init(struct device *dev) { diff --git a/src/southbridge/amd/sb800/sata.c b/src/southbridge/amd/sb800/sata.c index 48a8740122..8611272d78 100644 --- a/src/southbridge/amd/sb800/sata.c +++ b/src/southbridge/amd/sb800/sata.c @@ -22,6 +22,7 @@ #include #include #include "sb800.h" +#include "chip.h" static int sata_drive_detect(int portnum, u16 iobar) { diff --git a/src/southbridge/amd/sb800/sb800.c b/src/southbridge/amd/sb800/sb800.c index 801cc65e4a..c7efaec732 100644 --- a/src/southbridge/amd/sb800/sb800.c +++ b/src/southbridge/amd/sb800/sb800.c @@ -23,6 +23,7 @@ #include #include "sb800.h" #include "smbus.h" +#include "chip.h" static struct device *find_sm_dev(struct device *dev, u32 devfn) { diff --git a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h index 3715a3ac1c..07c78ec429 100644 --- a/src/southbridge/amd/sb800/sb800.h +++ b/src/southbridge/amd/sb800/sb800.h @@ -17,7 +17,8 @@ #ifndef SB800_H #define SB800_H -#include "chip.h" +#include +#include /* Power management index/data registers */ #define BIOSRAM_INDEX 0xcd4 @@ -42,15 +43,11 @@ u8 pm_ioread(u8 reg); void pm2_iowrite(u8 reg, u8 value); u8 pm2_ioread(u8 reg); -#ifndef __SIMPLE_DEVICE__ void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val); -#endif #define REV_SB800_A11 0x11 #define REV_SB800_A12 0x12 - -#ifdef __PRE_RAM__ void sb800_lpc_port80(void); void sb800_pci_port80(void); void sb800_clk_output_48Mhz(void); @@ -58,8 +55,6 @@ void sb800_clk_output_48Mhz(void); int s3_save_nvram_early(u32 dword, int size, int nvram_pos); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); -#else void sb800_enable(struct device *dev); -#endif #endif /* SB800_H */ diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index 90ca5641cc..8131e77e5f 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -725,13 +725,6 @@ static void add_ivrs_device_entries(struct device *parent, struct device *dev, struct device *sibling; struct bus *link; - if (!root_level) { - root_level = malloc(sizeof(int8_t)); - if (root_level == NULL) - die("Error: Could not allocate a byte!\n"); - *root_level = -1; - } - if ((dev->path.type == DEVICE_PATH_PCI) && (dev->bus->secondary == 0x0) && (dev->path.pci.devfn == 0x0)) *root_level = depth; @@ -798,9 +791,6 @@ static void add_ivrs_device_entries(struct device *parent, struct device *dev, sibling = sibling->sibling) add_ivrs_device_entries(dev, sibling, depth + 1, depth, root_level, current, length); - - if (depth == 0) - free(root_level); } unsigned long acpi_fill_mcfg(unsigned long current) @@ -879,7 +869,8 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) current += 8; /* Describe PCI devices */ - add_ivrs_device_entries(NULL, all_devices, 0, -1, NULL, ¤t, + int8_t root_level = -1; + add_ivrs_device_entries(NULL, all_devices, 0, -1, &root_level, ¤t, &ivrs->ivhd.length); /* Describe IOAPICs */ diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.h b/src/southbridge/broadcom/bcm5785/bcm5785.h index 4517ddad0c..e1c6f66191 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.h +++ b/src/southbridge/broadcom/bcm5785/bcm5785.h @@ -20,11 +20,8 @@ #include #include "chip.h" -#ifndef __PRE_RAM__ void bcm5785_enable(struct device *dev); -#else void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); -#endif void bcm5785_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device); diff --git a/src/southbridge/broadcom/bcm5785/ide.c b/src/southbridge/broadcom/bcm5785/ide.c index 2932a236bb..c143c22a53 100644 --- a/src/southbridge/broadcom/bcm5785/ide.c +++ b/src/southbridge/broadcom/bcm5785/ide.c @@ -17,7 +17,6 @@ #include #include #include -#include #include "bcm5785.h" static void bcm5785_ide_read_resources(struct device *dev) diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c index 759cb5d898..318086e7bf 100644 --- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c +++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index e3379d6af0..744fe7d6a6 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -23,6 +23,8 @@ #include #include #include + +#include "chip.h" #include "pch.h" #define HDA_ICII_REG 0x68 diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index bd3c993912..592c70f8b4 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -32,6 +32,7 @@ #include #include #include +#include "chip.h" #include "pch.h" #include "nvs.h" #include diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index 270886485d..203d0c038b 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -238,17 +238,14 @@ typedef enum { /* Defined in me_status.c for both romstage and ramstage */ void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes); -#ifdef __PRE_RAM__ void intel_early_me_status(void); int intel_early_me_init(void); int intel_early_me_uma_size(void); int intel_early_me_init_done(u8 status); -#endif -#ifdef __SMM__ void intel_me_finalize_smm(void); void intel_me8_finalize_smm(void); -#endif + typedef struct { u32 major_version : 16; u32 minor_version : 16; diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index e4eccd766d..475def33e4 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -24,9 +24,11 @@ #include #endif #include -#include "pch.h" #include +#include "chip.h" +#include "pch.h" + int pch_silicon_revision(void) { static int pch_revision_id = -1; diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index bc6c8b333f..fcb15ac99e 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -56,20 +56,19 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 -#if !defined(__ASSEMBLER__) -#if !defined(__PRE_RAM__) -#if !defined(__SIMPLE_DEVICE__) -#include "chip.h" -void pch_enable(struct device *dev); -#endif + int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -#else /* __PRE_RAM__ */ + void enable_smbus(void); void enable_usb_bar(void); + +#if ENV_ROMSTAGE int smbus_read_byte(unsigned device, unsigned address); +#endif + void early_thermal_init(void); void southbridge_configure_default_intmap(void); void southbridge_rcba_config(void); @@ -87,14 +86,11 @@ struct southbridge_usb_port }; #ifndef __ROMCC__ +void pch_enable(struct device *dev); extern const struct southbridge_usb_port mainboard_usb_ports[14]; #endif -void -early_usb_init (const struct southbridge_usb_port *portmap); - -#endif -#endif +void early_usb_init(const struct southbridge_usb_port *portmap); /* PM I/O Space */ #define UPRWC 0x3c diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index 2186287df2..6391de409c 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -77,7 +77,7 @@ static void ich_pci_bus_enable_resources(struct device *dev) dev->command |= PCI_COMMAND_IO; ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); ctrl |= dev->link_list->bridge_ctrl; - ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */ + ctrl |= (PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR); /* error check */ printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 97306e44cb..686930d80a 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -22,6 +22,8 @@ #include #include #include + +#include "chip.h" #include "pch.h" static void pch_pcie_pm_early(struct device *dev) diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 6a39873e7b..3ec065f287 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -24,6 +24,7 @@ #include #include +#include "chip.h" #include "pch.h" typedef struct southbridge_intel_bd82x6x_config config_t; diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 374a9d933e..ceac5982a3 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c index 85e450db5b..55c8948063 100644 --- a/src/southbridge/intel/bd82x6x/usb_xhci.c +++ b/src/southbridge/intel/bd82x6x/usb_xhci.c @@ -21,6 +21,7 @@ #include "pch.h" #include #include +#include "chip.h" static void usb_xhci_init(struct device *dev) { diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index 898ab60770..e7060361bd 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -31,6 +31,16 @@ ifneq ($(call strip_quotes,$(CONFIG_IFD_CHIPSET)),) IFDTOOL_USE_CHIPSET := -p $(CONFIG_IFD_CHIPSET) endif +add_intel_firmware: $(call strip_quotes,$(CONFIG_IFD_BIN_PATH)) +ifeq ($(CONFIG_HAVE_ME_BIN),y) +add_intel_firmware: $(call strip_quotes,$(CONFIG_ME_BIN_PATH)) +endif +ifeq ($(CONFIG_HAVE_GBE_BIN),y) +add_intel_firmware: $(call strip_quotes,$(CONFIG_GBE_BIN_PATH)) +endif +ifeq ($(CONFIG_HAVE_EC_BIN),y) +add_intel_firmware: $(call strip_quotes,$(CONFIG_EC_BIN_PATH)) +endif add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL) printf " DD Adding Intel Firmware Descriptor\n" dd if=$(IFD_BIN_PATH) \ diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c index 16ae3c6557..f7f08c8db1 100644 --- a/src/southbridge/intel/common/pmutil.c +++ b/src/southbridge/intel/common/pmutil.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index eb74aa57ce..cea5c82502 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -18,6 +18,7 @@ #define INTEL_COMMON_PMUTIL_H #include +#include #define D31F0_PMBASE 0x40 #define D31F0_GEN_PMCON_1 0xa0 diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index 398c6804e0..1348174389 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include @@ -34,7 +34,7 @@ u16 get_pmbase(void) return lpc_get_pmbase(); } -void southbridge_smm_init(void) +void smm_southbridge_enable_smi(void) { u32 smi_en; u16 pm1_en; @@ -123,7 +123,7 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1) ); } -void southbridge_smm_clear_state(void) +void smm_southbridge_clear_state(void) { u32 smi_en; diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 1479572452..d61238c865 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -500,14 +501,8 @@ static smi_handler_t southbridge_smi[32] = { /** * @brief Interrupt handler for SMI# - * @param node - * @param state_save */ -#if CONFIG(SMM_TSEG) void southbridge_smi_handler(void) -#else -void cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save) -#endif { int i, dump = 0; u32 smi_sts; diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 0095dd9ccb..268030b9c8 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -16,6 +16,7 @@ */ /* This file is derived from the flashrom project. */ +#include #include #include #include @@ -109,7 +110,7 @@ struct ich_spi_controller { uint8_t fpr_max; }; -static struct ich_spi_controller g_cntlr; +static struct ich_spi_controller g_cntlr CAR_GLOBAL; enum { SPIS_SCIP = 0x0001, @@ -254,7 +255,7 @@ static void read_reg(const void *src, void *value, uint32_t size) static void ich_set_bbar(uint32_t minaddr) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); const uint32_t bbar_mask = 0x00ffff00; uint32_t ichspi_bbar; @@ -264,9 +265,15 @@ static void ich_set_bbar(uint32_t minaddr) writel_(ichspi_bbar, cntlr->bbar); } +#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) +#define MENU_BYTES member_size(struct ich7_spi_regs, opmenu) +#else +#define MENU_BYTES member_size(struct ich9_spi_regs, opmenu) +#endif + void spi_init(void) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; @@ -408,9 +415,9 @@ static void spi_setup_type(spi_transaction *trans) static int spi_setup_opcode(spi_transaction *trans) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t optypes; - uint8_t opmenu[cntlr->menubytes]; + uint8_t opmenu[MENU_BYTES]; trans->opcode = trans->out[0]; spi_use_out(trans, 1); @@ -432,13 +439,12 @@ static int spi_setup_opcode(spi_transaction *trans) return 0; read_reg(cntlr->opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < cntlr->menubytes; - opcode_index++) { + for (opcode_index = 0; opcode_index < ARRAY_SIZE(opmenu); opcode_index++) { if (opmenu[opcode_index] == trans->opcode) break; } - if (opcode_index == cntlr->menubytes) { + if (opcode_index == ARRAY_SIZE(opmenu)) { printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", trans->opcode); return -1; @@ -489,7 +495,7 @@ static int spi_setup_offset(spi_transaction *trans) */ static int ich_status_poll(u16 bitmask, int wait_til_set) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); int timeout = 600000; /* This will result in 6 seconds */ u16 status = 0; @@ -510,7 +516,7 @@ static int ich_status_poll(u16 bitmask, int wait_til_set) static int spi_is_multichip(void) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); if (!(cntlr->hsfs & HSFS_FDV)) return 0; return !!((cntlr->flmap0 >> 8) & 3); @@ -519,7 +525,7 @@ static int spi_is_multichip(void) static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t control; int16_t opcode_index; int with_address; @@ -669,7 +675,7 @@ spi_xfer_exit: /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ static void ich_hwseq_set_addr(uint32_t addr) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint32_t addr_old = readl_(&cntlr->ich9_spi->faddr) & ~0x01FFFFFF; writel_((addr & 0x01FFFFFF) | addr_old, &cntlr->ich9_spi->faddr); @@ -682,7 +688,7 @@ static void ich_hwseq_set_addr(uint32_t addr) static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, unsigned int len) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t hsfs; uint32_t addr; @@ -722,7 +728,7 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset, size_t len) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); u32 start, end, erase_size; int ret; uint16_t hsfc; @@ -772,7 +778,7 @@ out: static void ich_read_data(uint8_t *data, int len) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); int i; uint32_t temp32 = 0; @@ -787,7 +793,7 @@ static void ich_read_data(uint8_t *data, int len) static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len, void *buf) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t hsfc; uint16_t timeout = 100 * 60; uint8_t block_len; @@ -833,7 +839,7 @@ static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len, */ static void ich_fill_data(const uint8_t *data, int len) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint32_t temp32 = 0; int i; @@ -857,7 +863,7 @@ static void ich_fill_data(const uint8_t *data, int len) static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len, const void *buf) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t hsfc; uint16_t timeout = 100 * 60; uint8_t block_len; @@ -913,7 +919,7 @@ static const struct spi_flash_ops spi_flash_ops = { static int spi_flash_programmer_probe(const struct spi_slave *spi, struct spi_flash *flash) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) return spi_flash_generic_probe(spi, flash); @@ -993,7 +999,7 @@ static int spi_flash_protect(const struct spi_flash *flash, const struct region *region, const enum ctrlr_prot_type type) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); u32 start = region_offset(region); u32 end = start + region_sz(region) - 1; u32 reg; @@ -1051,7 +1057,7 @@ static int spi_flash_protect(const struct spi_flash *flash, void spi_finalize_ops(void) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); u16 spi_opprefix; u16 optype = 0; struct intel_swseq_spi_config spi_config = { diff --git a/src/southbridge/intel/fsp_rangeley/acpi.c b/src/southbridge/intel/fsp_rangeley/acpi.c index aeb2d9b3bb..5605d41bc7 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi.c +++ b/src/southbridge/intel/fsp_rangeley/acpi.c @@ -22,6 +22,7 @@ #include #include #include +#include "chip.h" /** diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index af2e411584..be7913c06a 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -28,10 +28,11 @@ #include #include #include -#include +#include #include #include #include +#include "chip.h" #include "soc.h" #include "irq.h" #include "nvs.h" diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 2c2427eed1..f52a75205a 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -31,6 +31,7 @@ #include "southbridge/intel/fsp_rangeley/gpio.h" #include "southbridge/intel/fsp_rangeley/romstage.h" #include +#include #include "gpio.h" void main(FSP_INFO_HEADER *fsp_info_header) @@ -121,9 +122,11 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { *(u32*)cbmem_hob_ptr = (u32)hob_list_ptr; post_code(0x4e); - post_code(0x4f); + if (CONFIG(SMM_TSEG)) + smm_list_regions(); /* Load the ramstage. */ + post_code(0x4f); run_ramstage(); while (1); } diff --git a/src/southbridge/intel/fsp_rangeley/romstage.h b/src/southbridge/intel/fsp_rangeley/romstage.h index 5827b0fe9b..7921d8041b 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.h +++ b/src/southbridge/intel/fsp_rangeley/romstage.h @@ -17,10 +17,6 @@ #ifndef _RANGELEY_ROMSTAGE_H_ #define _RANGELEY_ROMSTAGE_H_ -#if !defined(__PRE_RAM__) -#error "Don't include romstage.h from a ramstage compilation unit!" -#endif - #include #include diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c index 58388a2fab..604c56636a 100644 --- a/src/southbridge/intel/fsp_rangeley/sata.c +++ b/src/southbridge/intel/fsp_rangeley/sata.c @@ -21,6 +21,7 @@ #include #include #include +#include "chip.h" #include "soc.h" typedef struct southbridge_intel_fsp_rangeley_config config_t; diff --git a/src/southbridge/intel/fsp_rangeley/smbus.c b/src/southbridge/intel/fsp_rangeley/smbus.c index 83533f1d03..610ce0cb85 100644 --- a/src/southbridge/intel/fsp_rangeley/smbus.c +++ b/src/southbridge/intel/fsp_rangeley/smbus.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include "soc.h" diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h index aceb425ab7..ce5e056514 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ b/src/southbridge/intel/fsp_rangeley/soc.h @@ -47,29 +47,26 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 -#if defined(__SMM__) && !defined(__ASSEMBLER__) void intel_soc_finalize_smm(void); + +#if !defined(__ROMCC__) +#include +void soc_enable(struct device *dev); +void acpi_fill_in_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt); #endif -#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) -#if !defined(__PRE_RAM__) && !defined(__SMM__) -#include "chip.h" int soc_silicon_revision(void); int soc_silicon_type(void); int soc_silicon_supported(int type, int rev); -void soc_enable(struct device *dev); -void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt); -#if CONFIG(ELOG) void soc_log_state(void); -#endif -#else void enable_smbus(void); void enable_usb_bar(void); -int smbus_read_byte(unsigned device, unsigned address); void rangeley_sb_early_initialization(void); -#endif + +#if ENV_ROMSTAGE +int smbus_read_byte(unsigned int device, unsigned int address); #endif #define MAINBOARD_POWER_OFF 0 diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index afd89a7dba..d2f2a0bd32 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -310,6 +310,8 @@ static inline int get_ich_version(uint16_t device_id) return 0; } +#define MENU_BYTES member_size(struct ich10_spi_regs, opmenu) + void spi_init(void) { int ich_version = 0; @@ -444,7 +446,7 @@ static void spi_setup_type(spi_transaction *trans) static int spi_setup_opcode(spi_transaction *trans) { uint16_t optypes; - uint8_t opmenu[cntlr.menubytes]; + uint8_t opmenu[MENU_BYTES]; trans->opcode = trans->out[0]; spi_use_out(trans, 1); @@ -465,13 +467,12 @@ static int spi_setup_opcode(spi_transaction *trans) return 0; read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < cntlr.menubytes; - opcode_index++) { + for (opcode_index = 0; opcode_index < ARRAY_SIZE(opmenu); opcode_index++) { if (opmenu[opcode_index] == trans->opcode) break; } - if (opcode_index == cntlr.menubytes) { + if (opcode_index == ARRAY_SIZE(opmenu)) { printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", trans->opcode); return -1; diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 5e0ff3f418..77931cb20c 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -17,18 +17,22 @@ #ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H #define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H -#if !defined(__ASSEMBLER__) && !defined(__ACPI__) -#if !defined(__PRE_RAM__) -#include -#include "chip.h" +#if !defined(__ACPI__) +#ifndef __ROMCC__ +#include void i82371eb_enable(struct device *dev); -void i82371eb_hard_reset(void); -#else -void enable_smbus(void); -int smbus_read_byte(u8 device, u8 address); -void enable_pm(void); #endif + +void i82371eb_hard_reset(void); + +void enable_smbus(void); +void enable_pm(void); + +#if ENV_ROMSTAGE +int smbus_read_byte(u8 device, u8 address); +#endif + #endif /* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the diff --git a/src/southbridge/intel/i82371eb/ide.c b/src/southbridge/intel/i82371eb/ide.c index 33f7ac7569..7a72a6552d 100644 --- a/src/southbridge/intel/i82371eb/ide.c +++ b/src/southbridge/intel/i82371eb/ide.c @@ -22,6 +22,7 @@ #include #include #include +#include "chip.h" #include "i82371eb.h" /** diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c index afc4d6ac1e..36a9f560fc 100644 --- a/src/southbridge/intel/i82371eb/smbus.c +++ b/src/southbridge/intel/i82371eb/smbus.c @@ -26,6 +26,7 @@ #include #include #include +#include "chip.h" #include "i82371eb.h" static void pwrmgt_enable(struct device *dev) diff --git a/src/southbridge/intel/i82801dx/ide.c b/src/southbridge/intel/i82801dx/ide.c index 51e2c8910c..2881cc0333 100644 --- a/src/southbridge/intel/i82801dx/ide.c +++ b/src/southbridge/intel/i82801dx/ide.c @@ -19,6 +19,7 @@ #include #include #include +#include "chip.h" #include "i82801dx.h" typedef struct southbridge_intel_i82801dx_config config_t; diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 94d8e14eb3..2daed4a7ab 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -26,6 +26,7 @@ #include #include #include +#include "chip.h" #include "i82801dx.h" #define NMI_OFF 0 diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c index 7dfed9d946..521b98db04 100644 --- a/src/southbridge/intel/i82801dx/smi.c +++ b/src/southbridge/intel/i82801dx/smi.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include "i82801dx.h" diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 18dc4d8705..d9720e0c0c 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -268,7 +268,7 @@ static void busmaster_disable_on_bus(int bus) } -static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_sleep(void) { u8 reg8; u32 reg32; @@ -341,7 +341,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat } } -static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_apmc(void) { u32 pmctrl; u8 reg8; @@ -403,7 +403,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state } } -static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_pm1(void) { u16 pm1_sts; @@ -421,7 +421,7 @@ static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_ } } -static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_gpe0(void) { u32 gpe0_sts; @@ -429,7 +429,7 @@ static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state dump_gpe0_status(gpe0_sts); } -static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_gpi(void) { u16 reg16; reg16 = inw(pmbase + ALT_GP_SMI_STS); @@ -443,7 +443,7 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); } -static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_mc(void) { u32 reg32; @@ -458,7 +458,7 @@ static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_s -static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_tco(void) { u32 tco_sts; @@ -495,7 +495,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_ } } -static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_periodic(void) { u32 reg32; @@ -508,7 +508,7 @@ static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *s printk(BIOS_DEBUG, "Periodic SMI.\n"); } -static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_monitor(void) { #define IOTRAP(x) (trap_sts & (1 << x)) #if 0 @@ -564,8 +564,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st #undef IOTRAP } -typedef void (*smi_handler_t)(unsigned int node, - smm_state_save_area_t *state_save); +typedef void (*smi_handler_t)(void); smi_handler_t southbridge_smi[32] = { NULL, // [0] reserved @@ -604,10 +603,8 @@ smi_handler_t southbridge_smi[32] = { /** * @brief Interrupt handler for SMI# - * @param node - * @param state_save */ -void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) +void southbridge_smi_handler(void) { int i, dump = 0; u32 smi_sts; @@ -627,9 +624,9 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav /* Call SMI sub handler for each of the status bits */ for (i = 0; i < 31; i++) { if (smi_sts & (1 << i)) { - if (southbridge_smi[i]) - southbridge_smi[i](node, state_save); - else { + if (southbridge_smi[i]) { + southbridge_smi[i](); + } else { printk(BIOS_DEBUG, "SMI_STS[%d] occurred, but no " "handler available.\n", i); dump = 1; @@ -640,5 +637,4 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav if (dump) { dump_smi_status(smi_sts); } - } diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 938dc4edd6..56baab1edc 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -22,6 +22,7 @@ #include #include #include +#include "chip.h" #include "i82801gx.h" #define HDA_ICII_REG 0x68 diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index fb855dc743..7fc0114aac 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -34,13 +34,14 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 -#if !defined(__ASSEMBLER__) -#if !defined(__PRE_RAM__) -#if !defined(__SIMPLE_DEVICE__) +#ifndef __ROMCC__ +#include void i82801gx_enable(struct device *dev); #endif -#else + void enable_smbus(void); + +#if ENV_ROMSTAGE int smbus_read_byte(unsigned int device, unsigned int address); int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes, u8 *buf); @@ -48,7 +49,6 @@ int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf); #endif -#endif #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index 22c516581f..1d1f902727 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -76,7 +76,7 @@ static void ich_pci_bus_enable_resources(struct device *dev) dev->command |= PCI_COMMAND_IO; ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); ctrl |= dev->link_list->bridge_ctrl; - ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */ + ctrl |= (PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR); /* error check */ printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c index 693c2dc96d..b2341a11d1 100644 --- a/src/southbridge/intel/i82801gx/smbus.c +++ b/src/southbridge/intel/i82801gx/smbus.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include "i82801gx.h" diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 31306fbe31..16ceb13e7e 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -16,7 +16,6 @@ #include #include -#include #include #include #include diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c index 16350d534e..f105a735f8 100644 --- a/src/southbridge/intel/i82801ix/hdaudio.c +++ b/src/southbridge/intel/i82801ix/hdaudio.c @@ -23,6 +23,7 @@ #include #include #include +#include "chip.h" #include "i82801ix.h" #define HDA_ICII_REG 0x68 diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index 99078dc402..341a98aec4 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -22,6 +22,7 @@ #include #include #include +#include "chip.h" #include "i82801ix.h" typedef struct southbridge_intel_i82801ix_config config_t; diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index 31eabb6e42..afaaade82d 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -18,12 +18,6 @@ #ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801IX_H #define SOUTHBRIDGE_INTEL_I82801GX_I82801IX_H -#ifndef __ACPI__ -#ifndef __ASSEMBLER__ -#include "chip.h" -#endif -#endif - #define DEFAULT_TBAR ((u8 *)0xfed1b000) #include @@ -214,12 +208,13 @@ static inline int lpc_is_mobile(const u16 devid) void aseg_smm_lock(void); -#if defined(__PRE_RAM__) void enable_smbus(void); -int smbus_read_byte(unsigned device, unsigned address); void i82801ix_early_init(void); void i82801ix_dmi_setup(void); void i82801ix_dmi_poll_vc1(void); + +#if ENV_ROMSTAGE +int smbus_read_byte(unsigned device, unsigned address); #endif #endif diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index ba2b0282e5..cb964de35f 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -30,6 +30,7 @@ #include #include #include +#include "chip.h" #include "i82801ix.h" #include "nvs.h" #include diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index 49d2d36b85..fa6c1df6b3 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -25,6 +25,7 @@ #include #include +#include "chip.h" #include "i82801ix.h" typedef struct southbridge_intel_i82801ix_config config_t; diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index 5d898cc3c6..0a80dd2ccf 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include "i82801ix.h" diff --git a/src/southbridge/intel/i82801jx/hdaudio.c b/src/southbridge/intel/i82801jx/hdaudio.c index c2a505b613..0628c435a9 100644 --- a/src/southbridge/intel/i82801jx/hdaudio.c +++ b/src/southbridge/intel/i82801jx/hdaudio.c @@ -23,6 +23,7 @@ #include #include #include +#include "chip.h" #include "i82801jx.h" #define HDA_ICII_REG 0x68 diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c index ec5576d381..490ece73f0 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.c +++ b/src/southbridge/intel/i82801jx/i82801jx.c @@ -22,6 +22,7 @@ #include #include #include +#include "chip.h" #include "i82801jx.h" typedef struct southbridge_intel_i82801jx_config config_t; diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 80d6cbd04f..28c9f68ea2 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -18,12 +18,6 @@ #ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801JX_H #define SOUTHBRIDGE_INTEL_I82801GX_I82801JX_H -#ifndef __ACPI__ -#ifndef __ASSEMBLER__ -#include "chip.h" -#endif -#endif - #define DEFAULT_TBAR ((u8 *)0xfed1b000) #include @@ -222,7 +216,6 @@ #ifndef __ACPI__ -#ifndef __ASSEMBLER__ #include @@ -232,7 +225,7 @@ static inline int lpc_is_mobile(const u16 devid) } #define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID)) -#if defined(__PRE_RAM__) +#if ENV_ROMSTAGE void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes, @@ -242,7 +235,6 @@ int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf); #endif -#endif #endif #endif diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 0fcb521430..6c63186336 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -31,6 +31,7 @@ #include #include #include +#include "chip.h" #include "i82801jx.h" #include "nvs.h" #include diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index ddaa783868..e6e08a31a4 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -25,6 +25,7 @@ #include #include +#include "chip.h" #include "i82801jx.h" typedef struct southbridge_intel_i82801jx_config config_t; diff --git a/src/southbridge/intel/i82870/Makefile.inc b/src/southbridge/intel/i82870/Makefile.inc index 790bd01513..d6ae171926 100644 --- a/src/southbridge/intel/i82870/Makefile.inc +++ b/src/southbridge/intel/i82870/Makefile.inc @@ -2,6 +2,5 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82870),y) ramstage-y += ioapic.c ramstage-y += pcibridge.c -#ramstage-y += pci_parity.c endif diff --git a/src/southbridge/intel/i82870/pci_parity.c b/src/southbridge/intel/i82870/pci_parity.c deleted file mode 100644 index 3bb05ccf03..0000000000 --- a/src/southbridge/intel/i82870/pci_parity.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -# - -void p64h2_pci_parity_enable(void) -{ - uint8_t reg; - - /* 2SERREN - SERR enable for PCI bridge secondary device */ - /* 2PEREN - Parity error for PCI bridge secondary device */ - pcibios_read_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, ®); - reg |= ((1 << 1) + (1 << 0)); - pcibios_write_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, reg); - - /* 2SERREN - SERR enable for PCI bridge secondary device */ - /* 2PEREN - Parity error for PCI bridge secondary device */ - pcibios_read_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, ®); - reg |= ((1 << 1) + (1 << 0)); - pcibios_write_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, reg); - - return; -} diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index fccb3a8656..83d083f3ae 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -37,7 +37,10 @@ ramstage-y += madt.c smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/pch.c -romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../common/gpio.c early_thermal.c +romstage-y += early_smbus.c +romstage-y +=../bd82x6x/early_me.c +romstage-y +=../bd82x6x/me_status.c +romstage-y += early_thermal.c romstage-y += ../bd82x6x/early_rcba.c endif diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index c7464a05f1..3e1f4a4350 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -34,6 +34,7 @@ #include #include #include +#include "chip.h" #include "pch.h" #include "nvs.h" #include @@ -265,10 +266,11 @@ static void pch_power_options(struct device *dev) outl(reg32, pmbase + 0x04); /* Clear magic status bits to prevent unexpected wake */ - reg32 = RCBA32(0x3310); - reg32 |= (1 << 4)|(1 << 5)|(1 << 0); - RCBA32(0x3310) = reg32; + reg32 = RCBA32(PRSTS); + reg32 |= (1 << 5) | (1 << 4) | (1 << 0); + RCBA32(PRSTS) = reg32; + /* FIXME: Does this even exist? */ reg32 = RCBA32(0x3f02); reg32 &= ~0xf; RCBA32(0x3f02) = reg32; diff --git a/src/southbridge/intel/ibexpeak/me.h b/src/southbridge/intel/ibexpeak/me.h index be65cc5454..5694dd763b 100644 --- a/src/southbridge/intel/ibexpeak/me.h +++ b/src/southbridge/intel/ibexpeak/me.h @@ -239,17 +239,14 @@ typedef enum { /* Defined in me_status.c for both romstage and ramstage */ void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes); -#ifdef __PRE_RAM__ void intel_early_me_status(void); int intel_early_me_init(void); int intel_early_me_uma_size(void); int intel_early_me_init_done(u8 status); -#endif -#ifdef __SMM__ void intel_me_finalize_smm(void); void intel_me8_finalize_smm(void); -#endif + typedef struct { u32 major_version : 16; u32 minor_version : 16; diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 24a7905ed2..e7cc9d2c7c 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -51,29 +51,26 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 -#if !defined(__ASSEMBLER__) -#if !defined(__PRE_RAM__) -#if !defined(__SIMPLE_DEVICE__) -#include "chip.h" -void pch_enable(struct device *dev); -#endif int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -#if CONFIG(ELOG) -void pch_log_state(void); -#endif -#else /* __PRE_RAM__ */ void enable_smbus(void); void enable_usb_bar(void); + +#if ENV_ROMSTAGE int smbus_read_byte(unsigned device, unsigned address); int smbus_write_byte(unsigned device, unsigned address, u8 data); int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf); +#endif + void early_thermal_init(void); void southbridge_configure_default_intmap(void); -#endif + +#ifndef __ROMCC__ +#include +void pch_enable(struct device *dev); #endif #define MAINBOARD_POWER_OFF 0 @@ -355,6 +352,8 @@ void southbridge_configure_default_intmap(void); #define SOFT_RESET_CTRL 0x38f4 #define SOFT_RESET_DATA 0x38f8 +#define PRSTS 0x3310 + #define DIR_ROUTE(x,a,b,c,d) \ RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ ((b) << DIR_IBR) | ((a) << DIR_IAR)) diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index e03f8b5884..c99e944513 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -25,6 +25,7 @@ #include #include +#include "chip.h" #include "pch.h" typedef struct southbridge_intel_ibexpeak_config config_t; diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 208075bbea..36688422a6 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c index 31b2cb6084..597d388b9d 100644 --- a/src/southbridge/intel/ibexpeak/thermal.c +++ b/src/southbridge/intel/ibexpeak/thermal.c @@ -20,7 +20,6 @@ #include #include "pch.h" #include -#include static void thermal_init(struct device *dev) { diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index b91ab15339..e56b32b9ec 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -117,6 +117,5 @@ struct southbridge_intel_lynxpoint_config { bool docking_supported; }; -extern struct chip_operations southbridge_intel_lynxpoint_ops; #endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */ diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index c36257747d..25ffdc495d 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -124,10 +124,7 @@ int early_pch_init(const void *gpio_map, wake_from_s3 = southbridge_detect_s3_resume(); -#if CONFIG(ELOG_BOOT_COUNT) - if (!wake_from_s3) - boot_count_increment(); -#endif + elog_boot_notify(wake_from_s3); /* Report if we are waking from s3. */ return wake_from_s3; diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c index e3d8f02805..bc8d8a1630 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.c +++ b/src/southbridge/intel/lynxpoint/lp_gpio.c @@ -24,7 +24,7 @@ static u16 get_gpio_base(void) { -#if defined(__PRE_RAM__) || defined(__SMM__) +#ifdef __SIMPLE_DEVICE__ return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; #else return pci_read_config16(pcidev_on_root(0x1f, 0), diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 84032cadd2..28e3544910 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -30,6 +30,7 @@ #include #include #include +#include "chip.h" #include "nvs.h" #include "pch.h" #include diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h index 775b4eced6..3b4bd510ca 100644 --- a/src/southbridge/intel/lynxpoint/me.h +++ b/src/southbridge/intel/lynxpoint/me.h @@ -326,17 +326,13 @@ typedef enum { /* Defined in me_status.c for both romstage and ramstage */ void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2); -#ifdef __PRE_RAM__ void intel_early_me_status(void); int intel_early_me_init(void); int intel_early_me_uma_size(void); int intel_early_me_init_done(u8 status); -#endif -#ifdef __SMM__ void intel_me_finalize_smm(void); void intel_me8_finalize_smm(void); -#endif /* * ME to BIOS Payload Datastructures and definitions. The ordering of the diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 09eeff26c3..8d86e68227 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -35,6 +35,7 @@ #include #include +#include "chip.h" #include "me.h" #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 626d22d57f..3f37887567 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -88,13 +88,10 @@ #ifndef __ACPI__ -#if defined(__SMM__) && !defined(__ASSEMBLER__) void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); void usb_ehci_disable(pci_devfn_t dev); void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); void usb_xhci_route_all(void); -#endif - /* State Machine configuration. */ #define RCBA_REG_SIZE_MASK 0x8000 @@ -135,7 +132,6 @@ struct rcba_config_instruction u32 or_value; }; -#if !defined(__ASSEMBLER__) void pch_config_rcba(const struct rcba_config_instruction *rcba_config); int pch_silicon_revision(void); int pch_silicon_id(void); @@ -169,38 +165,26 @@ void disable_all_gpe(void); void enable_gpe(u32 mask); void disable_gpe(u32 mask); -#if !defined(__PRE_RAM__) && !defined(__SMM__) -#include -#include "chip.h" void pch_enable(struct device *dev); void pch_disable_devfn(struct device *dev); u32 pch_iobp_read(u32 address); void pch_iobp_write(u32 address, u32 data); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -#if CONFIG(ELOG) void pch_log_state(void); -#endif void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); -/* These helpers are for performing SMM relocation. */ -void southbridge_trigger_smi(void); -void southbridge_clear_smi_status(void); -/* The initialization of the southbridge is split into 2 compoments. One is - * for clearing the state in the SMM registers. The other is for enabling - * SMIs. They are split so that other work between the 2 actions. */ -void southbridge_smm_clear_state(void); -void southbridge_smm_enable_smi(void); -#else void enable_smbus(void); -void enable_usb_bar(void); + +#if ENV_ROMSTAGE int smbus_read_byte(unsigned device, unsigned address); +#endif + +void enable_usb_bar(void); int early_pch_init(const void *gpio_map, const struct rcba_config_instruction *rcba_config); void pch_enable_lpc(void); void mainboard_config_superio(void); -#endif /* !__PRE_RAM__ && !__SMM__ */ -#endif /* __ASSEMBLER__ */ #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 2a8b44e0fc..a3b2e096d8 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -26,6 +26,7 @@ #include #include #include +#include "chip.h" #define MAX_NUM_ROOT_PORTS 8 diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index fd611ea2ca..aae48e7426 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -21,6 +21,7 @@ #include #include #include +#include "chip.h" #include "pch.h" typedef struct southbridge_intel_lynxpoint_config config_t; diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 23d8125d7f..b5ccfa6338 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -22,6 +22,7 @@ #include #include #include +#include "chip.h" #include "pch.h" #include "nvs.h" diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 3a6c4038c8..4fb00b507a 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -19,12 +19,13 @@ #include #include #include +#include #include #include #include "pch.h" -void southbridge_smm_clear_state(void) +void smm_southbridge_clear_state(void) { u32 smi_en; @@ -50,7 +51,7 @@ void southbridge_smm_clear_state(void) clear_gpe_status(); } -void southbridge_smm_enable_smi(void) +void smm_southbridge_enable_smi(void) { printk(BIOS_DEBUG, "Enabling SMIs.\n"); /* Configure events */ @@ -68,7 +69,7 @@ void southbridge_smm_enable_smi(void) enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); } -void southbridge_trigger_smi(void) +static void __unused southbridge_trigger_smi(void) { /** * There are several methods of raising a controlled SMI# via @@ -88,7 +89,7 @@ void southbridge_trigger_smi(void) outb(0x00, 0xb2); } -void southbridge_clear_smi_status(void) +static void __unused southbridge_clear_smi_status(void) { /* Clear SMI status */ clear_smi_status(); diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 88c599f782..de2866e08c 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index ddba351aae..686e06a6a9 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -21,6 +21,7 @@ #include #include #include +#include "chip.h" #include "pch.h" typedef struct southbridge_intel_lynxpoint_config config_t; diff --git a/src/southbridge/nvidia/ck804/ac97.c b/src/southbridge/nvidia/ck804/ac97.c index f7c6f42e59..28c5e74b2e 100644 --- a/src/southbridge/nvidia/ck804/ac97.c +++ b/src/southbridge/nvidia/ck804/ac97.c @@ -17,7 +17,6 @@ #include #include #include -#include #include "chip.h" static struct device_operations ac97audio_ops = { diff --git a/src/southbridge/nvidia/ck804/ck804.h b/src/southbridge/nvidia/ck804/ck804.h index 5505691d1c..6812b5b653 100644 --- a/src/southbridge/nvidia/ck804/ck804.h +++ b/src/southbridge/nvidia/ck804/ck804.h @@ -26,8 +26,6 @@ #define CK804B_BUSN 0x80 #define CK804B_DEVN_BASE (!CONFIG(SB_HT_CHAIN_UNITID_OFFSET_ONLY) ? CK804_DEVN_BASE : 1) -#ifdef __PRE_RAM__ void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); -#endif #endif diff --git a/src/southbridge/nvidia/ck804/smbus.c b/src/southbridge/nvidia/ck804/smbus.c index 2d223fdf83..b96dc6e6d4 100644 --- a/src/southbridge/nvidia/ck804/smbus.c +++ b/src/southbridge/nvidia/ck804/smbus.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include "chip.h" #include "smbus.h" diff --git a/src/southbridge/nvidia/ck804/smbus.h b/src/southbridge/nvidia/ck804/smbus.h index cec62b3f49..bf0ff3c719 100644 --- a/src/southbridge/nvidia/ck804/smbus.h +++ b/src/southbridge/nvidia/ck804/smbus.h @@ -49,7 +49,9 @@ static int smbus_wait_until_done(unsigned smbus_io_base) return -3; } -#ifndef __PRE_RAM__ + +/* Platform has severe issues placing non-inlined functions in headers. */ +#if ENV_RAMSTAGE static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) { unsigned char global_status_register, byte; @@ -114,7 +116,7 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, return 0; } -#endif +#endif /* ENV_RAMSTAGE */ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) diff --git a/src/southbridge/nvidia/mcp55/chip.h b/src/southbridge/nvidia/mcp55/chip.h index adf47252db..4bc8428a1a 100644 --- a/src/southbridge/nvidia/mcp55/chip.h +++ b/src/southbridge/nvidia/mcp55/chip.h @@ -18,8 +18,6 @@ #ifndef SOUTHBRIDGE_NVIDIA_MCP55_CHIP_H #define SOUTHBRIDGE_NVIDIA_MCP55_CHIP_H -#include - struct southbridge_nvidia_mcp55_config { unsigned int ide0_enable : 1; diff --git a/src/southbridge/nvidia/mcp55/ht.c b/src/southbridge/nvidia/mcp55/ht.c index 4c831ad61d..070f8b7125 100644 --- a/src/southbridge/nvidia/mcp55/ht.c +++ b/src/southbridge/nvidia/mcp55/ht.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include "mcp55.h" diff --git a/src/southbridge/nvidia/mcp55/ide.c b/src/southbridge/nvidia/mcp55/ide.c index 797b9d8780..36e20b4aa0 100644 --- a/src/southbridge/nvidia/mcp55/ide.c +++ b/src/southbridge/nvidia/mcp55/ide.c @@ -22,6 +22,8 @@ #include #include #include + +#include "chip.h" #include "mcp55.h" static void ide_init(struct device *dev) diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h index 8d595c952f..ac689094ca 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.h +++ b/src/southbridge/nvidia/mcp55/mcp55.h @@ -24,13 +24,17 @@ #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif -#ifndef __PRE_RAM__ -#include "chip.h" +#ifndef __ROMCC__ +#include void mcp55_enable(struct device *dev); extern struct pci_operations mcp55_pci_ops; -#else +#endif + void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); void enable_smbus(void); + +/* Concflict declarations with . */ +#if !ENV_RAMSTAGE int smbus_recv_byte(unsigned device); int smbus_send_byte(unsigned device, unsigned char val); int smbus_read_byte(unsigned device, unsigned address); @@ -40,6 +44,6 @@ int smbusx_send_byte(unsigned smb_index, unsigned device, unsigned char val); int smbusx_read_byte(unsigned smb_index, unsigned device, unsigned address); int smbusx_write_byte(unsigned smb_index, unsigned device, unsigned address, unsigned char val); -#endif +#endif /* !ENV_RAMSTAGE */ #endif diff --git a/src/southbridge/nvidia/mcp55/nic.c b/src/southbridge/nvidia/mcp55/nic.c index 4ee3a3b79a..af4df44293 100644 --- a/src/southbridge/nvidia/mcp55/nic.c +++ b/src/southbridge/nvidia/mcp55/nic.c @@ -25,6 +25,8 @@ #include #include #include + +#include "chip.h" #include "mcp55.h" static int phy_read(u8 *base, unsigned phy_addr, unsigned phy_reg) diff --git a/src/southbridge/nvidia/mcp55/sata.c b/src/southbridge/nvidia/mcp55/sata.c index 27f60738b3..9f70890ff7 100644 --- a/src/southbridge/nvidia/mcp55/sata.c +++ b/src/southbridge/nvidia/mcp55/sata.c @@ -23,6 +23,7 @@ #include #include +#include "chip.h" #include "mcp55.h" static void sata_init(struct device *dev) diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c index 1228d57db2..37f4a1e3f1 100644 --- a/src/southbridge/nvidia/mcp55/smbus.c +++ b/src/southbridge/nvidia/mcp55/smbus.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include "mcp55.h" #include "smbus.h" diff --git a/src/southbridge/nvidia/mcp55/usb.c b/src/southbridge/nvidia/mcp55/usb.c index 18e6a65f48..46e27750aa 100644 --- a/src/southbridge/nvidia/mcp55/usb.c +++ b/src/southbridge/nvidia/mcp55/usb.c @@ -20,7 +20,6 @@ #include #include #include -#include #include "mcp55.h" static struct device_operations usb_ops = { diff --git a/src/southbridge/ti/pcixx12/pcixx12.c b/src/southbridge/ti/pcixx12/pcixx12.c index fa1c67dbf2..984b60f8ea 100644 --- a/src/southbridge/ti/pcixx12/pcixx12.c +++ b/src/southbridge/ti/pcixx12/pcixx12.c @@ -15,7 +15,6 @@ #include #include -#include #include #include diff --git a/src/superio/aspeed/ast2400/Makefile.inc b/src/superio/aspeed/ast2400/Makefile.inc index a6f8b2003a..625390fdf8 100644 --- a/src/superio/aspeed/ast2400/Makefile.inc +++ b/src/superio/aspeed/ast2400/Makefile.inc @@ -16,3 +16,5 @@ ## ramstage-$(CONFIG_SUPERIO_ASPEED_AST2400) += superio.c +ramstage-$(CONFIG_SUPERIO_ASPEED_AST2400) += ../../common/ssdt.c +ramstage-$(CONFIG_SUPERIO_ASPEED_AST2400) += ../../common/generic.c diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c index dcb14fa668..54f3f3430d 100644 --- a/src/superio/aspeed/ast2400/superio.c +++ b/src/superio/aspeed/ast2400/superio.c @@ -22,6 +22,8 @@ #include #include #include +#include +#include #include "ast2400.h" static void ast2400_init(struct device *dev) @@ -36,6 +38,32 @@ static void ast2400_init(struct device *dev) } } +#if CONFIG(HAVE_ACPI_TABLES) +/* Provide ACPI HIDs for generic Super I/O SSDT */ +static const char *ast2400_acpi_hid(const struct device *dev) +{ + /* Sanity checks */ + if (dev->path.type != DEVICE_PATH_PNP) + return NULL; + if (dev->path.pnp.port == 0) + return NULL; + if ((dev->path.pnp.device & 0xff) > AST2400_MAILBOX) + return NULL; + + switch (dev->path.pnp.device & 0xff) { + case AST2400_SUART1: /* falltrough */ + case AST2400_SUART2: /* falltrough */ + case AST2400_SUART3: /* falltrough */ + case AST2400_SUART4: + return ACPI_HID_COM; + case AST2400_KBC: + return ACPI_HID_KEYBOARD; + default: + return ACPI_HID_PNP; + } +} +#endif + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, @@ -43,6 +71,11 @@ static struct device_operations ops = { .enable = pnp_enable, .init = ast2400_init, .ops_pnp_mode = &pnp_conf_mode_a5a5_aa, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt_generator = superio_common_fill_ssdt_generator, + .acpi_name = superio_common_ldn_acpi_name, + .acpi_hid = ast2400_acpi_hid, +#endif }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/common/chip.h b/src/superio/common/chip.h new file mode 100644 index 0000000000..fd618c54ce --- /dev/null +++ b/src/superio/common/chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SUPERIO_COMMON_CHIP_H__ +#define __SUPERIO_COMMON_CHIP_H__ + +struct superio_common_config { + /* FIXME: Add enter conf/exit conf codes here for SSDT generation */ +}; + +#endif /* __SUPERIO_COMMON_CHIP_H__ */ diff --git a/src/superio/common/generic.c b/src/superio/common/generic.c new file mode 100644 index 0000000000..96307a3988 --- /dev/null +++ b/src/superio/common/generic.c @@ -0,0 +1,196 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +static void generic_set_resources(struct device *dev) +{ + struct resource *res; + + for (res = dev->resource_list; res; res = res->next) { + if (!(res->flags & IORESOURCE_ASSIGNED)) + continue; + + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, ""); + } +} + +static void generic_read_resources(struct device *dev) +{ + struct resource *res = new_resource(dev, 0); + res->base = dev->path.pnp.port; + res->size = 2; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +#if CONFIG(HAVE_ACPI_TABLES) +static void generic_ssdt(struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + const char *name = acpi_device_name(dev); + + if (!scope || !name) { + printk(BIOS_ERR, "%s: Missing ACPI path/scope\n", + dev_path(dev)); + return; + } + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(name); + + printk(BIOS_DEBUG, "%s.%s: %s\n", scope, name, dev_path(dev)); + + acpigen_write_name_string("_HID", "PNP0C02"); + acpigen_write_name_string("_DDN", dev_name(dev)); + + /* OperationRegion("IOID", SYSTEMIO, port, 2) */ + struct opregion opreg = OPREGION("IOID", SYSTEMIO, dev->path.pnp.port, 2); + acpigen_write_opregion(&opreg); + + struct fieldlist l[] = { + FIELDLIST_OFFSET(0), + FIELDLIST_NAMESTR("INDX", 8), + FIELDLIST_NAMESTR("DATA", 8), + }; + + /* Field (IOID, AnyAcc, NoLock, Preserve) + * { + * Offset (0), + * INDX, 8, + * DATA, 8, + * } */ + acpigen_write_field(opreg.name, l, ARRAY_SIZE(l), FIELD_BYTEACC | FIELD_NOLOCK | + FIELD_PRESERVE); + + struct fieldlist i[] = { + FIELDLIST_OFFSET(0x07), + FIELDLIST_NAMESTR("LDN", 8), + FIELDLIST_OFFSET(0x21), + FIELDLIST_NAMESTR("SCF1", 8), + FIELDLIST_NAMESTR("SCF2", 8), + FIELDLIST_NAMESTR("SCF3", 8), + FIELDLIST_NAMESTR("SCF4", 8), + FIELDLIST_NAMESTR("SCF5", 8), + FIELDLIST_NAMESTR("SCF6", 8), + FIELDLIST_NAMESTR("SCF7", 8), + FIELDLIST_OFFSET(0x29), + FIELDLIST_NAMESTR("CKCF", 8), + FIELDLIST_OFFSET(0x2F), + FIELDLIST_NAMESTR("SCFF", 8), + FIELDLIST_OFFSET(0x30), + FIELDLIST_NAMESTR("ACT0", 1), + FIELDLIST_NAMESTR("ACT1", 1), + FIELDLIST_NAMESTR("ACT2", 1), + FIELDLIST_NAMESTR("ACT3", 1), + FIELDLIST_NAMESTR("ACT4", 1), + FIELDLIST_NAMESTR("ACT5", 1), + FIELDLIST_NAMESTR("ACT6", 1), + FIELDLIST_NAMESTR("ACT7", 1), + FIELDLIST_OFFSET(0x60), + FIELDLIST_NAMESTR("IOH0", 8), + FIELDLIST_NAMESTR("IOL0", 8), + FIELDLIST_NAMESTR("IOH1", 8), + FIELDLIST_NAMESTR("IOL1", 8), + FIELDLIST_NAMESTR("IOH2", 8), + FIELDLIST_NAMESTR("IOL2", 8), + FIELDLIST_NAMESTR("IOH3", 8), + FIELDLIST_NAMESTR("IOL3", 8), + FIELDLIST_OFFSET(0x70), + /* Interrupt level 0 (IRQ number) */ + FIELDLIST_NAMESTR("ITL0", 4), + FIELDLIST_OFFSET(0x71), + /* Interrupt type 0 */ + FIELDLIST_NAMESTR("ITT0", 2), + FIELDLIST_OFFSET(0x72), + /* Interrupt level 1 (IRQ number) */ + FIELDLIST_NAMESTR("ITL1", 4), + FIELDLIST_OFFSET(0x73), + /* Interrupt type 1 */ + FIELDLIST_NAMESTR("ITT1", 2), + FIELDLIST_OFFSET(0x74), + FIELDLIST_NAMESTR("DMCH", 8), + FIELDLIST_OFFSET(0xE0), + FIELDLIST_NAMESTR("RGE0", 8), + FIELDLIST_NAMESTR("RGE1", 8), + FIELDLIST_NAMESTR("RGE2", 8), + FIELDLIST_NAMESTR("RGE3", 8), + FIELDLIST_NAMESTR("RGE4", 8), + FIELDLIST_NAMESTR("RGE5", 8), + FIELDLIST_NAMESTR("RGE6", 8), + FIELDLIST_NAMESTR("RGE7", 8), + FIELDLIST_NAMESTR("RGE8", 8), + FIELDLIST_NAMESTR("RGE9", 8), + FIELDLIST_NAMESTR("RGEA", 8), + FIELDLIST_OFFSET(0xF0), + FIELDLIST_NAMESTR("OPT0", 8), + FIELDLIST_NAMESTR("OPT1", 8), + FIELDLIST_NAMESTR("OPT2", 8), + FIELDLIST_NAMESTR("OPT3", 8), + FIELDLIST_NAMESTR("OPT4", 8), + FIELDLIST_NAMESTR("OPT5", 8), + FIELDLIST_NAMESTR("OPT6", 8), + FIELDLIST_NAMESTR("OPT7", 8), + FIELDLIST_NAMESTR("OPT8", 8), + FIELDLIST_NAMESTR("OPT9", 8), + }; + + acpigen_write_indexfield("INDX", "DATA", i, ARRAY_SIZE(i), FIELD_BYTEACC | + FIELD_NOLOCK | FIELD_PRESERVE); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +static const char *generic_acpi_name(const struct device *dev) +{ + return "SIO0"; +} +#endif + +static struct device_operations ops = { + .read_resources = generic_read_resources, + .set_resources = generic_set_resources, + .enable_resources = DEVICE_NOOP, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt_generator = generic_ssdt, + .acpi_name = generic_acpi_name, +#endif +}; + +static void enable_dev(struct device *dev) +{ + if (dev->path.type != DEVICE_PATH_PNP) + printk(BIOS_ERR, "%s: Unsupported device type\n", dev_path(dev)); + else if (!dev->path.pnp.port) + printk(BIOS_ERR, "%s: Base address not set\n", dev_path(dev)); + else + dev->ops = &ops; + + /* + * Need to call enable_dev() on the devices "behind" the Generic Super I/O. + * coreboot's generic allocator doesn't expect them behind PnP devices. + */ + scan_static_bus(dev); +} + +struct chip_operations superio_common_ops = { + CHIP_NAME("Generic Super I/O") + .enable_dev = enable_dev, +}; diff --git a/src/superio/common/ssdt.c b/src/superio/common/ssdt.c new file mode 100644 index 0000000000..a919aa5620 --- /dev/null +++ b/src/superio/common/ssdt.c @@ -0,0 +1,247 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#include +#include +#include +#include +#include +#include +#include + +struct superio_dev { + const char *acpi_hid; + u16 io_base[4]; + u8 irq[2]; +}; + +static const struct superio_dev superio_devs[] = { + {ACPI_HID_FDC, {0x3f0, 0x3f2, 0x3f7}, {6, } }, + {ACPI_HID_KEYBOARD, {60, 64, }, {1, } }, + {ACPI_HID_MOUSE, {60, 64, }, {12, } }, + {ACPI_HID_COM, {0x3f8, 0x2f8, 0x3e8, 0x2e8}, {4, 3} }, + {ACPI_HID_LPT, {0x378, }, {7, } }, +}; + +static const u8 io_idx[] = {PNP_IDX_IO0, PNP_IDX_IO1, PNP_IDX_IO2, PNP_IDX_IO3}; +static const u8 irq_idx[] = {PNP_IDX_IRQ0, PNP_IDX_IRQ1}; + +static const struct superio_dev *superio_guess_function(struct device *dev) +{ + for (size_t i = 0; i < ARRAY_SIZE(io_idx); i++) { + struct resource *res = probe_resource(dev, io_idx[i]); + if (!res || !res->base) + continue; + + for (size_t j = 0; j < ARRAY_SIZE(superio_devs); j++) { + for (size_t k = 0; k < 4; k++) { + if (!superio_devs[j].io_base[k]) + continue; + if (superio_devs[j].io_base[k] == res->base) + return &superio_devs[j]; + } + } + } + for (size_t i = 0; i < ARRAY_SIZE(irq_idx); i++) { + struct resource *res = probe_resource(dev, irq_idx[i]); + if (!res || !res->size) + continue; + for (size_t j = 0; j < ARRAY_SIZE(superio_devs); j++) { + for (size_t k = 0; k < 2; k++) { + if (!superio_devs[j].irq[k]) + continue; + if (superio_devs[j].irq[k] == res->base) + return &superio_devs[j]; + } + } + } + return NULL; +} + +/* Return true if there are resources to report */ +static bool has_resources(struct device *dev) +{ + for (size_t i = 0; i < ARRAY_SIZE(io_idx); i++) { + struct resource *res = probe_resource(dev, io_idx[i]); + if (!res || !res->base || !res->size) + continue; + return 1; + } + for (size_t i = 0; i < ARRAY_SIZE(irq_idx); i++) { + struct resource *res = probe_resource(dev, irq_idx[i]); + if (!res || !res->size || res->base > 16) + continue; + return 1; + } + return 0; +} + +/* Add IO and IRQ resources for _CRS or _PRS */ +static void ldn_gen_resources(struct device *dev) +{ + uint16_t irq = 0; + for (size_t i = 0; i < ARRAY_SIZE(io_idx); i++) { + struct resource *res = probe_resource(dev, io_idx[i]); + if (!res || !res->base) + continue; + resource_t base = res->base; + resource_t size = res->size; + while (size > 0) { + resource_t sz = size > 255 ? 255 : size; + /* TODO: Needs test with regions >= 256 bytes */ + acpigen_write_io16(base, base, 1, sz, 1); + size -= sz; + base += sz; + } + } + for (size_t i = 0; i < ARRAY_SIZE(irq_idx); i++) { + struct resource *res = probe_resource(dev, irq_idx[i]); + if (!res || !res->size || res->base >= 16) + continue; + irq |= 1 << res->base; + } + if (irq) + acpigen_write_irq(irq); + +} + +/* Add resource base and size for additional SuperIO code */ +static void ldn_gen_resources_use(struct device *dev) +{ + char name[5]; + for (size_t i = 0; i < ARRAY_SIZE(io_idx); i++) { + struct resource *res = probe_resource(dev, io_idx[i]); + if (!res || !res->base || !res->size) + continue; + + snprintf(name, sizeof(name), "IO%zXB", i); + name[4] = '\0'; + acpigen_write_name_integer(name, res->base); + + snprintf(name, sizeof(name), "IO%zXS", i); + name[4] = '\0'; + acpigen_write_name_integer(name, res->size); + } +} + +const char *superio_common_ldn_acpi_name(const struct device *dev) +{ + u8 ldn = dev->path.pnp.device & 0xff; + u8 vldn = (dev->path.pnp.device >> 8) & 0x7; + static char name[5]; + + snprintf(name, sizeof(name), "L%02X%01X", ldn, vldn); + + name[4] = '\0'; + + return name; +} + +static const char *name_from_hid(const char *hid) +{ + static const struct { + const char *hid; + const char *name; + } lookup[] = { + {ACPI_HID_FDC, "FDC" }, + {ACPI_HID_KEYBOARD, "PS2 Keyboard" }, + {ACPI_HID_MOUSE, "PS2 Mouse"}, + {ACPI_HID_COM, "COM port" }, + {ACPI_HID_LPT, "LPT" }, + {ACPI_HID_PNP, "Generic PNP device" }, + }; + + for (size_t i = 0; hid && i < ARRAY_SIZE(lookup); i++) { + if (strcmp(hid, lookup[i].hid) == 0) + return lookup[i].name; + } + return "Generic device"; +} + +void superio_common_fill_ssdt_generator(struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + const char *name = acpi_device_name(dev); + const u8 ldn = dev->path.pnp.device & 0xff; + const u8 vldn = (dev->path.pnp.device >> 8) & 0x7; + const char *hid; + + if (!scope || !name) { + printk(BIOS_ERR, "%s: Missing ACPI path/scope\n", dev_path(dev)); + return; + } + if (vldn) { + printk(BIOS_DEBUG, "%s: Ignoring virtual LDN\n", dev_path(dev)); + return; + } + + printk(BIOS_DEBUG, "%s.%s: %s\n", scope, name, dev_path(dev)); + + /* Scope */ + acpigen_write_scope(scope); + + /* Device */ + acpigen_write_device(name); + + acpigen_write_name_byte("_UID", 0); + acpigen_write_name_byte("LDN", ldn); + acpigen_write_name_byte("VLDN", vldn); + + acpigen_write_STA(dev->enabled ? 0xf : 0); + + if (!dev->enabled) { + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + return; + } + + if (has_resources(dev)) { + /* Resources - _CRS */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + ldn_gen_resources(dev); + acpigen_write_resourcetemplate_footer(); + + /* Resources - _PRS */ + acpigen_write_name("_PRS"); + acpigen_write_resourcetemplate_header(); + ldn_gen_resources(dev); + acpigen_write_resourcetemplate_footer(); + + /* Resources base and size for 3rd party ACPI code */ + ldn_gen_resources_use(dev); + } + + hid = acpi_device_hid(dev); + if (!hid) { + printk(BIOS_ERR, "%s: SuperIO driver doesn't provide a _HID\n", dev_path(dev)); + /* Try to guess it... */ + const struct superio_dev *sdev = superio_guess_function(dev); + if (sdev && sdev->acpi_hid) { + hid = sdev->acpi_hid; + printk(BIOS_WARNING, "%s: Guessed _HID is '%s'\n", dev_path(dev), hid); + } else { + hid = ACPI_HID_PNP; + printk(BIOS_ERR, "%s: Failed to guessed _HID\n", dev_path(dev)); + } + } + + acpigen_write_name_string("_HID", hid); + acpigen_write_name_string("_DDN", name_from_hid(hid)); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} diff --git a/src/superio/common/ssdt.h b/src/superio/common/ssdt.h new file mode 100644 index 0000000000..8c63742798 --- /dev/null +++ b/src/superio/common/ssdt.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SUPERIO_COMMON_SSDT_H__ +#define __SUPERIO_COMMON_SSDT_H__ + +#include + +const char *superio_common_ldn_acpi_name(const struct device *dev); +void superio_common_fill_ssdt_generator(struct device *dev); + +#endif /* __SUPERIO_COMMON_SSDT_H__ */ diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c index ad8153f41c..4b9e345145 100644 --- a/src/superio/smsc/lpc47b397/superio.c +++ b/src/superio/smsc/lpc47b397/superio.c @@ -139,7 +139,7 @@ static struct pnp_info pnp_dev_info[] = { { NULL, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, }, { NULL, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, }, - { NULL_hwm, LPC47B397_HWM, PNP_IO0, 0x07f0, }, + { &ops_hwm, LPC47B397_HWM, PNP_IO0, 0x07f0, }, { NULL, LPC47B397_RT, PNP_IO0, 0x0780, }, }; diff --git a/src/superio/smsc/sio1007/early_serial.c b/src/superio/smsc/sio1007/early_serial.c index 022a1aba7c..2028e67fc3 100644 --- a/src/superio/smsc/sio1007/early_serial.c +++ b/src/superio/smsc/sio1007/early_serial.c @@ -15,7 +15,7 @@ #include #include -#include "chip.h" +#include "sio1007.h" void sio1007_setreg(u16 lpc_port, u8 reg, u8 value, u8 mask) { diff --git a/src/superio/smsc/sio1007/chip.h b/src/superio/smsc/sio1007/sio1007.h similarity index 87% rename from src/superio/smsc/sio1007/chip.h rename to src/superio/smsc/sio1007/sio1007.h index 78ac18a249..a99ec5c273 100644 --- a/src/superio/smsc/sio1007/chip.h +++ b/src/superio/smsc/sio1007/sio1007.h @@ -13,10 +13,11 @@ * GNU General Public License for more details. */ -#ifndef SUPERIO_SMSC_1007_CHIP_H -#define SUPERIO_SMSC_1007_CHIP_H +#ifndef SUPERIO_SMSC_SIO1007_H +#define SUPERIO_SMSC_SIO1007_H + +#include -/* FIXME: wrong place for this! */ void sio1007_setreg(u16 lpc_port, u8 reg, u8 value, u8 mask); int sio1007_enable_uart_at(u16 port); diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc index df34330da8..da5900498c 100644 --- a/src/vendorcode/amd/agesa/Makefile.inc +++ b/src/vendorcode/amd/agesa/Makefile.inc @@ -10,8 +10,14 @@ subdirs-y += common classes-y += libagesa libagesa-y = libagesa-generic-ccopts += -D__LIBAGESA__ +libagesa-generic-ccopts += -fno-zero-initialized-in-bss libagesa-generic-ccopts += $(AGESA_INC) $(AGESA_AUTOINCLUDES) +AGESA_CFLAGS := -march=k8-sse3 -mtune=k8-sse3 -fno-strict-aliasing + +CFLAGS_x86_32 += $(AGESA_CFLAGS) +CFLAGS_x86_64 += $(AGESA_CFLAGS) + ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) $(eval $(call create_class_compiler,libagesa,x86_32)) else diff --git a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h index f787014f96..b1a346a78a 100644 --- a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h +++ b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h @@ -2,7 +2,7 @@ #define AGESA_ENTRY_CFG_H -#if defined(__PRE_RAM__) +#if ENV_ROMSTAGE #define AGESA_ENTRY_INIT_RESET TRUE #define AGESA_ENTRY_INIT_EARLY TRUE diff --git a/src/vendorcode/amd/agesa/f12/Makefile.inc b/src/vendorcode/amd/agesa/f12/Makefile.inc index 9bc3c2600e..d53b3a3dc5 100644 --- a/src/vendorcode/amd/agesa/f12/Makefile.inc +++ b/src/vendorcode/amd/agesa/f12/Makefile.inc @@ -40,9 +40,6 @@ AGESA_INC += -I$(src)/mainboard/$(MAINBOARDDIR) # OptionsIds.h BUILDOPTS_INCLUDES = -I$(AGESA_ROOT)/Config $(AGESA_INC) $(AGESA_AUTOINCLUDES) -CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing -CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing - CPPFLAGS_x86_32 += $(AGESA_INC) CPPFLAGS_x86_64 += $(AGESA_INC) diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index da79a39f8f..9726345b94 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -40,9 +40,6 @@ AGESA_INC += -I$(src)/mainboard/$(MAINBOARDDIR) # OptionsIds.h BUILDOPTS_INCLUDES = -I$(AGESA_ROOT)/Config $(AGESA_INC) $(AGESA_AUTOINCLUDES) -CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing -CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing - CPPFLAGS_x86_32 += $(AGESA_INC) CPPFLAGS_x86_64 += $(AGESA_INC) diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc index 1c5dc18d85..24528da7f6 100644 --- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -40,9 +40,6 @@ AGESA_INC += -I$(src)/mainboard/$(MAINBOARDDIR) # OptionsIds.h BUILDOPTS_INCLUDES = -I$(AGESA_ROOT)/Config $(AGESA_INC) $(AGESA_AUTOINCLUDES) -CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing -CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing - # These are invalid, coreboot proper should not require # use of AGESA internal header files. CPPFLAGS_x86_ANY = diff --git a/src/vendorcode/amd/agesa/f16kb/Makefile.inc b/src/vendorcode/amd/agesa/f16kb/Makefile.inc index c423cf2bab..ddd6d62df7 100644 --- a/src/vendorcode/amd/agesa/f16kb/Makefile.inc +++ b/src/vendorcode/amd/agesa/f16kb/Makefile.inc @@ -40,9 +40,6 @@ AGESA_INC += -I$(src)/mainboard/$(MAINBOARDDIR) # OptionsIds.h BUILDOPTS_INCLUDES = -I$(AGESA_ROOT)/Config $(AGESA_INC) $(AGESA_AUTOINCLUDES) -CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing -CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing - # These are invalid, coreboot proper should not require # use of AGESA internal header files. CPPFLAGS_x86_ANY = diff --git a/src/vendorcode/amd/cimx/sb800/MEMLIB.c b/src/vendorcode/amd/cimx/sb800/MEMLIB.c index 5531c627d0..d9eb8fff38 100644 --- a/src/vendorcode/amd/cimx/sb800/MEMLIB.c +++ b/src/vendorcode/amd/cimx/sb800/MEMLIB.c @@ -46,9 +46,7 @@ ReadMEM ( *((UINT8*)Value) = *((UINT8*) ((UINTN)Address)); break; case AccWidthUint16: - //*((UINT16*)Value) = *((UINT16*) ((UINTN)Address)); //gcc break strict-aliasing rules - *((UINT8*)Value) = *((UINT8*) ((UINTN)Address)); - *((UINT8*)Value + 1) = *((UINT8*)((UINTN)Address) + 1); + *((UINT16*)Value) = *((UINT16*) ((UINTN)Address)); break; case AccWidthUint32: *((UINT32*)Value) = *((UINT32*) ((UINTN)Address)); @@ -69,9 +67,7 @@ WriteMEM ( *((UINT8*) ((UINTN)Address)) = *((UINT8*)Value); break; case AccWidthUint16: - //*((UINT16*) ((UINTN)Address)) = *((UINT16*)Value); //gcc break strict-aliasing rules - *((UINT8*)((UINTN)Address)) = *((UINT8*)Value); - *((UINT8*)((UINTN)Address) + 1) = *((UINT8*)Value + 1); + *((UINT16*) ((UINTN)Address)) = *((UINT16*)Value); break; case AccWidthUint32: *((UINT32*) ((UINTN)Address)) = *((UINT32*)Value); diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c index 8e348d0175..e078e7476f 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c @@ -18,7 +18,6 @@ static struct bdk_devicetree_key_value *config_fdt; -#if !defined(__PRE_RAM__) static struct bdk_devicetree_key_value *bdk_config_duplicate( const struct bdk_devicetree_key_value *old, size_t free_space) @@ -38,7 +37,7 @@ static struct bdk_devicetree_key_value *bdk_config_duplicate( return new; } -#endif + /** * Set the device tree used for configuration * @@ -49,11 +48,11 @@ static struct bdk_devicetree_key_value *bdk_config_duplicate( */ int bdk_config_set_fdt(const struct bdk_devicetree_key_value *fdt) { -#if !defined(__PRE_RAM__) - config_fdt = bdk_config_duplicate(fdt, 0); -#else - config_fdt = (void *)fdt; -#endif + if (ENV_STAGE_HAS_HEAP_SECTION) + config_fdt = bdk_config_duplicate(fdt, 0); + else + config_fdt = (void *)fdt; + return 0; } @@ -66,7 +65,6 @@ int bdk_config_set_fdt(const struct bdk_devicetree_key_value *fdt) */ static void set_value(const char *name, const char *val) { -#if !defined(__PRE_RAM__) struct bdk_devicetree_key_value *iter; char n[64]; @@ -98,7 +96,6 @@ static void set_value(const char *name, const char *val) iter++; iter->key = 0; iter->value = 0; -#endif } /** @@ -207,6 +204,9 @@ void bdk_config_set_int(int64_t value, bdk_config_t cfg_item, ...) /* Make sure the correct access function was called */ assert(config_info[cfg_item].ctype == BDK_CONFIG_TYPE_INT); + if (!ENV_STAGE_HAS_HEAP_SECTION) + return; + if (!config_fdt) return; diff --git a/src/vendorcode/cavium/include/bdk/libbdk-hal/bdk-config.h b/src/vendorcode/cavium/include/bdk/libbdk-hal/bdk-config.h index 9aa1a47251..8c950837cf 100644 --- a/src/vendorcode/cavium/include/bdk/libbdk-hal/bdk-config.h +++ b/src/vendorcode/cavium/include/bdk/libbdk-hal/bdk-config.h @@ -39,7 +39,7 @@ * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. ***********************license end**************************************/ -#include +#include #include /** diff --git a/src/vendorcode/eltan/security/lib/Makefile.inc b/src/vendorcode/eltan/security/lib/Makefile.inc index 5ef1bca65f..2e11fb5a00 100644 --- a/src/vendorcode/eltan/security/lib/Makefile.inc +++ b/src/vendorcode/eltan/security/lib/Makefile.inc @@ -40,7 +40,8 @@ CFLAGS_common += -I3rdparty/vboot/firmware/lib21/include ifneq ($(filter y,$(CONFIG_VENDORCODE_ELTAN_VBOOT) $(CONFIG_VENDORCODE_ELTAN_MBOOT)),) -bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += cb_sha.c +bootblock-y += cb_sha.c +bootblock-y += ../../../../security/vboot/vboot_logic.c $(eval $(call vendor-security-lib,bootblock)) bootblock-srcs += $(obj)/external/ven_sec_lib-bootblock/vboot_fw21.a diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 26ee31edc7..2ff7ec70b8 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -89,5 +89,11 @@ config CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME on normal boot as well as resume and coreboot is only involved in the resume piece w.r.t. the platform hierarchy. +config CHROMEOS_USE_EC_WATCHDOG_FLAG + bool + default n + help + Use the AP watchdog flag stored in EC. + endif # CHROMEOS endmenu diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 44162c88fc..81154550ec 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c index bbcb211c3a..01de60c835 100644 --- a/src/vendorcode/google/chromeos/sar.c +++ b/src/vendorcode/google/chromeos/sar.c @@ -61,11 +61,10 @@ int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) const char *wifi_sar_limit_key = CROS_VPD_WIFI_SAR_NAME; /* vpd_gets() reads in one less than size characters from the VPD * with a terminating null byte ('\0') stored as the last character into - * the buffer, thus the increasing by 1 for buffer_size. */ - const size_t buffer_size = (sizeof(struct wifi_sar_limits) / - sizeof(uint8_t)) * 2 + 1; - char wifi_sar_limit_str[buffer_size]; + * the buffer, thus the increasing by 1 for the buffer size. */ + char wifi_sar_limit_str[2 * sizeof(struct wifi_sar_limits) + 1]; uint8_t bin_buffer[sizeof(struct wifi_sar_limits)]; + const size_t buffer_size = ARRAY_SIZE(wifi_sar_limit_str); size_t sar_cbfs_len, sar_expected_len, bin_buff_adjusted_size; /* keep it backward compatible. Some older platform are shipping diff --git a/src/vendorcode/google/chromeos/watchdog.c b/src/vendorcode/google/chromeos/watchdog.c index 4557251ef6..2b2959f016 100644 --- a/src/vendorcode/google/chromeos/watchdog.c +++ b/src/vendorcode/google/chromeos/watchdog.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -30,13 +31,19 @@ DECLARE_OPTIONAL_REGION(watchdog_tombstone); static void elog_handle_watchdog_tombstone(void *unused) { - if (!REGION_SIZE(watchdog_tombstone)) - return; + bool flag = false; - if (read32(_watchdog_tombstone) == WATCHDOG_TOMBSTONE_MAGIC) + if (CONFIG(CHROMEOS_USE_EC_WATCHDOG_FLAG)) + flag |= google_chromeec_get_ap_watchdog_flag(); + + if (REGION_SIZE(watchdog_tombstone)) { + flag |= (read32(_watchdog_tombstone) == + WATCHDOG_TOMBSTONE_MAGIC); + write32(_watchdog_tombstone, 0); + } + + if (flag) elog_add_event(ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED); - - write32(_watchdog_tombstone, 0); } BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h index cb31f7e131..962463e425 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h @@ -37,19 +37,19 @@ are permitted provided that the following conditions are met: #pragma pack(1) - -#include - -/// -/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. -/// -typedef struct { - UINT8 Revision; ///< Chipset Init Info Revision - UINT8 Rsvd[3]; ///< Reserved - UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table - UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table -} CHIPSET_INIT_INFO; - + +#include + +/// +/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. +/// +typedef struct { + UINT8 Revision; ///< Chipset Init Info Revision + UINT8 Rsvd[3]; ///< Reserved + UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table + UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table +} CHIPSET_INIT_INFO; + /** Fsp M Configuration **/ @@ -106,15 +106,15 @@ typedef struct { **/ UINT8 DqsMapCpu2DramCh1[8]; -/** Offset 0x0082 - RcompResister settings - Indicates RcompReister settings: CNL - 0's means MRC auto configured based on Design - Guidelines, otherwise input an Ohmic value per segment. CFL will need to provide - the appropriate values. +/** Offset 0x0082 - RcompResistor settings + Indicates RcompResistor settings: CML - 0's means MRC auto configured based on + Design Guidelines, otherwise input an Ohmic value per segment. CFL will need to + provide the appropriate values. **/ UINT16 RcompResistor[3]; /** Offset 0x0088 - RcompTarget settings - RcompTarget settings: CNL - 0's mean MRC auto configured based on Design Guidelines, + RcompTarget settings: CML - 0's mean MRC auto configured based on Design Guidelines, otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values. **/ UINT16 RcompTarget[5]; @@ -138,92 +138,102 @@ typedef struct { **/ UINT8 SmramMask; -/** Offset 0x0095 - MRC Fast Boot +/** Offset 0x0095 - Time Measure + Time Measure: 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 MrcTimeMeasure; + +/** Offset 0x0096 - MRC Fast Boot Enables/Disable the MRC fast path thru the MRC $EN_DIS **/ UINT8 MrcFastBoot; -/** Offset 0x0096 - Rank Margin Tool per Task +/** Offset 0x0097 - Rank Margin Tool per Task This option enables the user to execute Rank Margin Tool per major training step in the MRC. $EN_DIS **/ UINT8 RmtPerTask; -/** Offset 0x0097 - Training Trace +/** Offset 0x0098 - Training Trace This option enables the trained state tracing feature in MRC. This feature will print out the key training parameters state across major training steps. $EN_DIS **/ UINT8 TrainTrace; -/** Offset 0x0098 - Intel Enhanced Debug +/** Offset 0x0099 +**/ + UINT8 UnusedUpdSpace0[3]; + +/** Offset 0x009C - Intel Enhanced Debug Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied 0 : Disable, 0x400000 : Enable **/ UINT32 IedSize; -/** Offset 0x009C - Tseg Size +/** Offset 0x00A0 - Tseg Size Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build 0x0400000:4MB, 0x01000000:16MB **/ UINT32 TsegSize; -/** Offset 0x00A0 - MMIO Size +/** Offset 0x00A4 - MMIO Size Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB **/ UINT16 MmioSize; -/** Offset 0x00A2 - Probeless Trace +/** Offset 0x00A6 - Probeless Trace Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. This also requires IED to be enabled. $EN_DIS **/ UINT8 ProbelessTrace; -/** Offset 0x00A3 - GDXC IOT SIZE +/** Offset 0x00A7 - GDXC IOT SIZE Size of IOT and MOT is in 8 MB chunks **/ UINT8 GdxcIotSize; -/** Offset 0x00A4 - GDXC MOT SIZE +/** Offset 0x00A8 - GDXC MOT SIZE Size of IOT and MOT is in 8 MB chunks **/ UINT8 GdxcMotSize; -/** Offset 0x00A5 - Spd Address Tabl +/** Offset 0x00A9 - Spd Address Tabl Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used if SPD Address is 00 **/ UINT8 SpdAddressTable[4]; -/** Offset 0x00A9 - Internal Graphics Pre-allocated Memory +/** Offset 0x00AD - Internal Graphics Pre-allocated Memory Size of memory preallocated for internal graphics. 0x00:0 MB, 0x01:32 MB, 0x02:64 MB **/ UINT8 IgdDvmt50PreAlloc; -/** Offset 0x00AA - Internal Graphics +/** Offset 0x00AE - Internal Graphics Enable/disable internal graphics. $EN_DIS **/ UINT8 InternalGfx; -/** Offset 0x00AB - Aperture Size +/** Offset 0x00AF - Aperture Size Select the Aperture Size. 0:128 MB, 1:256 MB, 2:512 MB **/ UINT8 ApertureSize; -/** Offset 0x00AC - Board Type +/** Offset 0x00B0 - Board Type MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile Halo, 7=UP Server 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server **/ UINT8 UserBd; -/** Offset 0x00AD - SA GV +/** Offset 0x00B1 - SA GV System Agent dynamic frequency support and when enabled memory will be training at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow, 2=FixedHigh, and 3=Enabled. @@ -231,7 +241,7 @@ typedef struct { **/ UINT8 SaGv; -/** Offset 0x00AE - DDR Frequency Limit +/** Offset 0x00B2 - DDR Frequency Limit Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk, i.e. divide by 133 or 100 1067:1067, 1333:1333, 1400:1400, 1600:1600, 1800:1800, 1867:1867, 2000:2000, 2133:2133, @@ -239,135 +249,128 @@ typedef struct { **/ UINT16 DdrFreqLimit; -/** Offset 0x00B0 - Low Frequency +/** Offset 0x00B4 - Low Frequency SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933 and 0 for Auto. 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto **/ UINT16 FreqSaGvLow; -/** Offset 0x00B2 - Mid Frequency - SAGV Mid Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, - 2400, 2667, 2933 and 0 for Auto. - 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto -**/ - UINT16 FreqSaGvMid; - -/** Offset 0x00B4 - Rank Margin Tool +/** Offset 0x00B6 - Rank Margin Tool Enable/disable Rank Margin Tool. $EN_DIS **/ UINT8 RMT; -/** Offset 0x00B5 - Channel A DIMM Control +/** Offset 0x00B7 - Channel A DIMM Control Channel A DIMM Control Support - Enable or Disable Dimms on Channel A. 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs **/ UINT8 DisableDimmChannel0; -/** Offset 0x00B6 - Channel B DIMM Control +/** Offset 0x00B8 - Channel B DIMM Control Channel B DIMM Control Support - Enable or Disable Dimms on Channel B. 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs **/ UINT8 DisableDimmChannel1; -/** Offset 0x00B7 - Scrambler Support +/** Offset 0x00B9 - Scrambler Support This option enables data scrambling in memory. $EN_DIS **/ UINT8 ScramblerSupport; -/** Offset 0x00B8 - Skip Multi-Processor Initialization +/** Offset 0x00BA - Skip Multi-Processor Initialization When this is skipped, boot loader must initialize processors before SilicionInit API. 0: Initialize; 1: Skip $EN_DIS **/ UINT8 SkipMpInit; -/** Offset 0x00B9 - SPD Profile Selected +/** Offset 0x00BB - SPD Profile Selected Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP Profile 1, 3=XMP Profile 2 0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2 **/ UINT8 SpdProfileSelected; -/** Offset 0x00BA - Memory Reference Clock +/** Offset 0x00BC - Memory Reference Clock 100MHz, 133MHz. 0:133MHz, 1:100MHz **/ UINT8 RefClk; -/** Offset 0x00BB +/** Offset 0x00BD **/ - UINT8 UnusedUpdSpace0; + UINT8 UnusedUpdSpace1; -/** Offset 0x00BC - Memory Voltage +/** Offset 0x00BE - Memory Voltage Memory Voltage Override (Vddq). Default = no override 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40 Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts **/ UINT16 VddVoltage; -/** Offset 0x00BE - Memory Ratio +/** Offset 0x00C0 - Memory Ratio Automatic or the frequency will equal ratio times reference clock. Set to Auto to recalculate memory timings listed below. 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 **/ UINT8 Ratio; -/** Offset 0x00BF - QCLK Odd Ratio +/** Offset 0x00C1 - QCLK Odd Ratio Adds 133 or 100 MHz to QCLK frequency, depending on RefClk $EN_DIS **/ UINT8 OddRatioMode; -/** Offset 0x00C0 - tCL +/** Offset 0x00C2 - tCL CAS Latency, 0: AUTO, max: 31 **/ UINT8 tCL; -/** Offset 0x00C1 - tCWL +/** Offset 0x00C3 - tCWL Min CAS Write Latency Delay Time, 0: AUTO, max: 34 **/ UINT8 tCWL; -/** Offset 0x00C2 - tRCD/tRP +/** Offset 0x00C4 - tRCD/tRP RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63 **/ UINT8 tRCDtRP; -/** Offset 0x00C3 - tRRD +/** Offset 0x00C5 - tRRD Min Row Active to Row Active Delay Time, 0: AUTO, max: 15 **/ UINT8 tRRD; -/** Offset 0x00C4 - tFAW +/** Offset 0x00C6 - tFAW Min Four Activate Window Delay Time, 0: AUTO, max: 63 **/ UINT16 tFAW; -/** Offset 0x00C6 - tRAS +/** Offset 0x00C8 - tRAS RAS Active Time, 0: AUTO, max: 64 **/ UINT16 tRAS; -/** Offset 0x00C8 - tREFI +/** Offset 0x00CA - tREFI Refresh Interval, 0: AUTO, max: 65535 **/ UINT16 tREFI; -/** Offset 0x00CA - tRFC +/** Offset 0x00CC - tRFC Min Refresh Recovery Delay Time, 0: AUTO, max: 1023 **/ UINT16 tRFC; -/** Offset 0x00CC - tRTP +/** Offset 0x00CE - tRTP Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12 **/ UINT8 tRTP; -/** Offset 0x00CD - tWR +/** Offset 0x00CF - tWR Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24, 30, 34, 40 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, @@ -375,63 +378,74 @@ typedef struct { **/ UINT8 tWR; -/** Offset 0x00CE - tWTR +/** Offset 0x00D0 - tWTR Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28 **/ UINT8 tWTR; -/** Offset 0x00CF - NMode +/** Offset 0x00D1 - NMode System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N **/ UINT8 NModeSupport; -/** Offset 0x00D0 - DllBwEn[0] +/** Offset 0x00D2 - DllBwEn[0] DllBwEn[0], for 1067 (0..7) **/ UINT8 DllBwEn0; -/** Offset 0x00D1 - DllBwEn[1] +/** Offset 0x00D3 - DllBwEn[1] DllBwEn[1], for 1333 (0..7) **/ UINT8 DllBwEn1; -/** Offset 0x00D2 - DllBwEn[2] +/** Offset 0x00D4 - DllBwEn[2] DllBwEn[2], for 1600 (0..7) **/ UINT8 DllBwEn2; -/** Offset 0x00D3 - DllBwEn[3] +/** Offset 0x00D5 - DllBwEn[3] DllBwEn[3], for 1867 and up (0..7) **/ UINT8 DllBwEn3; -/** Offset 0x00D4 - ISVT IO Port Address +/** Offset 0x00D6 - ISVT IO Port Address ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default **/ UINT8 IsvtIoPort; -/** Offset 0x00D5 - CPU Trace Hub Mode +/** Offset 0x00D7 - Margin Limit Check + Margin Limit Check. Choose level of margin check + 0:Disable, 1:L1, 2:L2, 3:Both +**/ + UINT8 MarginLimitCheck; + +/** Offset 0x00D8 - Margin Limit L2 + % of L1 check for margin limit check +**/ + UINT16 MarginLimitL2; + +/** Offset 0x00DA - CPU Trace Hub Mode Select 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. 0: Disable, 1:Target Debugger Mode **/ UINT8 CpuTraceHubMode; -/** Offset 0x00D6 - CPU Trace Hub Memory Region 0 +/** Offset 0x00DB - CPU Trace Hub Memory Region 0 CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB **/ UINT8 CpuTraceHubMemReg0Size; -/** Offset 0x00D7 - CPU Trace Hub Memory Region 1 +/** Offset 0x00DC - CPU Trace Hub Memory Region 1 CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB **/ UINT8 CpuTraceHubMemReg1Size; -/** Offset 0x00D8 - Enable or Disable Peci C10 Reset command +/** Offset 0x00DD - Enable or Disable Peci C10 Reset command Enable or Disable Peci C10 Reset command. If Enabled, BIOS will send the CPU message to disable peci reset on C10 exit. The default value is 0: Disable for CNL, and 1: Enable for all other CPU's @@ -439,175 +453,171 @@ typedef struct { **/ UINT8 PeciC10Reset; -/** Offset 0x00D9 - Enable or Disable Peci Sx Reset command +/** Offset 0x00DE - Enable or Disable Peci Sx Reset command Enable or Disable Peci Sx Reset command; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PeciSxReset; -/** Offset 0x00DA - HECI Timeouts +/** Offset 0x00DF - HECI Timeouts 0: Disable, 1: Enable (Default) timeout check for HECI $EN_DIS **/ UINT8 HeciTimeouts; -/** Offset 0x00DB -**/ - UINT8 UnusedUpdSpace1; - -/** Offset 0x00DC - HECI1 BAR address +/** Offset 0x00E0 - HECI1 BAR address BAR address of HECI1 **/ UINT32 Heci1BarAddress; -/** Offset 0x00E0 - HECI2 BAR address +/** Offset 0x00E4 - HECI2 BAR address BAR address of HECI2 **/ UINT32 Heci2BarAddress; -/** Offset 0x00E4 - HECI3 BAR address +/** Offset 0x00E8 - HECI3 BAR address BAR address of HECI3 **/ UINT32 Heci3BarAddress; -/** Offset 0x00E8 - SG dGPU Power Delay +/** Offset 0x00EC - SG dGPU Power Delay SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is 300=300 microseconds **/ UINT16 SgDelayAfterPwrEn; -/** Offset 0x00EA - SG dGPU Reset Delay +/** Offset 0x00EE - SG dGPU Reset Delay SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 microseconds **/ UINT16 SgDelayAfterHoldReset; -/** Offset 0x00EC - MMIO size adjustment for AUTO mode +/** Offset 0x00F0 - MMIO size adjustment for AUTO mode Positive number means increasing MMIO size, Negative value means decreasing MMIO size: 0 (Default)=no change to AUTO mode MMIO size **/ UINT16 MmioSizeAdjustment; -/** Offset 0x00EE - Enable/Disable DMI GEN3 Static EQ Phase1 programming +/** Offset 0x00F2 - Enable/Disable DMI GEN3 Static EQ Phase1 programming Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming $EN_DIS **/ UINT8 DmiGen3ProgramStaticEq; -/** Offset 0x00EF - Enable/Disable PEG 0 +/** Offset 0x00F3 - Enable/Disable PEG 0 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise 0:Disable, 1:Enable, 2:AUTO **/ UINT8 Peg0Enable; -/** Offset 0x00F0 - Enable/Disable PEG 1 +/** Offset 0x00F4 - Enable/Disable PEG 1 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise 0:Disable, 1:Enable, 2:AUTO **/ UINT8 Peg1Enable; -/** Offset 0x00F1 - Enable/Disable PEG 2 +/** Offset 0x00F5 - Enable/Disable PEG 2 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise 0:Disable, 1:Enable, 2:AUTO **/ UINT8 Peg2Enable; -/** Offset 0x00F2 - Enable/Disable PEG 3 +/** Offset 0x00F6 - Enable/Disable PEG 3 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise 0:Disable, 1:Enable, 2:AUTO **/ UINT8 Peg3Enable; -/** Offset 0x00F3 - PEG 0 Max Link Speed +/** Offset 0x00F7 - PEG 0 Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 **/ UINT8 Peg0MaxLinkSpeed; -/** Offset 0x00F4 - PEG 1 Max Link Speed +/** Offset 0x00F8 - PEG 1 Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 **/ UINT8 Peg1MaxLinkSpeed; -/** Offset 0x00F5 - PEG 2 Max Link Speed +/** Offset 0x00F9 - PEG 2 Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 **/ UINT8 Peg2MaxLinkSpeed; -/** Offset 0x00F6 - PEG 3 Max Link Speed +/** Offset 0x00FA - PEG 3 Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 **/ UINT8 Peg3MaxLinkSpeed; -/** Offset 0x00F7 - PEG 0 Max Link Width +/** Offset 0x00FB - PEG 0 Max Link Width Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8 0:Auto, 1:x1, 2:x2, 3:x4, 4:x8 **/ UINT8 Peg0MaxLinkWidth; -/** Offset 0x00F8 - PEG 1 Max Link Width +/** Offset 0x00FC - PEG 1 Max Link Width Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2, (0x3):Limit Link to x4 0:Auto, 1:x1, 2:x2, 3:x4 **/ UINT8 Peg1MaxLinkWidth; -/** Offset 0x00F9 - PEG 2 Max Link Width +/** Offset 0x00FD - PEG 2 Max Link Width Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2 0:Auto, 1:x1, 2:x2 **/ UINT8 Peg2MaxLinkWidth; -/** Offset 0x00FA - PEG 3 Max Link Width +/** Offset 0x00FE - PEG 3 Max Link Width Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2 0:Auto, 1:x1, 2:x2 **/ UINT8 Peg3MaxLinkWidth; -/** Offset 0x00FB - Power down unused lanes on PEG 0 +/** Offset 0x00FF - Power down unused lanes on PEG 0 (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width 0:No power saving, 1:Auto **/ UINT8 Peg0PowerDownUnusedLanes; -/** Offset 0x00FC - Power down unused lanes on PEG 1 +/** Offset 0x0100 - Power down unused lanes on PEG 1 (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width 0:No power saving, 1:Auto **/ UINT8 Peg1PowerDownUnusedLanes; -/** Offset 0x00FD - Power down unused lanes on PEG 2 +/** Offset 0x0101 - Power down unused lanes on PEG 2 (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width 0:No power saving, 1:Auto **/ UINT8 Peg2PowerDownUnusedLanes; -/** Offset 0x00FE - Power down unused lanes on PEG 3 +/** Offset 0x0102 - Power down unused lanes on PEG 3 (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width 0:No power saving, 1:Auto **/ UINT8 Peg3PowerDownUnusedLanes; -/** Offset 0x00FF - PCIe ASPM programming will happen in relation to the Oprom +/** Offset 0x0103 - PCIe ASPM programming will happen in relation to the Oprom Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume @@ -615,34 +625,34 @@ typedef struct { **/ UINT8 InitPcieAspmAfterOprom; -/** Offset 0x0100 - PCIe Disable Spread Spectrum Clocking +/** Offset 0x0104 - PCIe Disable Spread Spectrum Clocking PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled, Disable SSC(0X1) - Disable SSC per platform design or for compliance testing 0:Normal Operation, 1:Disable SSC **/ UINT8 PegDisableSpreadSpectrumClocking; -/** Offset 0x0101 - DMI Gen3 Root port preset values per lane +/** Offset 0x0105 - DMI Gen3 Root port preset values per lane Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane **/ UINT8 DmiGen3RootPortPreset[8]; -/** Offset 0x0109 - DMI Gen3 End port preset values per lane +/** Offset 0x010D - DMI Gen3 End port preset values per lane Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane **/ UINT8 DmiGen3EndPointPreset[8]; -/** Offset 0x0111 - DMI Gen3 End port Hint values per lane +/** Offset 0x0115 - DMI Gen3 End port Hint values per lane Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane **/ UINT8 DmiGen3EndPointHint[8]; -/** Offset 0x0119 - DMI Gen3 RxCTLEp per-Bundle control +/** Offset 0x011D - DMI Gen3 RxCTLEp per-Bundle control Range: 0-15, 0 is default for each bundle, must be specified based upon platform design **/ UINT8 DmiGen3RxCtlePeaking[4]; -/** Offset 0x011D - Thermal Velocity Boost Ratio clipping +/** Offset 0x0121 - Thermal Velocity Boost Ratio clipping 0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction caused by high package temperatures for processors that implement the Intel Thermal Velocity Boost (TVB) feature @@ -650,59 +660,59 @@ typedef struct { **/ UINT8 TvbRatioClipping; -/** Offset 0x011E - Thermal Velocity Boost voltage optimization +/** Offset 0x0122 - Thermal Velocity Boost voltage optimization 0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations for processors that implement the Intel Thermal Velocity Boost (TVB) feature. 0: Disabled, 1: Enabled **/ UINT8 TvbVoltageOptimization; -/** Offset 0x011F - PEG Gen3 RxCTLEp per-Bundle control +/** Offset 0x0123 - PEG Gen3 RxCTLEp per-Bundle control Range: 0-15, 12 is default for each bundle, must be specified based upon platform design **/ UINT8 PegGen3RxCtlePeaking[10]; -/** Offset 0x0129 +/** Offset 0x012D **/ UINT8 UnusedUpdSpace2[3]; -/** Offset 0x012C - Memory data pointer for saved preset search results +/** Offset 0x0130 - Memory data pointer for saved preset search results The reference code will store the Gen3 Preset Search results in the SaDataHob's PegData structure (SA_PEG_DATA) and platform code can save/restore this data to skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0 **/ UINT32 PegDataPtr; -/** Offset 0x0130 - PEG PERST# GPIO information +/** Offset 0x0134 - PEG PERST# GPIO information The reference code will use the information in this structure in order to reset PCIe Gen3 devices during equalization, if necessary **/ UINT8 PegGpioData[28]; -/** Offset 0x014C - PCIe Hot Plug Enable/Disable per port +/** Offset 0x0150 - PCIe Hot Plug Enable/Disable per port 0(Default): Disable, 1: Enable **/ UINT8 PegRootPortHPE[4]; -/** Offset 0x0150 - DeEmphasis control for DMI +/** Offset 0x0154 - DeEmphasis control for DMI DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB 0: -6dB, 1: -3.5dB **/ UINT8 DmiDeEmphasis; -/** Offset 0x0151 - Selection of the primary display device +/** Offset 0x0155 - Selection of the primary display device 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Switchable Graphics **/ UINT8 PrimaryDisplay; -/** Offset 0x0152 - Selection of iGFX GTT Memory size +/** Offset 0x0156 - Selection of iGFX GTT Memory size 1=2MB, 2=4MB, 3=8MB, Default is 3 1:2MB, 2:4MB, 3:8MB **/ UINT16 GttSize; -/** Offset 0x0154 - Temporary MMIO address for GMADR +/** Offset 0x0158 - Temporary MMIO address for GMADR The reference code will use this as Temporary MMIO address space to access GMADR Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress @@ -710,7 +720,7 @@ typedef struct { **/ UINT32 GmAdr; -/** Offset 0x0158 - Temporary MMIO address for GTTMMADR +/** Offset 0x015C - Temporary MMIO address for GTTMMADR The reference code will use this as Temporary MMIO address space to access GTTMMADR Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO @@ -718,155 +728,155 @@ typedef struct { **/ UINT32 GttMmAdr; -/** Offset 0x015C - Selection of PSMI Region size +/** Offset 0x0160 - Selection of PSMI Region size 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB **/ UINT8 PsmiRegionSize; -/** Offset 0x015D - Switchable Graphics GPIO information for PEG 0 +/** Offset 0x0161 - Switchable Graphics GPIO information for PEG 0 Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs **/ UINT8 SaRtd3Pcie0Gpio[24]; -/** Offset 0x0175 - Switchable Graphics GPIO information for PEG 1 +/** Offset 0x0179 - Switchable Graphics GPIO information for PEG 1 Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs **/ UINT8 SaRtd3Pcie1Gpio[24]; -/** Offset 0x018D - Switchable Graphics GPIO information for PEG 2 +/** Offset 0x0191 - Switchable Graphics GPIO information for PEG 2 Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs **/ UINT8 SaRtd3Pcie2Gpio[24]; -/** Offset 0x01A5 - Switchable Graphics GPIO information for PEG 3 +/** Offset 0x01A9 - Switchable Graphics GPIO information for PEG 3 Switchable Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs **/ UINT8 SaRtd3Pcie3Gpio[24]; -/** Offset 0x01BD - Enable/Disable MRC TXT dependency +/** Offset 0x01C1 - Enable/Disable MRC TXT dependency When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization $EN_DIS **/ UINT8 TxtImplemented; -/** Offset 0x01BE - Enable/Disable SA OcSupport +/** Offset 0x01C2 - Enable/Disable SA OcSupport Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport $EN_DIS **/ UINT8 SaOcSupport; -/** Offset 0x01BF - GT slice Voltage Mode +/** Offset 0x01C3 - GT slice Voltage Mode 0(Default): Adaptive, 1: Override 0: Adaptive, 1: Override **/ UINT8 GtVoltageMode; -/** Offset 0x01C0 - Maximum GTs turbo ratio override +/** Offset 0x01C4 - Maximum GTs turbo ratio override 0(Default)=Minimal/Auto, 60=Maximum **/ UINT8 GtMaxOcRatio; -/** Offset 0x01C1 +/** Offset 0x01C5 **/ UINT8 UnusedUpdSpace3; -/** Offset 0x01C2 - The voltage offset applied to GT slice +/** Offset 0x01C6 - The voltage offset applied to GT slice 0(Default)=Minimal, 1000=Maximum **/ UINT16 GtVoltageOffset; -/** Offset 0x01C4 - The GT slice voltage override which is applied to the entire range of GT frequencies +/** Offset 0x01C8 - The GT slice voltage override which is applied to the entire range of GT frequencies 0(Default)=Minimal, 2000=Maximum **/ UINT16 GtVoltageOverride; -/** Offset 0x01C6 - adaptive voltage applied during turbo frequencies +/** Offset 0x01CA - adaptive voltage applied during turbo frequencies 0(Default)=Minimal, 2000=Maximum **/ UINT16 GtExtraTurboVoltage; -/** Offset 0x01C8 - voltage offset applied to the SA +/** Offset 0x01CC - voltage offset applied to the SA 0(Default)=Minimal, 1000=Maximum **/ UINT16 SaVoltageOffset; -/** Offset 0x01CA - PCIe root port Function number for Switchable Graphics dGPU +/** Offset 0x01CE - PCIe root port Function number for Switchable Graphics dGPU Root port Index number to indicate which PCIe root port has dGPU **/ UINT8 RootPortIndex; -/** Offset 0x01CB - Realtime Memory Timing +/** Offset 0x01CF - Realtime Memory Timing 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform realtime memory timing changes after MRC_DONE. 0: Disabled, 1: Enabled **/ UINT8 RealtimeMemoryTiming; -/** Offset 0x01CC - Enable/Disable SA IPU +/** Offset 0x01D0 - Enable/Disable SA IPU Enable(Default): Enable SA IPU, Disable: Disable SA IPU $EN_DIS **/ UINT8 SaIpuEnable; -/** Offset 0x01CD - IPU IMR Configuration +/** Offset 0x01D1 - IPU IMR Configuration 0:IPU Camera, 1:IPU Gen Default is 0 0:IPU Camera, 1:IPU Gen **/ UINT8 SaIpuImrConfiguration; -/** Offset 0x01CE - Selection of PSMI Support On/Off +/** Offset 0x01D2 - Selection of PSMI Support On/Off 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support $EN_DIS **/ UINT8 GtPsmiSupport; -/** Offset 0x01CF - GT unslice Voltage Mode +/** Offset 0x01D3 - GT unslice Voltage Mode 0(Default): Adaptive, 1: Override 0: Adaptive, 1: Override **/ UINT8 GtusVoltageMode; -/** Offset 0x01D0 - voltage offset applied to GT unslice +/** Offset 0x01D4 - voltage offset applied to GT unslice 0(Default)=Minimal, 2000=Maximum **/ UINT16 GtusVoltageOffset; -/** Offset 0x01D2 - GT unslice voltage override which is applied to the entire range of GT frequencies +/** Offset 0x01D6 - GT unslice voltage override which is applied to the entire range of GT frequencies 0(Default)=Minimal, 2000=Maximum **/ UINT16 GtusVoltageOverride; -/** Offset 0x01D4 - adaptive voltage applied during turbo frequencies +/** Offset 0x01D8 - adaptive voltage applied during turbo frequencies 0(Default)=Minimal, 2000=Maximum **/ UINT16 GtusExtraTurboVoltage; -/** Offset 0x01D6 - Maximum GTus turbo ratio override +/** Offset 0x01DA - Maximum GTus turbo ratio override 0(Default)=Minimal, 60=Maximum **/ UINT8 GtusMaxOcRatio; -/** Offset 0x01D7 - SaPreMemProductionRsvd +/** Offset 0x01DB - SaPreMemProductionRsvd Reserved for SA Pre-Mem Production $EN_DIS **/ - UINT8 SaPreMemProductionRsvd[4]; + UINT8 SaPreMemProductionRsvd[3]; -/** Offset 0x01DB - BIST on Reset +/** Offset 0x01DE - BIST on Reset Enable or Disable BIST on Reset; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 BistOnReset; -/** Offset 0x01DC - Skip Stop PBET Timer Enable/Disable +/** Offset 0x01DF - Skip Stop PBET Timer Enable/Disable Skip Stop PBET Timer; 0: Disable; 1: Enable $EN_DIS **/ UINT8 SkipStopPbet; -/** Offset 0x01DD - C6DRAM power gating feature +/** Offset 0x01E0 - C6DRAM power gating feature This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature. @@ -874,54 +884,54 @@ typedef struct { **/ UINT8 EnableC6Dram; -/** Offset 0x01DE - Over clocking support +/** Offset 0x01E1 - Over clocking support Over clocking support; 0: Disable; 1: Enable $EN_DIS **/ UINT8 OcSupport; -/** Offset 0x01DF - Over clocking Lock +/** Offset 0x01E2 - Over clocking Lock Over clocking Lock Enable/Disable; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 OcLock; -/** Offset 0x01E0 - Maximum Core Turbo Ratio Override +/** Offset 0x01E3 - Maximum Core Turbo Ratio Override Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255 **/ UINT8 CoreMaxOcRatio; -/** Offset 0x01E1 - Core voltage mode +/** Offset 0x01E4 - Core voltage mode Core voltage mode; 0: Adaptive; 1: Override. $EN_DIS **/ UINT8 CoreVoltageMode; -/** Offset 0x01E2 - Program Cache Attributes +/** Offset 0x01E5 - Program Cache Attributes Program Cache Attributes; 0: Program; 1: Disable Program. $EN_DIS **/ UINT8 DisableMtrrProgram; -/** Offset 0x01E3 - Maximum clr turbo ratio override +/** Offset 0x01E6 - Maximum clr turbo ratio override Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255 **/ UINT8 RingMaxOcRatio; -/** Offset 0x01E4 - Hyper Threading Enable/Disable +/** Offset 0x01E7 - Hyper Threading Enable/Disable Enable or Disable Hyper Threading; 0: Disable; 1: Enable $EN_DIS **/ UINT8 HyperThreading; -/** Offset 0x01E5 - CPU ratio value +/** Offset 0x01E8 - CPU ratio value CPU ratio value. Valid Range 0 to 63. CPU Ratio is 0 when disabled. **/ UINT8 CpuRatio; -/** Offset 0x01E6 - Boot frequency +/** Offset 0x01E9 - Boot frequency Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.- 1: Maximum non-turbo performance.- 2: Turbo performance. @note If Turbo is selected BIOS will start in max non-turbo mode and switch to Turbo mode. @@ -929,164 +939,156 @@ typedef struct { **/ UINT8 BootFrequency; -/** Offset 0x01E7 - Number of active cores +/** Offset 0x01EA - Number of active cores Number of active cores(Depends on Number of cores). 0: All;1: 1 ;2: 2 ;3: 3 0:All, 1:1, 2:2, 3:3 **/ UINT8 ActiveCoreCount; -/** Offset 0x01E8 - Processor Early Power On Configuration FCLK setting +/** Offset 0x01EB - Processor Early Power On Configuration FCLK setting 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved **/ UINT8 FClkFrequency; -/** Offset 0x01E9 - Set JTAG power in C10 and deeper power states +/** Offset 0x01EC - Set JTAG power in C10 and deeper power states False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 and deeper power states for debug purpose. 0: False; 1: True. 0: False, 1: True **/ UINT8 JtagC10PowerGateDisable; -/** Offset 0x01EA - Enable or Disable VMX +/** Offset 0x01ED - Enable or Disable VMX Enable or Disable VMX; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 VmxEnable; -/** Offset 0x01EB - AVX2 Ratio Offset +/** Offset 0x01EE - AVX2 Ratio Offset 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. **/ UINT8 Avx2RatioOffset; -/** Offset 0x01EC - AVX3 Ratio Offset +/** Offset 0x01EF - AVX3 Ratio Offset 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. **/ UINT8 Avx3RatioOffset; -/** Offset 0x01ED - BCLK Adaptive Voltage Enable +/** Offset 0x01F0 - BCLK Adaptive Voltage Enable When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: Disable; 1: Enable $EN_DIS **/ UINT8 BclkAdaptiveVoltage; -/** Offset 0x01EE - Core PLL voltage offset +/** Offset 0x01F1 - Core PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-63 **/ UINT8 CorePllVoltageOffset; -/** Offset 0x01EF -**/ - UINT8 UnusedUpdSpace4; - -/** Offset 0x01F0 - core voltage override +/** Offset 0x01F2 - core voltage override The core voltage override which is applied to the entire range of cpu core frequencies. Valid Range 0 to 2000 **/ UINT16 CoreVoltageOverride; -/** Offset 0x01F2 - Core Turbo voltage Adaptive +/** Offset 0x01F4 - Core Turbo voltage Adaptive Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. Valid Range 0 to 2000 **/ UINT16 CoreVoltageAdaptive; -/** Offset 0x01F4 - Core Turbo voltage Offset +/** Offset 0x01F6 - Core Turbo voltage Offset The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000 **/ UINT16 CoreVoltageOffset; -/** Offset 0x01F6 - Ring Downbin +/** Offset 0x01F8 - Ring Downbin Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always lower than the core ratio.0: Disable; 1: Enable. $EN_DIS **/ UINT8 RingDownBin; -/** Offset 0x01F7 - Ring voltage mode +/** Offset 0x01F9 - Ring voltage mode Ring voltage mode; 0: Adaptive; 1: Override. $EN_DIS **/ UINT8 RingVoltageMode; -/** Offset 0x01F8 - Ring voltage override +/** Offset 0x01FA - Ring voltage override The ring voltage override which is applied to the entire range of cpu ring frequencies. Valid Range 0 to 2000 **/ UINT16 RingVoltageOverride; -/** Offset 0x01FA - Ring Turbo voltage Adaptive +/** Offset 0x01FC - Ring Turbo voltage Adaptive Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode. Valid Range 0 to 2000 **/ UINT16 RingVoltageAdaptive; -/** Offset 0x01FC - Ring Turbo voltage Offset +/** Offset 0x01FE - Ring Turbo voltage Offset The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000 **/ UINT16 RingVoltageOffset; -/** Offset 0x01FE - TjMax Offset +/** Offset 0x0200 - TjMax Offset TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63 **/ UINT8 TjMaxOffset; -/** Offset 0x01FF - BiosGuard +/** Offset 0x0201 - BiosGuard Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable $EN_DIS **/ UINT8 BiosGuard; -/** Offset 0x0200 +/** Offset 0x0202 **/ UINT8 BiosGuardToolsInterface; -/** Offset 0x0201 - EnableSgx +/** Offset 0x0203 - EnableSgx Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control 0: Disable, 1: Enable, 2: Software Control **/ UINT8 EnableSgx; -/** Offset 0x0202 - Txt +/** Offset 0x0204 - Txt Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable $EN_DIS **/ UINT8 Txt; -/** Offset 0x0203 +/** Offset 0x0205 **/ - UINT8 UnusedUpdSpace5; + UINT8 UnusedUpdSpace4[3]; -/** Offset 0x0204 - PrmrrSize +/** Offset 0x0208 - PrmrrSize 0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000 **/ UINT32 PrmrrSize; -/** Offset 0x0208 - SinitMemorySize +/** Offset 0x020C - SinitMemorySize Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable **/ UINT32 SinitMemorySize; -/** Offset 0x020C - TxtHeapMemorySize +/** Offset 0x0210 - TxtHeapMemorySize Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable **/ UINT32 TxtHeapMemorySize; -/** Offset 0x0210 - TxtDprMemorySize +/** Offset 0x0214 - TxtDprMemorySize Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable **/ UINT32 TxtDprMemorySize; -/** Offset 0x0214 -**/ - UINT8 UnusedUpdSpace6[4]; - /** Offset 0x0218 - TxtDprMemoryBase Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable **/ @@ -1436,7 +1438,7 @@ typedef struct { /** Offset 0x044E **/ - UINT8 UnusedUpdSpace7[2]; + UINT8 UnusedUpdSpace5[2]; /** Offset 0x0450 - Serial Io Uart Debug BaudRate Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, @@ -1462,11 +1464,96 @@ typedef struct { **/ UINT8 SerialIoUartDebugDataBits; -/** Offset 0x0457 - ReservedPchPreMem +/** Offset 0x0457 - Enable HD Audio DSP + Enable/disable HD Audio DSP feature. + $EN_DIS +**/ + UINT8 PchHdaDspEnable; + +/** Offset 0x0458 - VC Type + Virtual Channel Type Select: 0: VC0, 1: VC1. + 0: VC0, 1: VC1 +**/ + UINT8 PchHdaVcType; + +/** Offset 0x0459 - Universal Audio Architecture compliance for DSP enabled system + 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox + driver or SST driver supported). + $EN_DIS +**/ + UINT8 PchHdaDspUaaCompliance; + +/** Offset 0x045A - Enable HD Audio Link + Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkHda; + +/** Offset 0x045B - Enable HD Audio DMIC0 Link + Deprecated. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkDmic0; + +/** Offset 0x045C - Enable HD Audio DMIC1 Link + Deprecated. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkDmic1; + +/** Offset 0x045D - Enable HD Audio SSP0 Link + Enable/disable HD Audio SSP0/I2S link. Muxed with HDA. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSsp0; + +/** Offset 0x045E - Enable HD Audio SSP1 Link + Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSsp1; + +/** Offset 0x045F - Enable HD Audio SSP2 Link + Enable/disable HD Audio SSP2/I2S link. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSsp2; + +/** Offset 0x0460 - Enable HD Audio SoundWire#1 Link + Enable/disable HD Audio SNDW1 link. Muxed with HDA. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSndw1; + +/** Offset 0x0461 - Enable HD Audio SoundWire#2 Link + Enable/disable HD Audio SNDW2 link. Muxed with SSP1. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSndw2; + +/** Offset 0x0462 - Enable HD Audio SoundWire#3 Link + Enable/disable HD Audio SNDW3 link. Muxed with DMIC1. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSndw3; + +/** Offset 0x0463 - Enable HD Audio SoundWire#4 Link + Enable/disable HD Audio SNDW4 link. Muxed with DMIC0. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSndw4; + +/** Offset 0x0464 - Soundwire Clock Buffer GPIO RCOMP Setting + 0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance. + $EN_DIS +**/ + UINT8 PchHdaSndwBufferRcomp; + +/** Offset 0x0465 - ReservedPchPreMem Reserved for Pch Pre-Mem $EN_DIS **/ - UINT8 ReservedPchPreMem[16]; + UINT8 ReservedPchPreMem[2]; /** Offset 0x0467 - ISA Serial Base selection Select ISA Serial Base address. Default is 0x3F8. @@ -1842,7 +1929,7 @@ typedef struct { /** Offset 0x04A5 **/ - UINT8 UnusedUpdSpace8; + UINT8 UnusedUpdSpace6; /** Offset 0x04A6 - Ch Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to @@ -1931,7 +2018,7 @@ typedef struct { /** Offset 0x04BB **/ - UINT8 UnusedUpdSpace9; + UINT8 UnusedUpdSpace7; /** Offset 0x04BC - RAPL PL 2 Power range[0;2^14-1]= [2047.875;0]in W, (222= Def) @@ -2282,7 +2369,7 @@ typedef struct { Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose. 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load - Error Warnings and Info, 5:Load Error Warnings Info and Verbose + Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose **/ UINT8 PcdSerialDebugLevel; @@ -2376,13 +2463,39 @@ typedef struct { **/ UINT8 MrcTrainOnWarm; -/** Offset 0x050E +/** Offset 0x050E - Lpddr Dram Odt + Override Enable/Disable for the ODT logic for LPDDR3 memory. Default is 2 (AUTO) + 0:Disable, 1:Enable, 2:AUTO **/ - UINT8 UnusedUpdSpace10[2]; + UINT8 LpddrDramOdt; -/** Offset 0x0510 +/** Offset 0x050F - DDR4 Skip Refresh Enable + Enable/Disable of DDR4 Temperature Controlled Refresh on DRAM. Default is 1 (Enabled) + 0:Disable, 1:Enable **/ - UINT8 ReservedFspmUpd[8]; + UINT8 Ddr4SkipRefreshEn; + +/** Offset 0x0510 - SerialDebugMrcLevel + MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, + Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, + Info & Verbose. + 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load + Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose +**/ + UINT8 SerialDebugMrcLevel; + +/** Offset 0x0511 - Enable HD Audio Sndw Link IO Control + deprecated +**/ + UINT8 PchHdaSndwLinkIoControlEnabled[4]; + +/** Offset 0x0515 +**/ + UINT8 UnusedUpdSpace8[2]; + +/** Offset 0x0517 +**/ + UINT8 ReservedFspmUpd[1]; } FSP_M_CONFIG; /** Fsp M Test Configuration @@ -2607,7 +2720,7 @@ typedef struct { /** Offset 0x0571 **/ - UINT8 UnusedUpdSpace11; + UINT8 UnusedUpdSpace9; /** Offset 0x0572 - Jitter Dwell Time for PCIe Gen3 Software Equalization Range: 0-65535, default is 1000. @warning Do not change from the default @@ -2650,7 +2763,7 @@ typedef struct { /** Offset 0x057D **/ - UINT8 UnusedUpdSpace12; + UINT8 UnusedUpdSpace10; /** Offset 0x057E - Delta T12 Power Cycle Delay required in ms Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate @@ -2667,7 +2780,7 @@ typedef struct { /** Offset 0x0589 **/ - UINT8 UnusedUpdSpace13; + UINT8 UnusedUpdSpace11; /** Offset 0x058A - TotalFlashSize Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable @@ -2869,7 +2982,7 @@ typedef struct { /** Offset 0x05C0 **/ - UINT8 ReservedFspmTestUpd[4]; + UINT8 ReservedFspmTestUpd[8]; } FSP_M_TEST_CONFIG; /** Fsp M UPD Configuration @@ -2892,9 +3005,13 @@ typedef struct { **/ FSP_M_TEST_CONFIG FspmTestConfig; -/** Offset 0x05C4 +/** Offset 0x05C8 **/ - UINT32 UpdTerminator; + UINT8 UnusedUpdSpace12[6]; + +/** Offset 0x05CE +**/ + UINT16 UpdTerminator; } FSPM_UPD; #pragma pack() diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h index e6f891987e..0df3063e5c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h @@ -37,49 +37,49 @@ are permitted provided that the following conditions are met: #pragma pack(1) - -/// -/// Azalia Header structure -/// -typedef struct { - UINT16 VendorId; ///< Codec Vendor ID - UINT16 DeviceId; ///< Codec Device ID - UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. - UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. - UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. - UINT32 Reserved; ///< Reserved for future use. Must be set to 0. -} AZALIA_HEADER; - -/// -/// Audio Azalia Verb Table structure -/// -typedef struct { - AZALIA_HEADER Header; ///< AZALIA PCH header - UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header -} AUDIO_AZALIA_VERB_TABLE; - -/// -/// Refer to the definition of PCH_INT_PIN -/// -typedef enum { - SiPchNoInt, ///< No Interrupt Pin - SiPchIntA, - SiPchIntB, - SiPchIntC, - SiPchIntD -} SI_PCH_INT_PIN; -/// -/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. -/// -typedef struct { - UINT8 Device; ///< Device number - UINT8 Function; ///< Device function - UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) - UINT8 Irq; ///< IRQ to be set for device. -} SI_PCH_DEVICE_INTERRUPT_CONFIG; - -#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices - + +/// +/// Azalia Header structure +/// +typedef struct { + UINT16 VendorId; ///< Codec Vendor ID + UINT16 DeviceId; ///< Codec Device ID + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. + UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. + UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. + UINT32 Reserved; ///< Reserved for future use. Must be set to 0. +} AZALIA_HEADER; + +/// +/// Audio Azalia Verb Table structure +/// +typedef struct { + AZALIA_HEADER Header; ///< AZALIA PCH header + UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header +} AUDIO_AZALIA_VERB_TABLE; + +/// +/// Refer to the definition of PCH_INT_PIN +/// +typedef enum { + SiPchNoInt, ///< No Interrupt Pin + SiPchIntA, + SiPchIntB, + SiPchIntC, + SiPchIntD +} SI_PCH_INT_PIN; +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} SI_PCH_DEVICE_INTERRUPT_CONFIG; + +#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices + /** Fsp S Configuration **/ @@ -139,306 +139,316 @@ typedef struct { **/ UINT8 Heci3Enabled; -/** Offset 0x003B - AMT Switch +/** Offset 0x003B - HECI1 state + Determine if HECI1 is hidden prior to boot to OS. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 Heci1Disabled; + +/** Offset 0x003C - AMT Switch Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality. $EN_DIS **/ UINT8 AmtEnabled; -/** Offset 0x003C - WatchDog Timer Switch +/** Offset 0x003D - WatchDog Timer Switch Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting is invalid if AmtEnabled is 0. $EN_DIS **/ UINT8 WatchDogEnabled; -/** Offset 0x003D - Manageability Mode set by Mebx +/** Offset 0x003E - Manageability Mode set by Mebx Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode. $EN_DIS **/ UINT8 ManageabilityMode; -/** Offset 0x003E - PET Progress +/** Offset 0x003F - PET Progress Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive PET Events. Setting is invalid if AmtEnabled is 0. $EN_DIS **/ UINT8 FwProgress; -/** Offset 0x003F - SOL Switch +/** Offset 0x0040 - SOL Switch Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx. Setting is invalid if AmtEnabled is 0. $EN_DIS **/ UINT8 AmtSolEnabled; -/** Offset 0x0040 - OS Timer +/** Offset 0x0041 +**/ + UINT8 UnusedUpdSpace1; + +/** Offset 0x0042 - OS Timer 16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0. **/ UINT16 WatchDogTimerOs; -/** Offset 0x0042 - BIOS Timer +/** Offset 0x0044 - BIOS Timer 16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0. **/ UINT16 WatchDogTimerBios; -/** Offset 0x0044 - Remote Assistance Trigger Availablilty +/** Offset 0x0046 - Remote Assistance Trigger Availablilty Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx. $EN_DIS **/ UINT8 RemoteAssistance; -/** Offset 0x0045 - KVM Switch +/** Offset 0x0047 - KVM Switch Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. Setting is invalid if AmtEnabled is 0. $EN_DIS **/ UINT8 AmtKvmEnabled; -/** Offset 0x0046 - MEBX execution +/** Offset 0x0048 - MEBX execution Enable/Disable. 0: Disable, 1: enable, Force MEBX execution. $EN_DIS **/ UINT8 ForcMebxSyncUp; -/** Offset 0x0047 - Enable/Disable SA CRID +/** Offset 0x0049 - Enable/Disable SA CRID Enable: SA CRID, Disable (Default): SA CRID $EN_DIS **/ UINT8 CridEnable; -/** Offset 0x0048 - DMI ASPM +/** Offset 0x004A - DMI ASPM 0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1 0:Disable, 1:L0s, 2:L1, 3:L0sL1 **/ UINT8 DmiAspm; -/** Offset 0x0049 - PCIe DeEmphasis control per root port +/** Offset 0x004B - PCIe DeEmphasis control per root port 0: -6dB, 1(Default): -3.5dB 0:-6dB, 1:-3.5dB **/ UINT8 PegDeEmphasis[4]; -/** Offset 0x004D - PCIe Slot Power Limit value per root port +/** Offset 0x004F - PCIe Slot Power Limit value per root port Slot power limit value per root port **/ UINT8 PegSlotPowerLimitValue[4]; -/** Offset 0x0051 - PCIe Slot Power Limit scale per root port +/** Offset 0x0053 - PCIe Slot Power Limit scale per root port Slot power limit scale per root port 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x **/ UINT8 PegSlotPowerLimitScale[4]; -/** Offset 0x0055 +/** Offset 0x0057 **/ - UINT8 UnusedUpdSpace1[1]; + UINT8 UnusedUpdSpace2[1]; -/** Offset 0x0056 - PCIe Physical Slot Number per root port +/** Offset 0x0058 - PCIe Physical Slot Number per root port Physical Slot Number per root port **/ UINT16 PegPhysicalSlotNumber[4]; -/** Offset 0x005E - Enable/Disable PavpEnable +/** Offset 0x0060 - Enable/Disable PavpEnable Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable $EN_DIS **/ UINT8 PavpEnable; -/** Offset 0x005F - CdClock Frequency selection +/** Offset 0x0061 - CdClock Frequency selection 0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)=675 Mhz 0: 337.5 Mhz, 1: 450 Mhz, 2: 540 Mhz, 3: 675 Mhz **/ UINT8 CdClock; -/** Offset 0x0060 - Enable/Disable PeiGraphicsPeimInit +/** Offset 0x0062 - Enable/Disable PeiGraphicsPeimInit Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit $EN_DIS **/ UINT8 PeiGraphicsPeimInit; -/** Offset 0x0061 - Enable or disable GNA device +/** Offset 0x0063 - Enable or disable GNA device 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 GnaEnable; -/** Offset 0x0062 - State of X2APIC_OPT_OUT bit in the DMAR table +/** Offset 0x0064 - State of X2APIC_OPT_OUT bit in the DMAR table 0=Disable/Clear, 1=Enable/Set $EN_DIS **/ UINT8 X2ApicOptOutDeprecated; -/** Offset 0x0063 +/** Offset 0x0065 **/ - UINT8 UnusedUpdSpace2[1]; + UINT8 UnusedUpdSpace3[3]; -/** Offset 0x0064 - Base addresses for VT-d function MMIO access +/** Offset 0x0068 - Base addresses for VT-d function MMIO access Base addresses for VT-d MMIO access per VT-d engine **/ UINT32 VtdBaseAddressDeprecated[3]; -/** Offset 0x0070 - Enable or disable eDP device +/** Offset 0x0074 - Enable or disable eDP device 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortEdp; -/** Offset 0x0071 - Enable or disable HPD of DDI port B +/** Offset 0x0075 - Enable or disable HPD of DDI port B 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortBHpd; -/** Offset 0x0072 - Enable or disable HPD of DDI port C +/** Offset 0x0076 - Enable or disable HPD of DDI port C 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortCHpd; -/** Offset 0x0073 - Enable or disable HPD of DDI port D +/** Offset 0x0077 - Enable or disable HPD of DDI port D 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortDHpd; -/** Offset 0x0074 - Enable or disable HPD of DDI port F +/** Offset 0x0078 - Enable or disable HPD of DDI port F 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortFHpd; -/** Offset 0x0075 - Enable or disable DDC of DDI port B +/** Offset 0x0079 - Enable or disable DDC of DDI port B 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortBDdc; -/** Offset 0x0076 - Enable or disable DDC of DDI port C +/** Offset 0x007A - Enable or disable DDC of DDI port C 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortCDdc; -/** Offset 0x0077 - Enable or disable DDC of DDI port D +/** Offset 0x007B - Enable or disable DDC of DDI port D 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortDDdc; -/** Offset 0x0078 - Enable or disable DDC of DDI port F +/** Offset 0x007C - Enable or disable DDC of DDI port F 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPortFDdc; -/** Offset 0x0079 - Enable/Disable SkipS3CdClockInit +/** Offset 0x007D - Enable/Disable SkipS3CdClockInit Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full CD clock in S3 resume due to GOP absent $EN_DIS **/ UINT8 SkipS3CdClockInit; -/** Offset 0x007A - Delta T12 Power Cycle Delay required in ms +/** Offset 0x007E - Delta T12 Power Cycle Delay required in ms DEPRECATED 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay **/ UINT16 DeltaT12PowerCycleDelay; -/** Offset 0x007C - Blt Buffer Address +/** Offset 0x0080 - Blt Buffer Address Address of Blt buffer **/ UINT32 BltBufferAddress; -/** Offset 0x0080 - Blt Buffer Size +/** Offset 0x0084 - Blt Buffer Size Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of EFI_GRAPHICS_OUTPUT_BLT_PIXEL) **/ UINT32 BltBufferSize; -/** Offset 0x0084 - Program GT Chicken bits +/** Offset 0x0088 - Program GT Chicken bits Progarm the GT chicken bits in GTTMMADR + 0xD00 BITS [3:1] **/ UINT8 ProgramGtChickenBits; -/** Offset 0x0085 - SaPostMemProductionRsvd +/** Offset 0x0089 - SaPostMemProductionRsvd Reserved for SA Post-Mem Production $EN_DIS **/ UINT8 SaPostMemProductionRsvd[34]; -/** Offset 0x00A7 - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable +/** Offset 0x00AB - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for Alpine ridge **/ UINT8 PcieRootPortGen2PllL1CgDisable[24]; -/** Offset 0x00BF - Advanced Encryption Standard (AES) feature +/** Offset 0x00C3 - Advanced Encryption Standard (AES) feature Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable $EN_DIS **/ UINT8 AesEnable; -/** Offset 0x00C0 - Power State 3 enable/disable +/** Offset 0x00C4 - Power State 3 enable/disable PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. For all VR Indexes **/ UINT8 Psi3Enable[5]; -/** Offset 0x00C5 - Power State 4 enable/disable +/** Offset 0x00C9 - Power State 4 enable/disable PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For all VR Indexes **/ UINT8 Psi4Enable[5]; -/** Offset 0x00CA - Imon slope correction +/** Offset 0x00CE - Imon slope correction PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes **/ UINT8 ImonSlope[5]; -/** Offset 0x00CF - Imon offset correction +/** Offset 0x00D3 - Imon offset correction DEPRECATED **/ UINT8 ImonOffset[5]; -/** Offset 0x00D4 - Enable/Disable BIOS configuration of VR +/** Offset 0x00D8 - Enable/Disable BIOS configuration of VR Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes **/ UINT8 VrConfigEnable[5]; -/** Offset 0x00D9 - Thermal Design Current enable/disable +/** Offset 0x00DD - Thermal Design Current enable/disable PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: Enable.For all VR Indexes **/ UINT8 TdcEnable[5]; -/** Offset 0x00DE - HECI3 state +/** Offset 0x00E2 - HECI3 state PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms , 8 - 8ms , 10 - 10ms.For all VR Indexe **/ UINT8 TdcTimeWindow[5]; -/** Offset 0x00E3 - Thermal Design Current Lock +/** Offset 0x00E7 - Thermal Design Current Lock PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For all VR Indexes **/ UINT8 TdcLock[5]; -/** Offset 0x00E8 - Platform Psys slope correction +/** Offset 0x00EC - Platform Psys slope correction PCODE MMIO Mailbox: Platform Psys slope correction. 0 - Auto Specified in 1/100 increment values. Range is 0-200. 125 = 1.25 **/ UINT8 PsysSlope; -/** Offset 0x00E9 - Platform Psys offset correction +/** Offset 0x00ED - Platform Psys offset correction PCODE MMIO Mailbox: Platform Psys offset correction. 0 - Auto Units 1/4, Range 0-255. Value of 100 = 100/4 = 25 offset **/ UINT8 PsysOffset; -/** Offset 0x00EA - Acoustic Noise Mitigation feature +/** Offset 0x00EE - Acoustic Noise Mitigation feature Enable or Disable Acoustic Noise Mitigation feature. This has to be enabled to program slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.0: Disabled; 1: Enabled @@ -446,96 +456,96 @@ typedef struct { **/ UINT8 AcousticNoiseMitigation; -/** Offset 0x00EB - Disable Fast Slew Rate for Deep Package C States for VR IA domain +/** Offset 0x00EF - Disable Fast Slew Rate for Deep Package C States for VR IA domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True $EN_DIS **/ UINT8 FastPkgCRampDisableIa; -/** Offset 0x00EC - Slew Rate configuration for Deep Package C States for VR IA domain +/** Offset 0x00F0 - Slew Rate configuration for Deep Package C States for VR IA domain Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 **/ UINT8 SlowSlewRateForIa; -/** Offset 0x00ED - Slew Rate configuration for Deep Package C States for VR GT domain +/** Offset 0x00F1 - Slew Rate configuration for Deep Package C States for VR GT domain Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 **/ UINT8 SlowSlewRateForGt; -/** Offset 0x00EE - Slew Rate configuration for Deep Package C States for VR SA domain +/** Offset 0x00F2 - Slew Rate configuration for Deep Package C States for VR SA domain Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 **/ UINT8 SlowSlewRateForSa; -/** Offset 0x00EF +/** Offset 0x00F3 **/ - UINT8 UnusedUpdSpace3[1]; + UINT8 UnusedUpdSpace4[1]; -/** Offset 0x00F0 - Thermal Design Current current limit +/** Offset 0x00F4 - Thermal Design Current current limit PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes **/ UINT16 TdcPowerLimit[5]; -/** Offset 0x00FA - AcLoadline +/** Offset 0x00FE - AcLoadline PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249. Intel Recommended Defaults vary by domain and SKU. **/ UINT16 AcLoadline[5]; -/** Offset 0x0104 - DcLoadline +/** Offset 0x0108 - DcLoadline PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249.Intel Recommended Defaults vary by domain and SKU. **/ UINT16 DcLoadline[5]; -/** Offset 0x010E - Power State 1 Threshold current +/** Offset 0x0112 - Power State 1 Threshold current PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A. **/ UINT16 Psi1Threshold[5]; -/** Offset 0x0118 - Power State 2 Threshold current +/** Offset 0x011C - Power State 2 Threshold current PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A. **/ UINT16 Psi2Threshold[5]; -/** Offset 0x0122 - Power State 3 Threshold current +/** Offset 0x0126 - Power State 3 Threshold current PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A. **/ UINT16 Psi3Threshold[5]; -/** Offset 0x012C - Icc Max limit +/** Offset 0x0130 - Icc Max limit PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A **/ UINT16 IccMax[5]; -/** Offset 0x0136 - VR Voltage Limit +/** Offset 0x013A - VR Voltage Limit PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV. **/ UINT16 VrVoltageLimit[5]; -/** Offset 0x0140 - Disable Fast Slew Rate for Deep Package C States for VR GT domain +/** Offset 0x0144 - Disable Fast Slew Rate for Deep Package C States for VR GT domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True $EN_DIS **/ UINT8 FastPkgCRampDisableGt; -/** Offset 0x0141 - Disable Fast Slew Rate for Deep Package C States for VR SA domain +/** Offset 0x0145 - Disable Fast Slew Rate for Deep Package C States for VR SA domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True $EN_DIS **/ UINT8 FastPkgCRampDisableSa; -/** Offset 0x0142 - Enable VR specific mailbox command +/** Offset 0x0146 - Enable VR specific mailbox command VR specific mailbox commands. 00b - no VR specific command sent. 01b - A VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific command sent for PS4 exit issue. 11b - Reserved. @@ -543,209 +553,209 @@ typedef struct { **/ UINT8 SendVrMbxCmd; -/** Offset 0x0143 - Reserved +/** Offset 0x0147 - Reserved Reserved **/ UINT8 Reserved2; -/** Offset 0x0144 - Enable or Disable TXT +/** Offset 0x0148 - Enable or Disable TXT Enable or Disable TXT; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 TxtEnable; -/** Offset 0x0145 - Deprecated DO NOT USE Skip Multi-Processor Initialization +/** Offset 0x0149 - Deprecated DO NOT USE Skip Multi-Processor Initialization @deprecated SkipMpInit has been moved to FspmUpd $EN_DIS **/ UINT8 SkipMpInitDeprecated; -/** Offset 0x0146 - McIVR RFI Frequency Prefix +/** Offset 0x014A - McIVR RFI Frequency Prefix PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. 0: Plus (+); 1: Minus (-). **/ UINT8 McivrRfiFrequencyPrefix; -/** Offset 0x0147 - McIVR RFI Frequency Adjustment +/** Offset 0x014B - McIVR RFI Frequency Adjustment PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in increments of 100KHz. For subtraction, change McivrRfiFrequencyPrefix. 0: Auto. **/ UINT8 McivrRfiFrequencyAdjust; -/** Offset 0x0148 - FIVR RFI Frequency +/** Offset 0x014C - FIVR RFI Frequency PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. 0: Auto. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock; 0-1535 (Up to 153.5MHz) for 19MHz clock. **/ UINT16 FivrRfiFrequency; -/** Offset 0x014A - McIVR RFI Spread Spectrum +/** Offset 0x014E - McIVR RFI Spread Spectrum PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. 0: 0%; 1: +/- 0.5%; 2: +/- 1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%. **/ UINT8 McivrSpreadSpectrum; -/** Offset 0x014B - FIVR RFI Spread Spectrum +/** Offset 0x014F - FIVR RFI Spread Spectrum PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. 0: 0%; Range: 0.0% to 10.0% (0-100). **/ UINT8 FivrSpreadSpectrum; -/** Offset 0x014C - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain +/** Offset 0x0150 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True $EN_DIS **/ UINT8 FastPkgCRampDisableFivr; -/** Offset 0x014D - Slew Rate configuration for Deep Package C States for VR FIVR domain +/** Offset 0x0151 - Slew Rate configuration for Deep Package C States for VR FIVR domain Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 **/ UINT8 SlowSlewRateForFivr; -/** Offset 0x014E +/** Offset 0x0152 **/ - UINT8 UnusedUpdSpace4[2]; + UINT8 UnusedUpdSpace5[2]; -/** Offset 0x0150 - CpuBistData +/** Offset 0x0154 - CpuBistData Pointer CPU BIST Data **/ UINT32 CpuBistData; -/** Offset 0x0154 - Activates VR mailbox command for Intersil VR C-state issues. +/** Offset 0x0158 - Activates VR mailbox command for Intersil VR C-state issues. Intersil VR mailbox command. 0 - no mailbox command sent. 1 - VR mailbox command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails. **/ UINT8 IslVrCmd; -/** Offset 0x0155 +/** Offset 0x0159 **/ - UINT8 UnusedUpdSpace5[1]; + UINT8 UnusedUpdSpace6[1]; -/** Offset 0x0156 - Imon slope1 correction +/** Offset 0x015A - Imon slope1 correction PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes **/ UINT16 ImonSlope1[5]; -/** Offset 0x0160 - CPU VR Power Delivery Design +/** Offset 0x0164 - CPU VR Power Delivery Design Used to communicate the power delivery design capability of the board. This value is an enum of the available power delivery segments that are defined in the Platform Design Guide. **/ UINT32 VrPowerDeliveryDesign; -/** Offset 0x0164 - Pre Wake Randomization time +/** Offset 0x0168 - Pre Wake Randomization time PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled. Range 0-255 0. **/ UINT8 PreWake; -/** Offset 0x0165 - Ramp Up Randomization time +/** Offset 0x0169 - Ramp Up Randomization time PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Up randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range 0-255 0. **/ UINT8 RampUp; -/** Offset 0x0166 - Ramp Down Randomization time +/** Offset 0x016A - Ramp Down Randomization time PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Down randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range 0-255 0. **/ UINT8 RampDown; -/** Offset 0x0167 +/** Offset 0x016B **/ - UINT8 UnusedUpdSpace6; + UINT8 UnusedUpdSpace7; -/** Offset 0x0168 - CpuMpPpi +/** Offset 0x016C - CpuMpPpi Pointer for CpuMpPpi **/ UINT32 CpuMpPpi; -/** Offset 0x016C - CpuMpHob +/** Offset 0x0170 - CpuMpHob Pointer for CpuMpHob. This is optional data buffer for CpuMpPpi usage. **/ UINT32 CpuMpHob; -/** Offset 0x0170 - Enable or Disable processor debug features +/** Offset 0x0174 - Enable or Disable processor debug features Enable or Disable processor debug features; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DebugInterfaceEnable; -/** Offset 0x0171 +/** Offset 0x0175 **/ - UINT8 UnusedUpdSpace7[1]; + UINT8 UnusedUpdSpace8[1]; -/** Offset 0x0172 - Imon offset 1 correction +/** Offset 0x0176 - Imon offset 1 correction PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto **/ UINT16 ImonOffset1[5]; -/** Offset 0x017C - ReservedCpuPostMemProduction +/** Offset 0x0180 - ReservedCpuPostMemProduction Reserved for CPU Post-Mem Production $EN_DIS **/ UINT8 ReservedCpuPostMemProduction[8]; -/** Offset 0x0184 - Enable HD Audio DSP +/** Offset 0x0188 - Enable HD Audio DSP Enable/disable HD Audio DSP feature. $EN_DIS **/ UINT8 PchHdaDspEnable; -/** Offset 0x0185 - SPI0 Chip Select Polarity +/** Offset 0x0189 - SPI0 Chip Select Polarity Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, 1:PchSerialIoCsActiveHigh **/ UINT8 SerialIoSpi0CsPolarity[2]; -/** Offset 0x0187 - SPI1 Chip Select Polarity +/** Offset 0x018B - SPI1 Chip Select Polarity Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, 1:PchSerialIoCsActiveHigh **/ UINT8 SerialIoSpi1CsPolarity[2]; -/** Offset 0x0189 - SPI2 Chip Select Polarity +/** Offset 0x018D - SPI2 Chip Select Polarity Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, 1:PchSerialIoCsActiveHigh **/ UINT8 SerialIoSpi2CsPolarity[2]; -/** Offset 0x018B - SPI0 Chip Select Enable +/** Offset 0x018F - SPI0 Chip Select Enable 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled **/ UINT8 SerialIoSpi0CsEnable[2]; -/** Offset 0x018D - SPI1 Chip Select Enable +/** Offset 0x0191 - SPI1 Chip Select Enable 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled **/ UINT8 SerialIoSpi1CsEnable[2]; -/** Offset 0x018F - SPI2 Chip Select Enable +/** Offset 0x0193 - SPI2 Chip Select Enable 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled **/ UINT8 SerialIoSpi2CsEnable[2]; -/** Offset 0x0191 - SPIn Device Mode +/** Offset 0x0195 - SPIn Device Mode Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden **/ UINT8 SerialIoSpiMode[3]; -/** Offset 0x0194 - SPIn Default Chip Select Output +/** Offset 0x0198 - SPIn Default Chip Select Output Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available options: 0:CS0, 1:CS1 **/ UINT8 SerialIoSpiDefaultCsOutput[3]; -/** Offset 0x0197 - PCH SerialIo I2C Pads Termination +/** Offset 0x019B - PCH SerialIo I2C Pads Termination 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 @@ -753,1035 +763,1037 @@ typedef struct { **/ UINT8 PchSerialIoI2cPadsTermination[6]; -/** Offset 0x019D - I2Cn Device Mode +/** Offset 0x01A1 - I2Cn Device Mode Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden **/ UINT8 SerialIoI2cMode[6]; -/** Offset 0x01A3 - UARTn Device Mode +/** Offset 0x01A7 - UARTn Device Mode Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, 4:SerialIoUartSkipInit **/ UINT8 SerialIoUartMode[3]; -/** Offset 0x01A6 +/** Offset 0x01AA **/ - UINT8 UnusedUpdSpace8[2]; + UINT8 UnusedUpdSpace9[2]; -/** Offset 0x01A8 - Default BaudRate for each Serial IO UART +/** Offset 0x01AC - Default BaudRate for each Serial IO UART Set default BaudRate Supported from 0 - default to 6000000 **/ UINT32 SerialIoUartBaudRate[3]; -/** Offset 0x01B4 - Default ParityType for each Serial IO UART +/** Offset 0x01B8 - Default ParityType for each Serial IO UART Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity **/ UINT8 SerialIoUartParity[3]; -/** Offset 0x01B7 - Default DataBits for each Serial IO UART +/** Offset 0x01BB - Default DataBits for each Serial IO UART Set default word length. 0: Default, 5,6,7,8 **/ UINT8 SerialIoUartDataBits[3]; -/** Offset 0x01BA - Default StopBits for each Serial IO UART +/** Offset 0x01BE - Default StopBits for each Serial IO UART Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits **/ UINT8 SerialIoUartStopBits[3]; -/** Offset 0x01BD - Power Gating mode for each Serial IO UART that works in COM mode +/** Offset 0x01C1 - Power Gating mode for each Serial IO UART that works in COM mode Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto **/ UINT8 SerialIoUartPowerGating[3]; -/** Offset 0x01C0 - Enable Dma for each Serial IO UART that supports it +/** Offset 0x01C4 - Enable Dma for each Serial IO UART that supports it Set DMA/PIO mode. 0: Disabled, 1: Enabled **/ UINT8 SerialIoUartDmaEnable[3]; -/** Offset 0x01C3 - Enables UART hardware flow control, CTS and RTS lines +/** Offset 0x01C7 - Enables UART hardware flow control, CTS and RTS lines Enables UART hardware flow control, CTS and RTS lines. **/ UINT8 SerialIoUartAutoFlow[3]; -/** Offset 0x01C6 - Serial IO UART Pin Mux +/** Offset 0x01CA - Serial IO UART Pin Mux Applies only to UART0 muxed with CNVI 0 = GPIO C8 to C11 1 = GPIO F5 - F7 (PCH LP) J5 - J7 (PCH H) **/ UINT8 SerialIoUartPinMux[3]; -/** Offset 0x01C9 - UART Number For Debug Purpose +/** Offset 0x01CD - UART Number For Debug Purpose UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose. 0:UART0, 1:UART1, 2:UART2 **/ UINT8 SerialIoDebugUartNumber; -/** Offset 0x01CA - Serial IO UART DBG2 table +/** Offset 0x01CE - Serial IO UART DBG2 table Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable; 1: Enable. **/ UINT8 SerialIoUartDbg2[3]; -/** Offset 0x01CD - Enable eMMC Controller +/** Offset 0x01D1 - Enable eMMC Controller Enable/disable eMMC Controller. $EN_DIS **/ UINT8 ScsEmmcEnabled; -/** Offset 0x01CE - Enable eMMC HS400 Mode +/** Offset 0x01D2 - Enable eMMC HS400 Mode Enable eMMC HS400 Mode. $EN_DIS **/ UINT8 ScsEmmcHs400Enabled; -/** Offset 0x01CF - Enable SdCard Controller +/** Offset 0x01D3 - Enable SdCard Controller Enable/disable SD Card Controller. $EN_DIS **/ UINT8 ScsSdCardEnabled; -/** Offset 0x01D0 - Show SPI controller +/** Offset 0x01D4 - Show SPI controller Enable/disable to show SPI controller. $EN_DIS **/ UINT8 ShowSpiController; -/** Offset 0x01D1 - Enable SATA SALP Support +/** Offset 0x01D5 - Enable SATA SALP Support Enable/disable SATA Aggressive Link Power Management. $EN_DIS **/ UINT8 SataSalpSupport; -/** Offset 0x01D2 - Enable SATA ports +/** Offset 0x01D6 - Enable SATA ports Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 SataPortsEnable[8]; -/** Offset 0x01DA - Enable SATA DEVSLP Feature +/** Offset 0x01DE - Enable SATA DEVSLP Feature Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 SataPortsDevSlp[8]; -/** Offset 0x01E2 - Enable USB2 ports +/** Offset 0x01E6 - Enable USB2 ports Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 PortUsb20Enable[16]; -/** Offset 0x01F2 - Enable USB3 ports +/** Offset 0x01F6 - Enable USB3 ports Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 PortUsb30Enable[10]; -/** Offset 0x01FC - Enable xDCI controller +/** Offset 0x0200 - Enable xDCI controller Enable/disable to xDCI controller. $EN_DIS **/ UINT8 XdciEnable; -/** Offset 0x01FD +/** Offset 0x0201 **/ - UINT8 UnusedUpdSpace9[3]; + UINT8 UnusedUpdSpace10[3]; -/** Offset 0x0200 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. +/** Offset 0x0204 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. **/ UINT32 DevIntConfigPtr; -/** Offset 0x0204 - Number of DevIntConfig Entry +/** Offset 0x0208 - Number of DevIntConfig Entry Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr must not be NULL. **/ UINT8 NumOfDevIntConfig; -/** Offset 0x0205 - PIRQx to IRQx Map Config +/** Offset 0x0209 - PIRQx to IRQx Map Config PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy 8259 PCI mode. **/ UINT8 PxRcConfig[8]; -/** Offset 0x020D - Select GPIO IRQ Route +/** Offset 0x0211 - Select GPIO IRQ Route GPIO IRQ Select. The valid value is 14 or 15. **/ UINT8 GpioIrqRoute; -/** Offset 0x020E - Select SciIrqSelect +/** Offset 0x0212 - Select SciIrqSelect SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. **/ UINT8 SciIrqSelect; -/** Offset 0x020F - Select TcoIrqSelect +/** Offset 0x0213 - Select TcoIrqSelect TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. **/ UINT8 TcoIrqSelect; -/** Offset 0x0210 - Enable/Disable Tco IRQ +/** Offset 0x0214 - Enable/Disable Tco IRQ Enable/disable TCO IRQ $EN_DIS **/ UINT8 TcoIrqEnable; -/** Offset 0x0211 - PCH HDA Verb Table Entry Number +/** Offset 0x0215 - PCH HDA Verb Table Entry Number Number of Entries in Verb Table. **/ UINT8 PchHdaVerbTableEntryNum; -/** Offset 0x0212 +/** Offset 0x0216 **/ - UINT8 UnusedUpdSpace10[2]; + UINT8 UnusedUpdSpace11[2]; -/** Offset 0x0214 - PCH HDA Verb Table Pointer +/** Offset 0x0218 - PCH HDA Verb Table Pointer Pointer to Array of pointers to Verb Table. **/ UINT32 PchHdaVerbTablePtr; -/** Offset 0x0218 - PCH HDA Codec Sx Wake Capability +/** Offset 0x021C - PCH HDA Codec Sx Wake Capability Capability to detect wake initiated by a codec in Sx **/ UINT8 PchHdaCodecSxWakeCapability; -/** Offset 0x0219 - Enable SATA +/** Offset 0x021D - Enable SATA Enable/disable SATA controller. $EN_DIS **/ UINT8 SataEnable; -/** Offset 0x021A - SATA Mode +/** Offset 0x021E - SATA Mode Select SATA controller working mode. 0:AHCI, 1:RAID **/ UINT8 SataMode; -/** Offset 0x021B - USB Per Port HS Preemphasis Bias +/** Offset 0x021F - USB Per Port HS Preemphasis Bias USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. **/ UINT8 Usb2AfePetxiset[16]; -/** Offset 0x022B - USB Per Port HS Transmitter Bias +/** Offset 0x022F - USB Per Port HS Transmitter Bias USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. **/ UINT8 Usb2AfeTxiset[16]; -/** Offset 0x023B - USB Per Port HS Transmitter Emphasis +/** Offset 0x023F - USB Per Port HS Transmitter Emphasis USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. **/ UINT8 Usb2AfePredeemp[16]; -/** Offset 0x024B - USB Per Port Half Bit Pre-emphasis +/** Offset 0x024F - USB Per Port Half Bit Pre-emphasis USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port. **/ UINT8 Usb2AfePehalfbit[16]; -/** Offset 0x025B - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment +/** Offset 0x025F - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value in arrary can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxDeEmphEnable[10]; -/** Offset 0x0265 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting +/** Offset 0x0269 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. **/ UINT8 Usb3HsioTxDeEmph[10]; -/** Offset 0x026F - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment +/** Offset 0x0273 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxDownscaleAmpEnable[10]; -/** Offset 0x0279 - USB 3.0 TX Output Downscale Amplitude Adjustment +/** Offset 0x027D - USB 3.0 TX Output Downscale Amplitude Adjustment USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. One byte for each port. **/ UINT8 Usb3HsioTxDownscaleAmp[10]; -/** Offset 0x0283 - Enable xHCI LTR override +/** Offset 0x0287 - Enable xHCI LTR override Enables override of recommended LTR values for xHCI $EN_DIS **/ UINT8 PchUsbLtrOverrideEnable; -/** Offset 0x0284 - xHCI High Idle Time LTR override +/** Offset 0x0288 - xHCI High Idle Time LTR override Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting **/ UINT32 PchUsbLtrHighIdleTimeOverride; -/** Offset 0x0288 - xHCI Medium Idle Time LTR override +/** Offset 0x028C - xHCI Medium Idle Time LTR override Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting **/ UINT32 PchUsbLtrMediumIdleTimeOverride; -/** Offset 0x028C - xHCI Low Idle Time LTR override +/** Offset 0x0290 - xHCI Low Idle Time LTR override Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting **/ UINT32 PchUsbLtrLowIdleTimeOverride; -/** Offset 0x0290 - Enable LAN +/** Offset 0x0294 - Enable LAN Enable/disable LAN controller. $EN_DIS **/ UINT8 PchLanEnable; -/** Offset 0x0291 - Enable HD Audio Link +/** Offset 0x0295 - Enable HD Audio Link Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. $EN_DIS **/ UINT8 PchHdaAudioLinkHda; -/** Offset 0x0292 - Enable HD Audio DMIC0 Link +/** Offset 0x0296 - Enable HD Audio DMIC0 Link Enable/disable HD Audio DMIC0 link. Muxed with SNDW4. $EN_DIS **/ UINT8 PchHdaAudioLinkDmic0; -/** Offset 0x0293 - Enable HD Audio DMIC1 Link +/** Offset 0x0297 - Enable HD Audio DMIC1 Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. $EN_DIS **/ UINT8 PchHdaAudioLinkDmic1; -/** Offset 0x0294 - Enable HD Audio SSP0 Link +/** Offset 0x0298 - Enable HD Audio SSP0 Link Enable/disable HD Audio SSP0/I2S link. Muxed with HDA. $EN_DIS **/ UINT8 PchHdaAudioLinkSsp0; -/** Offset 0x0295 - Enable HD Audio SSP1 Link +/** Offset 0x0299 - Enable HD Audio SSP1 Link Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2. $EN_DIS **/ UINT8 PchHdaAudioLinkSsp1; -/** Offset 0x0296 - Enable HD Audio SSP2 Link +/** Offset 0x029A - Enable HD Audio SSP2 Link Enable/disable HD Audio SSP2/I2S link. $EN_DIS **/ UINT8 PchHdaAudioLinkSsp2; -/** Offset 0x0297 - Enable HD Audio SoundWire#1 Link +/** Offset 0x029B - Enable HD Audio SoundWire#1 Link Enable/disable HD Audio SNDW1 link. Muxed with HDA. $EN_DIS **/ UINT8 PchHdaAudioLinkSndw1; -/** Offset 0x0298 - Enable HD Audio SoundWire#2 Link +/** Offset 0x029C - Enable HD Audio SoundWire#2 Link Enable/disable HD Audio SNDW2 link. Muxed with SSP1. $EN_DIS **/ UINT8 PchHdaAudioLinkSndw2; -/** Offset 0x0299 - Enable HD Audio SoundWire#3 Link +/** Offset 0x029D - Enable HD Audio SoundWire#3 Link Enable/disable HD Audio SNDW3 link. Muxed with DMIC1. $EN_DIS **/ UINT8 PchHdaAudioLinkSndw3; -/** Offset 0x029A - Enable HD Audio SoundWire#4 Link +/** Offset 0x029E - Enable HD Audio SoundWire#4 Link Enable/disable HD Audio SNDW4 link. Muxed with DMIC0. $EN_DIS **/ UINT8 PchHdaAudioLinkSndw4; -/** Offset 0x029B - Soundwire Clock Buffer GPIO RCOMP Setting +/** Offset 0x029F - Soundwire Clock Buffer GPIO RCOMP Setting 0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance. $EN_DIS **/ UINT8 PchHdaSndwBufferRcomp; -/** Offset 0x029C - PTM for PCIE RP Mask +/** Offset 0x02A0 - PTM for PCIE RP Mask Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT32 PcieRpPtmMask; -/** Offset 0x02A0 - DPC for PCIE RP Mask +/** Offset 0x02A4 - DPC for PCIE RP Mask Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT32 PcieRpDpcMask; -/** Offset 0x02A4 - DPC Extensions PCIE RP Mask +/** Offset 0x02A8 - DPC Extensions PCIE RP Mask Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT32 PcieRpDpcExtensionsMask; -/** Offset 0x02A8 - USB PDO Programming +/** Offset 0x02AC - USB PDO Programming Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming during later phase. 1: enable, 0: disable $EN_DIS **/ UINT8 UsbPdoProgramming; -/** Offset 0x02A9 +/** Offset 0x02AD **/ - UINT8 UnusedUpdSpace11[3]; + UINT8 UnusedUpdSpace12[3]; -/** Offset 0x02AC - Power button debounce configuration +/** Offset 0x02B0 - Power button debounce configuration Debounce time for PWRBTN in microseconds. For values not supported by HW, they will be rounded down to closest supported on. 0: disable, 250-1024000us: supported range **/ UINT32 PmcPowerButtonDebounce; -/** Offset 0x02B0 - PCH eSPI Master and Slave BME enabled +/** Offset 0x02B4 - PCH eSPI Master and Slave BME enabled PCH eSPI Master and Slave BME enabled $EN_DIS **/ UINT8 PchEspiBmeMasterSlaveEnabled; -/** Offset 0x02B1 - PCH SATA use RST Legacy OROM +/** Offset 0x02B5 - PCH SATA use RST Legacy OROM Use PCH SATA RST Legacy OROM when CSM is Enabled $EN_DIS **/ UINT8 SataRstLegacyOrom; -/** Offset 0x02B2 +/** Offset 0x02B6 **/ - UINT8 UnusedUpdSpace12[2]; + UINT8 UnusedUpdSpace13[2]; -/** Offset 0x02B4 - Trace Hub Memory Base +/** Offset 0x02B8 - Trace Hub Memory Base If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub memory is configured properly. **/ UINT32 TraceHubMemBase; -/** Offset 0x02B8 - PMC Debug Message Enable +/** Offset 0x02BC - PMC Debug Message Enable When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix $EN_DIS **/ UINT8 PmcDbgMsgEn; -/** Offset 0x02B9 +/** Offset 0x02BD **/ - UINT8 UnusedUpdSpace13[3]; + UINT8 UnusedUpdSpace14[3]; -/** Offset 0x02BC - Pointer of ChipsetInit Binary +/** Offset 0x02C0 - Pointer of ChipsetInit Binary ChipsetInit Binary Pointer. **/ UINT32 ChipsetInitBinPtr; -/** Offset 0x02C0 - Length of ChipsetInit Binary +/** Offset 0x02C4 - Length of ChipsetInit Binary ChipsetInit Binary Length. **/ UINT32 ChipsetInitBinLen; -/** Offset 0x02C4 - Enable Ufs Controller +/** Offset 0x02C8 - Enable Ufs Controller Enable/disable Ufs 2.0 Controller. $EN_DIS **/ UINT8 ScsUfsEnabled; -/** Offset 0x02C5 - CNVi Configuration +/** Offset 0x02C9 - CNVi Configuration This option allows for automatic detection of Connectivity Solution. [Auto Detection] assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. 0:Disable, 1:Auto **/ UINT8 CnviMode; -/** Offset 0x02C6 - CNVi BT Core +/** Offset 0x02CA - CNVi BT Core Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviBtCore; -/** Offset 0x02C7 - CNVi BT Audio Offload +/** Offset 0x02CB - CNVi BT Audio Offload Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviBtAudioOffload; -/** Offset 0x02C8 - SdCard power enable polarity +/** Offset 0x02CC - SdCard power enable polarity Choose SD_PWREN# polarity 0: Active low, 1: Active high **/ UINT8 SdCardPowerEnableActiveHigh; -/** Offset 0x02C9 - PCH USB2 PHY Power Gating enable +/** Offset 0x02CD - PCH USB2 PHY Power Gating enable 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY Sus Well PG $EN_DIS **/ UINT8 PchUsb2PhySusPgEnable; -/** Offset 0x02CA - PCH USB OverCurrent mapping enable +/** Offset 0x02CE - PCH USB OverCurrent mapping enable 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin mapping allow for NOA usage of OC pins $EN_DIS **/ UINT8 PchUsbOverCurrentEnable; -/** Offset 0x02CB - Espi Lgmr Memory Range decode +/** Offset 0x02CF - Espi Lgmr Memory Range decode This option enables or disables espi lgmr $EN_DIS **/ UINT8 PchEspiLgmrEnable; -/** Offset 0x02CC - PCHHOT# pin +/** Offset 0x02D0 - PCHHOT# pin Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable $EN_DIS **/ UINT8 PchHotEnable; -/** Offset 0x02CD - SATA LED +/** Offset 0x02D1 - SATA LED SATA LED indicating SATA controller activity. 0: disable, 1: enable $EN_DIS **/ UINT8 SataLedEnable; -/** Offset 0x02CE - VRAlert# Pin +/** Offset 0x02D2 - VRAlert# Pin When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable $EN_DIS **/ UINT8 PchPmVrAlert; -/** Offset 0x02CF - SLP_S0 VM Dynamic Control +/** Offset 0x02D3 - SLP_S0 VM Dynamic Control SLP_S0 Voltage Margining Runtime Control Policy. 0: disable, 1: enable $EN_DIS **/ UINT8 PchPmSlpS0VmRuntimeControl; -/** Offset 0x02D0 - SLP_S0 VM 0.70V Support +/** Offset 0x02D4 - SLP_S0 VM 0.70V Support SLP_S0 Voltage Margining 0.70V Support Policy. 0: disable, 1: enable $EN_DIS **/ UINT8 PchPmSlpS0Vm070VSupport; -/** Offset 0x02D1 - SLP_S0 VM 0.75V Support +/** Offset 0x02D5 - SLP_S0 VM 0.75V Support SLP_S0 Voltage Margining 0.75V Support Policy. 0: disable, 1: enable $EN_DIS **/ UINT8 PchPmSlpS0Vm075VSupport; -/** Offset 0x02D2 - PCH PCIe root port connection type +/** Offset 0x02D6 - PCH PCIe root port connection type 0: built-in device, 1:slot **/ UINT8 PcieRpSlotImplemented[24]; -/** Offset 0x02EA - Usage type for ClkSrc +/** Offset 0x02EE - Usage type for ClkSrc 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used **/ UINT8 PcieClkSrcUsage[16]; -/** Offset 0x02FA - ClkReq-to-ClkSrc mapping +/** Offset 0x02FE - ClkReq-to-ClkSrc mapping Number of ClkReq signal assigned to ClkSrc **/ UINT8 PcieClkSrcClkReq[16]; -/** Offset 0x030A - PCIE RP Access Control Services Extended Capability +/** Offset 0x030E - PCIE RP Access Control Services Extended Capability Enable/Disable PCIE RP Access Control Services Extended Capability **/ UINT8 PcieRpAcsEnabled[24]; -/** Offset 0x0322 - PCIE RP Clock Power Management +/** Offset 0x0326 - PCIE RP Clock Power Management Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism **/ UINT8 PcieRpEnableCpm[24]; -/** Offset 0x033A - PCIE RP Detect Timeout Ms +/** Offset 0x033E - PCIE RP Detect Timeout Ms The number of milliseconds within 0~65535 in reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port. **/ UINT16 PcieRpDetectTimeoutMs[24]; -/** Offset 0x036A - ModPHY SUS Power Domain Dynamic Gating +/** Offset 0x036E - ModPHY SUS Power Domain Dynamic Gating Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on PCH-H. 0: disable, 1: enable $EN_DIS **/ UINT8 PmcModPhySusPgEnable; -/** Offset 0x036B - SlpS0WithGbeSupport - Enable/Disable SLP_S0 with GBE Support. Default is 0 when paired with WHL V0 stepping - CPU and 1 for all other CPUs. 0: Disable, 1: Enable +/** Offset 0x036F - SlpS0WithGbeSupport + Enable/Disable SLP_S0 with GBE Support. Default is 0 for PCH-LP, WHL V0 Stepping + CPU and 1 for PCH-H Series. 0: Disable, 1: Enable $EN_DIS **/ UINT8 SlpS0WithGbeSupport; -/** Offset 0x036C - Enable Power Optimizer +/** Offset 0x0370 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. $EN_DIS **/ UINT8 PchPwrOptEnable; -/** Offset 0x036D - PCH Flash Protection Ranges Write Enble +/** Offset 0x0371 - PCH Flash Protection Ranges Write Enble Write or erase is blocked by hardware. **/ UINT8 PchWriteProtectionEnable[5]; -/** Offset 0x0372 - PCH Flash Protection Ranges Read Enble +/** Offset 0x0376 - PCH Flash Protection Ranges Read Enble Read is blocked by hardware. **/ UINT8 PchReadProtectionEnable[5]; -/** Offset 0x0377 +/** Offset 0x037B **/ - UINT8 UnusedUpdSpace14[1]; + UINT8 UnusedUpdSpace15[1]; -/** Offset 0x0378 - PCH Protect Range Limit +/** Offset 0x037C - PCH Protect Range Limit Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison. **/ UINT16 PchProtectedRangeLimit[5]; -/** Offset 0x0382 - PCH Protect Range Base +/** Offset 0x0386 - PCH Protect Range Base Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. **/ UINT16 PchProtectedRangeBase[5]; -/** Offset 0x038C - Enable Pme +/** Offset 0x0390 - Enable Pme Enable Azalia wake-on-ring. $EN_DIS **/ UINT8 PchHdaPme; -/** Offset 0x038D - VC Type +/** Offset 0x0391 - VC Type Virtual Channel Type Select: 0: VC0, 1: VC1. 0: VC0, 1: VC1 **/ UINT8 PchHdaVcType; -/** Offset 0x038E - HD Audio Link Frequency +/** Offset 0x0392 - HD Audio Link Frequency HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. 0: 6MHz, 1: 12MHz, 2: 24MHz **/ UINT8 PchHdaLinkFrequency; -/** Offset 0x038F - iDisp-Link Frequency +/** Offset 0x0393 - iDisp-Link Frequency iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. 4: 96MHz, 3: 48MHz **/ UINT8 PchHdaIDispLinkFrequency; -/** Offset 0x0390 - iDisp-Link T-mode +/** Offset 0x0394 - iDisp-Link T-mode iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T. 0: 2T, 1: 1T **/ UINT8 PchHdaIDispLinkTmode; -/** Offset 0x0391 - Universal Audio Architecture compliance for DSP enabled system +/** Offset 0x0395 - Universal Audio Architecture compliance for DSP enabled system 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported). $EN_DIS **/ UINT8 PchHdaDspUaaCompliance; -/** Offset 0x0392 - iDisplay Audio Codec disconnection +/** Offset 0x0396 - iDisplay Audio Codec disconnection 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. $EN_DIS **/ UINT8 PchHdaIDispCodecDisconnect; -/** Offset 0x0393 - USB LFPS Filter selection +/** Offset 0x0397 - USB LFPS Filter selection For each byte bits 2:0 are for p, bits 4:6 are for n. 0h:1.6ns, 1h:2.4ns, 2h:3.2ns, 3h:4.0ns, 4h:4.8ns, 5h:5.6ns, 6h:6.4ns. **/ UINT8 PchUsbHsioFilterSel[10]; -/** Offset 0x039D - Enable PCH Io Apic Entry 24-119 +/** Offset 0x03A1 - Enable PCH Io Apic Entry 24-119 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIoApicEntry24_119; -/** Offset 0x039E - PCH Io Apic ID +/** Offset 0x03A2 - PCH Io Apic ID This member determines IOAPIC ID. Default is 0x02. **/ UINT8 PchIoApicId; -/** Offset 0x039F - Enable PCH ISH SPI GPIO pins assigned +/** Offset 0x03A3 - Enable PCH ISH SPI GPIO pins assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshSpiGpioAssign; -/** Offset 0x03A0 - Enable PCH ISH UART0 GPIO pins assigned +/** Offset 0x03A4 - Enable PCH ISH UART0 GPIO pins assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshUart0GpioAssign; -/** Offset 0x03A1 - Enable PCH ISH UART1 GPIO pins assigned +/** Offset 0x03A5 - Enable PCH ISH UART1 GPIO pins assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshUart1GpioAssign; -/** Offset 0x03A2 - Enable PCH ISH I2C0 GPIO pins assigned +/** Offset 0x03A6 - Enable PCH ISH I2C0 GPIO pins assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshI2c0GpioAssign; -/** Offset 0x03A3 - Enable PCH ISH I2C1 GPIO pins assigned +/** Offset 0x03A7 - Enable PCH ISH I2C1 GPIO pins assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshI2c1GpioAssign; -/** Offset 0x03A4 - Enable PCH ISH I2C2 GPIO pins assigned +/** Offset 0x03A8 - Enable PCH ISH I2C2 GPIO pins assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshI2c2GpioAssign; -/** Offset 0x03A5 - Enable PCH ISH GP_0 GPIO pin assigned +/** Offset 0x03A9 - Enable PCH ISH GP_0 GPIO pin assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshGp0GpioAssign; -/** Offset 0x03A6 - Enable PCH ISH GP_1 GPIO pin assigned +/** Offset 0x03AA - Enable PCH ISH GP_1 GPIO pin assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshGp1GpioAssign; -/** Offset 0x03A7 - Enable PCH ISH GP_2 GPIO pin assigned +/** Offset 0x03AB - Enable PCH ISH GP_2 GPIO pin assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshGp2GpioAssign; -/** Offset 0x03A8 - Enable PCH ISH GP_3 GPIO pin assigned +/** Offset 0x03AC - Enable PCH ISH GP_3 GPIO pin assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshGp3GpioAssign; -/** Offset 0x03A9 - Enable PCH ISH GP_4 GPIO pin assigned +/** Offset 0x03AD - Enable PCH ISH GP_4 GPIO pin assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshGp4GpioAssign; -/** Offset 0x03AA - Enable PCH ISH GP_5 GPIO pin assigned +/** Offset 0x03AE - Enable PCH ISH GP_5 GPIO pin assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshGp5GpioAssign; -/** Offset 0x03AB - Enable PCH ISH GP_6 GPIO pin assigned +/** Offset 0x03AF - Enable PCH ISH GP_6 GPIO pin assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshGp6GpioAssign; -/** Offset 0x03AC - Enable PCH ISH GP_7 GPIO pin assigned +/** Offset 0x03B0 - Enable PCH ISH GP_7 GPIO pin assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshGp7GpioAssign; -/** Offset 0x03AD - PCH ISH PDT Unlock Msg +/** Offset 0x03B1 - PCH ISH PDT Unlock Msg 0: False; 1: True. $EN_DIS **/ UINT8 PchIshPdtUnlock; -/** Offset 0x03AE - Enable PCH Lan LTR capabilty of PCH internal LAN +/** Offset 0x03B2 - Enable PCH Lan LTR capabilty of PCH internal LAN 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchLanLtrEnable; -/** Offset 0x03AF - Enable LOCKDOWN BIOS LOCK +/** Offset 0x03B3 - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection. $EN_DIS **/ UINT8 PchLockDownBiosLock; -/** Offset 0x03B0 - PCH Compatibility Revision ID +/** Offset 0x03B4 - PCH Compatibility Revision ID This member describes whether or not the CRID feature of PCH should be enabled. $EN_DIS **/ UINT8 PchCrid; -/** Offset 0x03B1 - RTC CMOS MEMORY LOCK +/** Offset 0x03B5 - RTC CMOS MEMORY LOCK Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM. $EN_DIS **/ UINT8 PchLockDownRtcMemoryLock; -/** Offset 0x03B2 - Enable PCIE RP HotPlug +/** Offset 0x03B6 - Enable PCIE RP HotPlug Indicate whether the root port is hot plug available. **/ UINT8 PcieRpHotPlug[24]; -/** Offset 0x03CA - Enable PCIE RP Pm Sci +/** Offset 0x03CE - Enable PCIE RP Pm Sci Indicate whether the root port power manager SCI is enabled. **/ UINT8 PcieRpPmSci[24]; -/** Offset 0x03E2 - Enable PCIE RP Ext Sync +/** Offset 0x03E6 - Enable PCIE RP Ext Sync Indicate whether the extended synch is enabled. **/ UINT8 PcieRpExtSync[24]; -/** Offset 0x03FA - Enable PCIE RP Transmitter Half Swing +/** Offset 0x03FE - Enable PCIE RP Transmitter Half Swing Indicate whether the Transmitter Half Swing is enabled. **/ UINT8 PcieRpTransmitterHalfSwing[24]; -/** Offset 0x0412 - Enable PCIE RP Clk Req Detect +/** Offset 0x0416 - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management. **/ UINT8 PcieRpClkReqDetect[24]; -/** Offset 0x042A - PCIE RP Advanced Error Report +/** Offset 0x042E - PCIE RP Advanced Error Report Indicate whether the Advanced Error Reporting is enabled. **/ UINT8 PcieRpAdvancedErrorReporting[24]; -/** Offset 0x0442 - PCIE RP Unsupported Request Report +/** Offset 0x0446 - PCIE RP Unsupported Request Report Indicate whether the Unsupported Request Report is enabled. **/ UINT8 PcieRpUnsupportedRequestReport[24]; -/** Offset 0x045A - PCIE RP Fatal Error Report +/** Offset 0x045E - PCIE RP Fatal Error Report Indicate whether the Fatal Error Report is enabled. **/ UINT8 PcieRpFatalErrorReport[24]; -/** Offset 0x0472 - PCIE RP No Fatal Error Report +/** Offset 0x0476 - PCIE RP No Fatal Error Report Indicate whether the No Fatal Error Report is enabled. **/ UINT8 PcieRpNoFatalErrorReport[24]; -/** Offset 0x048A - PCIE RP Correctable Error Report +/** Offset 0x048E - PCIE RP Correctable Error Report Indicate whether the Correctable Error Report is enabled. **/ UINT8 PcieRpCorrectableErrorReport[24]; -/** Offset 0x04A2 - PCIE RP System Error On Fatal Error +/** Offset 0x04A6 - PCIE RP System Error On Fatal Error Indicate whether the System Error on Fatal Error is enabled. **/ UINT8 PcieRpSystemErrorOnFatalError[24]; -/** Offset 0x04BA - PCIE RP System Error On Non Fatal Error +/** Offset 0x04BE - PCIE RP System Error On Non Fatal Error Indicate whether the System Error on Non Fatal Error is enabled. **/ UINT8 PcieRpSystemErrorOnNonFatalError[24]; -/** Offset 0x04D2 - PCIE RP System Error On Correctable Error +/** Offset 0x04D6 - PCIE RP System Error On Correctable Error Indicate whether the System Error on Correctable Error is enabled. **/ UINT8 PcieRpSystemErrorOnCorrectableError[24]; -/** Offset 0x04EA - PCIE RP Max Payload +/** Offset 0x04EE - PCIE RP Max Payload Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. **/ UINT8 PcieRpMaxPayload[24]; -/** Offset 0x0502 - PCH USB3 RX HSIO Tuning parameters +/** Offset 0x0506 - PCH USB3 RX HSIO Tuning parameters Bits 7:3 are for Signed Magnatude number added to the CTLE code, Bits 2:0 are for controlling the input offset **/ UINT8 PchUsbHsioRxTuningParameters[10]; -/** Offset 0x050C - PCH USB3 HSIO Rx Tuning Enable +/** Offset 0x0510 - PCH USB3 HSIO Rx Tuning Enable Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable, 1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable **/ UINT8 PchUsbHsioRxTuningEnable[10]; -/** Offset 0x0516 - PCIE RP Pcie Speed +/** Offset 0x051A - PCIE RP Pcie Speed Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED). **/ UINT8 PcieRpPcieSpeed[24]; -/** Offset 0x052E - PCIE RP Gen3 Equalization Phase Method +/** Offset 0x0532 - PCIE RP Gen3 Equalization Phase Method PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; 1: hardware equalization; 4: Fixed Coeficients. **/ UINT8 PcieRpGen3EqPh3Method[24]; -/** Offset 0x0546 - PCIE RP Physical Slot Number +/** Offset 0x054A - PCIE RP Physical Slot Number Indicates the slot number for the root port. Default is the value as root port index. **/ UINT8 PcieRpPhysicalSlotNumber[24]; -/** Offset 0x055E - PCIE RP Completion Timeout +/** Offset 0x0562 - PCIE RP Completion Timeout The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. **/ UINT8 PcieRpCompletionTimeout[24]; -/** Offset 0x0576 - PCIE RP Aspm +/** Offset 0x057A - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAspmAutoConfig. **/ UINT8 PcieRpAspm[24]; -/** Offset 0x058E - PCIE RP L1 Substates +/** Offset 0x0592 - PCIE RP L1 Substates The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is PchPcieL1SubstatesL1_1_2. **/ UINT8 PcieRpL1Substates[24]; -/** Offset 0x05A6 - PCIE RP Ltr Enable +/** Offset 0x05AA - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism. **/ UINT8 PcieRpLtrEnable[24]; -/** Offset 0x05BE - PCIE RP Ltr Config Lock +/** Offset 0x05C2 - PCIE RP Ltr Config Lock 0: Disable; 1: Enable. **/ UINT8 PcieRpLtrConfigLock[24]; -/** Offset 0x05D6 - PCIE Eq Ph3 Lane Param Cm +/** Offset 0x05DA - PCIE Eq Ph3 Lane Param Cm PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1. **/ UINT8 PcieEqPh3LaneParamCm[24]; -/** Offset 0x05EE - PCIE Eq Ph3 Lane Param Cp +/** Offset 0x05F2 - PCIE Eq Ph3 Lane Param Cp PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1. **/ UINT8 PcieEqPh3LaneParamCp[24]; -/** Offset 0x0606 - PCIE Sw Eq CoeffList Cm - PCH_PCIE_EQ_PARAM. Coefficient C-1. +/** Offset 0x060A - PCIE Sw Eq CoeffList Cm + PCH_PCIE_EQ_PARAM. Coefficient C-1. The values depend on PcieNumOfCoefficients, + the default value of PcieNumOfCoefficients is 3 hence only first 3 values are considered. **/ UINT8 PcieSwEqCoeffListCm[5]; -/** Offset 0x060B - PCIE Sw Eq CoeffList Cp - PCH_PCIE_EQ_PARAM. Coefficient C+1. +/** Offset 0x060F - PCIE Sw Eq CoeffList Cp + PCH_PCIE_EQ_PARAM. Coefficient C+1.The values depend on PcieNumOfCoefficients, the + default value of PcieNumOfCoefficients is 3 hence only first 3 values are considered. **/ UINT8 PcieSwEqCoeffListCp[5]; -/** Offset 0x0610 - PCIE Disable RootPort Clock Gating +/** Offset 0x0614 - PCIE Disable RootPort Clock Gating Describes whether the PCI Express Clock Gating for each root port is enabled by platform modules. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PcieDisableRootPortClockGating; -/** Offset 0x0611 - PCIE Enable Peer Memory Write +/** Offset 0x0615 - PCIE Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform. $EN_DIS **/ UINT8 PcieEnablePeerMemoryWrite; -/** Offset 0x0612 - PCIE Compliance Test Mode +/** Offset 0x0616 - PCIE Compliance Test Mode Compliance Test Mode shall be enabled when using Compliance Load Board. $EN_DIS **/ UINT8 PcieComplianceTestMode; -/** Offset 0x0613 - PCIE Rp Function Swap +/** Offset 0x0617 - PCIE Rp Function Swap Allows BIOS to use root port function number swapping when root port of function 0 is disabled. $EN_DIS **/ UINT8 PcieRpFunctionSwap; -/** Offset 0x0614 - Teton Glacier Cycle Router +/** Offset 0x0618 - Teton Glacier Cycle Router Specify to which cycle router Teton Glacier is connected, it is valid only when Teton Glacier support is enabled. Default is 0 for CNP-H system and 1 for CNP-LP system **/ UINT8 TetonGlacierCR; -/** Offset 0x0615 - PCH Pm PME_B0_S5_DIS +/** Offset 0x0619 - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. $EN_DIS **/ UINT8 PchPmPmeB0S5Dis; -/** Offset 0x0616 - PCIE IMR +/** Offset 0x061A - PCIE IMR Enables Isolated Memory Region for PCIe. $EN_DIS **/ UINT8 PcieRpImrEnabled; -/** Offset 0x0617 - PCIE IMR port number +/** Offset 0x061B - PCIE IMR port number Selects PCIE root port number for IMR feature. **/ UINT8 PcieRpImrSelection; -/** Offset 0x0618 - Teton Glacier Detection and Configuration Mode +/** Offset 0x061C - Teton Glacier Detection and Configuration Mode Enables support for Teton Glacier hybrid storage device. 0: Disabled; 1: Dynamic Configuration. Default is 0: Disabled 0: Disabled, 1: Dynamic Configuration **/ UINT8 TetonGlacierMode; -/** Offset 0x0619 - PCH Pm Wol Enable Override +/** Offset 0x061D - PCH Pm Wol Enable Override Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. $EN_DIS **/ UINT8 PchPmWolEnableOverride; -/** Offset 0x061A - PCH Pm Pcie Wake From DeepSx +/** Offset 0x061E - PCH Pm Pcie Wake From DeepSx Determine if enable PCIe to wake from deep Sx. $EN_DIS **/ UINT8 PchPmPcieWakeFromDeepSx; -/** Offset 0x061B - PCH Pm WoW lan Enable +/** Offset 0x061F - PCH Pm WoW lan Enable Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. $EN_DIS **/ UINT8 PchPmWoWlanEnable; -/** Offset 0x061C - PCH Pm WoW lan DeepSx Enable +/** Offset 0x0620 - PCH Pm WoW lan DeepSx Enable Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register. $EN_DIS **/ UINT8 PchPmWoWlanDeepSxEnable; -/** Offset 0x061D - PCH Pm Lan Wake From DeepSx +/** Offset 0x0621 - PCH Pm Lan Wake From DeepSx Determine if enable LAN to wake from deep Sx. $EN_DIS **/ UINT8 PchPmLanWakeFromDeepSx; -/** Offset 0x061E - PCH Pm Deep Sx Pol +/** Offset 0x0622 - PCH Pm Deep Sx Pol Deep Sx Policy. $EN_DIS **/ UINT8 PchPmDeepSxPol; -/** Offset 0x061F - PCH Pm Slp S3 Min Assert +/** Offset 0x0623 - PCH Pm Slp S3 Min Assert SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. **/ UINT8 PchPmSlpS3MinAssert; -/** Offset 0x0620 - PCH Pm Slp S4 Min Assert +/** Offset 0x0624 - PCH Pm Slp S4 Min Assert SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. **/ UINT8 PchPmSlpS4MinAssert; -/** Offset 0x0621 - PCH Pm Slp Sus Min Assert +/** Offset 0x0625 - PCH Pm Slp Sus Min Assert SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. **/ UINT8 PchPmSlpSusMinAssert; -/** Offset 0x0622 - PCH Pm Slp A Min Assert +/** Offset 0x0626 - PCH Pm Slp A Min Assert SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. **/ UINT8 PchPmSlpAMinAssert; -/** Offset 0x0623 - SLP_S0# Override +/** Offset 0x0627 - SLP_S0# Override Select 'Auto', it will be auto-configured according to probe type. Select 'Enabled' will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0# assertion when debug is enabled. \n @@ -1791,7 +1803,7 @@ typedef struct { **/ UINT8 SlpS0Override; -/** Offset 0x0624 - S0ix Override Settings +/** Offset 0x0628 - S0ix Override Settings Select 'Auto', it will be auto-configured according to probe type. 'No Change' will keep PMC default settings. Or select the desired debug probe type for S0ix Override settings.\n @@ -1802,498 +1814,498 @@ typedef struct { **/ UINT8 SlpS0DisQForDebug; -/** Offset 0x0625 - USB Overcurrent Override for DbC +/** Offset 0x0629 - USB Overcurrent Override for DbC This option overrides USB Over Current enablement state that USB OC will be disabled after enabling this option. Enable when DbC is used to avoid signaling conflicts. $EN_DIS **/ UINT8 PchEnableDbcObs; -/** Offset 0x0626 - PCH Legacy IO Low Latency Enable +/** Offset 0x062A - PCH Legacy IO Low Latency Enable Set to enable low latency of legacy IO. 0: Disable, 1: Enable $EN_DIS **/ UINT8 PchLegacyIoLowLatency; -/** Offset 0x0627 - PCH Pm Lpc Clock Run +/** Offset 0x062B - PCH Pm Lpc Clock Run This member describes whether or not the LPC ClockRun feature of PCH should be enabled. Default value is Disabled $EN_DIS **/ UINT8 PchPmLpcClockRun; -/** Offset 0x0628 - PCH Pm Slp Strch Sus Up +/** Offset 0x062C - PCH Pm Slp Strch Sus Up Enable SLP_X Stretching After SUS Well Power Up. $EN_DIS **/ UINT8 PchPmSlpStrchSusUp; -/** Offset 0x0629 - PCH Pm Slp Lan Low Dc +/** Offset 0x062D - PCH Pm Slp Lan Low Dc Enable/Disable SLP_LAN# Low on DC Power. $EN_DIS **/ UINT8 PchPmSlpLanLowDc; -/** Offset 0x062A - PCH Pm Pwr Btn Override Period +/** Offset 0x062E - PCH Pm Pwr Btn Override Period PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. **/ UINT8 PchPmPwrBtnOverridePeriod; -/** Offset 0x062B - PCH Pm Disable Dsx Ac Present Pulldown +/** Offset 0x062F - PCH Pm Disable Dsx Ac Present Pulldown When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. $EN_DIS **/ UINT8 PchPmDisableDsxAcPresentPulldown; -/** Offset 0x062C - PCH Pm Disable Native Power Button +/** Offset 0x0630 - PCH Pm Disable Native Power Button Power button native mode disable. $EN_DIS **/ UINT8 PchPmDisableNativePowerButton; -/** Offset 0x062D - PCH Pm Slp S0 Enable +/** Offset 0x0631 - PCH Pm Slp S0 Enable Indicates whether SLP_S0# is to be asserted when PCH reaches idle state. $EN_DIS **/ UINT8 PchPmSlpS0Enable; -/** Offset 0x062E - PCH Pm ME_WAKE_STS +/** Offset 0x0632 - PCH Pm ME_WAKE_STS Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. $EN_DIS **/ UINT8 PchPmMeWakeSts; -/** Offset 0x062F - PCH Pm WOL_OVR_WK_STS +/** Offset 0x0633 - PCH Pm WOL_OVR_WK_STS Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. $EN_DIS **/ UINT8 PchPmWolOvrWkSts; -/** Offset 0x0630 - PCH Pm Reset Power Cycle Duration +/** Offset 0x0634 - PCH Pm Reset Power Cycle Duration Could be customized in the unit of second. Please refer to EDS for all support settings. 0 is default, 1 is 1 second, 2 is 2 seconds, ... **/ UINT8 PchPmPwrCycDur; -/** Offset 0x0631 - PCH Pm Pcie Pll Ssc +/** Offset 0x0635 - PCH Pm Pcie Pll Ssc Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No BIOS override. **/ UINT8 PchPmPciePllSsc; -/** Offset 0x0632 - PCH Sata Pwr Opt Enable +/** Offset 0x0636 - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. $EN_DIS **/ UINT8 SataPwrOptEnable; -/** Offset 0x0633 - PCH Sata eSATA Speed Limit +/** Offset 0x0637 - PCH Sata eSATA Speed Limit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. $EN_DIS **/ UINT8 EsataSpeedLimit; -/** Offset 0x0634 - PCH Sata Speed Limit +/** Offset 0x0638 - PCH Sata Speed Limit Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault. **/ UINT8 SataSpeedLimit; -/** Offset 0x0635 - Enable SATA Port HotPlug +/** Offset 0x0639 - Enable SATA Port HotPlug Enable SATA Port HotPlug. **/ UINT8 SataPortsHotPlug[8]; -/** Offset 0x063D - Enable SATA Port Interlock Sw +/** Offset 0x0641 - Enable SATA Port Interlock Sw Enable SATA Port Interlock Sw. **/ UINT8 SataPortsInterlockSw[8]; -/** Offset 0x0645 - Enable SATA Port External +/** Offset 0x0649 - Enable SATA Port External Enable SATA Port External. **/ UINT8 SataPortsExternal[8]; -/** Offset 0x064D - Enable SATA Port SpinUp +/** Offset 0x0651 - Enable SATA Port SpinUp Enable the COMRESET initialization Sequence to the device. **/ UINT8 SataPortsSpinUp[8]; -/** Offset 0x0655 - Enable SATA Port Solid State Drive +/** Offset 0x0659 - Enable SATA Port Solid State Drive 0: HDD; 1: SSD. **/ UINT8 SataPortsSolidStateDrive[8]; -/** Offset 0x065D - Enable SATA Port Enable Dito Config +/** Offset 0x0661 - Enable SATA Port Enable Dito Config Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). **/ UINT8 SataPortsEnableDitoConfig[8]; -/** Offset 0x0665 - Enable SATA Port DmVal +/** Offset 0x0669 - Enable SATA Port DmVal DITO multiplier. Default is 15. **/ UINT8 SataPortsDmVal[8]; -/** Offset 0x066D +/** Offset 0x0671 **/ - UINT8 UnusedUpdSpace15[1]; + UINT8 UnusedUpdSpace16[1]; -/** Offset 0x066E - Enable SATA Port DmVal +/** Offset 0x0672 - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. **/ UINT16 SataPortsDitoVal[8]; -/** Offset 0x067E - Enable SATA Port ZpOdd +/** Offset 0x0682 - Enable SATA Port ZpOdd Support zero power ODD. **/ UINT8 SataPortsZpOdd[8]; -/** Offset 0x0686 - PCH Sata Rst Raid Device Id +/** Offset 0x068A - PCH Sata Rst Raid Device Id Enable RAID Alternate ID. 0:Client, 1:Alternate, 2:Server **/ UINT8 SataRstRaidDeviceId; -/** Offset 0x0687 - PCH Sata Rst Raid0 +/** Offset 0x068B - PCH Sata Rst Raid0 RAID0. $EN_DIS **/ UINT8 SataRstRaid0; -/** Offset 0x0688 - PCH Sata Rst Raid1 +/** Offset 0x068C - PCH Sata Rst Raid1 RAID1. $EN_DIS **/ UINT8 SataRstRaid1; -/** Offset 0x0689 - PCH Sata Rst Raid10 +/** Offset 0x068D - PCH Sata Rst Raid10 RAID10. $EN_DIS **/ UINT8 SataRstRaid10; -/** Offset 0x068A - PCH Sata Rst Raid5 +/** Offset 0x068E - PCH Sata Rst Raid5 RAID5. $EN_DIS **/ UINT8 SataRstRaid5; -/** Offset 0x068B - PCH Sata Rst Irrt +/** Offset 0x068F - PCH Sata Rst Irrt Intel Rapid Recovery Technology. $EN_DIS **/ UINT8 SataRstIrrt; -/** Offset 0x068C - PCH Sata Rst Orom Ui Banner +/** Offset 0x0690 - PCH Sata Rst Orom Ui Banner OROM UI and BANNER. $EN_DIS **/ UINT8 SataRstOromUiBanner; -/** Offset 0x068D - PCH Sata Rst Orom Ui Delay +/** Offset 0x0691 - PCH Sata Rst Orom Ui Delay 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY). **/ UINT8 SataRstOromUiDelay; -/** Offset 0x068E - PCH Sata Rst Hdd Unlock +/** Offset 0x0692 - PCH Sata Rst Hdd Unlock Indicates that the HDD password unlock in the OS is enabled. $EN_DIS **/ UINT8 SataRstHddUnlock; -/** Offset 0x068F - PCH Sata Rst Led Locate +/** Offset 0x0693 - PCH Sata Rst Led Locate Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS. $EN_DIS **/ UINT8 SataRstLedLocate; -/** Offset 0x0690 - PCH Sata Rst Irrt Only +/** Offset 0x0694 - PCH Sata Rst Irrt Only Allow only IRRT drives to span internal and external ports. $EN_DIS **/ UINT8 SataRstIrrtOnly; -/** Offset 0x0691 - PCH Sata Rst Smart Storage +/** Offset 0x0695 - PCH Sata Rst Smart Storage RST Smart Storage caching Bit. $EN_DIS **/ UINT8 SataRstSmartStorage; -/** Offset 0x0692 - PCH Sata Rst Pcie Storage Remap enable +/** Offset 0x0696 - PCH Sata Rst Pcie Storage Remap enable Enable Intel RST for PCIe Storage remapping. **/ UINT8 SataRstPcieEnable[3]; -/** Offset 0x0695 - PCH Sata Rst Pcie Storage Port +/** Offset 0x0699 - PCH Sata Rst Pcie Storage Port Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect). **/ UINT8 SataRstPcieStoragePort[3]; -/** Offset 0x0698 - PCH Sata Rst Pcie Device Reset Delay +/** Offset 0x069C - PCH Sata Rst Pcie Device Reset Delay PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms **/ UINT8 SataRstPcieDeviceResetDelay[3]; -/** Offset 0x069B - Enable eMMC HS400 Training +/** Offset 0x069F - Enable eMMC HS400 Training Deprecated. $EN_DIS **/ UINT8 PchScsEmmcHs400TuningRequired; -/** Offset 0x069C - Set HS400 Tuning Data Valid - Set if HS400 Tuning Data Valid. +/** Offset 0x06A0 - Set HS400 Tuning Data Valid + Deprecated $EN_DIS **/ UINT8 PchScsEmmcHs400DllDataValid; -/** Offset 0x069D - Rx Strobe Delay Control - Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode). +/** Offset 0x06A1 - Rx Strobe Delay Control + Deprecated **/ UINT8 PchScsEmmcHs400RxStrobeDll1; -/** Offset 0x069E - Tx Data Delay Control - Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode). +/** Offset 0x06A2 - Tx Data Delay Control + Deprecated **/ UINT8 PchScsEmmcHs400TxDataDll; -/** Offset 0x069F - I/O Driver Strength - Deprecated. +/** Offset 0x06A3 - I/O Driver Strength + Deprecated 0:33 Ohm, 1:40 Ohm, 2:50 Ohm **/ UINT8 PchScsEmmcHs400DriverStrength; -/** Offset 0x06A0 - Enable Serial IRQ +/** Offset 0x06A4 - Enable Serial IRQ Determines if enable Serial IRQ. $EN_DIS **/ UINT8 PchSirqEnable; -/** Offset 0x06A1 - Serial IRQ Mode Select +/** Offset 0x06A5 - Serial IRQ Mode Select Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode. $EN_DIS **/ UINT8 PchSirqMode; -/** Offset 0x06A2 - Start Frame Pulse Width +/** Offset 0x06A6 - Start Frame Pulse Width Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk. 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk **/ UINT8 PchStartFramePulse; -/** Offset 0x06A3 - Reserved +/** Offset 0x06A7 - Reserved Reserved $EN_DIS **/ UINT8 ReservedForFuture1; -/** Offset 0x06A4 - Thermal Device SMI Enable +/** Offset 0x06A8 - Thermal Device SMI Enable This locks down SMI Enable on Alert Thermal Sensor Trip. $EN_DIS **/ UINT8 PchTsmicLock; -/** Offset 0x06A5 +/** Offset 0x06A9 **/ - UINT8 UnusedUpdSpace16; + UINT8 UnusedUpdSpace17; -/** Offset 0x06A6 - Thermal Throttling Custimized T0Level Value +/** Offset 0x06AA - Thermal Throttling Custimized T0Level Value Custimized T0Level value. **/ UINT16 PchT0Level; -/** Offset 0x06A8 - Thermal Throttling Custimized T1Level Value +/** Offset 0x06AC - Thermal Throttling Custimized T1Level Value Custimized T1Level value. **/ UINT16 PchT1Level; -/** Offset 0x06AA - Thermal Throttling Custimized T2Level Value +/** Offset 0x06AE - Thermal Throttling Custimized T2Level Value Custimized T2Level value. **/ UINT16 PchT2Level; -/** Offset 0x06AC - Enable The Thermal Throttle +/** Offset 0x06B0 - Enable The Thermal Throttle Enable the thermal throttle function. $EN_DIS **/ UINT8 PchTTEnable; -/** Offset 0x06AD - PMSync State 13 +/** Offset 0x06B1 - PMSync State 13 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state. $EN_DIS **/ UINT8 PchTTState13Enable; -/** Offset 0x06AE - Thermal Throttle Lock +/** Offset 0x06B2 - Thermal Throttle Lock Thermal Throttle Lock. $EN_DIS **/ UINT8 PchTTLock; -/** Offset 0x06AF - Thermal Throttling Suggested Setting +/** Offset 0x06B3 - Thermal Throttling Suggested Setting Thermal Throttling Suggested Setting. $EN_DIS **/ UINT8 TTSuggestedSetting; -/** Offset 0x06B0 - Enable PCH Cross Throttling +/** Offset 0x06B4 - Enable PCH Cross Throttling Enable/Disable PCH Cross Throttling $EN_DIS **/ UINT8 TTCrossThrottling; -/** Offset 0x06B1 - DMI Thermal Sensor Autonomous Width Enable +/** Offset 0x06B5 - DMI Thermal Sensor Autonomous Width Enable DMI Thermal Sensor Autonomous Width Enable. $EN_DIS **/ UINT8 PchDmiTsawEn; -/** Offset 0x06B2 - DMI Thermal Sensor Suggested Setting +/** Offset 0x06B6 - DMI Thermal Sensor Suggested Setting DMT thermal sensor suggested representative values. $EN_DIS **/ UINT8 DmiSuggestedSetting; -/** Offset 0x06B3 - Thermal Sensor 0 Target Width +/** Offset 0x06B7 - Thermal Sensor 0 Target Width DMT thermal sensor suggested representative values. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS0TW; -/** Offset 0x06B4 - Thermal Sensor 1 Target Width +/** Offset 0x06B8 - Thermal Sensor 1 Target Width Thermal Sensor 1 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS1TW; -/** Offset 0x06B5 - Thermal Sensor 2 Target Width +/** Offset 0x06B9 - Thermal Sensor 2 Target Width Thermal Sensor 2 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS2TW; -/** Offset 0x06B6 - Thermal Sensor 3 Target Width +/** Offset 0x06BA - Thermal Sensor 3 Target Width Thermal Sensor 3 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS3TW; -/** Offset 0x06B7 - Port 0 T1 Multipler +/** Offset 0x06BB - Port 0 T1 Multipler Port 0 T1 Multipler. **/ UINT8 SataP0T1M; -/** Offset 0x06B8 - Port 0 T2 Multipler +/** Offset 0x06BC - Port 0 T2 Multipler Port 0 T2 Multipler. **/ UINT8 SataP0T2M; -/** Offset 0x06B9 - Port 0 T3 Multipler +/** Offset 0x06BD - Port 0 T3 Multipler Port 0 T3 Multipler. **/ UINT8 SataP0T3M; -/** Offset 0x06BA - Port 0 Tdispatch +/** Offset 0x06BE - Port 0 Tdispatch Port 0 Tdispatch. **/ UINT8 SataP0TDisp; -/** Offset 0x06BB - Port 1 T1 Multipler +/** Offset 0x06BF - Port 1 T1 Multipler Port 1 T1 Multipler. **/ UINT8 SataP1T1M; -/** Offset 0x06BC - Port 1 T2 Multipler +/** Offset 0x06C0 - Port 1 T2 Multipler Port 1 T2 Multipler. **/ UINT8 SataP1T2M; -/** Offset 0x06BD - Port 1 T3 Multipler +/** Offset 0x06C1 - Port 1 T3 Multipler Port 1 T3 Multipler. **/ UINT8 SataP1T3M; -/** Offset 0x06BE - Port 1 Tdispatch +/** Offset 0x06C2 - Port 1 Tdispatch Port 1 Tdispatch. **/ UINT8 SataP1TDisp; -/** Offset 0x06BF - Port 0 Tinactive +/** Offset 0x06C3 - Port 0 Tinactive Port 0 Tinactive. **/ UINT8 SataP0Tinact; -/** Offset 0x06C0 - Port 0 Alternate Fast Init Tdispatch +/** Offset 0x06C4 - Port 0 Alternate Fast Init Tdispatch Port 0 Alternate Fast Init Tdispatch. $EN_DIS **/ UINT8 SataP0TDispFinit; -/** Offset 0x06C1 - Port 1 Tinactive +/** Offset 0x06C5 - Port 1 Tinactive Port 1 Tinactive. **/ UINT8 SataP1Tinact; -/** Offset 0x06C2 - Port 1 Alternate Fast Init Tdispatch +/** Offset 0x06C6 - Port 1 Alternate Fast Init Tdispatch Port 1 Alternate Fast Init Tdispatch. $EN_DIS **/ UINT8 SataP1TDispFinit; -/** Offset 0x06C3 - Sata Thermal Throttling Suggested Setting +/** Offset 0x06C7 - Sata Thermal Throttling Suggested Setting Sata Thermal Throttling Suggested Setting. $EN_DIS **/ UINT8 SataThermalSuggestedSetting; -/** Offset 0x06C4 - Enable Memory Thermal Throttling +/** Offset 0x06C8 - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. $EN_DIS **/ UINT8 PchMemoryThrottlingEnable; -/** Offset 0x06C5 - Memory Thermal Throttling +/** Offset 0x06C9 - Memory Thermal Throttling Enable Memory Thermal Throttling. **/ UINT8 PchMemoryPmsyncEnable[2]; -/** Offset 0x06C7 - Enable Memory Thermal Throttling +/** Offset 0x06CB - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. **/ UINT8 PchMemoryC0TransmitEnable[2]; -/** Offset 0x06C9 - Enable Memory Thermal Throttling +/** Offset 0x06CD - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. **/ UINT8 PchMemoryPinSelection[2]; -/** Offset 0x06CB +/** Offset 0x06CF **/ - UINT8 UnusedUpdSpace17; + UINT8 UnusedUpdSpace18; -/** Offset 0x06CC - Thermal Device Temperature +/** Offset 0x06D0 - Thermal Device Temperature Decides the temperature. **/ UINT16 PchTemperatureHotLevel; -/** Offset 0x06CE - Enable xHCI Compliance Mode +/** Offset 0x06D2 - Enable xHCI Compliance Mode Compliance Mode can be enabled for testing through this option but this is disabled by default. $EN_DIS **/ UINT8 PchEnableComplianceMode; -/** Offset 0x06CF - USB2 Port Over Current Pin +/** Offset 0x06D3 - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. **/ UINT8 Usb2OverCurrentPin[16]; -/** Offset 0x06DF - USB3 Port Over Current Pin +/** Offset 0x06E3 - USB3 Port Over Current Pin Describe the specific over current pin number of USB 3.0 Port N. **/ UINT8 Usb3OverCurrentPin[10]; -/** Offset 0x06E9 - Enable 8254 Static Clock Gating +/** Offset 0x06ED - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support boot legacy OS using 8254 timer. Also enable this while S0ix is enabled. @@ -2301,19 +2313,19 @@ typedef struct { **/ UINT8 Enable8254ClockGating; -/** Offset 0x06EA - PCH Sata Rst Optane Memory +/** Offset 0x06EE - PCH Sata Rst Optane Memory Optane Memory $EN_DIS **/ UINT8 SataRstOptaneMemory; -/** Offset 0x06EB - PCH Sata Rst CPU Attached Storage +/** Offset 0x06EF - PCH Sata Rst CPU Attached Storage CPU Attached Storage $EN_DIS **/ UINT8 SataRstCpuAttachedStorage; -/** Offset 0x06EC - Enable 8254 Static Clock Gating On S3 +/** Offset 0x06F0 - Enable 8254 Static Clock Gating On S3 This is only applicable when Enable8254ClockGating is disabled. FSP will do the 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This avoids the SMI requirement for the programming. @@ -2321,11 +2333,11 @@ typedef struct { **/ UINT8 Enable8254ClockGatingOnS3; -/** Offset 0x06ED +/** Offset 0x06F1 **/ - UINT8 UnusedUpdSpace18[3]; + UINT8 UnusedUpdSpace19[3]; -/** Offset 0x06F0 - Pch PCIE device override table pointer +/** Offset 0x06F4 - Pch PCIE device override table pointer The PCIe device table is being used to override PCIe device ASPM settings. This is a pointer points to a 32bit address. And it's only used in PostMem phase. Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId @@ -2333,7 +2345,7 @@ typedef struct { **/ UINT32 PchPcieDeviceOverrideTablePtr; -/** Offset 0x06F4 - Enable TCO timer. +/** Offset 0x06F8 - Enable TCO timer. When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS. @@ -2341,7 +2353,7 @@ typedef struct { **/ UINT8 EnableTcoTimer; -/** Offset 0x06F5 - Enable PS_ON. +/** Offset 0x06F9 - Enable PS_ON. PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled. @@ -2349,155 +2361,196 @@ typedef struct { **/ UINT8 PsOnEnable; -/** Offset 0x06F6 - Pmc Cpu C10 Gate Pin Enable +/** Offset 0x06FA - Pmc Cpu C10 Gate Pin Enable Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails instead of SLP_S0# pin. $EN_DIS **/ UINT8 PmcCpuC10GatePinEnable; -/** Offset 0x06F7 - Pch Dmi Aspm Ctrl +/** Offset 0x06FB - Pch Dmi Aspm Ctrl ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto **/ UINT8 PchDmiAspmCtrl; -/** Offset 0x06F8 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 +/** Offset 0x06FC - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate3UniqTranEnable[10]; -/** Offset 0x0702 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 +/** Offset 0x0706 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate3UniqTran[10]; -/** Offset 0x070C - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 +/** Offset 0x0710 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate2UniqTranEnable[10]; -/** Offset 0x0716 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 +/** Offset 0x071A - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate2UniqTran[10]; -/** Offset 0x0720 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 +/** Offset 0x0724 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate1UniqTranEnable[10]; -/** Offset 0x072A - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 +/** Offset 0x072E - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate1UniqTran[10]; -/** Offset 0x0734 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 +/** Offset 0x0738 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate0UniqTranEnable[10]; -/** Offset 0x073E - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 +/** Offset 0x0742 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate0UniqTran[10]; -/** Offset 0x0748 - ReservedPchPostMem +/** Offset 0x074C - Number of Coefficients to be used + The number of coefficients to be used for equalization, default value is 3 +**/ + UINT8 PcieNumOfCoefficients; + +/** Offset 0x074D - GPIO RCOMP Community Clock Gating + 0 = Disable dynamic RCOMP clock local clock gating, 1 = Enable dynamic RCOMP clock + local clock gating, default value is 1 + $EN_DIS +**/ + UINT8 GpioPmRcompCommunityLocalClockGating; + +/** Offset 0x074E - Enable SD Card Write Protect Pin + Enable/disable SD Card Write Protect Pin. + $EN_DIS +**/ + UINT8 ScsSdCardWpPinEnabled; + +/** Offset 0x074F - Set SATA DEVSLP GPIO Reset Config + Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset, + 0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte + for each port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 SataPortsDevSlpResetConfig[8]; + +/** Offset 0x0757 - Flash Configuration Lock Down + Enable/disable flash lock down. If platform decides to skip this programming, it + must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post. + $EN_DIS +**/ + UINT8 SpiFlashCfgLockDown; + +/** Offset 0x0758 - Enable HD Audio Sndw Link IO Control + 0:Disabled, 1:Enabled. Enables IO Control to Sndw link if it is Enabled +**/ + UINT8 PchHdaSndwLinkIoControlEnabled[4]; + +/** Offset 0x075C - ReservedPchPostMem Reserved for Pch Post-Mem $EN_DIS **/ - UINT8 ReservedPchPostMem[16]; + UINT8 ReservedPchPostMem[3]; -/** Offset 0x0758 - BgpdtHash[4] +/** Offset 0x075F +**/ + UINT8 UnusedUpdSpace20[1]; + +/** Offset 0x0760 - BgpdtHash[4] BgpdtHash values **/ UINT64 BgpdtHash[4]; -/** Offset 0x0778 - BiosGuardAttr +/** Offset 0x0780 - BiosGuardAttr BiosGuardAttr default values **/ UINT32 BiosGuardAttr; -/** Offset 0x077C +/** Offset 0x0784 **/ - UINT8 UnusedUpdSpace19[4]; + UINT8 UnusedUpdSpace21[4]; -/** Offset 0x0780 - BiosGuardModulePtr +/** Offset 0x0788 - BiosGuardModulePtr BiosGuardModulePtr default values **/ UINT64 BiosGuardModulePtr; -/** Offset 0x0788 - SendEcCmd +/** Offset 0x0790 - SendEcCmd SendEcCmd function pointer. \n @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode **/ UINT64 SendEcCmd; -/** Offset 0x0790 - EcCmdProvisionEav +/** Offset 0x0798 - EcCmdProvisionEav Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC **/ UINT8 EcCmdProvisionEav; -/** Offset 0x0791 - EcCmdLock +/** Offset 0x0799 - EcCmdLock EcCmdLock default values. Locks Ephemeral Authorization Value sent previously **/ UINT8 EcCmdLock; -/** Offset 0x0792 +/** Offset 0x079A **/ - UINT8 UnusedUpdSpace20[6]; + UINT8 UnusedUpdSpace22[6]; -/** Offset 0x0798 - SgxEpoch0 +/** Offset 0x07A0 - SgxEpoch0 SgxEpoch0 default values **/ UINT64 SgxEpoch0; -/** Offset 0x07A0 - SgxEpoch1 +/** Offset 0x07A8 - SgxEpoch1 SgxEpoch1 default values **/ UINT64 SgxEpoch1; -/** Offset 0x07A8 - SgxSinitNvsData +/** Offset 0x07B0 - SgxSinitNvsData SgxSinitNvsData default values **/ UINT8 SgxSinitNvsData; -/** Offset 0x07A9 - Si Config CSM Flag. +/** Offset 0x07B1 - Si Config CSM Flag. Platform specific common policies that used by several silicon components. CSM status flag. $EN_DIS **/ UINT8 SiCsmFlag; -/** Offset 0x07AA +/** Offset 0x07B2 **/ - UINT8 UnusedUpdSpace21[2]; + UINT8 UnusedUpdSpace23[2]; -/** Offset 0x07AC - SVID SDID table Poniter. +/** Offset 0x07B4 - SVID SDID table Poniter. The address of the table of SVID SDID to customize each SVID SDID entry. **/ UINT32 SiSsidTablePtr; -/** Offset 0x07B0 - Number of ssid table. +/** Offset 0x07B8 - Number of ssid table. SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. **/ UINT16 SiNumberOfSsidTableEntry; -/** Offset 0x07B2 - SATA RST Interrupt Mode +/** Offset 0x07BA - SATA RST Interrupt Mode Allowes to choose which interrupts will be implemented by SATA controller in RAID mode. 0:Msix, 1:Msi, 2:Legacy **/ UINT8 SataRstInterrupt; -/** Offset 0x07B3 - ME Unconfig on RTC clear +/** Offset 0x07BB - ME Unconfig on RTC clear 0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. 2: Cmos is clear, status unkonwn. 3: Reserved 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos @@ -2505,11 +2558,11 @@ typedef struct { **/ UINT8 MeUnconfigOnRtcClear; -/** Offset 0x07B4 +/** Offset 0x07BC **/ - UINT8 UnusedUpdSpace22[3]; + UINT8 UnusedUpdSpace24[3]; -/** Offset 0x07B7 +/** Offset 0x07BF **/ UINT8 ReservedFspsUpd[1]; } FSP_S_CONFIG; @@ -2518,74 +2571,74 @@ typedef struct { **/ typedef struct { -/** Offset 0x07B8 +/** Offset 0x07C0 **/ UINT32 Signature; -/** Offset 0x07BC - Enable/Disable Device 7 +/** Offset 0x07C4 - Enable/Disable Device 7 Enable: Device 7 enabled, Disable (Default): Device 7 disabled $EN_DIS **/ UINT8 ChapDeviceEnable; -/** Offset 0x07BD - Skip PAM register lock +/** Offset 0x07C5 - Skip PAM register lock Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC $EN_DIS **/ UINT8 SkipPamLock; -/** Offset 0x07BE - EDRAM Test Mode +/** Offset 0x07C6 - EDRAM Test Mode Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode **/ UINT8 EdramTestMode; -/** Offset 0x07BF - DMI Extended Sync Control +/** Offset 0x07C7 - DMI Extended Sync Control Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended Sync Control $EN_DIS **/ UINT8 DmiExtSync; -/** Offset 0x07C0 - DMI IOT Control +/** Offset 0x07C8 - DMI IOT Control Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control $EN_DIS **/ UINT8 DmiIot; -/** Offset 0x07C1 - PEG Max Payload size per root port +/** Offset 0x07C9 - PEG Max Payload size per root port 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B **/ UINT8 PegMaxPayload[4]; -/** Offset 0x07C5 - Enable/Disable IGFX RenderStandby +/** Offset 0x07CD - Enable/Disable IGFX RenderStandby Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby $EN_DIS **/ UINT8 RenderStandby; -/** Offset 0x07C6 - Enable/Disable IGFX PmSupport +/** Offset 0x07CE - Enable/Disable IGFX PmSupport Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport $EN_DIS **/ UINT8 PmSupport; -/** Offset 0x07C7 - Enable/Disable CdynmaxClamp +/** Offset 0x07CF - Enable/Disable CdynmaxClamp Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp $EN_DIS **/ UINT8 CdynmaxClampEnable; -/** Offset 0x07C8 - Disable VT-d +/** Offset 0x07D0 - Disable VT-d 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) $EN_DIS **/ UINT8 VtdDisableDeprecated; -/** Offset 0x07C9 - GT Frequency Limit +/** Offset 0x07D1 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, @@ -2599,19 +2652,19 @@ typedef struct { **/ UINT8 GtFreqMax; -/** Offset 0x07CA - Disable Turbo GT +/** Offset 0x07D2 - Disable Turbo GT 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency $EN_DIS **/ UINT8 DisableTurboGt; -/** Offset 0x07CB - SaPostMemTestRsvd +/** Offset 0x07D3 - SaPostMemTestRsvd Reserved for SA Post-Mem Test $EN_DIS **/ UINT8 SaPostMemTestRsvd[11]; -/** Offset 0x07D6 - 1-Core Ratio Limit +/** Offset 0x07DE - 1-Core Ratio Limit 1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit, @@ -2619,79 +2672,79 @@ typedef struct { **/ UINT8 OneCoreRatioLimit; -/** Offset 0x07D7 - 2-Core Ratio Limit +/** Offset 0x07DF - 2-Core Ratio Limit 2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 **/ UINT8 TwoCoreRatioLimit; -/** Offset 0x07D8 - 3-Core Ratio Limit +/** Offset 0x07E0 - 3-Core Ratio Limit 3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 **/ UINT8 ThreeCoreRatioLimit; -/** Offset 0x07D9 - 4-Core Ratio Limit +/** Offset 0x07E1 - 4-Core Ratio Limit 4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 **/ UINT8 FourCoreRatioLimit; -/** Offset 0x07DA - Enable or Disable HWP +/** Offset 0x07E2 - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; 2-3:Reserved $EN_DIS **/ UINT8 Hwp; -/** Offset 0x07DB - Hardware Duty Cycle Control +/** Offset 0x07E3 - Hardware Duty Cycle Control Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved $EN_DIS **/ UINT8 HdcControl; -/** Offset 0x07DC - Package Long duration turbo mode time +/** Offset 0x07E4 - Package Long duration turbo mode time Package Long duration turbo mode time window in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 **/ UINT8 PowerLimit1Time; -/** Offset 0x07DD - Short Duration Turbo Mode +/** Offset 0x07E5 - Short Duration Turbo Mode Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable $EN_DIS **/ UINT8 PowerLimit2; -/** Offset 0x07DE - Turbo settings Lock +/** Offset 0x07E6 - Turbo settings Lock Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable $EN_DIS **/ UINT8 TurboPowerLimitLock; -/** Offset 0x07DF - Package PL3 time window +/** Offset 0x07E7 - Package PL3 time window Package PL3 time window range for this policy from 0 to 64ms **/ UINT8 PowerLimit3Time; -/** Offset 0x07E0 - Package PL3 Duty Cycle +/** Offset 0x07E8 - Package PL3 Duty Cycle Package PL3 Duty Cycle; Valid Range is 0 to 100 **/ UINT8 PowerLimit3DutyCycle; -/** Offset 0x07E1 - Package PL3 Lock +/** Offset 0x07E9 - Package PL3 Lock Package PL3 Lock Enable/Disable; 0: Disable ; 1: Enable $EN_DIS **/ UINT8 PowerLimit3Lock; -/** Offset 0x07E2 - Package PL4 Lock +/** Offset 0x07EA - Package PL4 Lock Package PL4 Lock Enable/Disable; 0: Disable ; 1: Enable $EN_DIS **/ UINT8 PowerLimit4Lock; -/** Offset 0x07E3 - TCC Activation Offset +/** Offset 0x07EB - TCC Activation Offset TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For Y SKU, the recommended default for this policy is 15, @@ -2699,7 +2752,7 @@ typedef struct { **/ UINT8 TccActivationOffset; -/** Offset 0x07E4 - Tcc Offset Clamp Enable/Disable +/** Offset 0x07EC - Tcc Offset Clamp Enable/Disable Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.For Y SKU, the recommended default for this policy is 1: Enabled, For all other SKUs the recommended default are 0: Disabled. @@ -2707,345 +2760,345 @@ typedef struct { **/ UINT8 TccOffsetClamp; -/** Offset 0x07E5 - Tcc Offset Lock +/** Offset 0x07ED - Tcc Offset Lock Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target; 0: Disabled; 1: Enabled. $EN_DIS **/ UINT8 TccOffsetLock; -/** Offset 0x07E6 - Custom Ratio State Entries +/** Offset 0x07EE - Custom Ratio State Entries The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table.Sets the number of custom P-states. At least 2 states must be present **/ UINT8 NumberOfEntries; -/** Offset 0x07E7 - Custom Short term Power Limit time window +/** Offset 0x07EF - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128, 0 = AUTO **/ UINT8 Custom1PowerLimit1Time; -/** Offset 0x07E8 - Custom Turbo Activation Ratio +/** Offset 0x07F0 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255 **/ UINT8 Custom1TurboActivationRatio; -/** Offset 0x07E9 - Custom Config Tdp Control +/** Offset 0x07F1 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 **/ UINT8 Custom1ConfigTdpControl; -/** Offset 0x07EA - Custom Short term Power Limit time window +/** Offset 0x07F2 - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128, 0 = AUTO **/ UINT8 Custom2PowerLimit1Time; -/** Offset 0x07EB - Custom Turbo Activation Ratio +/** Offset 0x07F3 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255 **/ UINT8 Custom2TurboActivationRatio; -/** Offset 0x07EC - Custom Config Tdp Control +/** Offset 0x07F4 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 **/ UINT8 Custom2ConfigTdpControl; -/** Offset 0x07ED - Custom Short term Power Limit time window +/** Offset 0x07F5 - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128, 0 = AUTO **/ UINT8 Custom3PowerLimit1Time; -/** Offset 0x07EE - Custom Turbo Activation Ratio +/** Offset 0x07F6 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255 **/ UINT8 Custom3TurboActivationRatio; -/** Offset 0x07EF - Custom Config Tdp Control +/** Offset 0x07F7 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 **/ UINT8 Custom3ConfigTdpControl; -/** Offset 0x07F0 - ConfigTdp mode settings Lock +/** Offset 0x07F8 - ConfigTdp mode settings Lock Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ConfigTdpLock; -/** Offset 0x07F1 - Load Configurable TDP SSDT +/** Offset 0x07F9 - Load Configurable TDP SSDT Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ConfigTdpBios; -/** Offset 0x07F2 - PL1 Enable value +/** Offset 0x07FA - PL1 Enable value PL1 Enable value to limit average platform power. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PsysPowerLimit1; -/** Offset 0x07F3 - PL1 timewindow +/** Offset 0x07FB - PL1 timewindow PL1 timewindow in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 **/ UINT8 PsysPowerLimit1Time; -/** Offset 0x07F4 - PL2 Enable Value +/** Offset 0x07FC - PL2 Enable Value PL2 Enable activates the PL2 value to limit average platform power.0: Disable; 1: Enable. $EN_DIS **/ UINT8 PsysPowerLimit2; -/** Offset 0x07F5 - Enable or Disable MLC Streamer Prefetcher +/** Offset 0x07FD - Enable or Disable MLC Streamer Prefetcher Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MlcStreamerPrefetcher; -/** Offset 0x07F6 - Enable or Disable MLC Spatial Prefetcher +/** Offset 0x07FE - Enable or Disable MLC Spatial Prefetcher Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable $EN_DIS **/ UINT8 MlcSpatialPrefetcher; -/** Offset 0x07F7 - Enable or Disable Monitor /MWAIT instructions +/** Offset 0x07FF - Enable or Disable Monitor /MWAIT instructions Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MonitorMwaitEnable; -/** Offset 0x07F8 - Enable or Disable initialization of machine check registers +/** Offset 0x0800 - Enable or Disable initialization of machine check registers Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MachineCheckEnable; -/** Offset 0x07F9 - Deprecated DO NOT USE Enable or Disable processor debug features +/** Offset 0x0801 - Deprecated DO NOT USE Enable or Disable processor debug features @deprecated Enable or Disable processor debug features; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DebugInterfaceEnable; -/** Offset 0x07FA - Lock or Unlock debug interface features +/** Offset 0x0802 - Lock or Unlock debug interface features Lock or Unlock debug interface features; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DebugInterfaceLockEnable; -/** Offset 0x07FB - AP Idle Manner of waiting for SIPI +/** Offset 0x0803 - AP Idle Manner of waiting for SIPI AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop. 1: HALT loop, 2: MWAIT loop, 3: RUN loop **/ UINT8 ApIdleManner; -/** Offset 0x07FC - Control on Processor Trace output scheme +/** Offset 0x0804 - Control on Processor Trace output scheme Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. 0: Single Range Output, 1: ToPA Output **/ UINT8 ProcessorTraceOutputScheme; -/** Offset 0x07FD - Enable or Disable Processor Trace feature +/** Offset 0x0805 - Enable or Disable Processor Trace feature Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ProcessorTraceEnable; -/** Offset 0x07FE +/** Offset 0x0806 **/ - UINT8 UnusedUpdSpace23[2]; + UINT8 UnusedUpdSpace25[2]; -/** Offset 0x0800 - Base of memory region allocated for Processor Trace +/** Offset 0x0808 - Base of memory region allocated for Processor Trace Base address of memory region allocated for Processor Trace. Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable **/ UINT64 ProcessorTraceMemBase; -/** Offset 0x0808 - Memory region allocation for Processor Trace +/** Offset 0x0810 - Memory region allocation for Processor Trace Length in bytes of memory region allocated for Processor Trace. Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable **/ UINT32 ProcessorTraceMemLength; -/** Offset 0x080C - Enable or Disable Voltage Optimization feature +/** Offset 0x0814 - Enable or Disable Voltage Optimization feature Enable or Disable Voltage Optimization feature 0: Disable; 1: Enable $EN_DIS **/ UINT8 VoltageOptimization; -/** Offset 0x080D - Enable or Disable Intel SpeedStep Technology +/** Offset 0x0815 - Enable or Disable Intel SpeedStep Technology Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable $EN_DIS **/ UINT8 Eist; -/** Offset 0x080E - Enable or Disable Energy Efficient P-state +/** Offset 0x0816 - Enable or Disable Energy Efficient P-state Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; 1: Enable $EN_DIS **/ UINT8 EnergyEfficientPState; -/** Offset 0x080F - Enable or Disable Energy Efficient Turbo +/** Offset 0x0817 - Enable or Disable Energy Efficient Turbo Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; 1: Enable $EN_DIS **/ UINT8 EnergyEfficientTurbo; -/** Offset 0x0810 - Enable or Disable T states +/** Offset 0x0818 - Enable or Disable T states Enable or Disable T states; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 TStates; -/** Offset 0x0811 - Enable or Disable Bi-Directional PROCHOT# +/** Offset 0x0819 - Enable or Disable Bi-Directional PROCHOT# Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable $EN_DIS **/ UINT8 BiProcHot; -/** Offset 0x0812 - Enable or Disable PROCHOT# signal being driven externally +/** Offset 0x081A - Enable or Disable PROCHOT# signal being driven externally Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DisableProcHotOut; -/** Offset 0x0813 - Enable or Disable PROCHOT# Response +/** Offset 0x081B - Enable or Disable PROCHOT# Response Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ProcHotResponse; -/** Offset 0x0814 - Enable or Disable VR Thermal Alert +/** Offset 0x081C - Enable or Disable VR Thermal Alert Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DisableVrThermalAlert; -/** Offset 0x0815 - Enable or Disable Thermal Reporting +/** Offset 0x081D - Enable or Disable Thermal Reporting Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 AutoThermalReporting; -/** Offset 0x0816 - Enable or Disable Thermal Monitor +/** Offset 0x081E - Enable or Disable Thermal Monitor Enable or Disable Thermal Monitor; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ThermalMonitor; -/** Offset 0x0817 - Enable or Disable CPU power states (C-states) +/** Offset 0x081F - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable $EN_DIS **/ UINT8 Cx; -/** Offset 0x0818 - Configure C-State Configuration Lock +/** Offset 0x0820 - Configure C-State Configuration Lock Configure C-State Configuration Lock; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PmgCstCfgCtrlLock; -/** Offset 0x0819 - Enable or Disable Enhanced C-states +/** Offset 0x0821 - Enable or Disable Enhanced C-states Enable or Disable Enhanced C-states. 0: Disable; 1: Enable $EN_DIS **/ UINT8 C1e; -/** Offset 0x081A - Enable or Disable Package Cstate Demotion +/** Offset 0x0822 - Enable or Disable Package Cstate Demotion Enable or Disable Package Cstate Demotion. 0: Disable; 1: Enable $EN_DIS **/ UINT8 PkgCStateDemotion; -/** Offset 0x081B - Enable or Disable Package Cstate UnDemotion +/** Offset 0x0823 - Enable or Disable Package Cstate UnDemotion Enable or Disable Package Cstate UnDemotion. 0: Disable; 1: Enable $EN_DIS **/ UINT8 PkgCStateUnDemotion; -/** Offset 0x081C - Enable or Disable CState-Pre wake +/** Offset 0x0824 - Enable or Disable CState-Pre wake Enable or Disable CState-Pre wake. 0: Disable; 1: Enable $EN_DIS **/ UINT8 CStatePreWake; -/** Offset 0x081D - Enable or Disable TimedMwait Support. +/** Offset 0x0825 - Enable or Disable TimedMwait Support. Enable or Disable TimedMwait Support. 0: Disable; 1: Enable $EN_DIS **/ UINT8 TimedMwait; -/** Offset 0x081E - Enable or Disable IO to MWAIT redirection +/** Offset 0x0826 - Enable or Disable IO to MWAIT redirection Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 CstCfgCtrIoMwaitRedirection; -/** Offset 0x081F - Set the Max Pkg Cstate +/** Offset 0x0827 - Set the Max Pkg Cstate Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto **/ UINT8 PkgCStateLimit; -/** Offset 0x0820 - TimeUnit for C-State Latency Control0 +/** Offset 0x0828 - TimeUnit for C-State Latency Control0 TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl0TimeUnit; -/** Offset 0x0821 - TimeUnit for C-State Latency Control1 +/** Offset 0x0829 - TimeUnit for C-State Latency Control1 TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl1TimeUnit; -/** Offset 0x0822 - TimeUnit for C-State Latency Control2 +/** Offset 0x082A - TimeUnit for C-State Latency Control2 TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl2TimeUnit; -/** Offset 0x0823 - TimeUnit for C-State Latency Control3 +/** Offset 0x082B - TimeUnit for C-State Latency Control3 TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl3TimeUnit; -/** Offset 0x0824 - TimeUnit for C-State Latency Control4 +/** Offset 0x082C - TimeUnit for C-State Latency Control4 Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl4TimeUnit; -/** Offset 0x0825 - TimeUnit for C-State Latency Control5 +/** Offset 0x082D - TimeUnit for C-State Latency Control5 TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl5TimeUnit; -/** Offset 0x0826 - Interrupt Redirection Mode Select +/** Offset 0x082E - Interrupt Redirection Mode Select Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change. **/ UINT8 PpmIrmSetting; -/** Offset 0x0827 - Lock prochot configuration +/** Offset 0x082F - Lock prochot configuration Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ProcHotLock; -/** Offset 0x0828 - Configuration for boot TDP selection +/** Offset 0x0830 - Configuration for boot TDP selection Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP Up;0xFF : Deactivate **/ UINT8 ConfigTdpLevel; -/** Offset 0x0829 - Race To Halt +/** Offset 0x0831 - Race To Halt Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)Disable; 1: Enable @@ -3053,19 +3106,19 @@ typedef struct { **/ UINT8 RaceToHalt; -/** Offset 0x082A - Max P-State Ratio +/** Offset 0x0832 - Max P-State Ratio Max P-State Ratio, Valid Range 0 to 0x7F **/ UINT8 MaxRatio; -/** Offset 0x082B - P-state ratios for custom P-state table +/** Offset 0x0833 - P-state ratios for custom P-state table P-state ratios for custom P-state table. NumberOfEntries has valid range between 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] are configurable. Valid Range of each entry is 0 to 0x7F **/ UINT8 StateRatio[40]; -/** Offset 0x0853 - P-state ratios for max 16 version of custom P-state table +/** Offset 0x085B - P-state ratios for max 16 version of custom P-state table P-state ratios for max 16 version of custom P-state table. This table is used for OS versions limited to a max of 16 P-States. If the first entry of this table is 0, or if Number of Entries is 16 or less, then this table will be ignored, and @@ -3074,391 +3127,501 @@ typedef struct { **/ UINT8 StateRatioMax16[16]; -/** Offset 0x0863 +/** Offset 0x086B **/ - UINT8 UnusedUpdSpace24; + UINT8 UnusedUpdSpace26; -/** Offset 0x0864 - Platform Power Pmax +/** Offset 0x086C - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. Range 0-1024 Watts. Value of 800 = 100W **/ UINT16 PsysPmax; -/** Offset 0x0866 - Interrupt Response Time Limit of C-State LatencyContol0 +/** Offset 0x086E - Interrupt Response Time Limit of C-State LatencyContol0 Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF **/ UINT16 CstateLatencyControl0Irtl; -/** Offset 0x0868 - Interrupt Response Time Limit of C-State LatencyContol1 +/** Offset 0x0870 - Interrupt Response Time Limit of C-State LatencyContol1 Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF **/ UINT16 CstateLatencyControl1Irtl; -/** Offset 0x086A - Interrupt Response Time Limit of C-State LatencyContol2 +/** Offset 0x0872 - Interrupt Response Time Limit of C-State LatencyContol2 Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF **/ UINT16 CstateLatencyControl2Irtl; -/** Offset 0x086C - Interrupt Response Time Limit of C-State LatencyContol3 +/** Offset 0x0874 - Interrupt Response Time Limit of C-State LatencyContol3 Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF **/ UINT16 CstateLatencyControl3Irtl; -/** Offset 0x086E - Interrupt Response Time Limit of C-State LatencyContol4 +/** Offset 0x0876 - Interrupt Response Time Limit of C-State LatencyContol4 Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF **/ UINT16 CstateLatencyControl4Irtl; -/** Offset 0x0870 - Interrupt Response Time Limit of C-State LatencyContol5 +/** Offset 0x0878 - Interrupt Response Time Limit of C-State LatencyContol5 Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF **/ UINT16 CstateLatencyControl5Irtl; -/** Offset 0x0872 +/** Offset 0x087A **/ - UINT8 UnusedUpdSpace25[2]; + UINT8 UnusedUpdSpace27[2]; -/** Offset 0x0874 - Package Long duration turbo mode power limit +/** Offset 0x087C - Package Long duration turbo mode power limit Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit1; -/** Offset 0x0878 - Package Short duration turbo mode power limit +/** Offset 0x0880 - Package Short duration turbo mode power limit Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit2Power; -/** Offset 0x087C - Package PL3 power limit +/** Offset 0x0884 - Package PL3 power limit Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit3; -/** Offset 0x0880 - Package PL4 power limit +/** Offset 0x0888 - Package PL4 power limit Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 1023875 in Step size of 125 **/ UINT32 PowerLimit4; -/** Offset 0x0884 - Tcc Offset Time Window for RATL +/** Offset 0x088C - Tcc Offset Time Window for RATL Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 1023875 in Step size of 125 **/ UINT32 TccOffsetTimeWindowForRatl; -/** Offset 0x0888 - Short term Power Limit value for custom cTDP level 1 +/** Offset 0x0890 - Short term Power Limit value for custom cTDP level 1 Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom1PowerLimit1; -/** Offset 0x088C - Long term Power Limit value for custom cTDP level 1 +/** Offset 0x0894 - Long term Power Limit value for custom cTDP level 1 Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom1PowerLimit2; -/** Offset 0x0890 - Short term Power Limit value for custom cTDP level 2 +/** Offset 0x0898 - Short term Power Limit value for custom cTDP level 2 Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom2PowerLimit1; -/** Offset 0x0894 - Long term Power Limit value for custom cTDP level 2 +/** Offset 0x089C - Long term Power Limit value for custom cTDP level 2 Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom2PowerLimit2; -/** Offset 0x0898 - Short term Power Limit value for custom cTDP level 3 +/** Offset 0x08A0 - Short term Power Limit value for custom cTDP level 3 Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom3PowerLimit1; -/** Offset 0x089C - Long term Power Limit value for custom cTDP level 3 +/** Offset 0x08A4 - Long term Power Limit value for custom cTDP level 3 Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom3PowerLimit2; -/** Offset 0x08A0 - Platform PL1 power +/** Offset 0x08A8 - Platform PL1 power Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PsysPowerLimit1Power; -/** Offset 0x08A4 - Platform PL2 power +/** Offset 0x08AC - Platform PL2 power Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PsysPowerLimit2Power; -/** Offset 0x08A8 - Set Three Strike Counter Disable +/** Offset 0x08B0 - Set Three Strike Counter Disable False (default): Three Strike counter will be incremented and True: Prevents Three Strike counter from incrementing; 0: False; 1: True. 0: False, 1: True **/ UINT8 ThreeStrikeCounterDisable; -/** Offset 0x08A9 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT +/** Offset 0x08B1 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 HwpInterruptControl; -/** Offset 0x08AA - 5-Core Ratio Limit +/** Offset 0x08B2 - 5-Core Ratio Limit 5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 5-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF **/ UINT8 FiveCoreRatioLimit; -/** Offset 0x08AB - 6-Core Ratio Limit +/** Offset 0x08B3 - 6-Core Ratio Limit 6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 6-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF **/ UINT8 SixCoreRatioLimit; -/** Offset 0x08AC - 7-Core Ratio Limit +/** Offset 0x08B4 - 7-Core Ratio Limit 7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 7-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF **/ UINT8 SevenCoreRatioLimit; -/** Offset 0x08AD - 8-Core Ratio Limit +/** Offset 0x08B5 - 8-Core Ratio Limit 8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 8-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF **/ UINT8 EightCoreRatioLimit; -/** Offset 0x08AE - Intel Turbo Boost Max Technology 3.0 +/** Offset 0x08B6 - Intel Turbo Boost Max Technology 3.0 Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled $EN_DIS **/ UINT8 EnableItbm; -/** Offset 0x08AF - Intel Turbo Boost Max Technology 3.0 Driver +/** Offset 0x08B7 - Intel Turbo Boost Max Technology 3.0 Driver Intel Turbo Boost Max Technology 3.0 Driver 0: Disabled; 1: Enabled $EN_DIS **/ UINT8 EnableItbmDriver; -/** Offset 0x08B0 - Enable or Disable C1 Cstate Demotion +/** Offset 0x08B8 - Enable or Disable C1 Cstate Demotion Enable or Disable C1 Cstate Demotion. Disable; 1: Enable $EN_DIS **/ UINT8 C1StateAutoDemotion; -/** Offset 0x08B1 - Enable or Disable C1 Cstate UnDemotion +/** Offset 0x08B9 - Enable or Disable C1 Cstate UnDemotion Enable or Disable C1 Cstate UnDemotion. Disable; 1: Enable $EN_DIS **/ UINT8 C1StateUnDemotion; -/** Offset 0x08B2 - CpuWakeUpTimer +/** Offset 0x08BA - CpuWakeUpTimer Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased to 180 seconds. 0: Disable; 1: Enable $EN_DIS **/ UINT8 CpuWakeUpTimer; -/** Offset 0x08B3 - Minimum Ring ratio limit override +/** Offset 0x08BB - Minimum Ring ratio limit override Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit **/ UINT8 MinRingRatioLimit; -/** Offset 0x08B4 - Minimum Ring ratio limit override +/** Offset 0x08BC - Minimum Ring ratio limit override Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit **/ UINT8 MaxRingRatioLimit; -/** Offset 0x08B5 - Enable or Disable C3 Cstate Demotion +/** Offset 0x08BD - Enable or Disable C3 Cstate Demotion Enable or Disable C3 Cstate Demotion. Disable; 1: Enable $EN_DIS **/ UINT8 C3StateAutoDemotion; -/** Offset 0x08B6 - Enable or Disable C3 Cstate UnDemotion +/** Offset 0x08BE - Enable or Disable C3 Cstate UnDemotion Enable or Disable C3 Cstate UnDemotion. Disable; 1: Enable $EN_DIS **/ UINT8 C3StateUnDemotion; -/** Offset 0x08B7 - ReservedCpuPostMemTest +/** Offset 0x08BF - Ratio Limit Num Core 0 + Ratio Limit Num Core0: This register defines the active core ranges for each frequency point +**/ + UINT8 RatioLimitNumCore0; + +/** Offset 0x08C0 - Ratio Limit Num Core 1 + Ratio Limit Num Core1: This register defines the active core ranges for each frequency point +**/ + UINT8 RatioLimitNumCore1; + +/** Offset 0x08C1 - Ratio Limit Num Core 2 + Ratio Limit Num Core2: This register defines the active core ranges for each frequency point +**/ + UINT8 RatioLimitNumCore2; + +/** Offset 0x08C2 - Ratio Limit Core 3 + Ratio Limit Num Core3: This register defines the active core ranges for each frequency point +**/ + UINT8 RatioLimitNumCore3; + +/** Offset 0x08C3 - Ratio Limit Num Core 4 + Ratio Limit Num Core4: This register defines the active core ranges for each frequency point +**/ + UINT8 RatioLimitNumCore4; + +/** Offset 0x08C4 - Ratio Limit Num Core 5 + Ratio Limit Num Core5: This register defines the active core ranges for each frequency point +**/ + UINT8 RatioLimitNumCore5; + +/** Offset 0x08C5 - Ratio Limit Num Core 6 + Ratio Limit Num Core6: This register defines the active core ranges for each frequency point +**/ + UINT8 RatioLimitNumCore6; + +/** Offset 0x08C6 - Ratio Limit Num Core 7 + Ratio Limit Num Core7: This register defines the active core ranges for each frequency point +**/ + UINT8 RatioLimitNumCore7; + +/** Offset 0x08C7 - ReservedCpuPostMemTest Reserved for CPU Post-Mem Test $EN_DIS **/ - UINT8 ReservedCpuPostMemTest[19]; + UINT8 ReservedCpuPostMemTest[11]; -/** Offset 0x08CA - SgxSinitDataFromTpm +/** Offset 0x08D2 - SgxSinitDataFromTpm SgxSinitDataFromTpm default values **/ UINT8 SgxSinitDataFromTpm; -/** Offset 0x08CB - End of Post message - Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): - EOP send in PEI, Send in DXE(0x2)(Default): EOP send in PEI +/** Offset 0x08D3 - End of Post message + Deprecated 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved **/ UINT8 EndOfPostMessage; -/** Offset 0x08CC - D0I3 Setting for HECI Disable +/** Offset 0x08D4 - D0I3 Setting for HECI Disable Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all HECI devices $EN_DIS **/ UINT8 DisableD0I3SettingForHeci; -/** Offset 0x08CD +/** Offset 0x08D5 **/ - UINT8 UnusedUpdSpace26; + UINT8 UnusedUpdSpace28; -/** Offset 0x08CE - HD Audio Reset Wait Timer +/** Offset 0x08D6 - HD Audio Reset Wait Timer The delay timer after Azalia reset, the value is number of microseconds. Default is 600. **/ UINT16 PchHdaResetWaitTimer; -/** Offset 0x08D0 - Enable LOCKDOWN SMI +/** Offset 0x08D8 - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. $EN_DIS **/ UINT8 PchLockDownGlobalSmi; -/** Offset 0x08D1 - Enable LOCKDOWN BIOS Interface +/** Offset 0x08D9 - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. $EN_DIS **/ UINT8 PchLockDownBiosInterface; -/** Offset 0x08D2 - Unlock all GPIO pads +/** Offset 0x08DA - Unlock all GPIO pads Force all GPIO pads to be unlocked for debug purpose. $EN_DIS **/ UINT8 PchUnlockGpioPads; -/** Offset 0x08D3 - PCH Unlock SideBand access +/** Offset 0x08DB - PCH Unlock SideBand access The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. $EN_DIS **/ UINT8 PchSbAccessUnlock; -/** Offset 0x08D4 - PCIE RP Ltr Max Snoop Latency +/** Offset 0x08DC - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. **/ UINT16 PcieRpLtrMaxSnoopLatency[24]; -/** Offset 0x0904 - PCIE RP Ltr Max No Snoop Latency +/** Offset 0x090C - PCIE RP Ltr Max No Snoop Latency Latency Tolerance Reporting, Max Non-Snoop Latency. **/ UINT16 PcieRpLtrMaxNoSnoopLatency[24]; -/** Offset 0x0934 - PCIE RP Snoop Latency Override Mode +/** Offset 0x093C - PCIE RP Snoop Latency Override Mode Latency Tolerance Reporting, Snoop Latency Override Mode. **/ UINT8 PcieRpSnoopLatencyOverrideMode[24]; -/** Offset 0x094C - PCIE RP Snoop Latency Override Multiplier +/** Offset 0x0954 - PCIE RP Snoop Latency Override Multiplier Latency Tolerance Reporting, Snoop Latency Override Multiplier. **/ UINT8 PcieRpSnoopLatencyOverrideMultiplier[24]; -/** Offset 0x0964 - PCIE RP Snoop Latency Override Value +/** Offset 0x096C - PCIE RP Snoop Latency Override Value Latency Tolerance Reporting, Snoop Latency Override Value. **/ UINT16 PcieRpSnoopLatencyOverrideValue[24]; -/** Offset 0x0994 - PCIE RP Non Snoop Latency Override Mode +/** Offset 0x099C - PCIE RP Non Snoop Latency Override Mode Latency Tolerance Reporting, Non-Snoop Latency Override Mode. **/ UINT8 PcieRpNonSnoopLatencyOverrideMode[24]; -/** Offset 0x09AC - PCIE RP Non Snoop Latency Override Multiplier +/** Offset 0x09B4 - PCIE RP Non Snoop Latency Override Multiplier Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. **/ UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24]; -/** Offset 0x09C4 - PCIE RP Non Snoop Latency Override Value +/** Offset 0x09CC - PCIE RP Non Snoop Latency Override Value Latency Tolerance Reporting, Non-Snoop Latency Override Value. **/ UINT16 PcieRpNonSnoopLatencyOverrideValue[24]; -/** Offset 0x09F4 - PCIE RP Slot Power Limit Scale +/** Offset 0x09FC - PCIE RP Slot Power Limit Scale Specifies scale used for slot power limit value. Leave as 0 to set to default. **/ UINT8 PcieRpSlotPowerLimitScale[24]; -/** Offset 0x0A0C - PCIE RP Slot Power Limit Value +/** Offset 0x0A14 - PCIE RP Slot Power Limit Value Specifies upper limit on power supplie by slot. Leave as 0 to set to default. **/ UINT16 PcieRpSlotPowerLimitValue[24]; -/** Offset 0x0A3C - PCIE RP Upstream Port Transmiter Preset +/** Offset 0x0A44 - PCIE RP Upstream Port Transmiter Preset Used during Gen3 Link Equalization. Used for all lanes. Default is 5. **/ UINT8 PcieRpUptp[24]; -/** Offset 0x0A54 - PCIE RP Downstream Port Transmiter Preset +/** Offset 0x0A5C - PCIE RP Downstream Port Transmiter Preset Used during Gen3 Link Equalization. Used for all lanes. Default is 7. **/ UINT8 PcieRpDptp[24]; -/** Offset 0x0A6C - PCIE RP Enable Port8xh Decode +/** Offset 0x0A74 - PCIE RP Enable Port8xh Decode This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PcieEnablePort8xhDecode; -/** Offset 0x0A6D - PCIE Port8xh Decode Port Index +/** Offset 0x0A75 - PCIE Port8xh Decode Port Index The Index of PCIe Port that is selected for Port8xh Decode (0 Based). **/ UINT8 PchPciePort8xhDecodePortIndex; -/** Offset 0x0A6E - PCH Energy Reporting +/** Offset 0x0A76 - PCH Energy Reporting Disable/Enable PCH to CPU energy report feature. $EN_DIS **/ UINT8 PchPmDisableEnergyReport; -/** Offset 0x0A6F - PCH Sata Test Mode +/** Offset 0x0A77 - PCH Sata Test Mode Allow entrance to the PCH SATA test modes. $EN_DIS **/ UINT8 SataTestMode; -/** Offset 0x0A70 - PCH USB OverCurrent mapping lock enable +/** Offset 0x0A78 - PCH USB OverCurrent mapping lock enable If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. $EN_DIS **/ UINT8 PchXhciOcLock; -/** Offset 0x0A71 - ReservedPchPostMemTest +/** Offset 0x0A79 - ReservedPchPostMemTest Reserved for Pch Post-Mem Test $EN_DIS **/ UINT8 ReservedPchPostMemTest[16]; -/** Offset 0x0A81 - Mctp Broadcast Cycle +/** Offset 0x0A89 - Mctp Broadcast Cycle Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MctpBroadcastCycle; -/** Offset 0x0A82 +/** Offset 0x0A8A - Use DLL values from policy + Set if FSP should use HS400 DLL values from policy + $EN_DIS **/ - UINT8 UnusedUpdSpace27[2]; + UINT8 EmmcUseCustomDlls; -/** Offset 0x0A84 +/** Offset 0x0A8B +**/ + UINT8 UnusedUpdSpace29; + +/** Offset 0x0A8C - Emmc Tx CMD Delay control register value + Please see Tx CMD Delay Control register definition for help +**/ + UINT32 EmmcTxCmdDelayRegValue; + +/** Offset 0x0A90 - Emmc Tx DATA Delay control 1 register value + Please see Tx DATA Delay control 1 register definition for help +**/ + UINT32 EmmcTxDataDelay1RegValue; + +/** Offset 0x0A94 - Emmc Tx DATA Delay control 2 register value + Please see Tx DATA Delay control 2 register definition for help +**/ + UINT32 EmmcTxDataDelay2RegValue; + +/** Offset 0x0A98 - Emmc Rx CMD + DATA Delay control 1 register value + Please see Rx CMD + DATA Delay control 1 register definition for help +**/ + UINT32 EmmcRxCmdDataDelay1RegValue; + +/** Offset 0x0A9C - Emmc Rx CMD + DATA Delay control 2 register value + Please see Rx CMD + DATA Delay control 2 register definition for help +**/ + UINT32 EmmcRxCmdDataDelay2RegValue; + +/** Offset 0x0AA0 - Emmc Rx Strobe Delay control register value + Please see Rx Strobe Delay control register definition for help +**/ + UINT32 EmmcRxStrobeDelayRegValue; + +/** Offset 0x0AA4 - Use tuned DLL values from policy + Set if FSP should use HS400 DLL values from policy + $EN_DIS +**/ + UINT8 SdCardUseCustomDlls; + +/** Offset 0x0AA5 +**/ + UINT8 UnusedUpdSpace30[3]; + +/** Offset 0x0AA8 - SdCard Tx CMD Delay control register value + Please see Tx CMD Delay Control register definition for help +**/ + UINT32 SdCardTxCmdDelayRegValue; + +/** Offset 0x0AAC - SdCard Tx DATA Delay control 1 register value + Please see Tx DATA Delay control 1 register definition for help +**/ + UINT32 SdCardTxDataDelay1RegValue; + +/** Offset 0x0AB0 - SdCard Tx DATA Delay control 2 register value + Please see Tx DATA Delay control 2 register definition for help +**/ + UINT32 SdCardTxDataDelay2RegValue; + +/** Offset 0x0AB4 - SdCard Rx CMD + DATA Delay control 1 register value + Please see Rx CMD + DATA Delay control 1 register definition for help +**/ + UINT32 SdCardRxCmdDataDelay1RegValue; + +/** Offset 0x0AB8 - SdCard Rx CMD + DATA Delay control 2 register value + Please see Rx CMD + DATA Delay control 2 register definition for help +**/ + UINT32 SdCardRxCmdDataDelay2RegValue; + +/** Offset 0x0ABC **/ UINT8 ReservedFspsTestUpd[12]; } FSP_S_TEST_CONFIG; @@ -3475,15 +3638,15 @@ typedef struct { **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x07B8 +/** Offset 0x07C0 **/ FSP_S_TEST_CONFIG FspsTestConfig; -/** Offset 0x0A90 +/** Offset 0x0AC8 **/ - UINT8 UnusedUpdSpace28[6]; + UINT8 UnusedUpdSpace31[6]; -/** Offset 0x0A96 +/** Offset 0x0ACE **/ UINT16 UpdTerminator; } FSPS_UPD; diff --git a/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c b/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c index ba56543975..bbcf753dce 100644 --- a/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c +++ b/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c @@ -43,9 +43,7 @@ are permitted provided that the following conditions are met: // // Pointer to the HOB should be initialized with the output of FSP INIT PARAMS // -#ifndef __PRE_RAM__ extern volatile void *FspHobListPtr; -#endif /** Reads a 64-bit value from memory that may be unaligned. @@ -116,12 +114,8 @@ GetHobList ( VOID ) { -#ifndef __PRE_RAM__ ASSERT (FspHobListPtr != NULL); return ((VOID *)FspHobListPtr); -#else - return ((VOID *)NULL); -#endif } /** diff --git a/toolchain.inc b/toolchain.inc index 875cb20387..4c0408ccfd 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -72,7 +72,7 @@ CFLAGS_ppc64 += # stack use, we use 1.5K as heuristic, assuming that we typically have lots # of tiny stack frames and the odd large one. # -# Store larger buffers in BSS, use MAYBE_STATIC to share code with __PRE_RAM__ +# Store larger buffers in BSS, use MAYBE_STATIC_BSS to share code with __PRE_RAM__ # on x86. # Since GCCs detection of dynamic array bounds unfortunately seems to be # very basic, you'll sometimes have to use a static upper bound for the diff --git a/util/abuild/abuild b/util/abuild/abuild index ef4e46b8ed..4a62cfa045 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -398,6 +398,10 @@ function compile_target if [ "$clean_work" = "true" ]; then rm -rf "${build_dir}" fi + if [ "$clean_objs" = "true" ]; then + find ${build_dir} \! \( -name coreboot.rom -o -name config.h -o -name config.build -o -name make.log \) -type f -exec rm {} + + find ${build_dir} -type d -exec rmdir -p {} + 2>/dev/null + fi return $MAKE_FAILED } @@ -595,6 +599,7 @@ Options:\n" (defaults to $XMLFILE) [-y|--ccache] Use ccache [-z|--clean] Remove build results when finished + [-Z|--clean-somewhat] Remove build but keep coreboot.rom + config [-V|--version] Print version number and exit [-h|--help] Print this help and exit @@ -641,12 +646,12 @@ getoptbrand="$(getopt -V)" # shellcheck disable=SC2086 if [ "${getoptbrand:0:6}" == "getopt" ]; then # Detected GNU getopt that supports long options. - args=$(getopt -l version,verbose,quiet,help,all,target:,board-variant:,payloads:,cpus:,silent,junit,config,loglevel:,remove,prefix:,update,scan-build,ccache,blobs,clang,any-toolchain,clean,outdir:,chromeos,xmlfile:,kconfig:,dir:,root:,recursive,checksum:,timeless,exitcode,asserts -o Vvqhat:b:p:c:sJCl:rP:uyBLAzo:xX:K:d:R:Ie -- "$@") || exit 1 + args=$(getopt -l version,verbose,quiet,help,all,target:,board-variant:,payloads:,cpus:,silent,junit,config,loglevel:,remove,prefix:,update,scan-build,ccache,blobs,clang,any-toolchain,clean,clean-somewhat,outdir:,chromeos,xmlfile:,kconfig:,dir:,root:,recursive,checksum:,timeless,exitcode,asserts -o Vvqhat:b:p:c:sJCl:rP:uyBLAzZo:xX:K:d:R:Ie -- "$@") || exit 1 eval set -- $args retval=$? else # Detected non-GNU getopt - args=$(getopt Vvqhat:b:p:c:sJCl:rP:uyBLAzo:xX:K:d:R:Ie "$@") + args=$(getopt Vvqhat:b:p:c:sJCl:rP:uyBLAZzo:xX:K:d:R:Ie "$@") set -- $args retval=$? fi @@ -658,6 +663,7 @@ fi chromeos=false clean_work=false +clean_objs=false verboseopt='V=0' customizing="" configoptions="" @@ -730,6 +736,10 @@ while true ; do customizing="${customizing}, clean" clean_work=true ;; + -Z|--clean-somewhat) shift + customizing="${customizing}, clean-somewhat" + clean_objs=true + ;; -o|--outdir) shift TARGET=$1; shift ;; diff --git a/util/autoport/main.go b/util/autoport/main.go index ab49a14a9d..03523a2c39 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -925,8 +925,7 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal, - others => Disabled); + Internal); end GMA.Mainboard; `) diff --git a/util/cbfstool/ifittool.c b/util/cbfstool/ifittool.c index 3b16c3fcf0..dce37c8084 100644 --- a/util/cbfstool/ifittool.c +++ b/util/cbfstool/ifittool.c @@ -336,7 +336,6 @@ int main(int argc, char *argv[]) case ADD_REGI_OP: { struct buffer region; - addr = 0; if (partitioned_file_read_region(®ion, image_file, name)) { addr = -convert_to_from_top_aligned(®ion, 0); diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index c7f63c3bee..9c10c7d56e 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -60,7 +60,7 @@ EXPAT_VERSION=2.2.7 # CLANG version number CLANG_VERSION=8.0.0 MAKE_VERSION=4.2.1 -CMAKE_VERSION=3.15.0 +CMAKE_VERSION=3.15.3 NASM_VERSION=2.14.02 # GCC toolchain archive locations diff --git a/util/crossgcc/sum/cmake-3.15.0.tar.gz.cksum b/util/crossgcc/sum/cmake-3.15.0.tar.gz.cksum deleted file mode 100644 index 3ec1605c5d..0000000000 --- a/util/crossgcc/sum/cmake-3.15.0.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -0a1c3870d566061da8b9ed02bbfe17a39c7bf3cd tarballs/cmake-3.15.0.tar.gz diff --git a/util/crossgcc/sum/cmake-3.15.3.tar.gz.cksum b/util/crossgcc/sum/cmake-3.15.3.tar.gz.cksum new file mode 100644 index 0000000000..c4676767e6 --- /dev/null +++ b/util/crossgcc/sum/cmake-3.15.3.tar.gz.cksum @@ -0,0 +1 @@ +f467388ba336ea3652f5800918a72cfcc4f7f403 tarballs/cmake-3.15.3.tar.gz diff --git a/util/futility/Makefile.inc b/util/futility/Makefile.inc index 782953e649..06e724c15f 100644 --- a/util/futility/Makefile.inc +++ b/util/futility/Makefile.inc @@ -5,6 +5,7 @@ $(objutil)/futility/build/futility/futility: unset CFLAGS LDFLAGS; $(MAKE) -C $(VBOOT_SOURCE) \ BUILD=$(abspath $@/../..) \ CC="$(HOSTCC)" \ + $(if $(HOSTPKGCONFIG), PKG_CONFIG="$(HOSTPKGCONFIG)") \ V=$(V) \ $(abspath $@) diff --git a/util/genbuild_h/genbuild_h.sh b/util/genbuild_h/genbuild_h.sh index c264b74635..8da68ba445 100755 --- a/util/genbuild_h/genbuild_h.sh +++ b/util/genbuild_h/genbuild_h.sh @@ -22,6 +22,13 @@ export LANG=C export LC_ALL=C export TZ=UTC0 +XCOMPILE=$1 + +if [ -z "$XCOMPILE" ] || [ "$1" = "--help" ]; then + echo "usage: $0 " >&2 + exit 1 +fi + # $1: format string get_git_head_data() { LANG= git log --no-show-signature -1 --format="format:$1" 2>/dev/null || \ @@ -53,7 +60,7 @@ esac } IASL=util/crossgcc/xgcc/bin/iasl -eval $(grep ^IASL:= .xcompile 2>/dev/null | sed s,:=,=,) +eval $(grep ^IASL:= "$XCOMPILE" 2>/dev/null | sed s,:=,=,) #Print out the information that goes into build.h printf "/* build system definitions (autogenerated) */\n" diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 741aed4cca..efeab5665f 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1047,6 +1047,19 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: + case PCI_DEVICE_ID_INTEL_C621: + case PCI_DEVICE_ID_INTEL_C622: + case PCI_DEVICE_ID_INTEL_C624: + case PCI_DEVICE_ID_INTEL_C625: + case PCI_DEVICE_ID_INTEL_C626: + case PCI_DEVICE_ID_INTEL_C627: + case PCI_DEVICE_ID_INTEL_C628: + case PCI_DEVICE_ID_INTEL_C629: + case PCI_DEVICE_ID_INTEL_C624_SUPER: + case PCI_DEVICE_ID_INTEL_C627_SUPER_1: + case PCI_DEVICE_ID_INTEL_C621_SUPER: + case PCI_DEVICE_ID_INTEL_C627_SUPER_2: + case PCI_DEVICE_ID_INTEL_C628_SUPER: case PCI_DEVICE_ID_INTEL_H310: case PCI_DEVICE_ID_INTEL_H370: case PCI_DEVICE_ID_INTEL_Z390: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 0387418250..321cf97970 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -2,6 +2,7 @@ * inteltool - dump all registers on an Intel CPU + chipset based system. * * Copyright (C) 2017 secunet Security Networks AG + * Copyright (C) 2019 YADRO * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -959,6 +960,461 @@ static const struct gpio_community *const sunrise_lp_communities[] = { &sunrise_community_gpd, &sunrise_lp_community_fg, }; +static const char *const lewisburg_group_a_names[] = { + "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", + "GPP_A1", "LAD0", "n/a", "ESPI_IO0", + "GPP_A2", "LAD1", "n/a", "ESPI_IO1", + "GPP_A3", "LAD2", "n/a", "ESPI_IO2", + "GPP_A4", "LAD3", "n/a", "ESPI_IO3", + "GPP_A5", "LFRAME#", "n/a", "ESPI_CS0#", + "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#", + "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "n/a", "n/a", + "GPP_A12", "BM_BUSY#", "n/a", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "n/a", "n/a", "ESPI_RESET#", + "GPP_A15", "SUS_ACK#", "n/a", "n/a", + "GPP_A16", "CLKOUT_LPC2", "n/a", "n/a", + "GPP_A17", "n/a", "n/a", "n/a", + "GPP_A18", "n/a", "n/a", "n/a", + "GPP_A19", "n/a", "n/a", "n/a", + "GPP_A20", "n/a", "n/a", "n/a", + "GPP_A21", "n/a", "n/a", "n/a", + "GPP_A22", "n/a", "n/a", "n/a", + "GPP_A23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group lewisburg_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = ARRAY_SIZE(lewisburg_group_a_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_a_names, +}; + +static const char *const lewisburg_group_b_names[] = { + "GPP_B0", "CORE_VID0", "n/a", "n/a", + "GPP_B1", "CORE_VID1", "n/a", "n/a", + "GPP_B2", "n/a", "n/a", "n/a", + "GPP_B3", "CPU_GP2", "n/a", "n/a", + "GPP_B4", "CPU_GP3", "n/a", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", + "GPP_B11", "n/a", "n/a", "n/a", + "GPP_B12", "GLB_RST_WARN_N#", "n/a", "n/a", + "GPP_B13", "PLTRST#", "n/a", "n/a", + "GPP_B14", "SPKR", "n/a", "n/a", + "GPP_B15", "n/a", "n/a", "n/a", + "GPP_B16", "n/a", "n/a", "n/a", + "GPP_B17", "n/a", "n/a", "n/a", + "GPP_B18", "n/a", "n/a", "n/a", + "GPP_B19", "n/a", "n/a", "n/a", + "GPP_B20", "n/a", "n/a", "n/a", + "GPP_B21", "n/a", "n/a", "n/a", + "GPP_B22", "n/a", "n/a", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", "MEIE_SML1ALRT#", +}; + +static const struct gpio_group lewisburg_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(lewisburg_group_b_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_b_names, +}; + +static const char *const lewisburg_group_c_names[] = { + "GPP_C0", "SMBCLK", "n/a", "n/a", + "GPP_C1", "SMBDATA", "n/a", "n/a", + "GPP_C2", "SMBALERT#", "n/a", "n/a", + "GPP_C3", "SML0CLK", "SML0CLK_IE#", "n/a", + "GPP_C4", "SML0DATA", "SML0DATA_IE", "n/a", + "GPP_C5", "SML0ALERT#", "SML0ALERT_IE#", "n/a", + "GPP_C6", "SML1CLK", "SML1CLK_IE", "n/a", + "GPP_C7", "SML1DATA", "SML1DATA_IE", "n/a", + "GPP_C8", "n/a", "n/a", "n/a", + "GPP_C9", "n/a", "n/a", "n/a", + "GPP_C10", "n/a", "n/a", "n/a", + "GPP_C11", "n/a", "n/a", "n/a", + "GPP_C12", "n/a", "n/a", "n/a", + "GPP_C13", "n/a", "n/a", "n/a", + "GPP_C14", "n/a", "n/a", "n/a", + "GPP_C15", "n/a", "n/a", "n/a", + "GPP_C16", "n/a", "n/a", "n/a", + "GPP_C17", "n/a", "n/a", "n/a", + "GPP_C18", "n/a", "n/a", "n/a", + "GPP_C19", "n/a", "n/a", "n/a", + "GPP_C20", "n/a", "n/a", "n/a", + "GPP_C21", "n/a", "n/a", "n/a", + "GPP_C22", "n/a", "n/a", "n/a", + "GPP_C23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group lewisburg_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(lewisburg_group_c_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_c_names, +}; + +static const char *const lewisburg_group_d_names[] = { + "GPP_D0", "n/a", "n/a", "SERIAL_BLINK", + "GPP_D1", "n/a", "n/a", "SERIAL_BLINK", + "GPP_D2", "n/a", "n/a", "SERIAL_BLINK", + "GPP_D3", "n/a", "n/a", "SERIAL_BLINK", + "GPP_D4", "n/a", "n/a", "SERIAL_BLINK", + "GPP_D5", "n/a", "n/a", "n/a", + "GPP_D6", "n/a", "n/a", "n/a", + "GPP_D7", "n/a", "n/a", "n/a", + "GPP_D8", "n/a", "n/a", "n/a", + "GPP_D9", "n/a", "n/a", "SSATA_DEVSLP3", + "GPP_D10", "n/a", "n/a", "SSATA_DEVSLP4", + "GPP_D11", "n/a", "n/a", "SSATA_DEVSLP5", + "GPP_D12", "n/a", "n/a", "SSATA_SDATAOUT1", + "GPP_D13", "n/a", "SML0BCLK", "SML0BCLK_IE", + "GPP_D14", "n/a", "SML0BDATA", "SML0BDATA_IE", + "GPP_D15", "n/a", "n/a", "SSATA_SDATAOUT0", + "GPP_D16", "n/a", "SML0BALERT#", "SML0BALERT_IE#", + "GPP_D17", "n/a", "n/a", "n/a", + "GPP_D18", "n/a", "n/a", "n/a", + "GPP_D19", "n/a", "n/a", "n/a", + "GPP_D20", "n/a", "n/a", "n/a", + "GPP_D21", "n/a", "n/a", "IE_UART_RX", + "GPP_D22", "n/a", "n/a", "IE_UART_TX", + "GPP_D23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group lewisburg_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(lewisburg_group_d_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_d_names, +}; + +/* The functions in this group are the same as in the pad group E for + the Sunrise-H PCH */ +static const struct gpio_group lewisburg_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(sunrise_group_e_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_e_names, +}; + +static const char *const lewisburg_group_f_names[] = { + "GPP_F0", "SATAXPCIE3", "n/a", "SATAGP3", + "GPP_F1", "SATAXPCIE4", "n/a", "SATAGP4", + "GPP_F2", "SATAXPCIE5", "n/a", "SATAGP5", + "GPP_F3", "SATAXPCIE6", "n/a", "SATAGP6", + "GPP_F4", "SATAXPCIE7", "n/a", "SATAGP7", + "GPP_F5", "SATA_DEVSLP3", "n/a", "n/a", + "GPP_F6", "SATA_DEVSLP4", "n/a", "n/a", + "GPP_F7", "SATA_DEVSLP5", "n/a", "n/a", + "GPP_F8", "SATA_DEVSLP6", "n/a", "n/a", + "GPP_F9", "SATA_DEVSLP7", "n/a", "n/a", + "GPP_F10", "SATA_SCLOCK", "n/a", "n/a", + "GPP_F11", "SATA_SLOAD", "n/a", "n/a", + "GPP_F12", "SATA_SDATAOUT1", "n/a", "n/a", + "GPP_F13", "SATA_SDATAOUT2", "n/a", "n/a", + "GPP_F14", "n/a", "n/a", "SSATA_LED#", + "GPP_F15", "USB_OC4#", "n/a", "n/a", + "GPP_F16", "USB_OC5#", "n/a", "n/a", + "GPP_F17", "USB_OC6#", "n/a", "n/a", + "GPP_F18", "USB_OC7#", "n/a", "n/a", + "GPP_F19", "LAN_SMBCLK", "n/a", "n/a", + "GPP_F20", "LAN_SMBDATA", "n/a", "n/a", + "GPP_F21", "LAN_SMBALRT#", "n/a", "n/a", + "GPP_F22", "n/a", "n/a", "SSATA_SCLOCK", + "GPP_F23", "n/a", "n/a", "SSATA_SLOAD", +}; + +static const struct gpio_group lewisburg_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(lewisburg_group_f_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_f_names, +}; + +static const char *const lewisburg_group_g_names[] = { + "GPP_G0", "FAN_TACH_0", "FAN_TACH_0_IE", "n/a", + "GPP_G1", "FAN_TACH_1", "FAN_TACH_1_IE", "n/a", + "GPP_G2", "FAN_TACH_2", "FAN_TACH_2_IE", "n/a", + "GPP_G3", "FAN_TACH_3", "FAN_TACH_3_IE", "n/a", + "GPP_G4", "FAN_TACH_4", "FAN_TACH_4_IE", "n/a", + "GPP_G5", "FAN_TACH_5", "FAN_TACH_5_IE", "n/a", + "GPP_G6", "FAN_TACH_6", "FAN_TACH_6_IE", "n/a", + "GPP_G7", "FAN_TACH_7", "FAN_TACH_7_IE", "n/a", + "GPP_G8", "FAN_PWM_0", "FAN_PWM_0_IE", "n/a", + "GPP_G9", "FAN_PWM_1", "FAN_PWM_1_IE", "n/a", + "GPP_G10", "FAN_PWM_2", "FAN_PWM_2_IE", "n/a", + "GPP_G11", "FAN_PWM_3", "FAN_PWM_3_IE", "n/a", + "GPP_G12", "n/a", "n/a", "n/a", + "GPP_G13", "n/a", "n/a", "n/a", + "GPP_G14", "n/a", "n/a", "n/a", + "GPP_G15", "n/a", "n/a", "n/a", + "GPP_G16", "n/a", "n/a", "n/a", + "GPP_G17", "ADR_COMPLETE", "n/a", "n/a", + "GPP_G18", "NMI#", "n/a", "n/a", + "GPP_G19", "SMI#", "n/a", "n/a", + "GPP_G20", "n/a", "SSATA_DEVSLP0", "n/a", + "GPP_G21", "n/a", "SSATA_DEVSLP1", "n/a", + "GPP_G22", "n/a", "SSATA_DEVSLP2", "n/a", + "GPP_G23", "n/a", "SSATAXPCIE0", "SSATAGP0", +}; + +static const struct gpio_group lewisburg_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(lewisburg_group_g_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_g_names, +}; + +static const char *const lewisburg_group_h_names[] = { + "GPP_H0", "SRCCLKREQ6#", "n/a", "n/a", + "GPP_H1", "SRCCLKREQ7#", "n/a", "n/a", + "GPP_H2", "SRCCLKREQ8#", "n/a", "n/a", + "GPP_H3", "SRCCLKREQ9#", "n/a", "n/a", + "GPP_H4", "SRCCLKREQ10#", "n/a", "n/a", + "GPP_H5", "SRCCLKREQ11#", "n/a", "n/a", + "GPP_H6", "SRCCLKREQ12#", "n/a", "n/a", + "GPP_H7", "SRCCLKREQ13#", "n/a", "n/a", + "GPP_H8", "SRCCLKREQ14#", "n/a", "n/a", + "GPP_H9", "SRCCLKREQ15#", "n/a", "n/a", + "GPP_H10", "SML2CLK", "SML2CLK_IE", "n/a", + "GPP_H11", "SML2DATA", "SML2DATA_IE", "n/a", + "GPP_H12", "SML2ALERT#", "SML2ALERT#_IE#", "n/a", + "GPP_H13", "SML3CLK", "SML3CLK_IE", "n/a", + "GPP_H14", "SML3DATA", "SML3DATA_IE", "n/a", + "GPP_H15", "SML3ALERT#", "SML3ALERT#_IE#", "n/a", + "GPP_H16", "SML4CLK", "SML4CLK_IE", "n/a", + "GPP_H17", "SML4DATA", "SML4DATA_IE", "n/a", + "GPP_H18", "SML4ALERT#", "SML4ALERT#_IE#", "n/a", + "GPP_H19", "n/a", "SSATAXPCIE1", "SSATAGP1", + "GPP_H20", "n/a", "SSATAXPCIE2", "SSATAGP2", + "GPP_H21", "n/a", "SSATAXPCIE3", "SSATAGP3", + "GPP_H22", "n/a", "SSATAXPCIE4", "SSATAGP4", + "GPP_H23", "n/a", "SSATAXPCIE5", "SSATAGP5", +}; + +static const struct gpio_group lewisburg_group_h = { + .display = "------- GPIO Group GPP_H -------", + .pad_count = ARRAY_SIZE(lewisburg_group_h_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_h_names, +}; + +static const char *const lewisburg_group_i_names[] = { + "GPP_I0", "n/a", "LAN_TDO", "n/a", + "GPP_I1", "n/a", "LAN_TCK", "n/a", + "GPP_I2", "n/a", "LAN_TMS", "n/a", + "GPP_I3", "n/a", "LAN_TDI", "n/a", + "GPP_I4", "n/a", "RESET_IN#", "n/a", + "GPP_I5", "n/a", "RESET_OUT#", "n/a", + "GPP_I6", "n/a", "RESET_DONE", "n/a", + "GPP_I7", "n/a", "LAN_TRST_IN", "n/a", + "GPP_I8", "n/a", "PCI_DIS", "n/a", + "GPP_I9", "n/a", "LAN_DIS", "n/a", + "GPP_I10", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group lewisburg_group_i = { + .display = "------- GPIO Group GPP_I -------", + .pad_count = ARRAY_SIZE(lewisburg_group_i_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_i_names, +}; + +static const char *const lewisburg_group_j_names[] = { + "GPP_J0", "LAN_LED_P0_0", "n/a", "n/a", + "GPP_J1", "LAN_LED_P0_1", "n/a", "n/a", + "GPP_J2", "LAN_LED_P1_0", "n/a", "n/a", + "GPP_J3", "LAN_LED_P1_1", "n/a", "n/a", + "GPP_J4", "LAN_LED_P2_0", "n/a", "n/a", + "GPP_J5", "LAN_LED_P2_1", "n/a", "n/a", + "GPP_J6", "LAN_LED_P3_0", "n/a", "n/a", + "GPP_J7", "LAN_LED_P3_1", "n/a", "n/a", + "GPP_J8", "LAN_I2C_SCL_MDC_P0", "n/a", "n/a", + "GPP_J9", "LAN_I2C_SDA_MDIO_P0", "n/a", "n/a", + "GPP_J10", "LAN_I2C_SCL_MDC_P1", "n/a", "n/a", + "GPP_J11", "LAN_I2C_SDA_MDIO_P1", "n/a", "n/a", + "GPP_J12", "LAN_I2C_SCL_MDC_P2", "n/a", "n/a", + "GPP_J13", "LAN_I2C_SDA_MDIO_P2", "n/a", "n/a", + "GPP_J14", "LAN_I2C_SCL_MDC_P3", "n/a", "n/a", + "GPP_J15", "LAN_I2C_SDA_MDIO_P3", "n/a", "n/a", + "GPP_J16", "LAN_SDP_P0_0", "n/a", "n/a", + "GPP_J17", "LAN_SDP_P0_1", "n/a", "n/a", + "GPP_J18", "LAN_SDP_P1_0", "n/a", "n/a", + "GPP_J19", "LAN_SDP_P1_1", "n/a", "n/a", + "GPP_J20", "LAN_SDP_P2_0", "n/a", "n/a", + "GPP_J21", "LAN_SDP_P2_1", "n/a", "n/a", + "GPP_J22", "LAN_SDP_P3_0", "n/a", "n/a", + "GPP_J23", "LAN_SDP_P3_1", "n/a", "n/a", +}; + +static const struct gpio_group lewisburg_group_j = { + .display = "------- GPIO Group GPP_J -------", + .pad_count = ARRAY_SIZE(lewisburg_group_j_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_j_names, +}; + +static const char *const lewisburg_group_k_names[] = { + "GPP_K0", "LAN_NCSI_CLK_IN", "n/a", "n/a", + "GPP_K1", "LAN_NCSI_TXD0", "n/a", "n/a", + "GPP_K2", "LAN_NCSI_TXD1", "n/a", "n/a", + "GPP_K3", "LAN_NCSI_TX_EN", "n/a", "n/a", + "GPP_K4", "LAN_NCSI_CRS_DV", "n/a", "n/a", + "GPP_K5", "LAN_NCSI_RXD0", "n/a", "n/a", + "GPP_K6", "LAN_NCSI_RXD1", "n/a", "n/a", + "GPP_K7", "RESERVED", "n/a", "n/a", + "GPP_K8", "LAN_NCSI_ARB_IN", "n/a", "n/a", + "GPP_K9", "LAN_NCSI_ARB_OUT", "n/a", "n/a", + "GPP_K10", "PE_RST#", "n/a", "n/a", +}; + +static const struct gpio_group lewisburg_group_k = { + .display = "------- GPIO Group GPP_K -------", + .pad_count = ARRAY_SIZE(lewisburg_group_k_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_k_names, +}; + +static const char *const lewisburg_group_l_names[] = { + "GPP_L2", "TESTCH0_D0", "n/a", "n/a", + "GPP_L3", "TESTCH0_D1", "n/a", "n/a", + "GPP_L4", "TESTCH0_D2", "n/a", "n/a", + "GPP_L5", "TESTCH0_D3", "n/a", "n/a", + "GPP_L6", "TESTCH0_D4", "n/a", "n/a", + "GPP_L7", "TESTCH0_D5", "n/a", "n/a", + "GPP_L8", "TESTCH0_D6", "n/a", "n/a", + "GPP_L9", "TESTCH0_D7", "n/a", "n/a", + "GPP_L10", "TESTCH0_CLK", "n/a", "n/a", + "GPP_L11", "TESTCH1_D0", "n/a", "n/a", + "GPP_L12", "TESTCH1_D1", "n/a", "n/a", + "GPP_L13", "TESTCH1_D2", "n/a", "n/a", + "GPP_L14", "TESTCH1_D3", "n/a", "n/a", + "GPP_L15", "TESTCH1_D4", "n/a", "n/a", + "GPP_L16", "TESTCH1_D5", "n/a", "n/a", + "GPP_L17", "TESTCH1_D6", "n/a", "n/a", + "GPP_L18", "TESTCH1_D7", "n/a", "n/a", + "GPP_L19", "TESTCH1_CLK", "n/a", "n/a", +}; + +static const struct gpio_group lewisburg_group_l = { + .display = "------- GPIO Group GPP_L -------", + .pad_count = ARRAY_SIZE(lewisburg_group_l_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_l_names, +}; + +static const char *const lewisburg_group_gpd_names[] = { + "GPD0", "POWER_DEBUG_N", "n/a", "n/a", + "GPD1", "ACPRESENT", "n/a", "n/a", + "GPD2", "GBE_WAKE#", "n/a", "n/a", + "GPD3", "PWRBTN#", "n/a", "n/a", + "GPD4", "SLP_S3#", "n/a", "n/a", + "GPD5", "SLP_S4#", "n/a", "n/a", + "GPD6", "SLP_A#", "n/a", "n/a", + "GPD7", "RESERVED", "n/a", "n/a", + "GPD8", "SUSCLK", "n/a", "n/a", + "GPD9", "RESERVED", "n/a", "n/a", + "GPD10", "SLP_S5#", "n/a", "n/a", + "GPD11", "GBEPHY", "n/a", "n/a", +}; + +static const struct gpio_group lewisburg_group_gpd = { + .display = "-------- GPIO Group GPD --------", + .pad_count = ARRAY_SIZE(lewisburg_group_gpd_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_gpd_names, +}; + +static const struct gpio_group *const lewisburg_community0_abf_groups[] = { + &lewisburg_group_a, + &lewisburg_group_b, + &lewisburg_group_f, +}; + +static const struct gpio_community lewisburg_community0_abf = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0xaf, + .group_count = ARRAY_SIZE(lewisburg_community0_abf_groups), + .groups = lewisburg_community0_abf_groups, +}; + +static const struct gpio_group *const lewisburg_community1_cde_groups[] = { + &lewisburg_group_c, + &lewisburg_group_d, + &lewisburg_group_e, +}; + +static const struct gpio_community lewisburg_community1_cde = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0xae, + .group_count = ARRAY_SIZE(lewisburg_community1_cde_groups), + .groups = lewisburg_community1_cde_groups, +}; + +static const struct gpio_group *const lewisburg_community2_gpd_groups[] = { + &lewisburg_group_gpd, +}; + +static const struct gpio_community lewisburg_community2_gpd = { + .name = "------- GPIO Community 2 -------", + .pcr_port_id = 0xad, + .group_count = ARRAY_SIZE(lewisburg_community2_gpd_groups), + .groups = lewisburg_community2_gpd_groups, +}; + +static const struct gpio_group *const lewisburg_community3_i_groups[] = { + &lewisburg_group_i, +}; + +static const struct gpio_community lewisburg_community3_i = { + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0xac, + .group_count = ARRAY_SIZE(lewisburg_community3_i_groups), + .groups = lewisburg_community3_i_groups, +}; + +static const struct gpio_group *const lewisburg_community4_jk_groups[] = { + &lewisburg_group_j, + &lewisburg_group_k, +}; + +static const struct gpio_community lewisburg_community4_jk = { + .name = "------- GPIO Community 4 -------", + .pcr_port_id = 0xab, + .group_count = ARRAY_SIZE(lewisburg_community4_jk_groups), + .groups = lewisburg_community4_jk_groups, +}; + +static const struct gpio_group *const lewisburg_community5_ghl_groups[] = { + &lewisburg_group_g, + &lewisburg_group_h, + &lewisburg_group_l, +}; + +static const struct gpio_community lewisburg_community5_ghl = { + .name = "------- GPIO Community 5 -------", + .pcr_port_id = 0x11, + .group_count = ARRAY_SIZE(lewisburg_community5_ghl_groups), + .groups = lewisburg_community5_ghl_groups, +}; + +static const struct gpio_community *const lewisburg_communities[] = { + &lewisburg_community0_abf, + &lewisburg_community1_cde, + &lewisburg_community2_gpd, + &lewisburg_community3_i, + &lewisburg_community4_jk, + &lewisburg_community5_ghl, +}; + static const char *const denverton_group_north_all_names[] = { "NORTH_ALL_GBE0_SDP0", "NORTH_ALL_GBE1_SDP0", @@ -1801,6 +2257,23 @@ void print_gpio_groups(struct pci_dev *const sb) communities = sunrise_lp_communities; pcr_init(sb); break; + case PCI_DEVICE_ID_INTEL_C621: + case PCI_DEVICE_ID_INTEL_C622: + case PCI_DEVICE_ID_INTEL_C624: + case PCI_DEVICE_ID_INTEL_C625: + case PCI_DEVICE_ID_INTEL_C626: + case PCI_DEVICE_ID_INTEL_C627: + case PCI_DEVICE_ID_INTEL_C628: + case PCI_DEVICE_ID_INTEL_C629: + case PCI_DEVICE_ID_INTEL_C624_SUPER: + case PCI_DEVICE_ID_INTEL_C627_SUPER_1: + case PCI_DEVICE_ID_INTEL_C621_SUPER: + case PCI_DEVICE_ID_INTEL_C627_SUPER_2: + case PCI_DEVICE_ID_INTEL_C628_SUPER: + community_count = ARRAY_SIZE(lewisburg_communities); + communities = lewisburg_communities; + pcr_init(sb); + break; case PCI_DEVICE_ID_INTEL_DNV_LPC: community_count = ARRAY_SIZE(denverton_communities); communities = denverton_communities; diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 76b1abed9c..db80bd26b1 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -128,6 +128,8 @@ static const struct { "6th generation (Skylake-S family) Core Processor (Desktop)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2, "6th generation (Skylake-S family) Core Processor (Desktop)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E, + "6th generation (Skylake family) Core Processor Xeon E (Server)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL, "Bay Trail" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U, "7th generation (Kaby Lake family) Core Processor (Mobile)" }, @@ -260,6 +262,19 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM175, "HM175" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM175, "QM175" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CM238, "CM238" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C621, "C621" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C622, "C622" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C624, "C624" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C625, "C625" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C626, "C626" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C627, "C627" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C628, "C628" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C629, "C629" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C624_SUPER, "C624 Super SKU" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C627_SUPER_1, "C627 Super SKU" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C621_SUPER, "C621 Super SKU" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C627_SUPER_2, "C627 Super SKU" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C628_SUPER, "C628 Super SKU" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H310, "H310" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H370, "H370" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z390, "Z390" }, @@ -358,6 +373,8 @@ static const struct { "Intel(R) HD 4000 Graphics" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_4000_2, "Intel(R) HD 4000 Graphics" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_4400, + "Intel(R) HD 4400 Graphics" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_4600, "Intel(R) HD 4600 Graphics" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_4600_1, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 483c93099e..fc6dc4b83f 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -170,6 +170,20 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_QM175 0xa153 #define PCI_DEVICE_ID_INTEL_CM238 0xa154 +#define PCI_DEVICE_ID_INTEL_C621 0xa1c1 +#define PCI_DEVICE_ID_INTEL_C622 0xa1c2 +#define PCI_DEVICE_ID_INTEL_C624 0xa1c3 +#define PCI_DEVICE_ID_INTEL_C625 0xa1c4 +#define PCI_DEVICE_ID_INTEL_C626 0xa1c5 +#define PCI_DEVICE_ID_INTEL_C627 0xa1c6 +#define PCI_DEVICE_ID_INTEL_C628 0xa1c7 +#define PCI_DEVICE_ID_INTEL_C629 0xa1ca +#define PCI_DEVICE_ID_INTEL_C624_SUPER 0xa242 +#define PCI_DEVICE_ID_INTEL_C627_SUPER_1 0xa243 +#define PCI_DEVICE_ID_INTEL_C621_SUPER 0xa244 +#define PCI_DEVICE_ID_INTEL_C627_SUPER_2 0xa245 +#define PCI_DEVICE_ID_INTEL_C628_SUPER 0xa246 + #define PCI_DEVICE_ID_INTEL_H310 0xa303 #define PCI_DEVICE_ID_INTEL_H370 0xa304 #define PCI_DEVICE_ID_INTEL_Z390 0xa305 @@ -272,6 +286,7 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M 0x1910 /* Skylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST 0x1918 /* Skylake (Workstation) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D 0x191f /* Skylake (Desktop) */ +#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E 0x2020 /* Skylake-E (Server) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U 0x5904 /* Kabylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y 0x590C /* Kabylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q 0x5914 /* Kabylake (Mobile) */ @@ -316,6 +331,7 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_HD_4000_2 0x016A #define PCI_DEVICE_ID_INTEL_HD_4600 0x0412 #define PCI_DEVICE_ID_INTEL_HD_4600_1 0x0416 +#define PCI_DEVICE_ID_INTEL_HD_4400 0x041E #define PCI_DEVICE_ID_INTEL_HD_5000 0x0422 #define PCI_DEVICE_ID_INTEL_HD_5000_1 0x0426 #define PCI_DEVICE_ID_INTEL_HD_5000_2 0x042A diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 222ac8afb0..e80f1ba15d 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -221,6 +221,7 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 33644ab9db..b7c72cb140 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -267,6 +267,7 @@ int print_epbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: @@ -393,6 +394,7 @@ int print_dmibar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: @@ -503,6 +505,7 @@ int print_pciexbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index c969620fa0..ef6bb39d16 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -103,6 +103,19 @@ void pcr_init(struct pci_dev *const sb) case PCI_DEVICE_ID_INTEL_HM175: case PCI_DEVICE_ID_INTEL_QM175: case PCI_DEVICE_ID_INTEL_CM238: + case PCI_DEVICE_ID_INTEL_C621: + case PCI_DEVICE_ID_INTEL_C622: + case PCI_DEVICE_ID_INTEL_C624: + case PCI_DEVICE_ID_INTEL_C625: + case PCI_DEVICE_ID_INTEL_C626: + case PCI_DEVICE_ID_INTEL_C627: + case PCI_DEVICE_ID_INTEL_C628: + case PCI_DEVICE_ID_INTEL_C629: + case PCI_DEVICE_ID_INTEL_C624_SUPER: + case PCI_DEVICE_ID_INTEL_C627_SUPER_1: + case PCI_DEVICE_ID_INTEL_C621_SUPER: + case PCI_DEVICE_ID_INTEL_C627_SUPER_2: + case PCI_DEVICE_ID_INTEL_C628_SUPER: case PCI_DEVICE_ID_INTEL_DNV_LPC: p2sb = pci_get_dev(sb->access, 0, 0, 0x1f, 1); break; diff --git a/util/kconfig/confdata.c b/util/kconfig/confdata.c index fc4a07a933..fc76e0e880 100644 --- a/util/kconfig/confdata.c +++ b/util/kconfig/confdata.c @@ -764,12 +764,22 @@ next_menu: return 0; } + +int conf_mktemp(const char *path, char *tmpfile) +{ + if (snprintf(tmpfile, PATH_MAX, "%s.tmp.XXXXXX", path) >= PATH_MAX) { + errno = EOVERFLOW; + return -1; + } + return mkstemp(tmpfile); +} + int conf_write(const char *name) { FILE *out; struct symbol *sym; struct menu *menu; - const char *basename; + const char *basename = NULL; const char *str; char dirname[PATH_MAX+1], tmpname[PATH_MAX+1], newname[PATH_MAX+1]; char *env; @@ -777,13 +787,20 @@ int conf_write(const char *name) dirname[0] = 0; if (name && name[0]) { struct stat st; - char *slash; if (!stat(name, &st) && S_ISDIR(st.st_mode)) { strcpy(dirname, name); strcat(dirname, "/"); basename = conf_get_configname(); - } else if ((slash = strrchr(name, '/'))) { + } + } else { + name = conf_get_configname(); + } + + if (!basename) { + char *slash = strrchr(name, '/'); + + if (slash) { int size = slash - name + 1; memcpy(dirname, name, size); dirname[size] = 0; @@ -791,15 +808,15 @@ int conf_write(const char *name) basename = slash + 1; else basename = conf_get_configname(); - } else + } else { basename = name; - } else - basename = conf_get_configname(); + } + } sprintf(newname, "%s%s", dirname, basename); env = getenv("KCONFIG_OVERWRITECONFIG"); if (!env || !*env) { - sprintf(tmpname, "%s.tmpconfig.%d", dirname, (int)getpid()); + conf_mktemp(newname, tmpname); out = fopen(tmpname, "w"); } else { *tmpname = 0; @@ -984,7 +1001,6 @@ out: int conf_write_autoconf(void) { struct symbol *sym; - const char *name; FILE *out, *tristate, *out_h; int i; int print_negatives; @@ -1001,49 +1017,41 @@ int conf_write_autoconf(void) if (conf_split_config()) return 1; - char *tmpconfig_name = malloc(PATH_MAX); - if (getenv("COREBOOT_BUILD_DIR")) { - sprintf(tmpconfig_name, "%s/.tmpconfig.XXXXXX", - getenv("COREBOOT_BUILD_DIR")); - } else { - tmpconfig_name = strdup(".tmpconfig.XXXXXX"); - } - if ((i = mkstemp(tmpconfig_name)) == -1) - return 1; + char tmpconfig_name[PATH_MAX]; + const char *config_name = conf_get_autoconfig_name(); + + i = conf_mktemp(config_name, tmpconfig_name); + if (i == -1) + goto error_auto_conf_cmd_tmp; out = fdopen(i, "w"); if (!out) - return 1; + goto error_auto_conf_cmd_open; + + char tmpconfig_triname[PATH_MAX]; + const char *config_triname = getenv("KCONFIG_TRISTATE"); + if (!config_triname) + config_triname = "include/config/tristate.conf"; + + i = conf_mktemp(config_triname, tmpconfig_triname); + if (i == -1) + goto error_tristate_tmp; - char *tmpconfig_triname = malloc(PATH_MAX); - if (getenv("COREBOOT_BUILD_DIR")) { - sprintf(tmpconfig_triname, "%s/.tmpconfig_tristate.XXXXXX", - getenv("COREBOOT_BUILD_DIR")); - } else { - tmpconfig_triname = strdup(".tmpconfig_tristate.XXXXXX"); - } - if ((i = mkstemp(tmpconfig_triname)) == -1) - return 1; tristate = fdopen(i, "w"); - if (!tristate) { - fclose(out); - return 1; - } + if (!tristate) + goto error_tristate_open; + + char tmpconfig_h[PATH_MAX]; + const char *config_h = getenv("KCONFIG_AUTOHEADER"); + if (!config_h) + config_h = "include/generated/autoconf.h"; + + i = conf_mktemp(config_h, tmpconfig_h); + if (i == -1) + goto error_auto_conf_h_tmp; - char *tmpconfig_h = malloc(PATH_MAX); - if (getenv("COREBOOT_BUILD_DIR")) { - sprintf(tmpconfig_h, "%s/.tmpconfig_tristate.XXXXXX", - getenv("COREBOOT_BUILD_DIR")); - } else { - tmpconfig_h = strdup(".tmpconfig_tristate.XXXXXX"); - } - if ((i = mkstemp(tmpconfig_h)) == -1) - return 1; out_h = fdopen(i, "w"); - if (!out_h) { - fclose(out); - fclose(tristate); - return 1; - } + if (!out_h) + goto error_auto_conf_h_open; conf_write_heading(out, &kconfig_printer_cb, NULL); @@ -1077,25 +1085,38 @@ int conf_write_autoconf(void) fclose(tristate); fclose(out_h); - name = getenv("KCONFIG_AUTOHEADER"); - if (!name) - name = "include/generated/autoconf.h"; - if (rename(tmpconfig_h, name)) + if (rename(tmpconfig_h, config_h)) return 1; - name = getenv("KCONFIG_TRISTATE"); - if (!name) - name = "include/config/tristate.conf"; - if (rename(tmpconfig_triname, name)) + + if (rename(tmpconfig_triname, config_triname)) return 1; - name = conf_get_autoconfig_name(); + /* * This must be the last step, kbuild has a dependency on auto.conf * and this marks the successful completion of the previous steps. */ - if (rename(tmpconfig_name, name)) + if (rename(tmpconfig_name, config_name)) return 1; return 0; + +error_auto_conf_h_open: + unlink(tmpconfig_h); + +error_auto_conf_h_tmp: + fclose(tristate); + +error_tristate_open: + unlink(tmpconfig_triname); + +error_tristate_tmp: + fclose(out); + +error_auto_conf_cmd_open: + unlink(tmpconfig_name); + +error_auto_conf_cmd_tmp: + return 1; } static int sym_change_count; diff --git a/util/lint/check-style b/util/lint/check-style index 2237ed6295..f72d7b42c5 100755 --- a/util/lint/check-style +++ b/util/lint/check-style @@ -137,7 +137,10 @@ cat "$patch" printf "\nYou can apply these changes with:\n git apply $patch\n" printf "(may need to be called from the root directory of your repository)\n" -printf "Aborting commit. Apply changes and commit again or skip checking with" -printf " --no-verify (not recommended).\n" -exit 1 +# FIXME: clang-format is currently unusable, so don't abort the commit. +# printf "Aborting commit. Apply changes and commit again or skip checking with" +# printf " --no-verify (not recommended).\n" +# exit 1 + +exit 0 diff --git a/util/lint/lint-stable-022-clang-format b/util/lint/lint-stable-022-clang-format index bd662e472f..48f51a8e77 100755 --- a/util/lint/lint-stable-022-clang-format +++ b/util/lint/lint-stable-022-clang-format @@ -33,6 +33,6 @@ if [ $(clang-format $files_to_check | wc -l) -gt 0 ]; then if [ "$(git diff --no-prefix HEAD~..HEAD -- $files_to_check | clang-format-diff)" != "" ]; then echo "Coding style mismatch. The following patch fixes it:" git diff --no-prefix HEAD~..HEAD -- $files_to_check | clang-format-diff - exit 1 + exit 0 fi fi diff --git a/util/mainboard/google/hatch/create_coreboot_variant.sh b/util/mainboard/google/hatch/create_coreboot_variant.sh new file mode 100755 index 0000000000..d4256a6ccc --- /dev/null +++ b/util/mainboard/google/hatch/create_coreboot_variant.sh @@ -0,0 +1,79 @@ +#!/bin/bash +# +# This file is part of the coreboot project. +# +# Copyright 2019 Google LLC. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +if [[ "$#" -ne 1 ]]; then + echo "Usage: $0 variant_name" + echo "e.g. $0 kohaku" + echo "Adds a new variant of Hatch to Kconfig and Kconfig.name, creates the" + echo "skeleton files for acpi, ec, and gpio, copies the makefile for" + echo "SPD sources, and sets up a basic overridetree" + exit 1 +fi + +# Note that this script is specific to Hatch, and so it does not allow +# you to specify the baseboard as one of the cmdline arguments. +# +# This is the name of the base board that we're cloning to make the variant. +base="hatch" +# This is the name of the variant that is being cloned +# ${var,,} converts to all lowercase +variant="${1,,}" + +# This script and the templates live in util/mainboard/google/hatch +# We need to create files in src/mainboard/google/hatch +pushd "${BASH_SOURCE%/*}" || exit +SRC=$(pwd) +popd || exit +pushd "${SRC}/../../../../src/mainboard/google/${base}" || { + echo "The baseboard directory for ${base} does not exist."; + exit; } + +# Make sure the variant doesn't already exist +if [[ -e variants/${variant} ]]; then + echo "variants/${variant} already exists." + echo "Have you already created this variant?" + popd || exit + exit 2 +fi + +# Start a branch. Use YMD timestamp to avoid collisions. +DATE=$(date +%Y%m%d) +git checkout -b "create_${variant}_${DATE}" + +# Copy the template tree to the target +mkdir -p "variants/${variant}/" +cp -pr "${SRC}/template/." "variants/${variant}/" +git add "variants/${variant}/" + +# Now add the new variant to Kconfig and Kconfig.name +# These files are in the current directory, e.g. src/mainboard/google/hatch +"${SRC}/kconfig.py" --name "${variant}" + +mv Kconfig.new Kconfig +mv Kconfig.name.new Kconfig.name + +git add Kconfig Kconfig.name + +# Now commit the files +git commit -sm "${base}: Create ${variant} variant + +BUG=none +TEST=util/abuild/abuild -p none -t google/${base} -x -a +make sure the build includes GOOGLE_${variant^^}" + +popd || exit + +echo "Please check all the files (git show), make any changes you want," +echo "and then push to coreboot HEAD:refs/for/master" diff --git a/util/mainboard/google/hatch/kconfig.py b/util/mainboard/google/hatch/kconfig.py new file mode 100755 index 0000000000..ecc24eeb49 --- /dev/null +++ b/util/mainboard/google/hatch/kconfig.py @@ -0,0 +1,155 @@ +#!/usr/bin/python3 +"""Add a new variant to the Kconfig and Kconfig.name for the baseboard + +To start a new variant of an existing baseboard, we need to add +the variant into the Kconfig and Kconfig.name files for the +baseboard. In Kconfig, we have three sections that need additional +entries, GBB_HWID, MAINBOARD_PART_NUMBER, and VARIANT_DIR. + +In GBB_HWID, we need to add a HWID that includes a numeric suffix. +The numeric suffix is the CRC-32 of the all-caps ASCII name, +modulo 10000. +For example, if the board name is "Fizz", we calculate the CRC of +"FIZZ TEST", which is 0x598C492D. In decimal, the value is 1502365997, +modulo 10000 is 5997. So the HWID string is "FIZZ TEST 5997" +In the past, we have used an online CRC-32 calculator such as +https://www.lammertbies.nl/comm/info/crc-calculation.html, and then +used the calculator app to convert to decimal and take the last +4 digits. + +The MAINBOARD_PART_NUMBER and VARIANT_DIR are simpler, just using +various capitalizations of the variant name to create the strings. + +Kconfig.name adds an entire section for the new variant, and all +of these use various capitalizations of the variant name. The strings +in this section are SOC-specific, so we'll need versions for each +SOC that we support. + +Copyright 2019 Google LLC. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; version 2 of the License. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. +""" + +import argparse +import zlib + + +def main(): + parser = argparse.ArgumentParser( + description="Add strings to coreboot Kconfig for a new board variant") + parser.add_argument('--name', type=str, required=True, + help='Name of the board variant') + args = parser.parse_args() + + add_to_Kconfig(args.name) + add_to_Kconfig_name(args.name) + + +def get_gbb_hwid(variant_name): + """Create the GBB_HWID for a variant + + variant_name The name of the board variant, e.g. 'kohaku' + + Returns: + GBB_HWID string for the board variant, e.g. 'KOHAKU TEST 1953' + + Note that the case of the variant name does not matter; it gets + converted to all uppercase as part of this function.""" + hwid = variant_name + ' test' + upperhwid = hwid.upper() + suffix = zlib.crc32(upperhwid.encode('UTF-8')) % 10000 + gbb_hwid = upperhwid + ' ' + str(suffix).zfill(4) + return gbb_hwid + + +def add_to_Kconfig(variant_name): + """Add options for the variant to the Kconfig + + Open the Kconfig file and read it line-by-line. When we detect that we're + in one of the sections of interest, wait until we get a blank line + (signalling the end of that section), and then add our new line before + the blank line. The updated lines are written out to Kconfig.new in the + same directory as Kconfig. + + variant_name The name of the board variant, e.g. 'kohaku'""" + # These are the part of the strings that we'll add to the sections + BOARD = 'BOARD_GOOGLE_' + variant_name.upper() + gbb_hwid = get_gbb_hwid(variant_name) + lowercase = variant_name.lower() + capitalized = lowercase.capitalize() + + # These flags track whether we're in a section where we need to add an option + in_gbb_hwid = False + in_mainboard_part_number = False + in_variant_dir = False + + inputname = 'Kconfig' + outputname = 'Kconfig.new' + with open(outputname, 'w') as outfile: + with open(inputname, 'r') as infile: + for rawline in infile: + line = rawline.rstrip('\r\n') + + # Are we in one of the sections of interest? + if line == 'config GBB_HWID': + in_gbb_hwid = True + if line == 'config MAINBOARD_PART_NUMBER': + in_mainboard_part_number = True + if line == 'config VARIANT_DIR': + in_variant_dir = True + + # Are we at the end of a section, and if so, is it one of the + # sections of interest? + if line == '': + if in_gbb_hwid: + print('\tdefault "' + gbb_hwid + '" if ' + BOARD, file=outfile) + in_gbb_hwid = False + if in_mainboard_part_number: + print('\tdefault "' + capitalized + '" if ' + BOARD, file=outfile) + in_mainboard_part_number = False + if in_variant_dir: + print('\tdefault "' + lowercase + '" if ' + BOARD, file=outfile) + in_variant_dir = False + + print(line, file=outfile) + + +def add_to_Kconfig_name(variant_name): + """Add a config section for the variant to the Kconfig.name + + Kconfig.name is easier to modify than Kconfig; it only has a block at + the end with the new variant's details. + + config BOARD_GOOGLE_${VARIANT} + + variant_name The name of the board variant, e.g. 'kohaku'""" + # Board name for the config section + uppercase = variant_name.upper() + BOARD = 'BOARD_GOOGLE_' + uppercase + capitalized = variant_name.lower().capitalize() + + inputname = 'Kconfig.name' + outputname = 'Kconfig.name.new' + with open(outputname, 'w') as outfile: + with open(inputname, 'r') as infile: + # Copy all input lines to output + for rawline in infile: + line = rawline.rstrip('\r\n') + print(line, file=outfile) + + # Now add the new section + print('\nconfig ' + BOARD, file=outfile) + print('\tbool "-> ' + capitalized + '"', file=outfile) + print('\tselect BOARD_GOOGLE_BASEBOARD_HATCH', file=outfile) + print('\tselect BOARD_ROMSIZE_KB_16384', file=outfile) + + +if __name__ == '__main__': + main() diff --git a/util/mainboard/google/hatch/template/Makefile.inc b/util/mainboard/google/hatch/template/Makefile.inc new file mode 100644 index 0000000000..38cf728d8f --- /dev/null +++ b/util/mainboard/google/hatch/template/Makefile.inc @@ -0,0 +1,13 @@ +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = diff --git a/util/mainboard/google/hatch/template/include/variant/acpi/dptf.asl b/util/mainboard/google/hatch/template/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..496334daab --- /dev/null +++ b/util/mainboard/google/hatch/template/include/variant/acpi/dptf.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/util/mainboard/google/hatch/template/include/variant/ec.h b/util/mainboard/google/hatch/template/include/variant/ec.h new file mode 100644 index 0000000000..25269627bd --- /dev/null +++ b/util/mainboard/google/hatch/template/include/variant/ec.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include + +#endif diff --git a/util/mainboard/google/hatch/template/include/variant/gpio.h b/util/mainboard/google/hatch/template/include/variant/gpio.h new file mode 100644 index 0000000000..1322233ad0 --- /dev/null +++ b/util/mainboard/google/hatch/template/include/variant/gpio.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/util/mainboard/google/hatch/template/overridetree.cb b/util/mainboard/google/hatch/template/overridetree.cb new file mode 100644 index 0000000000..abbcaaa08c --- /dev/null +++ b/util/mainboard/google/hatch/template/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/cannonlake + + device domain 0 on + end + +end diff --git a/util/nvidia/cbootimage b/util/nvidia/cbootimage index 64045f993c..65a6d94dd5 160000 --- a/util/nvidia/cbootimage +++ b/util/nvidia/cbootimage @@ -1 +1 @@ -Subproject commit 64045f993c2cd8989838aeaad3d22107d96d5596 +Subproject commit 65a6d94dd5f442578551e0a81ecbe5235e673fd4 diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 5e3a1d405e..6b421ec3d6 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -883,6 +883,18 @@ static void pass1(FILE *fil, struct device *ptr, struct device *next) emit_dev_links(fil, ptr); } +static void expose_device_names(FILE *fil, struct device *ptr, struct device *next) +{ + /* Only devices on root bus here. */ + if (ptr->bustype == PCI && ptr->parent->dev->bustype == DOMAIN) + fprintf(fil, "DEVTREE_CONST struct device *DEVTREE_CONST __pci_0_%02x_%d = &%s;\n", + ptr->path_a, ptr->path_b, ptr->name); + + if (ptr->bustype == PNP) + fprintf(fil, "DEVTREE_CONST struct device *DEVTREE_CONST __pnp_%04x_%02x = &%s;\n", + ptr->path_a, ptr->path_b, ptr->name); +} + static void add_siblings_to_queue(struct queue_entry **bfs_q_head, struct device *d) { @@ -1385,6 +1397,10 @@ int main(int argc, char **argv) fprintf(autogen, "\n/* pass 1 */\n"); walk_device_tree(autogen, &base_root_dev, pass1); + /* Expose static devicenames to global namespace. */ + fprintf(autogen, "\n/* expose_device_names */\n"); + walk_device_tree(autogen, &base_root_dev, expose_device_names); + fclose(autogen); return 0; diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c index 8f1e2ea019..2e21e80f4a 100644 --- a/util/superiotool/ite.c +++ b/util/superiotool/ite.c @@ -1064,6 +1064,71 @@ static const struct superio_registers reg_table[] = { {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT}, {0x00,0x02,0xf8,0x03,0x00,0x50,0x00,EOT}}, {EOT}}}, + {0x8987, "IT8987", { /* global registers 0x24, 0x27, 0x28, 0x29, 0x2a, 0x2b are reserved */ + {NOLDN, "Chip ID", + {0x20,0x21, EOT}, + {0x89,0x87, EOT}}, + {NOLDN, "Chip Version", + {0x22,EOT}, + {0x03,EOT}}, + {NOLDN, "Super I/O Control Register (SIOCTRL)", + {0x23,EOT}, + {0x01,EOT}}, + {NOLDN, "Super I/O Configuration Register (SIOIRQ)", + {0x25,EOT}, + {0x00,EOT}}, + {NOLDN, "Super I/O General Purpose Register (SIOGP)", + {0x26,EOT}, + {0x00,EOT}}, + {NOLDN, "Super I/O Power Mode Register (SIOPWR)", + {0x2d,EOT}, + {0x00,EOT}}, + {NOLDN, "Depth 2 I/O Address (D2ADR)", + {0x2e,EOT}, + {0x00,EOT}}, + {NOLDN, "Depth 2 I/O Data (D2DAT)", + {0x2f,EOT}, + {0x00,EOT}}, + {0x04, "System Wake-Up Control (SWUC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x01,EOT}}, + {0x05, "KBC/Mouse Interface", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x0c,0x01,EOT}}, + {0x06, "KBC/Keyboard Interface", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x60,0x00,0x64,0x01,0x01,EOT}}, + {0xa, "Consumer IR", + {0x30,0x60,0x61,0x70,0x71,EOT}, + {0x00,0x03,0x10,0x00,0x02,EOT}}, + {0x0f, "Shared Memory/Flash Interface (SMFI)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf4,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,NANA,EOT}}, + {0x10, "Real Time Clock (RTC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,0xf1,0xf2,EOT}, + {0x00,0x00,0x70,0x00,0x72,0x08,0x00,0x00,0x49,0x4a,EOT}}, + {0x11, "Power Management I/F Channel 1 (PMC1)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x62,0x00,0x66,0x01,0x01,EOT}}, + {0x12, "Power Management I/F Channel 2 (PMC2)", + {0x30,0x60,0x61,0x62,0x63,0x64,0x65,0x70,0x71,0xf0,EOT}, + {0x00,0x00,0x68,0x00,0x6c,0x00,0x00,0x01,0x01,NANA,EOT}}, + {0x13, "Serial Peripheral Interface (SSPI)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x03,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x14, "Platform Environment Control Interface (PECI)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x17, "Power Management I/F Channel 3 (PMC3)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x62,0x00,0x66,0x01,0x01,EOT}}, + {0x18, "Power Management I/F Channel 4 (PMC4)", + {0x30,0x60,0x61,0x62,0x63,0x64,0x65,0x70,0x71,0xf0,EOT}, + {0x00,0x00,0x68,0x00,0x6c,0x00,0x00,0x01,0x01,NANA,EOT}}, + {0x19, "Power Management I/F Channel 5 (PMC5)", + {0x30,0x60,0x61,0x62,0x63,0x64,0x65,0x70,0x71,0xf0,EOT}, + {0x00,0x00,0x68,0x00,0x6c,0x00,0x00,0x01,0x01,NANA,EOT}}, + {EOT}}}, {EOT} }; @@ -1280,6 +1345,68 @@ static const struct superio_registers bram_table[] = { {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, {EOT}}}, +{0x8987, "IT8987", { + {NOLDN, NULL, + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, + 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + 0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27, + 0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37, + 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x40,0x41,0x42,0x43,0x44,0x45,0x46,0x47, + 0x48,0x49,0x4a,0x4b,0x4c,0x4d,0x4e,0x4f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57, + 0x58,0x59,0x5a,0x5b,0x5c,0x5d,0x5e,0x5f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x60,0x61,0x62,0x63,0x64,0x65,0x66,0x67, + 0x68,0x69,0x6a,0x6b,0x6c,0x6d,0x6e,0x6f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x70,0x71,0x72,0x73,0x74,0x75,0x76,0x77, + 0x78,0x79,0x7a,0x7b,0x7c,0x7d,0x7e,0x7f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, + 0x88,0x89,0x8a,0x8b,0x8c,0x8d,0x8e,0x8f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97, + 0x98,0x99,0x9a,0x9b,0x9c,0x9d,0x9e,0x9f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0xa0,0xa1,0xa2,0xa3,0xa4,0xa5,0xa6,0xa7, + 0xa8,0xa9,0xaa,0xab,0xac,0xad,0xae,0xaf,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0xb0,0xb1,0xb2,0xb3,0xb4,0xb5,0xb6,0xb7, + 0xb8,0xb9,0xba,0xbb,0xbc,0xbd,0xbe,0xbf,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {EOT}}}, {EOT} }; @@ -1351,6 +1478,14 @@ static void enter_conf_mode_ite_it8228e(uint16_t port) OUTB((port == 0x2e) ? 0x55 : 0xaa, port); } +static void enter_conf_mode_ite_it8987e(uint16_t port) +{ + OUTB(0x89, port); + OUTB(0x87, port); + OUTB(0x55, port); + OUTB((port == 0x2e) ? 0x55 : 0xaa, port); +} + static void exit_conf_mode_ite(uint16_t port) { regwrite(port, 0x02, 0x02); @@ -1444,6 +1579,12 @@ void probe_idregs_ite(uint16_t port) if (chip_found_at_port) return; + enter_conf_mode_ite_it8987e(port); + probe_idregs_ite_helper("(init=it8987e) ", port); + exit_conf_mode_ite(port); + if (chip_found_at_port) + return; + enter_conf_mode_winbond_fintek_ite_8787(port); probe_idregs_ite_helper("(init=0x87,0x87) ", port); exit_conf_mode_winbond_fintek_ite_8787(port); diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc index d84c5a4f9b..2028c84bd3 100644 --- a/util/testing/Makefile.inc +++ b/util/testing/Makefile.inc @@ -80,16 +80,19 @@ CPUS?=4 lint lint-stable lint-extended: util/lint/lint $@ -ABUILD_OPTIONS=-B -J -c $(CPUS) -z -p $(JENKINS_PAYLOAD) +ABUILD_OPTIONS=-B -J -c $(CPUS) -Z -p $(JENKINS_PAYLOAD) ABUILD_OPTIONS+=$(if $(V),-v,) ABUILD_OPTIONS+=$(if $(JENKINS_NOCCACHE),,-y) ABUILD_OPTIONS+=$(JENKINS_ABUILD_OPT) +COREBOOT_BUILD_DIR?=coreboot-builds + what-jenkins-does: + rm -rf $(COREBOOT_BUILD_DIR)/chromeos $(COREBOOT_BUILD_DIR)/default util/lint/lint lint-stable --junit util/lint/lint lint-extended --junit - util/abuild/abuild $(ABUILD_OPTIONS) -x -X $(top)/abuild-chromeos.xml - util/abuild/abuild $(ABUILD_OPTIONS) + util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/chromeos $(ABUILD_OPTIONS) -x -X $(top)/abuild-chromeos.xml + util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/default $(ABUILD_OPTIONS) $(foreach tool, $(TOOLLIST), $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR="util/$(tool)" BLD="$(tool)" MFLAGS= MAKEFLAGS= MAKETARGET= junit.xml; ) unset COREBOOT_BUILD_DIR;$(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=payloads/nvramcui BLD=nvramcui MFLAGS= MAKEFLAGS= MAKETARGET=all junit.xml unset COREBOOT_BUILD_DIR;$(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=payloads/coreinfo BLD=coreinfo MFLAGS= MAKEFLAGS= MAKETARGET=defaultbuild junit.xml