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cpu/intel/model_206ax: Program Ivy Bridge defaults for MSR_PKGC_IRTL

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Ivy Bridge has lower latencies than Sandy Bridge has. Update MSRs
MSR_PKGC_IRTL with values from BWG.

Test: Lenovo X220 still boots.

Change-Id: Ib307e3b191ba68e016cc348f82e2dccf1dc9ae16
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78609
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Patrick Rudolph 2023-10-20 14:41:27 +02:00 committed by Felix Held
parent 93791db23e
commit 57e36a3320
1 changed files with 12 additions and 3 deletions
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15
src/cpu/intel/model_206ax/model_206ax_init.c
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@ -190,17 +190,26 @@ static void configure_c_states(struct device *dev)
/* C3 Interrupt Response Time Limit */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
if (IS_IVY_CPU(cpu_get_cpuid()))
msr.lo = IRTL_VALID | IRTL_1024_NS | 0x3b;
else
msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
wrmsr(MSR_PKGC3_IRTL, msr);
/* C6 Interrupt Response Time Limit */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
if (IS_IVY_CPU(cpu_get_cpuid()))
msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
else
msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
wrmsr(MSR_PKGC6_IRTL, msr);
/* C7 Interrupt Response Time Limit */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
if (IS_IVY_CPU(cpu_get_cpuid()))
msr.lo = IRTL_VALID | IRTL_1024_NS | 0x57;
else
msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
wrmsr(MSR_PKGC7_IRTL, msr);
/* Primary Plane Current Limit (Icc) */