From 5807b15bc29e40ea8f315b01d2b462e27459d573 Mon Sep 17 00:00:00 2001
From: Tim Crawford <tcrawford@system76.com>
Date: Tue, 21 Sep 2021 23:23:14 -0600
Subject: [PATCH] soc/intel/tigerlake: Add values for GMA registers

Change-Id: Id5dbf50c501e5fdd64a194d064198c776ab3d897
Signed-off-by: Tim Crawford <tcrawford@system76.com>
---
 src/soc/intel/tigerlake/Kconfig | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 699433217c..b80ac040fb 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -258,6 +258,18 @@ config EARLY_TCSS_DISPLAY
 	help
 	  Enable displays to be detected over Type-C ports during boot.
 
+config INTEL_GMA_BCLV_OFFSET
+	default 0xc8258
+
+config INTEL_GMA_BCLV_WIDTH
+	default 32
+
+config INTEL_GMA_BCLM_OFFSET
+	default 0xc8254
+
+config INTEL_GMA_BCLM_WIDTH
+	default 32
+
 config DISABLE_ME
 	bool "Disable the IME by setting the HAP bit at run-time"
 	# XXX: Prevents CPU from reaching C10