From 581081092ecd2e677b0466db0a6d709c0e175a34 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Tue, 27 Oct 2020 08:36:48 -0600 Subject: [PATCH] Update galp5 power limits Change-Id: Ic9b22570cc2e61b5489f7bbdb58e7920a4507b7f --- src/mainboard/system76/galp5/devicetree.cb | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/system76/galp5/devicetree.cb b/src/mainboard/system76/galp5/devicetree.cb index 8a4597a485..2cf5cbbdd2 100644 --- a/src/mainboard/system76/galp5/devicetree.cb +++ b/src/mainboard/system76/galp5/devicetree.cb @@ -23,13 +23,13 @@ chip soc/intel/tigerlake # Power limits register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ // /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw - .tdp_pl1_override = 15, + .tdp_pl1_override = 28, // /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw .tdp_pl2_override = 60, }" register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ // /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw - .tdp_pl1_override = 15, + .tdp_pl1_override = 28, // /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw .tdp_pl2_override = 60, }" @@ -72,7 +72,7 @@ chip soc/intel/tigerlake # System Agent dynamic frequency support register "SaGv" = "SaGv_Enabled" - #TODO: TCSS USB3 + # TCSS USB3 register "TcssXhciEn" = "1" # FSP Silicon (soc/intel/tigerlake/fsp_params.c) @@ -177,7 +177,7 @@ chip soc/intel/tigerlake register "gfx" = "GMA_STATIC_DISPLAYS(0)" # PMC (soc/intel/tigerlake/pmc.c) - # TODO: Disable deep Sx states + # Disable deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" register "deep_s5_enable_ac" = "0"