Revert "Remove FSP Rangeley SOC and mohonpeak board support"
This chip is still being used and should not have been deleted. It's
a current intel chip, and doesn't even require an ME binary.
This reverts commit 959478a763.
Change-Id: I78594871f87af6e882a245077b59727e15f8021a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11860
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Martin Roth
478
src/southbridge/intel/fsp_rangeley/lpc.c
Normal file
478
src/southbridge/intel/fsp_rangeley/lpc.c
Normal file
@@ -0,0 +1,478 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
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||||
*
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||||
* Copyright (C) 2008-2009 coresystems GmbH
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||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
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||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
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||||
|
||||
#include <console/console.h>
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||||
#include <device/device.h>
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||||
#include <device/pci.h>
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#include <device/pci_ids.h>
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||||
#include <pc80/mc146818rtc.h>
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#include <pc80/isa-dma.h>
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#include <pc80/i8259.h>
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||||
#include <arch/io.h>
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#include <arch/ioapic.h>
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#include <arch/acpi.h>
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#include <cpu/cpu.h>
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#include <elog.h>
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||||
#include <string.h>
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#include <cbmem.h>
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#include <arch/acpi.h>
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||||
#include <arch/acpigen.h>
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#include "soc.h"
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||||
#include "irq.h"
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||||
#include "nvs.h"
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||||
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#define NMI_OFF 0
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||||
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#define ENABLE_ACPI_MODE_IN_COREBOOT 0
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#define TEST_SMM_FLASH_LOCKDOWN 0
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typedef struct southbridge_intel_fsp_rangeley_config config_t;
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static void soc_enable_apic(struct device *dev)
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{
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int i;
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u32 reg32;
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volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
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volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
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u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0x0f);
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||||
/*
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* Enable ACPI I/O and power management.
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* Set SCI IRQ to IRQ9
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*/
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write32(ilb_base + ILB_OIC, 0x100); /* AEN */
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reg32 = read32(ilb_base + ILB_OIC); /* Read back per BWG */
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write32(ilb_base + ILB_ACTL, 0); /* ACTL bit 2:0 SCIS IRQ9 */
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*ioapic_index = 0;
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*ioapic_data = (1 << 25);
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/* Affirm full set of redirection table entries ("write once") */
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*ioapic_index = 1;
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reg32 = *ioapic_data;
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*ioapic_index = 1;
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*ioapic_data = reg32;
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*ioapic_index = 0;
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reg32 = *ioapic_data;
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printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
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if (reg32 != (1 << 25))
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die("APIC Error\n");
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printk(BIOS_SPEW, "Dumping IOAPIC registers\n");
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for (i=0; i<3; i++) {
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*ioapic_index = i;
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printk(BIOS_SPEW, " reg 0x%04x:", i);
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reg32 = *ioapic_data;
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printk(BIOS_SPEW, " 0x%08x\n", reg32);
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}
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*ioapic_index = 3; /* Select Boot Configuration register. */
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*ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
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}
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static void soc_enable_serial_irqs(struct device *dev)
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{
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||||
u8 *ibase;
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ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF);
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||||
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||||
/* Set packet length and toggle silent mode bit for one frame. */
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write8(ibase + ILB_SERIRQ_CNTL, (1 << 7));
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#if !CONFIG_SERIRQ_CONTINUOUS_MODE
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write8(ibase + ILB_SERIRQ_CNTL, 0);
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#endif
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||||
}
|
||||
|
||||
/*
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||||
* Write PCI config space IRQ assignments. PCI devices have the INT_LINE
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||||
* (0x3C) and INT_PIN (0x3D) registers which report interrupt routing
|
||||
* information to operating systems and drivers. The INT_PIN register is
|
||||
* generally read only and reports which interrupt pin A - D it uses. The
|
||||
* INT_LINE register is configurable and reports which IRQ (generally the
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||||
* PIC IRQs 1 - 15) it will use. This needs to take interrupt pin swizzling
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||||
* on devices that are downstream on a PCI bridge into account.
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||||
*
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* This function will loop through all enabled PCI devices and program the
|
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* INT_LINE register with the correct PIC IRQ number for the INT_PIN that it
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* uses. It then configures each interrupt in the pic to be level triggered.
|
||||
*/
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||||
static void write_pci_config_irqs(void)
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||||
{
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||||
device_t irq_dev;
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device_t targ_dev;
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||||
uint8_t int_line = 0;
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uint8_t original_int_pin = 0;
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uint8_t new_int_pin = 0;
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uint16_t current_bdf = 0;
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uint16_t parent_bdf = 0;
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uint8_t pirq = 0;
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||||
uint8_t device_num = 0;
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const struct rangeley_irq_route *ir = &global_rangeley_irq_route;
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||||
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||||
if (ir == NULL) {
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printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because"
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" 'global_rangeley_irq_route' structure does not exist\n");
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return;
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}
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||||
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/*
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* Loop through all enabled devices and program their
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* INT_LINE, INT_PIN registers from values taken from
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* the Interrupt Route registers in the ILB
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*/
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printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n");
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for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
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if ((irq_dev->path.type != DEVICE_PATH_PCI) ||
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||||
(!irq_dev->enabled))
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continue;
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current_bdf = irq_dev->path.pci.devfn |
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||||
irq_dev->bus->secondary << 8;
|
||||
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||||
/*
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||||
* Step 1: Get the INT_PIN and device structure to look for
|
||||
* in the pirq_data table defined in the mainboard directory.
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||||
*/
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targ_dev = NULL;
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||||
new_int_pin = get_pci_irq_pins(irq_dev, &targ_dev);
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if (targ_dev == NULL || new_int_pin < 1)
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continue;
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||||
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||||
/* Get the original INT_PIN for record keeping */
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original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
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||||
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||||
parent_bdf = targ_dev->path.pci.devfn
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||||
| targ_dev->bus->secondary << 8;
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device_num = PCI_SLOT(parent_bdf);
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||||
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||||
if (ir->pcidev[device_num] == 0) {
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||||
printk(BIOS_WARNING,
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"Warning: PCI Device %d does not have an IRQ entry, skipping it\n",
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device_num);
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||||
continue;
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||||
}
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||||
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||||
/* Find the PIRQ that is attached to the INT_PIN this device uses */
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pirq = (ir->pcidev[device_num] >> ((new_int_pin - 1) * 4)) & 0xF;
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||||
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||||
/* Get the INT_LINE this device/function will use */
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||||
int_line = ir->pic[pirq];
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||||
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||||
if (int_line != PIRQ_PIC_IRQDISABLE) {
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||||
/* Set this IRQ to level triggered since it is used by a PCI device */
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||||
i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED);
|
||||
/* Set the Interrupt Line register in PCI config space */
|
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pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
|
||||
} else {
|
||||
/* Set the Interrupt line register as "unknown or unused" */
|
||||
pci_write_config8(irq_dev, PCI_INTERRUPT_LINE,
|
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PIRQ_PIC_UNKNOWN_UNUSED);
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||||
}
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|
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printk(BIOS_SPEW, "\tINT_PIN\t\t: %d (%s)\n",
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original_int_pin, pin_to_str(original_int_pin));
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||||
if (parent_bdf != current_bdf)
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printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n",
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new_int_pin, pin_to_str(new_int_pin));
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printk(BIOS_SPEW, "\tPIRQ\t\t: %c\n"
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"\tINT_LINE\t: 0x%X (IRQ %d)\n",
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'A' + pirq, int_line, int_line);
|
||||
}
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||||
printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n");
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||||
}
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||||
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||||
static void soc_pirq_init(device_t dev)
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{
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int i, j;
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||||
int pirq;
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u8 *ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF);
|
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u8 *pr_base = ibase + 0x08;
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||||
u16 *ir_base = (u16 *)(ibase + 0x20);
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u32 *actl = (u32 *)ibase;
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const struct rangeley_irq_route *ir = &global_rangeley_irq_route;
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|
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/* Set up the PIRQ PIC routing based on static config. */
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printk(BIOS_SPEW, "Start writing IRQ assignments\n"
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"PIRQ\tA \tB \tC \tD \tE \tF \tG \tH\n"
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"IRQ ");
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for (i = 0; i < NUM_PIRQS; i++) {
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write8(pr_base + i*sizeof(ir->pic[i]), ir->pic[i]);
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printk(BIOS_SPEW, "\t%d", ir->pic[i]);
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}
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printk(BIOS_SPEW, "\n\n");
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/* Set up the per device PIRQ routing based on static config. */
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printk(BIOS_SPEW, "\t\t\tPIRQ[A-H] routed to each INT_PIN[A-D]\n"
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"Dev\tINTA (IRQ)\tINTB (IRQ)\tINTC (IRQ)\tINTD (IRQ)\n");
|
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for (i = 0; i < NUM_OF_PCI_DEVS; i++) {
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write16(ir_base + i, ir->pcidev[i]);
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||||
/* If the entry is more than just 0, print it out */
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if(ir->pcidev[i]) {
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printk(BIOS_SPEW, " %d: ", i);
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for (j = 0; j < 4; j++) {
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pirq = (ir->pcidev[i] >> (j * 4)) & 0xF;
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||||
printk(BIOS_SPEW, "\t%-4c (%d)", 'A' + pirq, ir->pic[pirq]);
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}
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printk(BIOS_SPEW, "\n");
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||||
}
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||||
}
|
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|
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/* Route SCI to IRQ9 */
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write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9);
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||||
printk(BIOS_SPEW, "Finished writing IRQ assignments\n");
|
||||
|
||||
/* Write IRQ assignments to PCI config space */
|
||||
write_pci_config_irqs();
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||||
}
|
||||
|
||||
static void soc_power_options(device_t dev)
|
||||
{
|
||||
u8 reg8;
|
||||
u16 pmbase;
|
||||
u32 reg32;
|
||||
|
||||
/* Get the chip configuration */
|
||||
config_t *config = dev->chip_info;
|
||||
|
||||
int nmi_option;
|
||||
|
||||
/* Set up NMI on errors. */
|
||||
reg8 = inb(0x61);
|
||||
reg8 &= 0x0f; /* Higher Nibble must be 0 */
|
||||
reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
|
||||
// reg8 &= ~(1 << 2); /* PCI SERR# Enable */
|
||||
reg8 |= (1 << 2); /* PCI SERR# Disable for now */
|
||||
outb(reg8, 0x61);
|
||||
|
||||
reg8 = inb(0x70);
|
||||
nmi_option = NMI_OFF;
|
||||
get_option(&nmi_option, "nmi");
|
||||
if (nmi_option) {
|
||||
printk(BIOS_INFO, "NMI sources enabled.\n");
|
||||
reg8 &= ~(1 << 7); /* Set NMI. */
|
||||
} else {
|
||||
printk(BIOS_INFO, "NMI sources disabled.\n");
|
||||
reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
|
||||
}
|
||||
outb(reg8, 0x70);
|
||||
|
||||
pmbase = pci_read_config16(dev, ABASE) & ~0xf;
|
||||
|
||||
outl(config->gpe0_en, pmbase + GPE0_EN);
|
||||
outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN);
|
||||
|
||||
/* Set up power management block and determine sleep mode */
|
||||
reg32 = inl(pmbase + PM1_CNT); // PM1_CNT
|
||||
reg32 &= ~(7 << 10); // SLP_TYP
|
||||
reg32 |= (1 << 0); // SCI_EN
|
||||
outl(reg32, pmbase + PM1_CNT);
|
||||
}
|
||||
|
||||
/* Disable the HPET, Clear the counter, and re-enable it. */
|
||||
static void enable_hpet(void)
|
||||
{
|
||||
write8((u8 *)HPET_GCFG, 0x00);
|
||||
write32((u32 *)HPET_MCV, 0x00000000);
|
||||
write32((u32 *)(HPET_MCV + 0x04), 0x00000000);
|
||||
write8((u8 *)HPET_GCFG, 0x01);
|
||||
}
|
||||
|
||||
static void soc_disable_smm_only_flashing(struct device *dev)
|
||||
{
|
||||
u8 reg8;
|
||||
|
||||
printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");
|
||||
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
|
||||
reg8 &= ~(1 << 5);
|
||||
pci_write_config8(dev, 0xdc, reg8);
|
||||
}
|
||||
|
||||
static void lpc_init(struct device *dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "soc: lpc_init\n");
|
||||
|
||||
/* Set the value for PCI command register. */
|
||||
pci_write_config16(dev, PCI_COMMAND, 0x000f);
|
||||
|
||||
/* IO APIC initialization. */
|
||||
soc_enable_apic(dev);
|
||||
|
||||
soc_enable_serial_irqs(dev);
|
||||
|
||||
/* Setup the PIRQ. */
|
||||
soc_pirq_init(dev);
|
||||
|
||||
/* Setup power options. */
|
||||
soc_power_options(dev);
|
||||
|
||||
/* Initialize power management */
|
||||
switch (soc_silicon_type()) {
|
||||
case SOC_TYPE_RANGELEY:
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_DEBUG, "Unknown Chipset: 0x%04x\n", dev->device);
|
||||
}
|
||||
|
||||
/* Initialize ISA DMA. */
|
||||
isa_dma_init();
|
||||
|
||||
/* Initialize the High Precision Event Timers, if present. */
|
||||
enable_hpet();
|
||||
|
||||
setup_i8259();
|
||||
|
||||
/* Interrupt 9 should be level triggered (SCI) */
|
||||
i8259_configure_irq_trigger(9, 1);
|
||||
|
||||
soc_disable_smm_only_flashing(dev);
|
||||
}
|
||||
|
||||
static void soc_lpc_read_resources(device_t dev)
|
||||
{
|
||||
struct resource *res;
|
||||
config_t *config = dev->chip_info;
|
||||
u8 io_index = 0;
|
||||
|
||||
/* Get the normal PCI resources of this device. */
|
||||
pci_dev_read_resources(dev);
|
||||
|
||||
/* Add an extra subtractive resource for both memory and I/O. */
|
||||
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
|
||||
res->base = 0;
|
||||
res->size = 0x1000;
|
||||
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
|
||||
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
|
||||
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
|
||||
res->base = 0xff800000;
|
||||
res->size = 0x00800000; /* 8 MB for flash */
|
||||
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
|
||||
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
|
||||
res = new_resource(dev, 3); /* IOAPIC */
|
||||
res->base = IO_APIC_ADDR;
|
||||
res->size = 0x00001000;
|
||||
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
|
||||
/* Set SOC IO decode ranges if required.*/
|
||||
if ((config->gen1_dec & 0xFFFC) > 0x1000) {
|
||||
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
|
||||
res->base = config->gen1_dec & 0xFFFC;
|
||||
res->size = (config->gen1_dec >> 16) & 0xFC;
|
||||
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
|
||||
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
}
|
||||
|
||||
if ((config->gen2_dec & 0xFFFC) > 0x1000) {
|
||||
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
|
||||
res->base = config->gen2_dec & 0xFFFC;
|
||||
res->size = (config->gen2_dec >> 16) & 0xFC;
|
||||
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
|
||||
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
}
|
||||
|
||||
if ((config->gen3_dec & 0xFFFC) > 0x1000) {
|
||||
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
|
||||
res->base = config->gen3_dec & 0xFFFC;
|
||||
res->size = (config->gen3_dec >> 16) & 0xFC;
|
||||
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
|
||||
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
}
|
||||
|
||||
if ((config->gen4_dec & 0xFFFC) > 0x1000) {
|
||||
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
|
||||
res->base = config->gen4_dec & 0xFFFC;
|
||||
res->size = (config->gen4_dec >> 16) & 0xFC;
|
||||
res->flags = IORESOURCE_IO| IORESOURCE_SUBTRACTIVE |
|
||||
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
}
|
||||
}
|
||||
|
||||
static void soc_lpc_enable_resources(device_t dev)
|
||||
{
|
||||
return pci_dev_enable_resources(dev);
|
||||
}
|
||||
|
||||
static void soc_lpc_enable(device_t dev)
|
||||
{
|
||||
soc_enable(dev);
|
||||
}
|
||||
|
||||
static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
|
||||
{
|
||||
if (!vendor || !device) {
|
||||
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
|
||||
pci_read_config32(dev, PCI_VENDOR_ID));
|
||||
} else {
|
||||
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
|
||||
((device & 0xffff) << 16) | (vendor & 0xffff));
|
||||
}
|
||||
}
|
||||
|
||||
static void southbridge_inject_dsdt(device_t dev)
|
||||
{
|
||||
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs));
|
||||
|
||||
if (gnvs) {
|
||||
memset(gnvs, 0, sizeof(*gnvs));
|
||||
acpi_create_gnvs(gnvs);
|
||||
acpi_save_gnvs((unsigned long)gnvs);
|
||||
#if CONFIG_HAVE_SMI_HANDLER
|
||||
/* And tell SMI about it */
|
||||
smm_setup_structures(gnvs, NULL, NULL);
|
||||
#endif
|
||||
|
||||
/* Add it to DSDT. */
|
||||
acpigen_write_scope("\\");
|
||||
acpigen_write_name_dword("NVSA", (u32) gnvs);
|
||||
acpigen_pop_len();
|
||||
}
|
||||
}
|
||||
|
||||
static struct pci_operations pci_ops = {
|
||||
.set_subsystem = set_subsystem,
|
||||
};
|
||||
|
||||
static struct device_operations device_ops = {
|
||||
.read_resources = soc_lpc_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = soc_lpc_enable_resources,
|
||||
.init = lpc_init,
|
||||
.write_acpi_tables = acpi_write_hpet,
|
||||
.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
|
||||
.enable = soc_lpc_enable,
|
||||
.scan_bus = scan_lpc_bus,
|
||||
.ops_pci = &pci_ops,
|
||||
};
|
||||
|
||||
/* IDs for LPC device of Intel 89xx Series Chipset */
|
||||
static const unsigned short pci_device_ids[] = { 0x1F38, 0x1F39, 0x1F3A, 0x1F3B,
|
||||
0 };
|
||||
|
||||
static const struct pci_driver soc_lpc __pci_driver = {
|
||||
.ops = &device_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.devices = pci_device_ids,
|
||||
};
|
||||
Reference in New Issue
Block a user