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src/cpu: Capitalize ROM and RAM

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Change-Id: I103167a0c39627bcd2ca1d0d4288eb5df02a6cd2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15935
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Elyes HAOUAS
2016-07-28 19:15:34 +02:00
committed by Martin Roth
parent 9071670a84
commit 585d1a0e7d
12 changed files with 14 additions and 14 deletions
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2
src/cpu/intel/haswell/cache_as_ram.inc
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@@ -145,7 +145,7 @@ clear_mtrrs:
wrmsr
post_code(0x27)
/* Enable caching for ram init code to run faster */
/* Enable caching for RAM init code to run faster */
movl $MTRR_PHYS_BASE(2), %ecx
movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
xorl %edx, %edx

6
src/cpu/intel/haswell/romstage.c
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@@ -113,8 +113,8 @@ static void *setup_romstage_stack_after_car(void)
num_mtrrs++;
top_of_ram = (uint32_t)cbmem_top();
/* Cache 8MiB below the top of ram. On haswell systems the top of
* ram under 4GiB is the start of the TSEG region. It is required to
/* Cache 8MiB below the top of RAM. On haswell systems the top of
* RAM under 4GiB is the start of the TSEG region. It is required to
* be 8MiB aligned. Set this area as cacheable so it can be used later
* for ramstage before setting up the entire RAM as cacheable. */
slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
@@ -123,7 +123,7 @@ static void *setup_romstage_stack_after_car(void)
slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);
num_mtrrs++;
/* Cache 8MiB at the top of ram. Top of ram on haswell systems
/* Cache 8MiB at the top of RAM. Top of RAM on haswell systems
* is where the TSEG region resides. However, it is not restricted
* to SMM mode until SMM has been relocated. By setting the region
* to cacheable it provides faster access when relocating the SMM

2
src/cpu/intel/haswell/stage_cache.c
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@@ -20,7 +20,7 @@
void stage_cache_external_region(void **base, size_t *size)
{
/* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
* The top of ram is defined to be the TSEG base address. */
* The top of RAM is defined to be the TSEG base address. */
*size = RESERVED_SMM_SIZE;
*base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET);
}