Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"

In the end it does not look like RCBA register offsets are fully
compatible over southbridges.

This reverts commit d2d2aef6a3.

Is squashed with revert of "sb/intel/common: Fix conflicting OIC
register definition" 8aaa00401b.

Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/southbridge/intel/ibexpeak/azalia.c

@@ -23,7 +23,6 @@
 #include <arch/io.h>
 #include <delay.h>
 #include <device/azalia_device.h>
-#include <southbridge/intel/common/rcba.h>
 #include "pch.h"
 
 #define HDA_ICII_REG 0x68

src/southbridge/intel/ibexpeak/lpc.c

@@ -36,7 +36,6 @@
 #include "nvs.h"
 #include <southbridge/intel/common/pciehp.h>
 #include <southbridge/intel/common/acpi_pirq_gen.h>
-#include <southbridge/intel/common/rcba.h>
 
 #define NMI_OFF	0
 

src/southbridge/intel/ibexpeak/me.c

@@ -30,7 +30,6 @@
 #include <string.h>
 #include <delay.h>
 #include <elog.h>
-#include <southbridge/intel/common/rcba.h>
 
 #ifdef __SMM__
 #include <arch/io.h>

src/southbridge/intel/ibexpeak/pch.h

@@ -46,6 +46,12 @@
 #define DEFAULT_GPIOBASE	0x0480
 #define DEFAULT_PMBASE		0x0500
 
+#ifndef __ACPI__
+#define DEFAULT_RCBA		((u8 *)0xfed1c000)
+#else
+#define DEFAULT_RCBA		0xfed1c000
+#endif
+
 #ifndef __ACPI__
 #define DEBUG_PERIODIC_SMIS 0
 
@@ -235,6 +241,75 @@ void southbridge_configure_default_intmap(void);
 
 /* Root Complex Register Block */
 #define RCBA		0xf0
+
+#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
+#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
+#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
+
+#define RCBA_AND_OR(bits, x, and, or) \
+        RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
+#define RCBA8_AND_OR(x, and, or)  RCBA_AND_OR(8, x, and, or)
+#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
+#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
+#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
+
+#define VCH		0x0000	/* 32bit */
+#define VCAP1		0x0004	/* 32bit */
+#define VCAP2		0x0008	/* 32bit */
+#define PVC		0x000c	/* 16bit */
+#define PVS		0x000e	/* 16bit */
+
+#define V0CAP		0x0010	/* 32bit */
+#define V0CTL		0x0014	/* 32bit */
+#define V0STS		0x001a	/* 16bit */
+
+#define V1CAP		0x001c	/* 32bit */
+#define V1CTL		0x0020	/* 32bit */
+#define V1STS		0x0026	/* 16bit */
+
+#define RCTCL		0x0100	/* 32bit */
+#define ESD		0x0104	/* 32bit */
+#define ULD		0x0110	/* 32bit */
+#define ULBA		0x0118	/* 64bit */
+
+#define RP1D		0x0120	/* 32bit */
+#define RP1BA		0x0128	/* 64bit */
+#define RP2D		0x0130	/* 32bit */
+#define RP2BA		0x0138	/* 64bit */
+#define RP3D		0x0140	/* 32bit */
+#define RP3BA		0x0148	/* 64bit */
+#define RP4D		0x0150	/* 32bit */
+#define RP4BA		0x0158	/* 64bit */
+#define HDD		0x0160	/* 32bit */
+#define HDBA		0x0168	/* 64bit */
+#define RP5D		0x0170	/* 32bit */
+#define RP5BA		0x0178	/* 64bit */
+#define RP6D		0x0180	/* 32bit */
+#define RP6BA		0x0188	/* 64bit */
+
+#define RPC		0x0400	/* 32bit */
+#define RPFN		0x0404	/* 32bit */
+
+/* Root Port configuratinon space hide */
+#define RPFN_HIDE(port)         (1 << (((port) * 4) + 3))
+/* Get the function number assigned to a Root Port */
+#define RPFN_FNGET(reg,port)    (((reg) >> ((port) * 4)) & 7)
+/* Set the function number for a Root Port */
+#define RPFN_FNSET(port,func)   (((func) & 7) << ((port) * 4))
+/* Root Port function number mask */
+#define RPFN_FNMASK(port)       (7 << ((port) * 4))
+
+#define TRSR		0x1e00	/*  8bit */
+#define TRCR		0x1e10	/* 64bit */
+#define TWDR		0x1e18	/* 64bit */
+
+#define IOTR0		0x1e80	/* 64bit */
+#define IOTR1		0x1e88	/* 64bit */
+#define IOTR2		0x1e90	/* 64bit */
+#define IOTR3		0x1e98	/* 64bit */
+
+#define TCTL		0x3000	/*  8bit */
+
 #define NOINT		0
 #define INTA		1
 #define INTB		2
@@ -263,9 +338,86 @@ void southbridge_configure_default_intmap(void);
 #define  IOBPS_WRITE_AX	((1 << 9)|(1 << 10))
 #define  IOBPS_READ_AX	((1 << 8)|(1 << 9)|(1 << 10))
 
+#define D31IP		0x3100	/* 32bit */
+#define D31IP_TTIP	24	/* Thermal Throttle Pin */
+#define D31IP_SIP2	20	/* SATA Pin 2 */
+#define D31IP_UNKIP	16
+#define D31IP_SMIP	12	/* SMBUS Pin */
+#define D31IP_SIP	8	/* SATA Pin */
+#define D30IP		0x3104	/* 32bit */
+#define D30IP_PIP	0	/* PCI Bridge Pin */
+#define D29IP		0x3108	/* 32bit */
+#define D29IP_E1P	0	/* EHCI #1 Pin */
+#define D28IP		0x310c	/* 32bit */
+#define D28IP_P8IP	28	/* PCI Express Port 8 */
+#define D28IP_P7IP	24	/* PCI Express Port 7 */
+#define D28IP_P6IP	20	/* PCI Express Port 6 */
+#define D28IP_P5IP	16	/* PCI Express Port 5 */
+#define D28IP_P4IP	12	/* PCI Express Port 4 */
+#define D28IP_P3IP	8	/* PCI Express Port 3 */
+#define D28IP_P2IP	4	/* PCI Express Port 2 */
+#define D28IP_P1IP	0	/* PCI Express Port 1 */
+#define D27IP		0x3110	/* 32bit */
+#define D27IP_ZIP	0	/* HD Audio Pin */
+#define D26IP		0x3114	/* 32bit */
+#define D26IP_E2P	0	/* EHCI #2 Pin */
+#define D25IP		0x3118	/* 32bit */
+#define D25IP_LIP	0	/* GbE LAN Pin */
+#define D22IP		0x3124	/* 32bit */
+#define D22IP_KTIP	12	/* KT Pin */
+#define D22IP_IDERIP	8	/* IDE-R Pin */
+#define D22IP_MEI2IP	4	/* MEI #2 Pin */
+#define D22IP_MEI1IP	0	/* MEI #1 Pin */
+#define D20IP		0x3128  /* 32bit */
+#define D20IP_XHCIIP	0
+#define D31IR		0x3140	/* 16bit */
+#define D30IR		0x3142	/* 16bit */
+#define D29IR		0x3144	/* 16bit */
+#define D28IR		0x3146	/* 16bit */
+#define D27IR		0x3148	/* 16bit */
+#define D26IR		0x314c	/* 16bit */
+#define D25IR		0x3150	/* 16bit */
+#define D22IR		0x315c	/* 16bit */
+#define D20IR		0x3160	/* 16bit */
+#define OIC		0x31fe	/* 16bit */
 #define SOFT_RESET_CTRL 0x38f4
 #define SOFT_RESET_DATA 0x38f8
 
+#define DIR_ROUTE(x,a,b,c,d) \
+  RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
+               ((b) << DIR_IBR) | ((a) << DIR_IAR))
+
+#define RC		0x3400	/* 32bit */
+#define HPTC		0x3404	/* 32bit */
+#define GCS		0x3410	/* 32bit */
+#define BUC		0x3414	/* 32bit */
+#define PCH_DISABLE_GBE		(1 << 5)
+#define FD		0x3418	/* 32bit */
+#define DISPBDF		0x3424  /* 16bit */
+#define FD2		0x3428	/* 32bit */
+#define CG		0x341c	/* 32bit */
+
+/* Function Disable 1 RCBA 0x3418 */
+#define PCH_DISABLE_ALWAYS	((1 << 0)|(1 << 26))
+#define PCH_DISABLE_P2P		(1 << 1)
+#define PCH_DISABLE_SATA1	(1 << 2)
+#define PCH_DISABLE_SMBUS	(1 << 3)
+#define PCH_DISABLE_HD_AUDIO	(1 << 4)
+#define PCH_DISABLE_EHCI2	(1 << 13)
+#define PCH_DISABLE_LPC		(1 << 14)
+#define PCH_DISABLE_EHCI1	(1 << 15)
+#define PCH_DISABLE_PCIE(x)	(1 << (16 + x))
+#define PCH_DISABLE_THERMAL	(1 << 24)
+#define PCH_DISABLE_SATA2	(1 << 25)
+#define PCH_DISABLE_XHCI	(1 << 27)
+
+/* Function Disable 2 RCBA 0x3428 */
+#define PCH_DISABLE_KT		(1 << 4)
+#define PCH_DISABLE_IDER	(1 << 3)
+#define PCH_DISABLE_MEI2	(1 << 2)
+#define PCH_DISABLE_MEI1	(1 << 1)
+#define PCH_ENABLE_DBDF		(1 << 0)
+
 /* ICH7 PMBASE */
 #define PM1_STS		0x00
 #define   WAK_STS	(1 << 15)

src/southbridge/intel/ibexpeak/smihandler.c

@@ -24,7 +24,6 @@
 #include <halt.h>
 #include <pc80/mc146818rtc.h>
 #include "pch.h"
-#include <southbridge/intel/common/rcba.h>
 
 #include "nvs.h"
 

src/southbridge/intel/ibexpeak/usb_ehci.c

@@ -22,7 +22,6 @@
 #include "pch.h"
 #include <device/pci_ehci.h>
 #include <arch/io.h>
-#include <southbridge/intel/common/rcba.h>
 
 static void usb_ehci_init(struct device *dev)
 {