soc/intel/common/block/cpu: Fix ways count computation regression

Commit 16ab9bdcd578612bb3822373547f939eb90afd82 ("soc/intel/common:
Calculate and configure SF Mask 2") breaks the computation of the
number of ways and as result, all the derived masks. It results in MSR
such as `IA32_L3_MASK_1' to be improperly programmed yielding
unpredictable NEM issues such as hangs.

Indeed, this commit has introduced a backup of 0x1 into %edx before
comparing the requested cache-as-RAM size against the way size. When
the requested cache-as-RAM is larger, it reaches the second part of
the algorithm which computes the necessary number of ways to fit the
requested cache-as-RAM.

This algorithm uses the `div' instruction. Per specification, the div
instruction divides the 64 bits combination of %edx and %eax register.
Since 0x1 got backed up in %edx and assuming a
`CONFIG_DCACHE_RAM_SIZE' of 0x200000, we end up dividing 0x100200000
by the way size instead of 0x200000 which result in a necessary number
of ways of 4098 for a way size of 0x100000.

This commit clears the %edx register before calling the `div'
instruction.

BUG=b:360332771
TEST=Verified on PTL Intel reference platform

Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521d
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83948
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/common/block/cpu/car/cache_as_ram.S

@@ -510,6 +510,7 @@ find_llc_subleaf:
 	 * ways to be configured for non-eviction
 	 */
 	mov	$CONFIG_DCACHE_RAM_SIZE, %eax
+	xor	%edx, %edx /* Clear the upper 32-bit of dividend */
 	div	%ecx
 	mov	%eax, %edx /* back up data_ways in edx */
 	mov	%eax, %ecx