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soc/intel/elkhartlake: Enable PCH GBE

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Enable PCH GBE with following changes:
1. Configure PCH GBE related FSP UPD flags
2. Use EHL own GBE ACPI instead of common code version due to
   different B:D.F from the usual GBE
3. Add kconfig PMC_EPOC to use the PMC XTAL read function

Due to EHL GBE comes with time sensitive networking (TSN)
capability integrated, EHL FSP is using 'PchTsn' instead of the
usual 'PchLan' naming convention across the board.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I6b0108e892064e804693a34e360034ae7dbee68f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Lean Sheng Tan
2021-06-09 06:51:22 -07:00
committed by Werner Zeh
parent bed1b602d0
commit 58ec51cc0a
6 changed files with 72 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
src/soc/intel/elkhartlake/chip.h
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@@ -42,6 +42,12 @@ struct ehl_ibecc_config {
uint16_t region_mask[MAX_IBECC_REGIONS];
};
/* TSN GBE Link Speed: 0: 2.5Gbps, 1: 1Gbps */
enum tsn_gbe_link_speed {
Tsn_2_5_Gbps,
Tsn_1_Gbps,
};
struct soc_intel_elkhartlake_config {
/* Common struct containing soc config data required by common code */
@@ -156,7 +162,7 @@ struct soc_intel_elkhartlake_config {
* clksrc. */
uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_SRC];
/* Enable PCIe Precision Time Measurement for Root Ports (disabled by default) */
/* Enable PCIe Precision Time Measurement for Root Ports (disabled by default) */
uint8_t PciePtm[CONFIG_MAX_ROOT_PORTS];
/* Probe CLKREQ# signal before enabling CLKREQ# based power management.
@@ -400,6 +406,14 @@ struct soc_intel_elkhartlake_config {
* Values: 0x0 - 4s, 0x1 - 6s, 0x2 - 8s, 0x3 - 10s, 0x4 - 12s, 0x5 - 14s
*/
u8 PchPmPwrBtnOverridePeriod;
/* GBE related */
/* PCH TSN GBE Link Speed: 0: 2.5Gbps, 1: 1Gbps */
enum tsn_gbe_link_speed PchTsnGbeLinkSpeed;
/* PCH TSN GBE SGMII Support: Disable (0) / Enable (1) */
bool PchTsnGbeSgmiiEnable;
/* PCH TSN GBE Multiple Virtual Channel: Disable (0) / Enable (1) */
bool PchTsnGbeMultiVcEnable;
};
typedef struct soc_intel_elkhartlake_config config_t;