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build: separate CPPFLAGS from CFLAGS

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There are a couple of places where CPPFLAGS are
pasted into CFLAGS, eliminate them.

Change-Id: Ic7f568cf87a7d9c5c52e2942032a867161036bd7
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5765
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Patrick Georgi
2014-05-17 14:00:12 +02:00
parent 98f49d2823
commit 58f73a69cd
11 changed files with 20 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/arch/armv7/Makefile.inc
View File

@ -155,7 +155,7 @@ $(objgenerated)/crt0.s: $(objgenerated)/crt0.romstage.S $(obj)/config.h $(obj)/b
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
@printf " CC romstage.inc\n"
$(CC_romstage) -MMD $(CFLAGS_romstage) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@
$(CC_romstage) -MMD $(CFLAGS_romstage) $(CPPFLAGS_romstage) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@
endif # CONFIG_ARCH_ROMSTAGE_ARMV7
@ -192,7 +192,7 @@ $(objgenerated)/ramstage.o: $(stages_o) $$(ramstage-objs) $(LIBGCC_FILE_NAME_ram
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
$(LD_ramstage) -m -m armelf_linux_eabi -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) --end-group
else
$(CC_ramstage) $(CFLAGS_ramstage) -nostdlib -r -o $@ -Wl,--start-group $(stages_o) $(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) -Wl,--end-group
$(CC_ramstage) $(CFLAGS_ramstage) $(CPPFLAGS_ramstage) -nostdlib -r -o $@ -Wl,--start-group $(stages_o) $(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) -Wl,--end-group
endif
ifeq ($(CONFIG_GENERATE_PIRQ_TABLE),y)

2
src/arch/x86/Makefile.inc
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@ -193,7 +193,7 @@ else
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
@printf " CC romstage.inc\n"
$(CC_romstage) -MMD $(CFLAGS_romstage) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@
$(CC_romstage) -MMD $(CFLAGS_romstage) $(CPPFLAGS_romstage) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc
@printf " POST romstage.inc\n"

2
src/cpu/intel/fsp_model_206ax/Makefile.inc
View File

@ -9,6 +9,6 @@ cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
ifneq ($(wildcard $(shell realpath -L "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
CPPFLAGS += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
endif
endif

2
src/drivers/intel/fsp/Makefile.inc
View File

@ -22,7 +22,7 @@ romstage-y += fsp_util.c
ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
CPPFLAGS += -Isrc/drivers/intel/fsp
CPPFLAGS_common += -Isrc/drivers/intel/fsp
ifeq ($(CONFIG_USE_GENERIC_FSP_CAR_INC),y)
cpu_incs += $(src)/drivers/intel/fsp/cache_as_ram.inc

2
src/northbridge/intel/fsp_sandybridge/Makefile.inc
View File

@ -32,6 +32,6 @@ romstage-y += ../../../arch/x86/lib/walkcbfs.S
smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
CPPFLAGS += -I$(src)/northbridge/intel/fsp_sandybridge/fsp
CPPFLAGS_common += -I$(src)/northbridge/intel/fsp_sandybridge/fsp
$(obj)/northbridge/intel/fsp_sandybridge/acpi.ramstage.o : $(obj)/build.h

2
src/soc/intel/baytrail/Makefile.inc
View File

@ -53,7 +53,7 @@ ramstage-$(CONFIG_ELOG) += elog.c
# Remove as ramstage gets fleshed out
ramstage-y += placeholders.c
CPPFLAGS += -Isrc/soc/intel/baytrail/
CPPFLAGS_common += -Isrc/soc/intel/baytrail/
# Run an intermediate step when producing coreboot.rom
# that adds additional components to the final firmware

2
src/southbridge/intel/fsp_bd82x6x/Makefile.inc
View File

@ -70,4 +70,4 @@ endif
PHONY += bd82x6x_add_me
CPPFLAGS += -I$(src)/southbridge/intel/fsp_bd82x6x
CPPFLAGS_common += -I$(src)/southbridge/intel/fsp_bd82x6x

2
src/vendorcode/google/chromeos/Makefile.inc
View File

@ -48,7 +48,7 @@ VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-ROMSTAGE-y))
VB_SOURCE := vboot_reference
# Add the vboot include paths.
CPPFLAGS += -I$(VB_SOURCE)/firmware/include
CPPFLAGS_common += -I$(VB_SOURCE)/firmware/include
VBOOT_STUB_ELF = $(obj)/vendorcode/google/chromeos/vbootstub.elf
VBOOT_STUB = $(VBOOT_STUB_ELF).rmod