nb/intel/sandybridge: Clean up TC_OTHP writes
ODT stretch is configured for both slots in `dram_odt_stretch`. Also drop an unjustified OR, which is setting ODT stretch for one slot. Tested on Asus P8H61-M PRO, still boots. Change-Id: I3a9076afec96e33cfdd12f9b78ca4101b3776dab Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47490 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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		@@ -142,7 +142,7 @@ static void dram_odt_stretch(ramctr_timing *ctrl, int channel)
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void dram_timing_regs(ramctr_timing *ctrl)
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					void dram_timing_regs(ramctr_timing *ctrl)
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{
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					{
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	u32 reg, addr, val32;
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						u32 reg, val32;
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	int channel;
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						int channel;
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	FOR_ALL_CHANNELS {
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						FOR_ALL_CHANNELS {
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@@ -169,14 +169,13 @@ void dram_timing_regs(ramctr_timing *ctrl)
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		MCHBAR32(TC_RAP_ch(channel)) = reg;
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							MCHBAR32(TC_RAP_ch(channel)) = reg;
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		/* Other parameters */
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							/* Other parameters */
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		addr = TC_OTHP_ch(channel);
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		reg = 0;
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							reg = 0;
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		reg |= (ctrl->tXPDLL << 0);
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							reg |= (ctrl->tXPDLL << 0);
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		reg |= (ctrl->tXP    << 5);
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							reg |= (ctrl->tXP    << 5);
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		reg |= (ctrl->tAONPD << 8);
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							reg |= (ctrl->tAONPD << 8);
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		reg |= 0xa0000;
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							reg |= 0xa0000;
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		printram("OTHP [%x] = %x\n", addr, reg);
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							printram("OTHP [%x] = %x\n", TC_OTHP_ch(channel), reg);
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		MCHBAR32(addr) = reg;
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							MCHBAR32(TC_OTHP_ch(channel)) = reg;
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		/* Debug parameters - only applies to Ivy Bridge */
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							/* Debug parameters - only applies to Ivy Bridge */
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		if (IS_IVY_CPU(ctrl->cpu)) {
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							if (IS_IVY_CPU(ctrl->cpu)) {
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@@ -195,8 +194,6 @@ void dram_timing_regs(ramctr_timing *ctrl)
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			MCHBAR32(TC_DTP_ch(channel)) = reg;
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								MCHBAR32(TC_DTP_ch(channel)) = reg;
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		}
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							}
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		MCHBAR32_OR(addr, 0x00020000);
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		dram_odt_stretch(ctrl, channel);
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							dram_odt_stretch(ctrl, channel);
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		/*
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							/*
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