AGESA: Switch to MMCONF_SUPPORT_DEFAULT

Vendorcode always does PCI MMCONF access once it is
enabled via MSR.

In coreboot proper, we don't give opportunity to make
pci_read/write calls before PCI MMCONF is enabled via MSR.
This happens early in romstage amd_initmmio() for all cores.

Change-Id: If31bc0a67b480bcc1d955632f413f5cdeec51a54
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17533
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/mainboard/biostar/am1ml/romstage.c

@@ -113,6 +113,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	pci_devfn_t dev;
 	u32 *addr32;
 
+	/* Must come first to enable PCI MMCONF. */
+	amd_initmmio();
+
 	/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
 	 * LpcClk[1:0]".  To be consistent with Parmer, setting to 4mA
 	 * even though the register is not documented in the Kabini BKDG.
@@ -121,7 +124,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	outb(0xD2, 0xcd6);
 	outb(0x00, 0xcd7);
 
-	amd_initmmio();
 	/* Set LPC decode enables. */
 	pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3);
 	pci_write_config32(dev2, 0x44, 0xff03ffd5);