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exynos5420: minor clean-up memory related stuff

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This cleans up a few minor things (mostly #defines) of the memory code
for exynos5420, pit, and kirby. Specifically:

- CONCONTROL.empty is read-only, so don't try to set it and also
  get rid of the unneeded DMC_CONCONTROL_EMPTY_ENABLE #define.
- MEMBASECONFIG* overlaps members of the mem_timings struct and
  are mainboard-dependent anyway, so get rid of 'em.
- DMC_MEMCONTROL_TP_DISABLE corresponds to a reserved bit. It may
  have been deprecated.
- Same with TIMING* #defines.
- Clarify DDR_MODE_* usage and use mem->mem_type when appropriate.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: Ideb21efcc97b24f7e115e90051c20daef4480f17
Reviewed-on: https://chromium-review.googlesource.com/167500
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: ron minnich <rminnich@chromium.org>
(cherry picked from commit 650dba32cb217414c422907398f68e784e5720e8)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6614
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This commit is contained in:
David Hendricks
2013-08-29 13:12:56 -07:00
committed by Isaac Christensen
parent 122b6d6ce6
commit 5a0fdb4565
4 changed files with 12 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
src/cpu/samsung/exynos5420/dmc.h
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@@ -259,10 +259,11 @@ struct exynos5_tzasc {
} __attribute__((packed)); } __attribute__((packed));
enum ddr_mode { enum ddr_mode {
DDR_MODE_DDR2, /* This is in order of ctrl_ddr_mode values. Do not change. */
DDR_MODE_DDR3, DDR_MODE_DDR2 = 0x0,
DDR_MODE_LPDDR2, DDR_MODE_DDR3 = 0x1,
DDR_MODE_LPDDR3, DDR_MODE_LPDDR2 = 0x2,
DDR_MODE_LPDDR3 = 0x3,
DDR_MODE_COUNT, DDR_MODE_COUNT,
}; };

8
src/cpu/samsung/exynos5420/dmc_init_ddr3.c
View File

@@ -70,12 +70,12 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
/* Specify the DDR memory type as DDR3 */ /* Specify the DDR memory type as DDR3 */
val = readl(&phy0_ctrl->phy_con0); val = readl(&phy0_ctrl->phy_con0);
val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT); val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT); val |= (mem->mem_type << PHY_CON0_CTRL_DDR_MODE_SHIFT);
writel(val, &phy0_ctrl->phy_con0); writel(val, &phy0_ctrl->phy_con0);
val = readl(&phy1_ctrl->phy_con0); val = readl(&phy1_ctrl->phy_con0);
val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT); val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT); val |= (mem->mem_type << PHY_CON0_CTRL_DDR_MODE_SHIFT);
writel(val, &phy1_ctrl->phy_con0); writel(val, &phy1_ctrl->phy_con0);
/* Set Read Latency and Burst Length for PHY0 and PHY1 */ /* Set Read Latency and Burst Length for PHY0 and PHY1 */
@@ -142,8 +142,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
clrbits_le32(&drex0->concontrol, DFI_INIT_START); clrbits_le32(&drex0->concontrol, DFI_INIT_START);
clrbits_le32(&drex1->concontrol, DFI_INIT_START); clrbits_le32(&drex1->concontrol, DFI_INIT_START);
update_reset_dll(drex0, DDR_MODE_DDR3); update_reset_dll(drex0, mem->mem_type);
update_reset_dll(drex1, DDR_MODE_DDR3); update_reset_dll(drex1, mem->mem_type);
/* MEMBASECONFIG0 (CS0) */ /* MEMBASECONFIG0 (CS0) */
writel(mem->membaseconfig0, &tzasc0->membaseconfig0); writel(mem->membaseconfig0, &tzasc0->membaseconfig0);

24
src/cpu/samsung/exynos5420/setup.h
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@@ -106,7 +106,6 @@ struct exynos5_phy_control;
#define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0) #define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0)
#define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1) #define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1)
#define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE (0 << 2) #define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE (0 << 2)
#define DMC_MEMCONTROL_TP_DISABLE (0 << 4)
#define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5) #define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5)
#define DMC_MEMCONTROL_DSREF_ENABLE (1 << 5) #define DMC_MEMCONTROL_DSREF_ENABLE (1 << 5)
#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6) #define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6)
@@ -139,13 +138,6 @@ struct exynos5_phy_control;
#define DMC_MEMCONFIGx_CHIP_ROW_16 (4 << 4) #define DMC_MEMCONFIGx_CHIP_ROW_16 (4 << 4)
#define DMC_MEMCONFIGx_CHIP_BANK_8 (3 << 0) #define DMC_MEMCONFIGx_CHIP_BANK_8 (3 << 0)
#define DMC_MEMBASECONFIGx_CHIP_BASE(x) (x << 16)
#define DMC_MEMBASECONFIGx_CHIP_MASK(x) (x << 0)
#define DMC_MEMBASECONFIG_VAL(x) ( \
DMC_MEMBASECONFIGx_CHIP_BASE(x) | \
DMC_MEMBASECONFIGx_CHIP_MASK(0x780) \
)
#define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40) #define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40)
#define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80) #define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80)
@@ -170,8 +162,6 @@ struct exynos5_phy_control;
/* COJCONTROL register bit fields */ /* COJCONTROL register bit fields */
#define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3) #define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3)
#define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5) #define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5)
#define DMC_CONCONTROL_EMPTY_DISABLE (0 << 8)
#define DMC_CONCONTROL_EMPTY_ENABLE (1 << 8)
#define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12) #define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12)
#define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16) #define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16)
#define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28) #define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)
@@ -634,6 +624,8 @@ struct exynos5_phy_control;
#define LPDDR3PHY_CTRL_PHY_RESET (1 << 0) #define LPDDR3PHY_CTRL_PHY_RESET (1 << 0)
#define LPDDR3PHY_CTRL_PHY_RESET_OFF (0 << 0) #define LPDDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)
/* FIXME(dhendrix): misleading name. The reset value is 0x17021a40, bits 12:11
+ default to 0x3 which indicates LPDDR3. We want DDR3, so we use 0x1. */
#define PHY_CON0_RESET_VAL 0x17020a40 #define PHY_CON0_RESET_VAL 0x17020a40
#define P0_CMD_EN (1 << 14) #define P0_CMD_EN (1 << 14)
#define BYTE_RDLVL_EN (1 << 13) #define BYTE_RDLVL_EN (1 << 13)
@@ -743,7 +735,7 @@ struct exynos5_phy_control;
#define CMD_DEFAULT_LPDDR3 0xF #define CMD_DEFAULT_LPDDR3 0xF
#define CMD_DEFUALT_OFFSET 0 #define CMD_DEFUALT_OFFSET 0
#define T_WRDATA_EN 0x7 #define T_WRDATA_EN 0x7
#define T_WRDATA_EN_DDR3 0x8 #define T_WRDATA_EN_DDR3 0x8 /* FIXME(dhendrix): 6 for DDR3? see T_wrdata_en */
#define T_WRDATA_EN_OFFSET 16 #define T_WRDATA_EN_OFFSET 16
#define T_WRDATA_EN_MASK 0x1f #define T_WRDATA_EN_MASK 0x1f
@@ -775,20 +767,10 @@ struct exynos5_phy_control;
#define DMC_CHIP_MASK_2GB 0x780 #define DMC_CHIP_MASK_2GB 0x780
#define DMC_CHIP_MASK_4GB 0x700 #define DMC_CHIP_MASK_4GB 0x700
#define MEMBASECONFIG_CHIP_MASK_VAL 0x7E0
#define MEMBASECONFIG_CHIP_MASK_OFFSET 0
#define MEMBASECONFIG0_CHIP_BASE_VAL 0x20
#define MEMBASECONFIG1_CHIP_BASE_VAL 0x40
#define CHIP_BASE_OFFSET 16
#define MEMCONFIG_VAL 0x1323 #define MEMCONFIG_VAL 0x1323
#define PRECHCONFIG_DEFAULT_VAL 0xFF000000 #define PRECHCONFIG_DEFAULT_VAL 0xFF000000
#define PWRDNCONFIG_DEFAULT_VAL 0xFFFF00FF #define PWRDNCONFIG_DEFAULT_VAL 0xFFFF00FF
#define TIMINGAREF_VAL 0x5d
#define TIMINGROW_VAL 0x345A8692
#define TIMINGDATA_VAL 0x3630065C
#define TIMINGPOWER_VAL 0x50380336
#define DFI_INIT_COMPLETE (1 << 3) #define DFI_INIT_COMPLETE (1 << 3)
#define BRBRSVCONTROL_VAL 0x00000033 #define BRBRSVCONTROL_VAL 0x00000033

2
src/mainboard/google/pit/memory.c
View File

@@ -81,7 +81,6 @@ const struct mem_timings mem_timings = {
.memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
DMC_MEMCONTROL_DPWRDN_DISABLE | DMC_MEMCONTROL_DPWRDN_DISABLE |
DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
DMC_MEMCONTROL_TP_DISABLE |
DMC_MEMCONTROL_DSREF_DISABLE | DMC_MEMCONTROL_DSREF_DISABLE |
DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
DMC_MEMCONTROL_MEM_TYPE_DDR3 | DMC_MEMCONTROL_MEM_TYPE_DDR3 |
@@ -107,7 +106,6 @@ const struct mem_timings mem_timings = {
.concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
DMC_CONCONTROL_TIMEOUT_LEVEL0 | DMC_CONCONTROL_TIMEOUT_LEVEL0 |
DMC_CONCONTROL_RD_FETCH_DISABLE | DMC_CONCONTROL_RD_FETCH_DISABLE |
DMC_CONCONTROL_EMPTY_DISABLE |
DMC_CONCONTROL_AREF_EN_DISABLE | DMC_CONCONTROL_AREF_EN_DISABLE |
DMC_CONCONTROL_IO_PD_CON_DISABLE, DMC_CONCONTROL_IO_PD_CON_DISABLE,
.dmc_channels = 1, .dmc_channels = 1,