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nb/intel: Fix 16-bit read/write PCI_COMMAND register

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Change-Id: I7c7fb10308a6fcd1ead292c53ed03ddc693f6f15
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Elyes HAOUAS
2020-04-29 09:09:12 +02:00
committed by Patrick Georgi
parent b30fe36734
commit 5ac723e5a4
4 changed files with 6 additions and 19 deletions
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6
src/northbridge/intel/pineview/northbridge.c
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@ -147,12 +147,8 @@ static void mch_domain_set_resources(struct device *dev)
static void mch_domain_init(struct device *dev)
{
u32 reg32;
/* Enable SERR */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_SERR;
pci_write_config32(dev, PCI_COMMAND, reg32);
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
}
static const char *northbridge_acpi_name(const struct device *dev)