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commonlib/mem_pool: Allow configuring the alignment

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AMD platforms require the destination to be 64 byte aligned in order to
use the SPI DMA controller. This is enforced by the destination address
register because the first 6 bits are marked as reserved.

This change adds an option to the mem_pool so the alignment can be
configured.

BUG=b:179699789
TEST=Boot guybrush to OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8d77ffe4411f86c54450305320c9f52ab41a3075
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56580
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Raul E Rangel
2021-07-23 16:43:18 -06:00
committed by Patrick Georgi
parent 533fc4dfb1
commit 5ac82dcc20
3 changed files with 21 additions and 11 deletions
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7
src/commonlib/mem_pool.c
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@ -7,8 +7,11 @@ void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
{
void *p;
/* Make all allocations be at least 8 byte aligned. */
sz = ALIGN_UP(sz, 8);
if (mp->alignment == 0)
return NULL;
/* We assume that mp->buf started mp->alignment aligned */
sz = ALIGN_UP(sz, mp->alignment);
/* Determine if any space available. */
if ((mp->size - mp->free_offset) < sz)