sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

commonlib/mem_pool: Allow configuring the alignment

Browse Source 
AMD platforms require the destination to be 64 byte aligned in order to
use the SPI DMA controller. This is enforced by the destination address
register because the first 6 bits are marked as reserved.

This change adds an option to the mem_pool so the alignment can be
configured.

BUG=b:179699789
TEST=Boot guybrush to OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8d77ffe4411f86c54450305320c9f52ab41a3075
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56580
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Raul E Rangel
2021-07-23 16:43:18 -06:00
committed by Patrick Georgi
parent 533fc4dfb1
commit 5ac82dcc20
3 changed files with 21 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
src/lib/cbfs.c
View File

@ -19,16 +19,17 @@
#include <timestamp.h>
#if ENV_STAGE_HAS_DATA_SECTION
struct mem_pool cbfs_cache = MEM_POOL_INIT(_cbfs_cache, REGION_SIZE(cbfs_cache));
struct mem_pool cbfs_cache =
MEM_POOL_INIT(_cbfs_cache, REGION_SIZE(cbfs_cache), sizeof(uint64_t));
#else
struct mem_pool cbfs_cache = MEM_POOL_INIT(NULL, 0);
struct mem_pool cbfs_cache = MEM_POOL_INIT(NULL, 0, 0);
#endif
static void switch_to_postram_cache(int unused)
{
if (_preram_cbfs_cache != _postram_cbfs_cache)
mem_pool_init(&cbfs_cache, _postram_cbfs_cache,
REGION_SIZE(postram_cbfs_cache));
mem_pool_init(&cbfs_cache, _postram_cbfs_cache, REGION_SIZE(postram_cbfs_cache),
sizeof(uint64_t));
}
ROMSTAGE_CBMEM_INIT_HOOK(switch_to_postram_cache);