From de20b28fe48be9f279f34469f585f9b3aa6db818 Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Thu, 19 Nov 2020 14:09:47 +0800 Subject: [PATCH 01/34] mb/google/zork: correct USB2 phy TXVREFTUNE0 parameter name From spec, [31:28] "HS DC Voltage Level Adjustment" is "TXVREFTUNE0". correct rx_vref_tune -> tx_vref_tune BUG=None BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kevin Chiu Change-Id: I27003a952d8f8bdd8fe52af8a37010e23ee9cdfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/47735 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- .../amd/mandolin/variants/cereme/devicetree.cb | 12 ++++++------ .../amd/mandolin/variants/mandolin/devicetree.cb | 12 ++++++------ .../zork/variants/baseboard/devicetree_dalboz.cb | 12 ++++++------ .../zork/variants/baseboard/devicetree_trembyle.cb | 12 ++++++------ .../google/zork/variants/berknip/overridetree.cb | 8 ++++---- .../google/zork/variants/ezkinil/overridetree.cb | 4 ++-- .../google/zork/variants/morphius/overridetree.cb | 2 +- .../google/zork/variants/woomax/overridetree.cb | 4 ++-- src/soc/amd/picasso/chip.h | 2 +- 9 files changed, 34 insertions(+), 34 deletions(-) diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb index 155328871c..86ff51c666 100644 --- a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb @@ -21,7 +21,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x6, + .tx_vref_tune = 0x6, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" @@ -34,7 +34,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x6, + .tx_vref_tune = 0x6, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" @@ -47,7 +47,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x6, + .tx_vref_tune = 0x6, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" @@ -60,7 +60,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x6, + .tx_vref_tune = 0x6, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" @@ -73,7 +73,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x02, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x5, + .tx_vref_tune = 0x5, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" @@ -86,7 +86,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x02, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x5, + .tx_vref_tune = 0x5, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index 3de58129cd..15b492482f 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -21,7 +21,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x6, + .tx_vref_tune = 0x6, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" @@ -34,7 +34,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x6, + .tx_vref_tune = 0x6, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" @@ -47,7 +47,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x6, + .tx_vref_tune = 0x6, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" @@ -60,7 +60,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x6, + .tx_vref_tune = 0x6, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" @@ -73,7 +73,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x02, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x5, + .tx_vref_tune = 0x5, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" @@ -86,7 +86,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x02, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x5, + .tx_vref_tune = 0x5, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 9f5ef0c37b..0b64855dad 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -64,7 +64,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x6, + .tx_vref_tune = 0x6, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" @@ -77,7 +77,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x6, + .tx_vref_tune = 0x6, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" @@ -90,7 +90,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x6, + .tx_vref_tune = 0x6, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" @@ -103,7 +103,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x6, + .tx_vref_tune = 0x6, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" @@ -116,7 +116,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x02, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x5, + .tx_vref_tune = 0x5, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" @@ -129,7 +129,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x02, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x5, + .tx_vref_tune = 0x5, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index ffe2b7f3f3..4181b4ad81 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -64,7 +64,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x6, + .tx_vref_tune = 0x6, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" @@ -77,7 +77,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x6, + .tx_vref_tune = 0x6, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" @@ -90,7 +90,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x6, + .tx_vref_tune = 0x6, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" @@ -103,7 +103,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x6, + .tx_vref_tune = 0x6, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" @@ -116,7 +116,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x02, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x5, + .tx_vref_tune = 0x5, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" @@ -129,7 +129,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x02, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x5, + .tx_vref_tune = 0x5, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb index f563419b29..4745b45c60 100644 --- a/src/mainboard/google/zork/variants/berknip/overridetree.cb +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -30,7 +30,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0xf, + .tx_vref_tune = 0xf, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" @@ -42,7 +42,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0xf, + .tx_vref_tune = 0xf, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" @@ -54,7 +54,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0xf, + .tx_vref_tune = 0xf, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" @@ -66,7 +66,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0xf, + .tx_vref_tune = 0xf, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" diff --git a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb index 6f4a38e241..b7fee3949f 100644 --- a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb +++ b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb @@ -37,7 +37,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x9, + .tx_vref_tune = 0x9, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" @@ -49,7 +49,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x9, + .tx_vref_tune = 0x9, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index 9d3b7ee670..dbdf2e9a34 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -43,7 +43,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0xf, + .tx_vref_tune = 0xf, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" diff --git a/src/mainboard/google/zork/variants/woomax/overridetree.cb b/src/mainboard/google/zork/variants/woomax/overridetree.cb index 5a2bc9922c..15d6ee8476 100644 --- a/src/mainboard/google/zork/variants/woomax/overridetree.cb +++ b/src/mainboard/google/zork/variants/woomax/overridetree.cb @@ -30,7 +30,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0xf, + .tx_vref_tune = 0xf, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" @@ -42,7 +42,7 @@ chip soc/amd/picasso .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0xf, + .tx_vref_tune = 0xf, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 9d8fb8e70a..28d2040968 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -30,7 +30,7 @@ struct __packed usb2_phy_tune { /* HS Transmitter Rise/Fall Time Adjustment. Range: 0 - 0x3 */ uint8_t tx_rise_tune; /* HS DC Voltage Level Adjustment. Range 0 - 0xF */ - uint8_t rx_vref_tune; + uint8_t tx_vref_tune; /* Transmitter High-Speed Crossover Adjustment. Range 0 - 0x3 */ uint8_t tx_hsxv_tune; /* USB Source Impedance Adjustment. Range 0 - 0x3. */ From 58d0336ef382cf299923777e269d11fd9fadcfa1 Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Tue, 20 Oct 2020 15:31:17 +0300 Subject: [PATCH 02/34] nb/amd/agesa/family15tn: define macro for internal HDMI audio controller Following the example of CB:7630 done for family16kb boards (git commit 3ff4f85ccd9fdb7cd4885a10f025b5ab297a445f). Signed-off-by: Mike Banon Change-Id: Ic48c7475ceadb60f825ca9e3c3427c8a7525a266 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46589 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Angel Pons --- src/northbridge/amd/agesa/family15tn/pci_devs.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/northbridge/amd/agesa/family15tn/pci_devs.h b/src/northbridge/amd/agesa/family15tn/pci_devs.h index ea79970afb..22ce8f5e95 100644 --- a/src/northbridge/amd/agesa/family15tn/pci_devs.h +++ b/src/northbridge/amd/agesa/family15tn/pci_devs.h @@ -12,6 +12,10 @@ #define GFX_FUNC 0 #define GFX_DEVFN PCI_DEVFN(GFX_DEV,GFX_FUNC) +/* Integrated GPU Internal HDMI Audio Controller */ +#define ACTL_FUNC 1 +#define ACTL_DEVFN PCI_DEVFN(GFX_DEV,ACTL_FUNC) + /* PCIe Ports */ #define NB_PCIE_PORT1_DEV 0x2 #define NB_PCIE_PORT2_DEV 0x3 From 1e6a227f1001825f3a948b0734fe60dc0313a88c Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Sat, 21 Nov 2020 21:58:50 +0300 Subject: [PATCH 03/34] nb/amd/agesa/family15tn: define macros for GNB and IOMMU devices Follow the example of newer AMD code for Stoneyridge and Picasso. Signed-off-by: Mike Banon Change-Id: I9c17d4cb4953b28a47483f5d7db308ccc89e9281 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47848 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Angel Pons --- src/northbridge/amd/agesa/family15tn/pci_devs.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/northbridge/amd/agesa/family15tn/pci_devs.h b/src/northbridge/amd/agesa/family15tn/pci_devs.h index 22ce8f5e95..56138433e3 100644 --- a/src/northbridge/amd/agesa/family15tn/pci_devs.h +++ b/src/northbridge/amd/agesa/family15tn/pci_devs.h @@ -7,6 +7,16 @@ #define BUS0 0 +/* GNB Root Complex */ +#define GNB_DEV 0x0 +#define GNB_FUNC 0 +#define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC) + +/* IOMMU */ +#define IOMMU_DEV 0x0 +#define IOMMU_FUNC 2 +#define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC) + /* Graphics and Display */ #define GFX_DEV 0x1 #define GFX_FUNC 0 From 9ee1b82db42623fb700b62d21b5f6d95a0e2e02c Mon Sep 17 00:00:00 2001 From: Benjamin Doron Date: Sat, 24 Oct 2020 02:25:54 +0000 Subject: [PATCH 04/34] soc/intel/skylake: Use correct NHLT_PDM_DEV definition According to the NHLT specification[1], PDM_DEV is defined as "1" on Kabylake based platforms. coreboot currently sets it to "0" on all platforms. Add an entry to the enum and use it to define NHLT_PDM_DEV for Kabylake. "Device Type" will resume from "2" on all platforms, but entries are currently reserved. Tested on an Acer Aspire VN7-572G (Skylake-U), which has a 1ch array DMIC, on Windows 10. 1. https://01.org/sites/default/files/595976_intel_sst_nhlt.pdf Change-Id: Ifbc67228c9e7af7db5154d597ca8d67860cfd2ed Signed-off-by: Benjamin Doron Reviewed-on: https://review.coreboot.org/c/coreboot/+/45010 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/include/nhlt.h | 1 + src/soc/intel/skylake/nhlt/dmic.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/include/nhlt.h b/src/include/nhlt.h index 335580144c..167be520dc 100644 --- a/src/include/nhlt.h +++ b/src/include/nhlt.h @@ -187,6 +187,7 @@ enum { enum { NHLT_PDM_DEV, + NHLT_PDM_DEV_CAVS15, // NHLT_PDM_DEV on cAVS1.5 (KBL) based platforms }; /* Endpoint direction. */ diff --git a/src/soc/intel/skylake/nhlt/dmic.c b/src/soc/intel/skylake/nhlt/dmic.c index 16eb605557..76c1990826 100644 --- a/src/soc/intel/skylake/nhlt/dmic.c +++ b/src/soc/intel/skylake/nhlt/dmic.c @@ -33,7 +33,7 @@ static const struct nhlt_dmic_array_config dmic_2ch_mic_config = { static const struct nhlt_endp_descriptor dmic_2ch_descriptors[] = { { .link = NHLT_LINK_PDM, - .device = NHLT_PDM_DEV, + .device = NHLT_PDM_DEV_CAVS15, .direction = NHLT_DIR_CAPTURE, .vid = NHLT_VID, .did = NHLT_DID_DMIC, @@ -77,7 +77,7 @@ static const struct nhlt_dmic_array_config dmic_4ch_mic_config = { static const struct nhlt_endp_descriptor dmic_4ch_descriptors[] = { { .link = NHLT_LINK_PDM, - .device = NHLT_PDM_DEV, + .device = NHLT_PDM_DEV_CAVS15, .direction = NHLT_DIR_CAPTURE, .vid = NHLT_VID, .did = NHLT_DID_DMIC, From eecaf360de2ae3068f51746a64e943c8d18a4f6f Mon Sep 17 00:00:00 2001 From: Benjamin Doron Date: Tue, 4 Aug 2020 06:45:46 +0000 Subject: [PATCH 05/34] soc/intel/skylake: Support NHLT 1ch DMIC Allows advertising support for a 1ch array DMIC in the NHLT table. Boards use the NHLT if a microphone is connected to the DSP. Tested on an Acer Aspire VN7-572G (Skylake-U) on Windows 10. A custom ALSA topology will be required for Linux. Change-Id: Idba3a714faab5ca1958de7dcfc0fc667c60ea7fd Signed-off-by: Benjamin Doron Reviewed-on: https://review.coreboot.org/c/coreboot/+/43072 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/skylake/Kconfig | 6 +++++ src/soc/intel/skylake/nhlt/Makefile.inc | 5 ++++ src/soc/intel/skylake/nhlt/dmic.c | 36 +++++++++++++++++++++++++ 3 files changed, 47 insertions(+) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index ed81e2470b..ba3af84fc7 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -161,6 +161,12 @@ config SKYLAKE_SOC_PCH_H help Choose this option if you have a PCH-H chipset. +config NHLT_DMIC_1CH + bool + default n + help + Include DSP firmware settings for 1 channel DMIC array. + config NHLT_DMIC_2CH bool default n diff --git a/src/soc/intel/skylake/nhlt/Makefile.inc b/src/soc/intel/skylake/nhlt/Makefile.inc index 5c8bd80e3c..7596492f48 100644 --- a/src/soc/intel/skylake/nhlt/Makefile.inc +++ b/src/soc/intel/skylake/nhlt/Makefile.inc @@ -15,6 +15,7 @@ else NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/skylake/nhlt-blobs endif +DMIC_1CH_48KHZ_16B = dmic-1ch-48khz-16b.bin DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin DMIC_2CH_48KHZ_32B = dmic-2ch-48khz-32b.bin DMIC_4CH_48KHZ_16B = dmic-4ch-48khz-16b.bin @@ -31,6 +32,10 @@ SSM4567_RENDER = ssm4567-render-2ch-48khz-24b.bin SSM4567_CAPTURE = ssm4567-capture-4ch-48khz-32b.bin DA7219_RENDER_CAPTURE = dialog-2ch-48khz-24b.bin +cbfs-files-$(CONFIG_NHLT_DMIC_1CH) += $(DMIC_1CH_48KHZ_16B) +$(DMIC_1CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_1CH_48KHZ_16B) +$(DMIC_1CH_48KHZ_16B)-type := raw + cbfs-files-$(CONFIG_NHLT_DMIC_2CH) += $(DMIC_2CH_48KHZ_16B) $(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B) $(DMIC_2CH_48KHZ_16B)-type := raw diff --git a/src/soc/intel/skylake/nhlt/dmic.c b/src/soc/intel/skylake/nhlt/dmic.c index 76c1990826..b8802a6b2c 100644 --- a/src/soc/intel/skylake/nhlt/dmic.c +++ b/src/soc/intel/skylake/nhlt/dmic.c @@ -2,6 +2,39 @@ #include +static const struct nhlt_format_config dmic_1ch_formats[] = { + /* 48 KHz 16-bits per sample. */ + { + .num_channels = 1, + .sample_freq_khz = 48, + .container_bits_per_sample = 16, + .valid_bits_per_sample = 16, + .speaker_mask = SPEAKER_FRONT_CENTER, + .settings_file = "dmic-1ch-48khz-16b.bin", + }, +}; + +static const struct nhlt_dmic_array_config dmic_1ch_mic_config = { + .tdm_config = { + .config_type = NHLT_TDM_BASIC, + }, + .array_type = NHLT_MIC_ARRAY_VENDOR_DEFINED, +}; + +static const struct nhlt_endp_descriptor dmic_1ch_descriptors[] = { + { + .link = NHLT_LINK_PDM, + .device = NHLT_PDM_DEV_CAVS15, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_DMIC, + .cfg = &dmic_1ch_mic_config, + .cfg_size = sizeof(dmic_1ch_mic_config), + .formats = dmic_1ch_formats, + .num_formats = ARRAY_SIZE(dmic_1ch_formats), + }, +}; + static const struct nhlt_format_config dmic_2ch_formats[] = { /* 48 KHz 16-bits per sample. */ { @@ -91,6 +124,9 @@ static const struct nhlt_endp_descriptor dmic_4ch_descriptors[] = { int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels) { switch (num_channels) { + case 1: + return nhlt_add_endpoints(nhlt, dmic_1ch_descriptors, + ARRAY_SIZE(dmic_1ch_descriptors)); case 2: return nhlt_add_endpoints(nhlt, dmic_2ch_descriptors, ARRAY_SIZE(dmic_2ch_descriptors)); From b3b4ccfb26b88e7d78f15f2d62f9d46e4b1302ac Mon Sep 17 00:00:00 2001 From: Zhuohao Lee Date: Mon, 23 Nov 2020 11:41:25 +0800 Subject: [PATCH 06/34] mb/google/volteer: fw_config: Add setting for new sd readers This patch adds three settings for the new sd readers. The new assigned values are: 1. RTS5227S: 3 2. L9750: 4 3. SD_OZ711LV2LN: 5 BUG=b:173676531 BRANCH=volteer TEST=abuild -t google/volteer Change-Id: I595695f99d3298f146fcdb7c2b942ce007ae9327 Signed-off-by: Zhuohao Lee Reviewed-on: https://review.coreboot.org/c/coreboot/+/47856 Tested-by: build bot (Jenkins) Reviewed-by: Caveh Jalali --- src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 1590415d96..7964885ffa 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -37,6 +37,9 @@ fw_config option SD_ABSENT 0 option SD_GL9755S 1 option SD_RTS5261 2 + option SD_RTS5227S 3 + option SD_L9750 4 + option SD_OZ711LV2LN 5 end field KB_LAYOUT 20 21 option KB_LAYOUT_DEFAULT 0 From f4f332dba992212165b4d8b755a220d27c267c01 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 19 Nov 2020 14:23:46 +0100 Subject: [PATCH 07/34] soc/intel/xeon_sp: Hook up the PMC driver The soc code was already there but it was never linked. Change-Id: I75ee08dab524bc40f1630612f93cbd42025b6d4e Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/47763 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 5c7a667d2f..ea38dfda01 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -50,6 +50,8 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_P2SB + select SOC_INTEL_COMMON_BLOCK_PMC + select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE select TSC_MONOTONIC_TIMER select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS @@ -57,6 +59,8 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_CAR select NO_SMM + select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select REG_SCRIPT config MAINBOARD_USES_FSP2_0 bool From f4721246db125e08b5e60a8a38a08cb92c478bd3 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 19 Nov 2020 16:20:27 +0100 Subject: [PATCH 08/34] soc/intel/xeon_sp: Select INTEL_COMMON_BLOCK_TCO TCO is configured by FSP. This mostly makes it possible to report TCO events in SMM if enabled. Change-Id: I4f81c7888e45ed01ee68b1d6e6a9986a4d735467 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/47764 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/Kconfig | 1 + .../intel/xeon_sp/cpx/include/soc/pci_devs.h | 2 ++ src/soc/intel/xeon_sp/include/soc/smbus.h | 23 +++++++++++++++++++ src/soc/intel/xeon_sp/pmc.c | 22 ++++++++++++++++++ .../intel/xeon_sp/skx/include/soc/pci_devs.h | 2 ++ 5 files changed, 50 insertions(+) create mode 100644 src/soc/intel/xeon_sp/include/soc/smbus.h diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index ea38dfda01..2b1034b206 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -52,6 +52,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_P2SB select SOC_INTEL_COMMON_BLOCK_PMC select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE + select SOC_INTEL_COMMON_BLOCK_TCO select TSC_MONOTONIC_TIMER select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index bcb26414d3..53503dfb88 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -102,10 +102,12 @@ #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) #define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) #define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) +#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4) #define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) #define PCH_DEV_LPC _PCH_DEV(LPC, 0) #define PCH_DEV_P2SB _PCH_DEV(LPC, 1) #define PCH_DEV_PMC _PCH_DEV(LPC, 2) +#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) #define PCH_DEV_SPI _PCH_DEV(LPC, 5) #define HPET_BUS_NUM 0x0 diff --git a/src/soc/intel/xeon_sp/include/soc/smbus.h b/src/soc/intel/xeon_sp/include/soc/smbus.h new file mode 100644 index 0000000000..00aae2cbe8 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/smbus.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_SMBUS_H_ +#define _SOC_SMBUS_H_ + +/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ +#define TCO1_STS 0x04 +#define TCO_TIMEOUT (1 << 3) +#define TCO2_STS 0x06 +#define TCO_STS_SECOND_TO (1 << 1) +#define TCO_INTRD_DET (1 << 0) +#define TCO1_CNT 0x08 +#define TCO_LOCK (1 << 12) +#define TCO_TMR_HLT (1 << 11) +#define TCO2_CNT 0x0A +#define TCO_INTRD_SEL_MASK (3 << 1) +#define TCO_INTRD_SEL_SMI (1 << 2) +#define TCO_INTRD_SEL_INT (1 << 1) + +/* SMBus I/O bits. */ +#define SMBUS_SLAVE_ADDR 0x24 + +#endif diff --git a/src/soc/intel/xeon_sp/pmc.c b/src/soc/intel/xeon_sp/pmc.c index a418ae5bab..b4f86db20a 100644 --- a/src/soc/intel/xeon_sp/pmc.c +++ b/src/soc/intel/xeon_sp/pmc.c @@ -193,3 +193,25 @@ const char *const *soc_smi_sts_array(size_t *smi_arr) *smi_arr = ARRAY_SIZE(smi_sts_bits); return smi_sts_bits; } + +const char *const *soc_tco_sts_array(size_t *tco_arr) +{ + static const char *const tco_sts_bits[] = { + [0] = "NMI2SMI", + [1] = "OS_TCO", + [2] = "TCO_INT", + [3] = "TIMEOUT", + [7] = "NEWCENTURY", + [8] = "BIOSWR", + [9] = "CPUSCI", + [10] = "CPUSMI", + [12] = "CPUSERR", + [13] = "SLVSEL", + [16] = "INTRD_DET", + [17] = "SECOND_TO", + [20] = "SMLINK_SLV" + }; + + *tco_arr = ARRAY_SIZE(tco_sts_bits); + return tco_sts_bits; +} diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index cd5d553755..353955566b 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -141,10 +141,12 @@ #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) #define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) #define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) +#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4) #define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) #define PCH_DEV_LPC _PCH_DEV(LPC, 0) #define PCH_DEV_P2SB _PCH_DEV(LPC, 1) #define PCH_DEV_PMC _PCH_DEV(LPC, 2) +#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) #define PCH_DEV_SPI _PCH_DEV(LPC, 5) #define CBDMA_DEV_NUM 0x04 From 17a798b68cc6d475d5d0c14e1a4a39b14754203c Mon Sep 17 00:00:00 2001 From: Rocky Phagura Date: Thu, 8 Oct 2020 13:32:41 -0700 Subject: [PATCH 09/34] soc/intel/xeon_sp: Enable SMI handler SMI handler was not installed for Xeon_sp platforms. This enables SMM relocation and SMI handling. TESTED: - SMRR are correctly set - The save state revision is correct (0x00030101) - SMI's are properly generated and handled - SMM MSR save state are not supported, so relocate SMM on all cores in series - Verified on OCP/Deltalake mainboard. NOTE: - Code for accessing a CPU save state is not working for SMMLOADERV2, so some SMM features like GSMI, SMMSTORE, updating the ACPI GNVS pointer are not supported. - This hooks up to some soc/intel/common like TCO and ACPI GNVS. GNVS is broken and needs to be fixed separately. It is unknown if TCO is supported. This might require a cleanup in the future. Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Signed-off-by: Rocky Phagura Signed-off-by: Christian Walter Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/46231 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/Kconfig | 6 +- src/soc/intel/xeon_sp/Makefile.inc | 2 + src/soc/intel/xeon_sp/cpx/Kconfig | 4 + src/soc/intel/xeon_sp/cpx/Makefile.inc | 1 + src/soc/intel/xeon_sp/cpx/cpu.c | 13 +- src/soc/intel/xeon_sp/include/soc/nvs.h | 5 +- .../intel/xeon_sp/include/soc/smmrelocate.h | 9 ++ src/soc/intel/xeon_sp/skx/Kconfig | 4 + src/soc/intel/xeon_sp/skx/Makefile.inc | 2 +- src/soc/intel/xeon_sp/skx/cpu.c | 20 ++- src/soc/intel/xeon_sp/smihandler.c | 14 ++ src/soc/intel/xeon_sp/smmrelocate.c | 144 ++++++++++++++++++ 12 files changed, 205 insertions(+), 19 deletions(-) create mode 100644 src/soc/intel/xeon_sp/include/soc/smmrelocate.h create mode 100644 src/soc/intel/xeon_sp/smihandler.c create mode 100644 src/soc/intel/xeon_sp/smmrelocate.c diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 2b1034b206..2028a5e219 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -52,6 +52,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_P2SB select SOC_INTEL_COMMON_BLOCK_PMC select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE + select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_TCO select TSC_MONOTONIC_TIMER select UDELAY_TSC @@ -59,8 +60,11 @@ config CPU_SPECIFIC_OPTIONS select MICROCODE_BLOB_NOT_HOOKED_UP select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_CAR - select NO_SMM + select CPU_INTEL_COMMON_SMM select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select SMM_TSEG + select HAVE_SMI_HANDLER + select X86_SMM_LOADER_VERSION2 select REG_SCRIPT config MAINBOARD_USES_FSP2_0 diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 2e50e64c25..cfda7d5d87 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -12,6 +12,8 @@ ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c ramstage.c ch ramstage-y += memmap.c pch.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c pmc.c postcar-y += spi.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 28e7b83386..369d474552 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -78,6 +78,10 @@ config FSP_TEMP_RAM_SIZE documentation says this needs to be at least 128KiB, but practice show this needs to be 256KiB or more. +config IED_REGION_SIZE + hex + default 0x400000 + config SOC_INTEL_COMMON_BLOCK_P2SB def_bool y diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index b2e653e50e..a5c6848852 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -5,6 +5,7 @@ ifeq ($(CONFIG_SOC_INTEL_COOPERLAKE_SP),y) subdirs-y += ../../../../cpu/intel/turbo subdirs-y += ../../../../cpu/x86/lapic subdirs-y += ../../../../cpu/x86/mtrr +subdirs-y += ../../../../cpu/x86/smm subdirs-y += ../../../../cpu/x86/tsc subdirs-y += ../../../../cpu/intel/microcode diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index d1bcbd7977..2f4ab0663e 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -7,7 +7,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -17,6 +19,7 @@ #include #include #include +#include #include #include "chip.h" @@ -172,16 +175,16 @@ static void post_mp_init(void) /* Set Max Ratio */ set_max_turbo_freq(); - /* - * TODO: Now that all APs have been relocated as well as the BSP let SMIs - * start flowing. - */ - if (0) global_smi_enable(); + if (CONFIG(HAVE_SMI_HANDLER)) + global_smi_enable(); } static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_thread_count, + .get_smm_info = get_smm_info, + .pre_mp_smm_init = smm_initialize, + .relocation_handler = smm_relocation_handler, .get_microcode_info = get_microcode_info, .post_mp_init = post_mp_init, }; diff --git a/src/soc/intel/xeon_sp/include/soc/nvs.h b/src/soc/intel/xeon_sp/include/soc/nvs.h index becdd76570..100a442178 100644 --- a/src/soc/intel/xeon_sp/include/soc/nvs.h +++ b/src/soc/intel/xeon_sp/include/soc/nvs.h @@ -8,10 +8,13 @@ /* TODO - this requires xeon sp, server board support */ /* NOTE: We do not use intelblocks/nvs.h since it includes mostly client specific attributes */ + +/* TODO: This is not aligned with the ACPI asl code */ struct __packed global_nvs { uint8_t pcnt; /* 0x00 - Processor Count */ uint32_t cbmc; /* 0x01 - coreboot memconsole */ - uint8_t rsvd3[251]; + uint8_t uior; + uint8_t rsvd3[250]; }; #endif /* _SOC_NVS_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/smmrelocate.h b/src/soc/intel/xeon_sp/include/soc/smmrelocate.h new file mode 100644 index 0000000000..314ebd49db --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/smmrelocate.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SOC_SMMRELOCATE_H_ +#define _SOC_SMMRELOCATE_H_ + +void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size); + +#endif diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index 2e0778ee12..08242b12e7 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -59,4 +59,8 @@ config HEAP_SIZE hex default 0x80000 +config IED_REGION_SIZE + hex + default 0x400000 + endif diff --git a/src/soc/intel/xeon_sp/skx/Makefile.inc b/src/soc/intel/xeon_sp/skx/Makefile.inc index f042d36890..6ee610eded 100644 --- a/src/soc/intel/xeon_sp/skx/Makefile.inc +++ b/src/soc/intel/xeon_sp/skx/Makefile.inc @@ -8,7 +8,7 @@ subdirs-y += ../../../../cpu/x86/lapic subdirs-y += ../../../../cpu/x86/mtrr subdirs-y += ../../../../cpu/x86/tsc subdirs-y += ../../../../cpu/x86/cache -subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm +subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../../cpu/x86/smm postcar-y += soc_util.c diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c index 874bcfd6d7..d36f11be66 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/skx/cpu.c @@ -10,9 +10,13 @@ #include #include #include +#include #include #include #include "chip.h" +#include +#include + static const config_t *chip_config = NULL; @@ -197,11 +201,8 @@ static void post_mp_init(void) /* Set Max Ratio */ set_max_turbo_freq(); - /* - * TODO: Now that all APs have been relocated as well as the BSP let SMIs - * start flowing. - */ - if (0) global_smi_enable(); + if (CONFIG(HAVE_SMI_HANDLER)) + global_smi_enable(); } /* @@ -214,12 +215,9 @@ static void post_mp_init(void) static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_platform_thread_count, - //.get_smm_info = get_smm_info, /* TODO */ - .get_smm_info = NULL, - //.pre_mp_smm_init = southcluster_smm_clear_state, /* TODO */ - .pre_mp_smm_init = NULL, - //.relocation_handler = relocation_handler, /* TODO */ - .relocation_handler = NULL, + .get_smm_info = get_smm_info, + .pre_mp_smm_init = smm_initialize, + .relocation_handler = smm_relocation_handler, .post_mp_init = post_mp_init, }; diff --git a/src/soc/intel/xeon_sp/smihandler.c b/src/soc/intel/xeon_sp/smihandler.c new file mode 100644 index 0000000000..db3b429e61 --- /dev/null +++ b/src/soc/intel/xeon_sp/smihandler.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* This is needed by common SMM code */ +const smi_handler_t southbridge_smi[SMI_STS_BITS] = { + [APM_STS_BIT] = smihandler_southbridge_apmc, + [PM1_STS_BIT] = smihandler_southbridge_pm1, +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) + [TCO_STS_BIT] = smihandler_southbridge_tco, +#endif +}; diff --git a/src/soc/intel/xeon_sp/smmrelocate.c b/src/soc/intel/xeon_sp/smmrelocate.c new file mode 100644 index 0000000000..a71a740955 --- /dev/null +++ b/src/soc/intel/xeon_sp/smmrelocate.c @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void fill_in_relocation_params(struct smm_relocation_params *params) +{ + uintptr_t tseg_base; + size_t tseg_size; + + smm_region(&tseg_base, &tseg_size); + + if (!IS_ALIGNED(tseg_base, tseg_size)) { + /* + * Note SMRR2 is supported which might support base/size combinations. + * For now it looks like FSP-M always uses aligned base/size, so let's + * not care about that. + */ + printk(BIOS_WARNING, + "TSEG base not aligned with TSEG SIZE! Not setting SMRR\n"); + return; + } + + /* SMRR has 32-bits of valid address aligned to 4KiB. */ + if (!IS_ALIGNED(tseg_size, 4 * KiB)) { + printk(BIOS_WARNING, + "TSEG size not aligned to the minimum 4KiB! Not setting SMRR\n"); + return; + } + + smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); + + params->smrr_base.lo = tseg_base | MTRR_TYPE_WRBACK; + params->smrr_base.hi = 0; + params->smrr_mask.lo = ~(tseg_size - 1) | MTRR_PHYS_MASK_VALID; + params->smrr_mask.hi = 0; +} + +static void setup_ied_area(struct smm_relocation_params *params) +{ + char *ied_base; + + const struct ied_header ied = { + .signature = "INTEL RSVD", + .size = params->ied_size, + .reserved = {0}, + }; + + ied_base = (void *)params->ied_base; + + printk(BIOS_DEBUG, "IED base = 0x%08x\n", (u32)params->ied_base); + printk(BIOS_DEBUG, "IED size = 0x%08x\n", (u32)params->ied_size); + + /* Place IED header at IEDBASE. */ + memcpy(ied_base, &ied, sizeof(ied)); + + assert(params->ied_size > 1 * MiB + 32 * KiB); + + /* Zero out 32KiB at IEDBASE + 1MiB */ + memset(ied_base + 1 * MiB, 0, 32 * KiB); +} + +void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size) +{ + fill_in_relocation_params(&smm_reloc_params); + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + + if (smm_reloc_params.ied_size) + setup_ied_area(&smm_reloc_params); + + *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); +} + +static void update_save_state(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase, + struct smm_relocation_params *relo_params) +{ + u32 smbase; + u32 iedbase; + int apic_id; + em64t101_smm_state_save_area_t *save_state; + /* + * The relocated handler runs with all CPUs concurrently. Therefore + * stagger the entry points adjusting SMBASE downwards by save state + * size * CPU num. + */ + smbase = staggered_smbase; + iedbase = relo_params->ied_base; + + apic_id = cpuid_ebx(1) >> 24; + printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n apic_id=0x%x\n", + smbase, iedbase, apic_id); + + save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state)); + + save_state->smbase = smbase; + save_state->iedbase = iedbase; +} + +/* + * The relocation work is actually performed in SMM context, but the code + * resides in the ramstage module. This occurs by trampolining from the default + * SMRAM entry point to here. + */ +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase) +{ + msr_t mtrr_cap; + struct smm_relocation_params *relo_params = &smm_reloc_params; + + printk(BIOS_DEBUG, "%s : CPU %d\n", __func__, cpu); + + /* Make appropriate changes to the save state map. */ + update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); + + /* Write SMRR MSRs based on indicated support. */ + mtrr_cap = rdmsr(MTRR_CAP_MSR); + if (mtrr_cap.lo & SMRR_SUPPORTED) + write_smrr(relo_params); +} + +void smm_initialize(void) +{ + /* Clear the SMM state in the southbridge. */ + smm_southbridge_clear_state(); + /* Run the relocation handler for on the BSP . */ + smm_initiate_relocation(); +} + +void smm_relocate(void) +{ + /* Save states via MSR does not seem to be supported on CPX */ + if (!boot_cpu()) + smm_initiate_relocation(); +} From c5395bc95d28927b81cbf97741cf80fa0e0e78c1 Mon Sep 17 00:00:00 2001 From: Sheng-Liang Pan Date: Mon, 23 Nov 2020 16:06:44 +0800 Subject: [PATCH 10/34] mb/google/volteer/var/voxel: Update DPTF parameters update the DPTF parameters received from the thermal team. BUG=b:167523658 TEST=emerge-volteer coreboot Signed-off-by: Pan Sheng-Liang Change-Id: Iafc3fb389ade5cfec79a816a28880262bdce7c74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47858 Reviewed-by: Tim Wawrzynczak Reviewed-by: Sumeet R Pawnikar Tested-by: build bot (Jenkins) --- .../google/volteer/variants/voxel/overridetree.cb | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index dd29553e82..9c4aa47d2f 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -23,22 +23,22 @@ chip soc/intel/tigerlake ## Active Policy register "policies.active" = "{ [0] = {.target = DPTF_CPU, - .thresholds = {TEMP_PCT(94, 100),}}, + .thresholds = {TEMP_PCT(98, 100),}}, [1] = {.target = DPTF_TEMP_SENSOR_2, .thresholds = {TEMP_PCT(64, 100), TEMP_PCT(60, 90), TEMP_PCT(56, 80), TEMP_PCT(52, 70), - TEMP_PCT(48, 60), - TEMP_PCT(44, 50), - TEMP_PCT(40, 40),}}}" + TEMP_PCT(47, 60), + TEMP_PCT(42, 50), + TEMP_PCT(35, 40),}}}" ## Passive Policy register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000), [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000), - [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 54, 6000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 52, 6000), [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}" ## Critical Policy @@ -58,7 +58,7 @@ chip soc/intel/tigerlake .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200,}, - .pl2 = {.min_power = 15000, + .pl2 = {.min_power = 51000, .max_power = 51000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, From 8e021d96b3c1844093f9d692bd8a30364bd0e9a9 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 3 Nov 2020 00:45:25 +0100 Subject: [PATCH 11/34] mb/**/cmos.layout: Drop copy-pasted SNB entries on non-SNB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Only Sandy Bridge MRC stores scrambler seeds in CMOS. Non-Sandybridge boards ended up with these entries because of copy-paste programming. Change-Id: I5a5bda6ea4e63ba03a4219bb2a6aa546bb6ecd7a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47149 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/asrock/h110m/cmos.layout | 4 ---- src/mainboard/google/auron/cmos.layout | 4 ---- src/mainboard/google/beltino/cmos.layout | 4 ---- src/mainboard/google/cyan/cmos.layout | 4 ---- src/mainboard/google/glados/cmos.layout | 4 ---- src/mainboard/google/jecht/cmos.layout | 4 ---- src/mainboard/google/rambi/cmos.layout | 4 ---- src/mainboard/google/slippy/cmos.layout | 4 ---- src/mainboard/intel/kblrvp/cmos.layout | 4 ---- src/mainboard/intel/kunimitsu/cmos.layout | 4 ---- src/mainboard/intel/strago/cmos.layout | 4 ---- src/mainboard/intel/wtm2/cmos.layout | 4 ---- 12 files changed, 48 deletions(-) diff --git a/src/mainboard/asrock/h110m/cmos.layout b/src/mainboard/asrock/h110m/cmos.layout index 929f7aaf9b..80a4d218a4 100644 --- a/src/mainboard/asrock/h110m/cmos.layout +++ b/src/mainboard/asrock/h110m/cmos.layout @@ -28,10 +28,6 @@ entries #Used by ChromeOS: 416 128 r 0 vbnv -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/google/auron/cmos.layout b/src/mainboard/google/auron/cmos.layout index 283aa1ea35..77ff74375e 100644 --- a/src/mainboard/google/auron/cmos.layout +++ b/src/mainboard/google/auron/cmos.layout @@ -26,10 +26,6 @@ entries #Used by ChromeOS: 416 128 r 0 vbnv -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/google/beltino/cmos.layout b/src/mainboard/google/beltino/cmos.layout index 283aa1ea35..77ff74375e 100644 --- a/src/mainboard/google/beltino/cmos.layout +++ b/src/mainboard/google/beltino/cmos.layout @@ -26,10 +26,6 @@ entries #Used by ChromeOS: 416 128 r 0 vbnv -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/google/cyan/cmos.layout b/src/mainboard/google/cyan/cmos.layout index 929f7aaf9b..80a4d218a4 100644 --- a/src/mainboard/google/cyan/cmos.layout +++ b/src/mainboard/google/cyan/cmos.layout @@ -28,10 +28,6 @@ entries #Used by ChromeOS: 416 128 r 0 vbnv -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/google/glados/cmos.layout b/src/mainboard/google/glados/cmos.layout index 929f7aaf9b..80a4d218a4 100644 --- a/src/mainboard/google/glados/cmos.layout +++ b/src/mainboard/google/glados/cmos.layout @@ -28,10 +28,6 @@ entries #Used by ChromeOS: 416 128 r 0 vbnv -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/google/jecht/cmos.layout b/src/mainboard/google/jecht/cmos.layout index 929f7aaf9b..80a4d218a4 100644 --- a/src/mainboard/google/jecht/cmos.layout +++ b/src/mainboard/google/jecht/cmos.layout @@ -28,10 +28,6 @@ entries #Used by ChromeOS: 416 128 r 0 vbnv -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/google/rambi/cmos.layout b/src/mainboard/google/rambi/cmos.layout index 283aa1ea35..77ff74375e 100644 --- a/src/mainboard/google/rambi/cmos.layout +++ b/src/mainboard/google/rambi/cmos.layout @@ -26,10 +26,6 @@ entries #Used by ChromeOS: 416 128 r 0 vbnv -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout index 283aa1ea35..77ff74375e 100644 --- a/src/mainboard/google/slippy/cmos.layout +++ b/src/mainboard/google/slippy/cmos.layout @@ -26,10 +26,6 @@ entries #Used by ChromeOS: 416 128 r 0 vbnv -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/intel/kblrvp/cmos.layout b/src/mainboard/intel/kblrvp/cmos.layout index 929f7aaf9b..80a4d218a4 100644 --- a/src/mainboard/intel/kblrvp/cmos.layout +++ b/src/mainboard/intel/kblrvp/cmos.layout @@ -28,10 +28,6 @@ entries #Used by ChromeOS: 416 128 r 0 vbnv -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/intel/kunimitsu/cmos.layout b/src/mainboard/intel/kunimitsu/cmos.layout index 929f7aaf9b..80a4d218a4 100644 --- a/src/mainboard/intel/kunimitsu/cmos.layout +++ b/src/mainboard/intel/kunimitsu/cmos.layout @@ -28,10 +28,6 @@ entries #Used by ChromeOS: 416 128 r 0 vbnv -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/intel/strago/cmos.layout b/src/mainboard/intel/strago/cmos.layout index 929f7aaf9b..80a4d218a4 100644 --- a/src/mainboard/intel/strago/cmos.layout +++ b/src/mainboard/intel/strago/cmos.layout @@ -28,10 +28,6 @@ entries #Used by ChromeOS: 416 128 r 0 vbnv -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/intel/wtm2/cmos.layout b/src/mainboard/intel/wtm2/cmos.layout index 283aa1ea35..77ff74375e 100644 --- a/src/mainboard/intel/wtm2/cmos.layout +++ b/src/mainboard/intel/wtm2/cmos.layout @@ -26,10 +26,6 @@ entries #Used by ChromeOS: 416 128 r 0 vbnv -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - # coreboot config options: check sums 984 16 h 0 check_sum From de50d399a1c6ab163de25fff7740c26b9e9da4ab Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 3 Nov 2020 00:51:34 +0100 Subject: [PATCH 12/34] mb/**/cmos.layout: Drop copy-pasted `volume` entries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This option only applies to boards using the Lenovo H8 EC code. Change-Id: I3b16a61a0aa9f51a4061b1b5e58fc276e7383415 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47150 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/apple/macbookair4_2/cmos.layout | 1 - src/mainboard/hp/snb_ivb_laptops/cmos.layout | 2 -- src/mainboard/sapphire/pureplatinumh61/cmos.layout | 2 -- 3 files changed, 5 deletions(-) diff --git a/src/mainboard/apple/macbookair4_2/cmos.layout b/src/mainboard/apple/macbookair4_2/cmos.layout index 6a23ab6853..7f153a0ad7 100644 --- a/src/mainboard/apple/macbookair4_2/cmos.layout +++ b/src/mainboard/apple/macbookair4_2/cmos.layout @@ -18,7 +18,6 @@ entries # coreboot config options: cpu # coreboot config options: northbridge #432 5 e 11 gfx_uma_size -#440 8 h 0 volume # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/hp/snb_ivb_laptops/cmos.layout b/src/mainboard/hp/snb_ivb_laptops/cmos.layout index 31889ad24b..f7a9390101 100644 --- a/src/mainboard/hp/snb_ivb_laptops/cmos.layout +++ b/src/mainboard/hp/snb_ivb_laptops/cmos.layout @@ -28,8 +28,6 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -440 8 h 0 volume - # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/sapphire/pureplatinumh61/cmos.layout b/src/mainboard/sapphire/pureplatinumh61/cmos.layout index 8a45f420d3..979c8e28ad 100644 --- a/src/mainboard/sapphire/pureplatinumh61/cmos.layout +++ b/src/mainboard/sapphire/pureplatinumh61/cmos.layout @@ -15,8 +15,6 @@ entries # coreboot config options: console 395 4 e 6 debug_level -400 8 h 0 volume - # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail From d5f1c088164d03a501fb94217bca94ffd382079e Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Fri, 20 Nov 2020 12:42:28 +0000 Subject: [PATCH 13/34] include/device/pci_ids.h: Add PCI IDs used in Lynxpoint chipsets MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Used documents: - 328904-003 - 329003-003 Change-Id: I95790cda6f7c42a9de57bf5e92eb829ee1807dbe Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/47807 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/include/device/pci_ids.h | 55 ++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index ebf02a8fd1..c123002b75 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2777,6 +2777,9 @@ #define PCI_DID_INTEL_IBEXPEAK_HECI1 0x3b64 #define PCI_DID_INTEL_IBEXPEAK_THERMAL 0x3b32 +/* Intel SDMA device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_LP_SDMA 0x9c60 + /* Intel LPC device ids */ #define PCI_DEVICE_ID_INTEL_LPT_MOBILE_SAMPLE 0x8c41 #define PCI_DEVICE_ID_INTEL_LPT_DESKTOP_SAMPLE 0x8c42 @@ -2989,6 +2992,21 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_31 0x7a9f /* Intel PCIE device ids */ +#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP1 0x8c10 +#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP2 0x8c12 +#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP3 0x8c14 +#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP4 0x8c16 +#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP5 0x8c18 +#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP6 0x8c1a +#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP7 0x8c1c +#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP8 0x8c1e +#define PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP1 0x9c10 +#define PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP2 0x9c12 +#define PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP3 0x9c14 +#define PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP4 0x9c16 +#define PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP5 0x9c18 +#define PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP6 0x9c1a + #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10 #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP2 0x9d11 #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP3 0x9d12 @@ -3268,6 +3286,23 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP28 0x7acb /* Intel SATA device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_IDE 0x8c00 +#define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_AHCI 0x8c02 +#define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_RAID_1 0x8c04 +#define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_RAID_PREM 0x8c06 +#define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_IDE_P45 0x8c08 +#define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_RAID_2 0x8c0e +#define PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_IDE 0x8c01 +#define PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_AHCI 0x8c03 +#define PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_RAID_1 0x8c05 +#define PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_RAID_PREM 0x8c07 +#define PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_IDE_P45 0x8c09 +#define PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_RAID_2 0x8c0f +#define PCI_DEVICE_ID_INTEL_LPT_LP_SATA_AHCI 0x9c03 +#define PCI_DEVICE_ID_INTEL_LPT_LP_SATA_RAID_1 0x9c05 +#define PCI_DEVICE_ID_INTEL_LPT_LP_SATA_RAID_PREM 0x9c07 +#define PCI_DEVICE_ID_INTEL_LPT_LP_SATA_RAID_2 0x9c0f + #define PCI_DEVICE_ID_INTEL_SPT_U_SATA 0x9d03 #define PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA 0x9d07 #define PCI_DEVICE_ID_INTEL_SPT_KBL_SATA 0x282a @@ -3337,6 +3372,8 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_PMC 0x7aa1 /* Intel I2C device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_LP_I2C0 0x9c61 +#define PCI_DEVICE_ID_INTEL_LPT_LP_I2C1 0x9c62 #define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60 #define PCI_DEVICE_ID_INTEL_SPT_I2C1 0x9d61 #define PCI_DEVICE_ID_INTEL_SPT_I2C2 0x9d62 @@ -3428,6 +3465,8 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_I2C5 0x7afd /* Intel UART device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_LP_UART0 0x9c63 +#define PCI_DEVICE_ID_INTEL_LPT_LP_UART1 0x9c64 #define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27 #define PCI_DEVICE_ID_INTEL_SPT_UART1 0x9d28 #define PCI_DEVICE_ID_INTEL_SPT_UART2 0x9d66 @@ -3487,6 +3526,8 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_UART6 0x7adf /* Intel SPI device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_LP_GSPI0 0x9c65 +#define PCI_DEVICE_ID_INTEL_LPT_LP_GSPI1 0x9c66 #define PCI_DEVICE_ID_INTEL_SPT_SPI1 0x9d24 #define PCI_DEVICE_ID_INTEL_SPT_SPI2 0x9d29 #define PCI_DEVICE_ID_INTEL_SPT_SPI3 0x9d2a @@ -3786,6 +3827,8 @@ #define PCI_DEVICE_ID_INTEL_ADL_P_ID_8 0x4661 #define PCI_DEVICE_ID_INTEL_ADL_P_ID_9 0x467f /* Intel SMBUS device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_H_SMBUS 0x8c22 +#define PCI_DEVICE_ID_INTEL_LPT_LP_SMBUS 0x9c22 #define PCI_DEVICE_ID_INTEL_APL_SMBUS 0x5ad4 #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 #define PCI_DEVICE_ID_INTEL_SPT_H_SMBUS 0xa123 @@ -3802,7 +3845,14 @@ #define PCI_DEVICE_ID_INTEL_ADP_P_SMBUS 0xa0a3 #define PCI_DEVICE_ID_INTEL_ADP_S_SMBUS 0x7aa3 +/* Intel EHCI device IDs */ +#define PCI_DEVICE_ID_INTEL_LPT_H_EHCI_1 0x8c26 +#define PCI_DEVICE_ID_INTEL_LPT_H_EHCI_2 0x8c2d +#define PCI_DEVICE_ID_INTEL_LPT_LP_EHCI 0x9c26 + /* Intel XHCI device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_H_XHCI 0x8c31 +#define PCI_DEVICE_ID_INTEL_LPT_LP_XHCI 0x9c31 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 #define PCI_DEVICE_ID_INTEL_GLK_XHCI 0x31a8 #define PCI_DEVICE_ID_INTEL_SPT_LP_XHCI 0x9d2f @@ -3856,6 +3906,8 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_SRAM 0x7aa7 /* Intel AUDIO device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_H_AUDIO 0x8c20 +#define PCI_DEVICE_ID_INTEL_LPT_LP_AUDIO 0x9c20 #define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98 #define PCI_DEVICE_ID_INTEL_GLK_AUDIO 0x3198 #define PCI_DEVICE_ID_INTEL_CNL_AUDIO 0x9dc8 @@ -3883,6 +3935,8 @@ #define PCI_DEVICE_ID_INTEL_ADP_P_AUDIO 0x51c8 /* Intel HECI/ME device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_H_MEI 0x8c3a +#define PCI_DEVICE_ID_INTEL_LPT_LP_MEI 0x9c3a #define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a #define PCI_DEVICE_ID_INTEL_GLK_CSE0 0x319a #define PCI_DEVICE_ID_INTEL_CNL_CSE0 0x9de0 @@ -3932,6 +3986,7 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_XDCI 0x7ae1 /* Intel SD device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_LP_SD 0x9c35 #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca #define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca #define PCI_DEVICE_ID_INTEL_SKL_SD 0x9d2d From 4ea08f9f5668cec116478a2fc226945c0a66259a Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Fri, 20 Nov 2020 12:56:44 +0000 Subject: [PATCH 14/34] sb/intel/lynxpoint: Replace hard-coded IDs with defines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace hard-coded IDs with defines introduced in CB:47807. Used documents: - 328904-003 - 329003-003 Built lenovo/t440p with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I910ab356dd8728c316018989bfb2689d4c67c2dc Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/47808 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/southbridge/intel/lynxpoint/azalia.c | 6 +++- src/southbridge/intel/lynxpoint/lpc.c | 41 +++++++++++----------- src/southbridge/intel/lynxpoint/me_9.x.c | 4 +-- src/southbridge/intel/lynxpoint/pcie.c | 18 +++++++--- src/southbridge/intel/lynxpoint/sata.c | 19 ++++++++-- src/southbridge/intel/lynxpoint/serialio.c | 16 ++++----- src/southbridge/intel/lynxpoint/smbus.c | 3 +- src/southbridge/intel/lynxpoint/usb_ehci.c | 7 +++- src/southbridge/intel/lynxpoint/usb_xhci.c | 8 +++-- 9 files changed, 79 insertions(+), 43 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index 68958f08d0..ef450a501f 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -132,7 +132,11 @@ static struct device_operations azalia_ops = { .ops_pci = &pci_dev_ops_pci, }; -static const unsigned short pci_device_ids[] = { 0x8c20, 0x9c20, 0 }; +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_LPT_H_AUDIO, + PCI_DEVICE_ID_INTEL_LPT_LP_AUDIO, + 0 +}; static const struct pci_driver pch_azalia __pci_driver = { .ops = &azalia_ops, diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 232ad2ec95..915c181c2f 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -787,26 +787,27 @@ static struct device_operations device_ops = { /* IDs for LPC device of Intel 8 Series Chipset (Lynx Point) */ static const unsigned short pci_device_ids[] = { - 0x8c41, /* Mobile Full Featured Engineering Sample. */ - 0x8c42, /* Desktop Full Featured Engineering Sample. */ - 0x8c44, /* Z87 SKU */ - 0x8c46, /* Z85 SKU */ - 0x8c49, /* HM86 SKU */ - 0x8c4a, /* H87 SKU */ - 0x8c4b, /* HM87 SKU */ - 0x8c4c, /* Q85 SKU */ - 0x8c4e, /* Q87 SKU */ - 0x8c4f, /* QM87 SKU */ - 0x8c50, /* B85 SKU */ - 0x8c52, /* C222 SKU */ - 0x8c54, /* C224 SKU */ - 0x8c56, /* C226 SKU */ - 0x8c5c, /* H81 SKU */ - 0x9c41, /* LP Full Featured Engineering Sample */ - 0x9c43, /* LP Premium SKU */ - 0x9c45, /* LP Mainstream SKU */ - 0x9c47, /* LP Value SKU */ - 0 }; + PCI_DEVICE_ID_INTEL_LPT_MOBILE_SAMPLE, + PCI_DEVICE_ID_INTEL_LPT_DESKTOP_SAMPLE, + PCI_DEVICE_ID_INTEL_LPT_Z87, + PCI_DEVICE_ID_INTEL_LPT_Z85, + PCI_DEVICE_ID_INTEL_LPT_HM86, + PCI_DEVICE_ID_INTEL_LPT_H87, + PCI_DEVICE_ID_INTEL_LPT_HM87, + PCI_DEVICE_ID_INTEL_LPT_Q85, + PCI_DEVICE_ID_INTEL_LPT_Q87, + PCI_DEVICE_ID_INTEL_LPT_QM87, + PCI_DEVICE_ID_INTEL_LPT_B85, + PCI_DEVICE_ID_INTEL_LPT_C222, + PCI_DEVICE_ID_INTEL_LPT_C224, + PCI_DEVICE_ID_INTEL_LPT_C226, + PCI_DEVICE_ID_INTEL_LPT_H81, + PCI_DEVICE_ID_INTEL_LPT_LP_SAMPLE, + PCI_DEVICE_ID_INTEL_LPT_LP_PREMIUM, + PCI_DEVICE_ID_INTEL_LPT_LP_MAINSTREAM, + PCI_DEVICE_ID_INTEL_LPT_LP_VALUE, + 0 +}; static const struct pci_driver pch_lpc __pci_driver = { .ops = &device_ops, diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index f32ee5bf67..9910658b82 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -836,8 +836,8 @@ static struct device_operations device_ops = { }; static const unsigned short pci_device_ids[] = { - 0x8c3a, /* Mobile */ - 0x9c3a, /* Low Power */ + PCI_DEVICE_ID_INTEL_LPT_H_MEI, + PCI_DEVICE_ID_INTEL_LPT_LP_MEI, 0 }; diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 19eb9fa396..5f21e619a5 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -749,10 +749,20 @@ static struct device_operations device_ops = { }; static const unsigned short pci_device_ids[] = { - /* Lynxpoint Mobile */ - 0x8c10, 0x8c12, 0x8c14, 0x8c16, 0x8c18, 0x8c1a, 0x8c1c, 0x8c1e, - /* Lynxpoint Low Power */ - 0x9c10, 0x9c12, 0x9c14, 0x9c16, 0x9c18, 0x9c1a, + PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP1, + PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP2, + PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP3, + PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP4, + PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP5, + PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP6, + PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP7, + PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP8, + PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP1, + PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP2, + PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP3, + PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP4, + PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP5, + PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP6, 0 }; diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 6899e81351..a0a606dfbb 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -214,9 +214,22 @@ static struct device_operations sata_ops = { }; static const unsigned short pci_device_ids[] = { - 0x8c00, 0x8c02, 0x8c04, 0x8c06, 0x8c08, 0x8c0e, /* Desktop */ - 0x8c01, 0x8c03, 0x8c05, 0x8c07, 0x8c09, 0x8c0f, /* Mobile */ - 0x9c03, 0x9c05, 0x9c07, 0x9c0f, /* Low Power */ + PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_IDE, + PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_AHCI, + PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_RAID_1, + PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_RAID_PREM, + PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_IDE_P45, + PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_RAID_2, + PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_IDE, + PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_AHCI, + PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_RAID_1, + PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_RAID_PREM, + PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_IDE_P45, + PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_RAID_2, + PCI_DEVICE_ID_INTEL_LPT_LP_SATA_AHCI, + PCI_DEVICE_ID_INTEL_LPT_LP_SATA_RAID_1, + PCI_DEVICE_ID_INTEL_LPT_LP_SATA_RAID_PREM, + PCI_DEVICE_ID_INTEL_LPT_LP_SATA_RAID_2, 0 }; diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 199cf9f896..d212d88621 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -228,14 +228,14 @@ static struct device_operations device_ops = { }; static const unsigned short pci_device_ids[] = { - 0x9c60, /* 0:15.0 - SDMA */ - 0x9c61, /* 0:15.1 - I2C0 */ - 0x9c62, /* 0:15.2 - I2C1 */ - 0x9c65, /* 0:15.3 - SPI0 */ - 0x9c66, /* 0:15.4 - SPI1 */ - 0x9c63, /* 0:15.5 - UART0 */ - 0x9c64, /* 0:15.6 - UART1 */ - 0x9c35, /* 0:17.0 - SDIO */ + PCI_DEVICE_ID_INTEL_LPT_LP_SDMA, + PCI_DEVICE_ID_INTEL_LPT_LP_I2C0, + PCI_DEVICE_ID_INTEL_LPT_LP_I2C1, + PCI_DEVICE_ID_INTEL_LPT_LP_GSPI0, + PCI_DEVICE_ID_INTEL_LPT_LP_GSPI1, + PCI_DEVICE_ID_INTEL_LPT_LP_UART0, + PCI_DEVICE_ID_INTEL_LPT_LP_UART1, + PCI_DEVICE_ID_INTEL_LPT_LP_SD, 0 }; diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index 2741951a4e..d0a621eea1 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -80,7 +80,8 @@ static struct device_operations smbus_ops = { }; static const unsigned short pci_device_ids[] = { - 0x8c22, 0x9c22, + PCI_DEVICE_ID_INTEL_LPT_H_SMBUS, + PCI_DEVICE_ID_INTEL_LPT_LP_SMBUS, 0 }; diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index f121aa84ce..d718ab3280 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -169,7 +169,12 @@ static struct device_operations usb_ehci_ops = { .ops_pci = &lops_pci, }; -static const unsigned short pci_device_ids[] = { 0x9c26, 0x8c26, 0x8c2d, 0 }; +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_LPT_LP_EHCI, + PCI_DEVICE_ID_INTEL_LPT_H_EHCI_1, + PCI_DEVICE_ID_INTEL_LPT_H_EHCI_2, + 0 +}; static const struct pci_driver pch_usb_ehci __pci_driver = { .ops = &usb_ehci_ops, diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 6a58d41a18..d4611a77db 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -342,9 +342,11 @@ static struct device_operations usb_xhci_ops = { .ops_pci = &pci_dev_ops_pci, }; -static const unsigned short pci_device_ids[] = { 0x8c31, /* LynxPoint-H */ - 0x9c31, /* LynxPoint-LP */ - 0 }; +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_LPT_H_XHCI, + PCI_DEVICE_ID_INTEL_LPT_LP_XHCI, + 0 +}; static const struct pci_driver pch_usb_xhci __pci_driver = { .ops = &usb_xhci_ops, From f84e304ea1e22228872c092bf2292d5e3078db24 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sun, 22 Nov 2020 16:43:09 +0000 Subject: [PATCH 15/34] mb/kontron/bsl6: Use include folder for header files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Id73a7385f7701920efebaa3e293ac50a6ba93272 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/47849 Reviewed-by: Nico Huber Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/kontron/bsl6/Makefile.inc | 2 ++ src/mainboard/kontron/bsl6/{ => include/mainboard}/gpio.h | 0 src/mainboard/kontron/bsl6/{ => include}/variant.h | 0 src/mainboard/kontron/bsl6/ramstage.c | 2 +- src/mainboard/kontron/bsl6/romstage.c | 3 +-- src/mainboard/kontron/bsl6/variants/boxer26/romstage.c | 3 +-- src/mainboard/kontron/bsl6/variants/bsl6/romstage.c | 3 +-- 7 files changed, 6 insertions(+), 7 deletions(-) rename src/mainboard/kontron/bsl6/{ => include/mainboard}/gpio.h (100%) rename src/mainboard/kontron/bsl6/{ => include}/variant.h (100%) diff --git a/src/mainboard/kontron/bsl6/Makefile.inc b/src/mainboard/kontron/bsl6/Makefile.inc index 1e12ee479b..49c9a6c570 100644 --- a/src/mainboard/kontron/bsl6/Makefile.inc +++ b/src/mainboard/kontron/bsl6/Makefile.inc @@ -1,5 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + bootblock-y += bootblock.c romstage-y += variants/$(VARIANT_DIR)/romstage.c diff --git a/src/mainboard/kontron/bsl6/gpio.h b/src/mainboard/kontron/bsl6/include/mainboard/gpio.h similarity index 100% rename from src/mainboard/kontron/bsl6/gpio.h rename to src/mainboard/kontron/bsl6/include/mainboard/gpio.h diff --git a/src/mainboard/kontron/bsl6/variant.h b/src/mainboard/kontron/bsl6/include/variant.h similarity index 100% rename from src/mainboard/kontron/bsl6/variant.h rename to src/mainboard/kontron/bsl6/include/variant.h diff --git a/src/mainboard/kontron/bsl6/ramstage.c b/src/mainboard/kontron/bsl6/ramstage.c index 2664a4ff82..b26c62fc85 100644 --- a/src/mainboard/kontron/bsl6/ramstage.c +++ b/src/mainboard/kontron/bsl6/ramstage.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include "gpio.h" +#include void mainboard_silicon_init_params(FSP_SIL_UPD *params) { diff --git a/src/mainboard/kontron/bsl6/romstage.c b/src/mainboard/kontron/bsl6/romstage.c index 9d9169c0d2..0cb7b06375 100644 --- a/src/mainboard/kontron/bsl6/romstage.c +++ b/src/mainboard/kontron/bsl6/romstage.c @@ -8,8 +8,7 @@ #include #include #include - -#include "variant.h" +#include /* Rcomp resistor */ static const u16 rcomp_resistors[3] = { 121, 75, 100 }; diff --git a/src/mainboard/kontron/bsl6/variants/boxer26/romstage.c b/src/mainboard/kontron/bsl6/variants/boxer26/romstage.c index 9c14d84ea7..f1409e0b42 100644 --- a/src/mainboard/kontron/bsl6/variants/boxer26/romstage.c +++ b/src/mainboard/kontron/bsl6/variants/boxer26/romstage.c @@ -5,8 +5,7 @@ #include #include #include - -#include "../../variant.h" +#include void variant_memory_init_params(FSPM_UPD *const mupd) { diff --git a/src/mainboard/kontron/bsl6/variants/bsl6/romstage.c b/src/mainboard/kontron/bsl6/variants/bsl6/romstage.c index 8b32bf5bf6..c9122c1c24 100644 --- a/src/mainboard/kontron/bsl6/variants/bsl6/romstage.c +++ b/src/mainboard/kontron/bsl6/variants/bsl6/romstage.c @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include - -#include "../../variant.h" +#include void variant_memory_init_params(FSPM_UPD *const mupd) { From 12e5fda49602812b85f9be76eaecdfe4954544bc Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sun, 22 Nov 2020 17:22:53 +0000 Subject: [PATCH 16/34] mb/kontron/bsl6: Move GPIO configuration to C file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I008de1bf91ba97ee5eefbde11947c73059fff5f7 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/47851 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Michael Niewöhner --- src/mainboard/kontron/bsl6/Makefile.inc | 2 +- src/mainboard/kontron/bsl6/gpio.c | 226 ++++++++++++++++++ .../kontron/bsl6/include/mainboard/gpio.h | 224 +---------------- src/mainboard/kontron/bsl6/ramstage.c | 2 +- 4 files changed, 229 insertions(+), 225 deletions(-) create mode 100644 src/mainboard/kontron/bsl6/gpio.c diff --git a/src/mainboard/kontron/bsl6/Makefile.inc b/src/mainboard/kontron/bsl6/Makefile.inc index 49c9a6c570..5164272950 100644 --- a/src/mainboard/kontron/bsl6/Makefile.inc +++ b/src/mainboard/kontron/bsl6/Makefile.inc @@ -6,6 +6,6 @@ bootblock-y += bootblock.c romstage-y += variants/$(VARIANT_DIR)/romstage.c +ramstage-y += gpio.c ramstage-y += ramstage.c - ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads diff --git a/src/mainboard/kontron/bsl6/gpio.c b/src/mainboard/kontron/bsl6/gpio.c new file mode 100644 index 0000000000..c99a53d4b3 --- /dev/null +++ b/src/mainboard/kontron/bsl6/gpio.c @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), + PAD_CFG_GPI_INT(GPP_A7, NONE, PLTRST, OFF), + PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A9, DN_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A10, DN_20K, PLTRST, NF1), + PAD_CFG_GPI_INT(GPP_A11, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_A12, 1, PLTRST), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), + PAD_CFG_GPI_INT(GPP_A16, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_A19, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_A20, 1, DEEP), + PAD_CFG_GPO(GPP_A21, 1, DEEP), + PAD_CFG_GPO(GPP_A22, 1, DEEP), + PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, OFF), + + PAD_CFG_GPI_INT(GPP_B0, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B1, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B2, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_B3, 1, DEEP), + PAD_CFG_NF(GPP_B4, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_B6, 1, DEEP), + PAD_CFG_GPO(GPP_B7, 1, DEEP), + PAD_CFG_GPO(GPP_B8, 1, DEEP), + PAD_CFG_GPO(GPP_B9, 1, DEEP), + PAD_CFG_GPO(GPP_B10, 1, DEEP), + PAD_CFG_GPI_INT(GPP_B11, NONE, PLTRST, OFF), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), + PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B16, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_B17, 1, DEEP), + PAD_CFG_GPI_INT(GPP_B18, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B19, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B20, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B21, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B22, NONE, PLTRST, OFF), + PAD_CFG_TERM_GPO(GPP_B23, 1, UP_20K, DEEP), + + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + PAD_CFG_GPI_SCI(GPP_C2, NONE, DEEP, EDGE_SINGLE, INVERT), + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + PAD_CFG_GPI_INT(GPP_C5, NONE, PLTRST, OFF), + /* XXX: C6 not readable */ + /* XXX: C7 not readable */ + PAD_CFG_NF(GPP_C8, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C9, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C10, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C11, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C12, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C13, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C14, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C15, NONE, PLTRST, NF1), + PAD_CFG_GPI_INT(GPP_C16, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_C17, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_C18, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_C19, NONE, PLTRST, OFF), + PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C22, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C23, NONE, PLTRST, NF1), + + PAD_CFG_GPO(GPP_D0, 1, DEEP), + PAD_CFG_GPI_INT(GPP_D1, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPP_D2, NONE, DEEP, OFF), + PAD_CFG_GPO(GPP_D3, 1, DEEP), + PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, OFF), + PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D6, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1), + PAD_CFG_GPO(GPP_D9, 0, DEEP), + PAD_CFG_GPO(GPP_D10, 0, DEEP), + PAD_CFG_GPI_SCI_HIGH(GPP_D11, NONE, DEEP, LEVEL), + PAD_CFG_GPI_SCI_HIGH(GPP_D12, NONE, DEEP, LEVEL), + PAD_CFG_GPI_INT(GPP_D13, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_D14, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_D15, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_D16, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_D17, 0, DEEP), + PAD_CFG_GPI_INT(GPP_D18, NONE, DEEP, OFF), + PAD_CFG_GPO(GPP_D19, 0, DEEP), + PAD_CFG_GPO(GPP_D20, 0, DEEP), + PAD_CFG_GPO(GPP_D21, 1, DEEP), + PAD_CFG_GPO(GPP_D22, 0, DEEP), + PAD_CFG_GPI_INT(GPP_D23, NONE, PLTRST, OFF), + + PAD_CFG_NF(GPP_E0, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_E1, UP_20K, PLTRST, NF1), + PAD_CFG_GPI_INT(GPP_E2, NONE, PLTRST, OFF), + PAD_CFG_GPI_SCI_HIGH(GPP_E3, NONE, DEEP, LEVEL), + PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1), + PAD_CFG_GPI_INT(GPP_E5, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_E6, NONE, PLTRST, OFF), + PAD_CFG_GPI_SCI(GPP_E7, NONE, DEEP, EDGE_SINGLE, INVERT), + PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + + PAD_CFG_GPI_INT(GPP_F0, NONE, PLTRST, OFF), + PAD_CFG_NF(GPP_F1, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_F2, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_F3, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_F4, NONE, PLTRST, NF1), + PAD_CFG_GPI_SCI(GPP_F5, NONE, DEEP, EDGE_SINGLE, NONE), + PAD_CFG_NF(GPP_F6, NONE, PWROK, NF1), + PAD_CFG_GPI_INT(GPP_F7, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), + PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), + PAD_CFG_GPI_INT(GPP_F11, NONE, PLTRST, OFF), + PAD_CFG_GPI_APIC_LOW(GPP_F12, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_F13, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_F14, NONE, DEEP), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_F18, 1, PLTRST), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_F22, 1, PLTRST), + PAD_CFG_GPO(GPP_F23, 1, DEEP), + + PAD_CFG_GPO(GPP_G0, 1, PLTRST), + PAD_CFG_GPO(GPP_G1, 1, PLTRST), + PAD_CFG_GPI_SCI_LOW(GPP_G2, NONE, PLTRST, LEVEL), + PAD_CFG_GPI_SCI_LOW(GPP_G3, NONE, PLTRST, LEVEL), + PAD_CFG_GPO(GPP_G4, 1, DEEP), + PAD_CFG_GPI_APIC_HIGH(GPP_G5, NONE, PLTRST), + PAD_CFG_GPI_SCI(GPP_G6, NONE, PLTRST, EDGE_SINGLE, INVERT), + PAD_CFG_GPO(GPP_G7, 1, DEEP), + PAD_CFG_GPI_INT(GPP_G8, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G9, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G10, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G11, NONE, PLTRST, OFF), + PAD_CFG_GPI_SCI(GPP_G12, DN_20K, PLTRST, EDGE_SINGLE, INVERT), + PAD_CFG_GPO(GPP_G13, 1, PLTRST), + PAD_CFG_GPI_SCI(GPP_G14, NONE, PLTRST, EDGE_SINGLE, INVERT), + PAD_CFG_GPO(GPP_G15, 0, PLTRST), + PAD_CFG_TERM_GPO(GPP_G16, 1, DN_20K, PLTRST), + PAD_CFG_GPI_INT(GPP_G17, NONE, PLTRST, OFF), + PAD_CFG_GPI_APIC_HIGH(GPP_G18, NONE, PLTRST), + PAD_CFG_NF(GPP_G19, NONE, PLTRST, NF1), + PAD_CFG_GPI_APIC_HIGH(GPP_G20, NONE, PLTRST), + PAD_CFG_GPI_SCI(GPP_G21, NONE, DEEP, EDGE_SINGLE, INVERT), + PAD_CFG_GPO(GPP_G22, 1, PLTRST), + PAD_CFG_GPO(GPP_G23, 1, PLTRST), + + PAD_CFG_GPO(GPP_H0, 1, DEEP), + PAD_CFG_GPO(GPP_H1, 1, DEEP), + PAD_CFG_GPO(GPP_H2, 1, DEEP), + PAD_CFG_GPO(GPP_H3, 1, DEEP), + PAD_CFG_GPO(GPP_H4, 1, DEEP), + PAD_CFG_GPO(GPP_H5, 1, DEEP), + PAD_CFG_GPO(GPP_H6, 1, DEEP), + PAD_CFG_GPO(GPP_H7, 1, DEEP), + PAD_CFG_GPO(GPP_H8, 1, DEEP), + PAD_CFG_GPO(GPP_H9, 1, DEEP), + PAD_CFG_GPI_INT(GPP_H10, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H11, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H12, NONE, PLTRST, OFF), + PAD_CFG_GPI_APIC_HIGH(GPP_H13, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_H14, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_H15, NONE, PLTRST), + PAD_CFG_GPI_INT(GPP_H16, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_H17, 1, PLTRST), + PAD_CFG_GPI_INT(GPP_H18, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H19, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H20, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H21, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H22, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_H23, 0, DEEP), + + PAD_CFG_GPI_INT(GPD0, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPD1, 0, PWROK), + PAD_CFG_NF(GPD2, NONE, PWROK, NF1), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_CFG_GPO(GPD7, 1, PWROK), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_CFG_GPO(GPD9, 0, PWROK), + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), + + PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I6, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I8, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I10, NONE, PLTRST, NF1), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/kontron/bsl6/include/mainboard/gpio.h b/src/mainboard/kontron/bsl6/include/mainboard/gpio.h index d6e976ee10..ef2a21c418 100644 --- a/src/mainboard/kontron/bsl6/include/mainboard/gpio.h +++ b/src/mainboard/kontron/bsl6/include/mainboard/gpio.h @@ -3,228 +3,6 @@ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H -#include -#include - -#ifndef __ACPI__ - -/* Pad configuration in ramstage. */ -static const struct pad_config gpio_table[] = { - PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), - PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), - PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), - PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), - PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), - PAD_CFG_GPI_INT(GPP_A7, NONE, PLTRST, OFF), - PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_A9, DN_20K, PLTRST, NF1), - PAD_CFG_NF(GPP_A10, DN_20K, PLTRST, NF1), - PAD_CFG_GPI_INT(GPP_A11, NONE, PLTRST, OFF), - PAD_CFG_GPO(GPP_A12, 1, PLTRST), - PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), - PAD_CFG_GPI_INT(GPP_A16, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_A19, NONE, PLTRST, OFF), - PAD_CFG_GPO(GPP_A20, 1, DEEP), - PAD_CFG_GPO(GPP_A21, 1, DEEP), - PAD_CFG_GPO(GPP_A22, 1, DEEP), - PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, OFF), - - PAD_CFG_GPI_INT(GPP_B0, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_B1, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_B2, NONE, PLTRST, OFF), - PAD_CFG_GPO(GPP_B3, 1, DEEP), - PAD_CFG_NF(GPP_B4, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), - PAD_CFG_GPO(GPP_B6, 1, DEEP), - PAD_CFG_GPO(GPP_B7, 1, DEEP), - PAD_CFG_GPO(GPP_B8, 1, DEEP), - PAD_CFG_GPO(GPP_B9, 1, DEEP), - PAD_CFG_GPO(GPP_B10, 1, DEEP), - PAD_CFG_GPI_INT(GPP_B11, NONE, PLTRST, OFF), - PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), - PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_B16, NONE, PLTRST, OFF), - PAD_CFG_GPO(GPP_B17, 1, DEEP), - PAD_CFG_GPI_INT(GPP_B18, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_B19, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_B20, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_B21, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_B22, NONE, PLTRST, OFF), - PAD_CFG_TERM_GPO(GPP_B23, 1, UP_20K, DEEP), - - PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), - PAD_CFG_GPI_SCI(GPP_C2, NONE, DEEP, EDGE_SINGLE, INVERT), - PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), - PAD_CFG_GPI_INT(GPP_C5, NONE, PLTRST, OFF), - /* XXX: C6 not readable */ - /* XXX: C7 not readable */ - PAD_CFG_NF(GPP_C8, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_C9, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_C10, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_C11, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_C12, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_C13, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_C14, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_C15, NONE, PLTRST, NF1), - PAD_CFG_GPI_INT(GPP_C16, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_C17, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_C18, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_C19, NONE, PLTRST, OFF), - PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_C22, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_C23, NONE, PLTRST, NF1), - - PAD_CFG_GPO(GPP_D0, 1, DEEP), - PAD_CFG_GPI_INT(GPP_D1, NONE, DEEP, OFF), - PAD_CFG_GPI_INT(GPP_D2, NONE, DEEP, OFF), - PAD_CFG_GPO(GPP_D3, 1, DEEP), - PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, OFF), - PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D6, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1), - PAD_CFG_GPO(GPP_D9, 0, DEEP), - PAD_CFG_GPO(GPP_D10, 0, DEEP), - PAD_CFG_GPI_SCI_HIGH(GPP_D11, NONE, DEEP, LEVEL), - PAD_CFG_GPI_SCI_HIGH(GPP_D12, NONE, DEEP, LEVEL), - PAD_CFG_GPI_INT(GPP_D13, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_D14, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_D15, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_D16, NONE, PLTRST, OFF), - PAD_CFG_GPO(GPP_D17, 0, DEEP), - PAD_CFG_GPI_INT(GPP_D18, NONE, DEEP, OFF), - PAD_CFG_GPO(GPP_D19, 0, DEEP), - PAD_CFG_GPO(GPP_D20, 0, DEEP), - PAD_CFG_GPO(GPP_D21, 1, DEEP), - PAD_CFG_GPO(GPP_D22, 0, DEEP), - PAD_CFG_GPI_INT(GPP_D23, NONE, PLTRST, OFF), - - PAD_CFG_NF(GPP_E0, UP_20K, PLTRST, NF1), - PAD_CFG_NF(GPP_E1, UP_20K, PLTRST, NF1), - PAD_CFG_GPI_INT(GPP_E2, NONE, PLTRST, OFF), - PAD_CFG_GPI_SCI_HIGH(GPP_E3, NONE, DEEP, LEVEL), - PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1), - PAD_CFG_GPI_INT(GPP_E5, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_E6, NONE, PLTRST, OFF), - PAD_CFG_GPI_SCI(GPP_E7, NONE, DEEP, EDGE_SINGLE, INVERT), - PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), - - PAD_CFG_GPI_INT(GPP_F0, NONE, PLTRST, OFF), - PAD_CFG_NF(GPP_F1, UP_20K, PLTRST, NF1), - PAD_CFG_NF(GPP_F2, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_F3, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_F4, NONE, PLTRST, NF1), - PAD_CFG_GPI_SCI(GPP_F5, NONE, DEEP, EDGE_SINGLE, NONE), - PAD_CFG_NF(GPP_F6, NONE, PWROK, NF1), - PAD_CFG_GPI_INT(GPP_F7, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), - PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), - PAD_CFG_GPI_INT(GPP_F11, NONE, PLTRST, OFF), - PAD_CFG_GPI_APIC_LOW(GPP_F12, NONE, PLTRST), - PAD_CFG_GPI_APIC_HIGH(GPP_F13, NONE, PLTRST), - PAD_CFG_GPI_APIC_LOW(GPP_F14, NONE, DEEP), - PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), - PAD_CFG_GPO(GPP_F18, 1, PLTRST), - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), - PAD_CFG_GPO(GPP_F22, 1, PLTRST), - PAD_CFG_GPO(GPP_F23, 1, DEEP), - - PAD_CFG_GPO(GPP_G0, 1, PLTRST), - PAD_CFG_GPO(GPP_G1, 1, PLTRST), - PAD_CFG_GPI_SCI_LOW(GPP_G2, NONE, PLTRST, LEVEL), - PAD_CFG_GPI_SCI_LOW(GPP_G3, NONE, PLTRST, LEVEL), - PAD_CFG_GPO(GPP_G4, 1, DEEP), - PAD_CFG_GPI_APIC_HIGH(GPP_G5, NONE, PLTRST), - PAD_CFG_GPI_SCI(GPP_G6, NONE, PLTRST, EDGE_SINGLE, INVERT), - PAD_CFG_GPO(GPP_G7, 1, DEEP), - PAD_CFG_GPI_INT(GPP_G8, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_G9, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_G10, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_G11, NONE, PLTRST, OFF), - PAD_CFG_GPI_SCI(GPP_G12, DN_20K, PLTRST, EDGE_SINGLE, INVERT), - PAD_CFG_GPO(GPP_G13, 1, PLTRST), - PAD_CFG_GPI_SCI(GPP_G14, NONE, PLTRST, EDGE_SINGLE, INVERT), - PAD_CFG_GPO(GPP_G15, 0, PLTRST), - PAD_CFG_TERM_GPO(GPP_G16, 1, DN_20K, PLTRST), - PAD_CFG_GPI_INT(GPP_G17, NONE, PLTRST, OFF), - PAD_CFG_GPI_APIC_HIGH(GPP_G18, NONE, PLTRST), - PAD_CFG_NF(GPP_G19, NONE, PLTRST, NF1), - PAD_CFG_GPI_APIC_HIGH(GPP_G20, NONE, PLTRST), - PAD_CFG_GPI_SCI(GPP_G21, NONE, DEEP, EDGE_SINGLE, INVERT), - PAD_CFG_GPO(GPP_G22, 1, PLTRST), - PAD_CFG_GPO(GPP_G23, 1, PLTRST), - - PAD_CFG_GPO(GPP_H0, 1, DEEP), - PAD_CFG_GPO(GPP_H1, 1, DEEP), - PAD_CFG_GPO(GPP_H2, 1, DEEP), - PAD_CFG_GPO(GPP_H3, 1, DEEP), - PAD_CFG_GPO(GPP_H4, 1, DEEP), - PAD_CFG_GPO(GPP_H5, 1, DEEP), - PAD_CFG_GPO(GPP_H6, 1, DEEP), - PAD_CFG_GPO(GPP_H7, 1, DEEP), - PAD_CFG_GPO(GPP_H8, 1, DEEP), - PAD_CFG_GPO(GPP_H9, 1, DEEP), - PAD_CFG_GPI_INT(GPP_H10, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_H11, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_H12, NONE, PLTRST, OFF), - PAD_CFG_GPI_APIC_HIGH(GPP_H13, NONE, PLTRST), - PAD_CFG_GPI_APIC_HIGH(GPP_H14, NONE, PLTRST), - PAD_CFG_GPI_APIC_HIGH(GPP_H15, NONE, PLTRST), - PAD_CFG_GPI_INT(GPP_H16, NONE, PLTRST, OFF), - PAD_CFG_GPO(GPP_H17, 1, PLTRST), - PAD_CFG_GPI_INT(GPP_H18, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_H19, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_H20, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_H21, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_H22, NONE, PLTRST, OFF), - PAD_CFG_GPO(GPP_H23, 0, DEEP), - - PAD_CFG_GPI_INT(GPD0, NONE, PLTRST, OFF), - PAD_CFG_GPO(GPD1, 0, PWROK), - PAD_CFG_NF(GPD2, NONE, PWROK, NF1), - PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), - PAD_CFG_NF(GPD4, NONE, PWROK, NF1), - PAD_CFG_NF(GPD5, NONE, PWROK, NF1), - PAD_CFG_NF(GPD6, NONE, PWROK, NF1), - PAD_CFG_GPO(GPD7, 1, PWROK), - PAD_CFG_NF(GPD8, NONE, PWROK, NF1), - PAD_CFG_GPO(GPD9, 0, PWROK), - PAD_CFG_NF(GPD10, NONE, PWROK, NF1), - PAD_CFG_NF(GPD11, NONE, PWROK, NF1), - - PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_I6, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_I8, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_I10, NONE, PLTRST, NF1), -}; - -#endif +void mainboard_configure_gpios(void); #endif diff --git a/src/mainboard/kontron/bsl6/ramstage.c b/src/mainboard/kontron/bsl6/ramstage.c index b26c62fc85..19518f74a4 100644 --- a/src/mainboard/kontron/bsl6/ramstage.c +++ b/src/mainboard/kontron/bsl6/ramstage.c @@ -5,5 +5,5 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params) { - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + mainboard_configure_gpios(); } From ec8f5c79a5fd16531006dd950dc3fad71c97ca8b Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sat, 21 Nov 2020 00:16:06 +0000 Subject: [PATCH 17/34] mb/clevo/kbl-u: Configure GPIOs using mainboard_ops MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hook up the mainboard_ops driver and configure the GPIOs using .init, since mainboard_silicon_init_params() is meant for the configuration of the FSP, not the GPIOs. Change-Id: I82f1eaf6693d9b117fb211776047058cdc787288 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/47825 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- src/mainboard/clevo/kbl-u/ramstage.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/mainboard/clevo/kbl-u/ramstage.c b/src/mainboard/clevo/kbl-u/ramstage.c index b5d67864a0..9368021e7f 100644 --- a/src/mainboard/clevo/kbl-u/ramstage.c +++ b/src/mainboard/clevo/kbl-u/ramstage.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include -#include /* * TODO: @@ -12,7 +12,11 @@ * - Make TBT port configurable (TBT <> DisplayPort) */ -void mainboard_silicon_init_params(FSP_SIL_UPD *params) +static void init_mainboard(void *chip_info) { mainboard_configure_gpios(); } + +struct chip_operations mainboard_ops = { + .init = init_mainboard, +}; From c19cbeeb6b4ec1f083951156e6b67d02390369b5 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 10 Nov 2020 20:39:41 +0100 Subject: [PATCH 18/34] device: Drop unused HyperTransport code Only two definitions are actually used somewhere, the rest is unused. Change-Id: Iec52d0d47fce6a1ec5455b670824b995a7a34a4c Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47407 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/device/Kconfig | 12 - src/device/Makefile.inc | 1 - src/device/hypertransport.c | 499 ------------------ src/device/pci_device.c | 14 - src/include/device/hypertransport.h | 11 - src/include/device/hypertransport_def.h | 28 - .../amd/agesa/family14/northbridge.c | 1 - .../amd/agesa/family15tn/northbridge.c | 1 - .../amd/agesa/family16kb/northbridge.c | 1 - src/northbridge/amd/agesa/nb_common.h | 3 + src/northbridge/amd/pi/00630F01/northbridge.c | 1 - src/northbridge/amd/pi/00730F01/northbridge.c | 1 - src/northbridge/amd/pi/nb_common.h | 3 + 13 files changed, 6 insertions(+), 570 deletions(-) delete mode 100644 src/device/hypertransport.c delete mode 100644 src/include/device/hypertransport.h delete mode 100644 src/include/device/hypertransport_def.h diff --git a/src/device/Kconfig b/src/device/Kconfig index d564f00b9c..a472a6abbb 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -491,18 +491,6 @@ config MMCONF_SUPPORT bool default !NO_MMCONF_SUPPORT -config HYPERTRANSPORT_PLUGIN_SUPPORT - bool - default n - -config HT_CHAIN_UNITID_BASE - int - default 0 - -config HT_CHAIN_END_UNITID_BASE - int - default 0 - config PCIX_PLUGIN_SUPPORT bool default y diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index 2fae44ab24..f5e2c685be 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -35,7 +35,6 @@ postcar-y += pci_ops.c ramstage-y += pci_ops.c smm-y += pci_ops.c -ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c deleted file mode 100644 index 068c489b05..0000000000 --- a/src/device/hypertransport.c +++ /dev/null @@ -1,499 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include - -struct ht_link { - struct device *dev; - unsigned int pos; - unsigned char ctrl_off, config_off, freq_off, freq_cap_off; -}; - -static struct device *ht_scan_get_devs(struct device **old_devices) -{ - struct device *first, *last; - - first = *old_devices; - last = first; - - /* - * Extract the chain of devices to (first through last) for the next - * hypertransport device. - */ - while (last && last->sibling && - (last->sibling->path.type == DEVICE_PATH_PCI) && - (last->sibling->path.pci.devfn > last->path.pci.devfn)) - { - last = last->sibling; - } - - if (first) { - struct device *child; - - /* Unlink the chain from the list of old devices. */ - *old_devices = last->sibling; - last->sibling = 0; - - /* Now add the device to the list of devices on the bus. */ - /* Find the last child of our parent. */ - for (child = first->bus->children; child && child->sibling;) - child = child->sibling; - - /* Place the chain on the list of children of their parent. */ - if (child) - child->sibling = first; - else - first->bus->children = first; - } - return first; -} - -static int ht_setup_link(struct ht_link *prev, struct device *dev, unsigned int pos) -{ - struct ht_link cur[1]; - int linkb_to_host; - - /* Set the hypertransport link width and frequency. */ - - /* - * See which side of the device our previous write to set the unitid - * came from. - */ - cur->dev = dev; - cur->pos = pos; - linkb_to_host = - (pci_read_config16(cur->dev, cur->pos + PCI_CAP_FLAGS) >> 10) & 1; - - if (!linkb_to_host) { - cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL0; - cur->config_off = PCI_HT_CAP_SLAVE_WIDTH0; - cur->freq_off = PCI_HT_CAP_SLAVE_FREQ0; - cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP0; - } else { - cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL1; - cur->config_off = PCI_HT_CAP_SLAVE_WIDTH1; - cur->freq_off = PCI_HT_CAP_SLAVE_FREQ1; - cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1; - } - - /* - * Remember the current link as the previous link, but look at the - * other offsets. - */ - prev->dev = cur->dev; - prev->pos = cur->pos; - if (cur->ctrl_off == PCI_HT_CAP_SLAVE_CTRL0) { - prev->ctrl_off = PCI_HT_CAP_SLAVE_CTRL1; - prev->config_off = PCI_HT_CAP_SLAVE_WIDTH1; - prev->freq_off = PCI_HT_CAP_SLAVE_FREQ1; - prev->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1; - } else { - prev->ctrl_off = PCI_HT_CAP_SLAVE_CTRL0; - prev->config_off = PCI_HT_CAP_SLAVE_WIDTH0; - prev->freq_off = PCI_HT_CAP_SLAVE_FREQ0; - prev->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP0; - } - - return 0; -} - -static unsigned int ht_lookup_slave_capability(struct device *dev) -{ - unsigned int pos; - - pos = 0; - do { - pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos); - if (pos) { - u16 flags; - flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS); - printk(BIOS_SPEW, "flags: 0x%04x\n", flags); - if ((flags >> 13) == 0) { - /* Entry is a slave secondary, success... */ - break; - } - } - } while (pos); - - return pos; -} - -static void ht_collapse_early_enumeration(struct bus *bus, - unsigned int offset_unitid) -{ - unsigned int devfn; - struct ht_link prev; - u16 ctrl; - - /* Initialize the hypertransport enumeration state. */ - prev.dev = bus->dev; - prev.pos = bus->cap; - prev.ctrl_off = PCI_HT_CAP_HOST_CTRL; - prev.config_off = PCI_HT_CAP_HOST_WIDTH; - prev.freq_off = PCI_HT_CAP_HOST_FREQ; - prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP; - - /* Wait until the link initialization is complete. */ - do { - ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off); - - /* Is this the end of the hypertransport chain? */ - if (ctrl & (1 << 6)) - return; - - /* Has the link failed? */ - if (ctrl & (1 << 4)) { - /* - * Either the link has failed, or we have a CRC error. - * Sometimes this can happen due to link retrain, so - * lets knock it down and see if its transient. - */ - ctrl |= ((1 << 4) | (1 << 8)); /* Link fail + CRC */ - pci_write_config16(prev.dev, prev.pos + prev.ctrl_off, - ctrl); - ctrl = pci_read_config16(prev.dev, - prev.pos + prev.ctrl_off); - if (ctrl & ((1 << 4) | (1 << 8))) { - printk(BIOS_ALERT, "Detected error on " - "Hypertransport link\n"); - return; - } - } - } while ((ctrl & (1 << 5)) == 0); - - /* Actually, only for one HT device HT chain, and unitid is 0. */ -#if !CONFIG_HT_CHAIN_UNITID_BASE - if (offset_unitid) - return; -#endif - - /* Check if is already collapsed. */ - if ((!offset_unitid) || (offset_unitid - && (!((CONFIG_HT_CHAIN_END_UNITID_BASE == 0) - && (CONFIG_HT_CHAIN_END_UNITID_BASE - < CONFIG_HT_CHAIN_UNITID_BASE))))) { - - struct device dummy; - u32 id; - - dummy.bus = bus; - dummy.path.type = DEVICE_PATH_PCI; - dummy.path.pci.devfn = PCI_DEVFN(0, 0); - - id = pci_read_config32(&dummy, PCI_VENDOR_ID); - if (!((id == 0xffffffff) || (id == 0x00000000) - || (id == 0x0000ffff) || (id == 0xffff0000))) { - return; - } - } - - /* Spin through the devices and collapse any early HT enumeration. */ - for (devfn = PCI_DEVFN(1, 0); devfn <= 0xff; devfn += 8) { - struct device dummy; - u32 id; - unsigned int pos, flags; - - dummy.bus = bus; - dummy.path.type = DEVICE_PATH_PCI; - dummy.path.pci.devfn = devfn; - - id = pci_read_config32(&dummy, PCI_VENDOR_ID); - if ((id == 0xffffffff) || (id == 0x00000000) - || (id == 0x0000ffff) || (id == 0xffff0000)) { - continue; - } - - dummy.vendor = id & 0xffff; - dummy.device = (id >> 16) & 0xffff; - dummy.hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE); - - pos = ht_lookup_slave_capability(&dummy); - if (!pos) - continue; - - /* Clear the unitid. */ - flags = pci_read_config16(&dummy, pos + PCI_CAP_FLAGS); - flags &= ~0x1f; - pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags); - printk(BIOS_SPEW, "Collapsing %s [%04x/%04x]\n", - dev_path(&dummy), dummy.vendor, dummy.device); - } -} - -static unsigned int do_hypertransport_scan_chain(struct bus *bus, unsigned int min_devfn, - unsigned int max_devfn, - unsigned int *ht_unitid_base, - unsigned int offset_unitid) -{ - /* - * Even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this - * function, because of end_of_chain check. Also, we need it to - * optimize link. - */ - unsigned int next_unitid, last_unitid, min_unitid, max_unitid; - struct device *old_devices, *dev, *func, *last_func = NULL; - struct ht_link prev; - int ht_dev_num = 0; - - printk(BIOS_SPEW, "%s for bus %02x\n", __func__, bus->secondary); - - min_unitid = (offset_unitid) ? CONFIG_HT_CHAIN_UNITID_BASE : 1; - -#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - /* - * Let's record the device of last HT device, so we can set the unitid - * to CONFIG_HT_CHAIN_END_UNITID_BASE. - */ - unsigned int real_last_unitid = 0, end_used = 0; - u8 real_last_pos = 0; - struct device *real_last_dev = NULL; -#endif - - /* Restore the hypertransport chain to it's uninitialized state. */ - ht_collapse_early_enumeration(bus, offset_unitid); - - /* See which static device nodes I have. */ - old_devices = bus->children; - bus->children = 0; - - /* Initialize the hypertransport enumeration state. */ - prev.dev = bus->dev; - prev.pos = bus->cap; - - prev.ctrl_off = PCI_HT_CAP_HOST_CTRL; - prev.config_off = PCI_HT_CAP_HOST_WIDTH; - prev.freq_off = PCI_HT_CAP_HOST_FREQ; - prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP; - - /* If present, assign unitid to a hypertransport chain. */ - max_unitid = next_unitid = min_unitid; - do { - u8 pos; - u16 flags, ctrl; - unsigned int count, static_count; - - last_unitid = next_unitid; - - /* Wait until the link initialization is complete. */ - do { - ctrl = pci_read_config16(prev.dev, - prev.pos + prev.ctrl_off); - - /* End of chain? */ - if (ctrl & (1 << 6)) - goto end_of_chain; - - if (ctrl & ((1 << 4) | (1 << 8))) { - /* - * Either the link has failed, or we have a CRC - * error. Sometimes this can happen due to link - * retrain, so lets knock it down and see if - * it's transient. - */ - ctrl |= ((1 << 4) | (1 <<8)); // Link fail + CRC - pci_write_config16(prev.dev, - prev.pos + prev.ctrl_off, ctrl); - ctrl = pci_read_config16(prev.dev, - prev.pos + prev.ctrl_off); - if (ctrl & ((1 << 4) | (1 << 8))) { - printk(BIOS_ALERT, "Detected error on " - "hypertransport link\n"); - goto end_of_chain; - } - } - } while ((ctrl & (1 << 5)) == 0); - - /* Get and setup the device_structure. */ - dev = ht_scan_get_devs(&old_devices); - - /* See if a device is present and setup the device structure. */ - dev = pci_probe_dev(dev, bus, 0); - if (!dev || !dev->enabled) - break; - - /* Find the hypertransport link capability. */ - pos = ht_lookup_slave_capability(dev); - if (pos == 0) { - printk(BIOS_ERR, "%s Hypertransport link capability " - "not found", dev_path(dev)); - break; - } - - /* Update the unitid of the current device. */ - flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS); - - /* - * If the device has a unitid set and is at devfn 0 we are - * done. This can happen with shadow hypertransport devices, - * or if we have reached the bottom of a HT device chain. - */ - if (flags & 0x1f) - break; - - flags &= ~0x1f; /* Mask out base Unit ID. */ - - count = (flags >> 5) & 0x1f; /* Het unit count. */ - -#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if (offset_unitid) { - /* max_devfn will be (0x17<<3)|7 or (0x1f<<3)|7. */ - if (next_unitid > (max_devfn >> 3)) { - if (!end_used) { - next_unitid = - CONFIG_HT_CHAIN_END_UNITID_BASE; - end_used = 1; - } else { - goto end_of_chain; - } - } - } -#endif - - flags |= next_unitid & 0x1f; - pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags); - - /* Update the unitid in the device structure. */ - static_count = 1; - for (func = dev; func; func = func->sibling) { - func->path.pci.devfn += (next_unitid << 3); - static_count = (func->path.pci.devfn >> 3) - - (dev->path.pci.devfn >> 3) + 1; - last_func = func; - } - - /* Compute the number of unitids consumed. */ - printk(BIOS_SPEW, "%s count: %04x static_count: %04x\n", - dev_path(dev), count, static_count); - if (count < static_count) - count = static_count; - - /* Update the unitid of the next device. */ - ht_unitid_base[ht_dev_num] = next_unitid; - ht_dev_num++; - -#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if (offset_unitid) { - real_last_pos = pos; - real_last_unitid = next_unitid; - real_last_dev = dev; - } -#endif - next_unitid += count; - if (next_unitid > max_unitid) - max_unitid = next_unitid; - - /* Setup the hypertransport link. */ - bus->reset_needed |= ht_setup_link(&prev, dev, pos); - - printk(BIOS_DEBUG, "%s [%04x/%04x] %s next_unitid: %04x\n", - dev_path(dev), dev->vendor, dev->device, - (dev->enabled? "enabled" : "disabled"), next_unitid); - - } while (last_unitid != next_unitid); - -end_of_chain: - -#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if (offset_unitid && (ht_dev_num > 1) - && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) - && !end_used) { - u16 flags; - flags = pci_read_config16(real_last_dev, - real_last_pos + PCI_CAP_FLAGS); - flags &= ~0x1f; - flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f; - pci_write_config16(real_last_dev, - real_last_pos + PCI_CAP_FLAGS, flags); - - for (func = real_last_dev; func; func = func->sibling) { - func->path.pci.devfn -= ((real_last_unitid - - CONFIG_HT_CHAIN_END_UNITID_BASE) << 3); - last_func = func; - } - - /* Update last one. */ - ht_unitid_base[ht_dev_num-1] = CONFIG_HT_CHAIN_END_UNITID_BASE; - - printk(BIOS_DEBUG, " unitid: %04x --> %04x\n", - real_last_unitid, CONFIG_HT_CHAIN_END_UNITID_BASE); - } -#endif - next_unitid = max_unitid; - - if (next_unitid > 0x20) - next_unitid = 0x20; - - if ((bus->secondary == 0) && (next_unitid > 0x18)) - next_unitid = 0x18; /* Avoid K8 on bus 0. */ - - /* - * Die if any leftover static devices are are found. There's probably - * a problem in devicetree.cb. - */ - if (old_devices) { - struct device *left; - for (left = old_devices; left; left = left->sibling) - printk(BIOS_DEBUG, "%s\n", dev_path(left)); - - printk(BIOS_ERR, "HT: Leftover static devices. " - "Check your devicetree.cb\n"); - - /* - * Put back the leftover static device, and let pci_scan_bus() - * disable it. - */ - if (last_func && !last_func->sibling) - last_func->sibling = old_devices; - } - - return next_unitid; -} - -/** - * Scan a PCI bridge and the buses behind the bridge. - * - * Determine the existence of buses behind the bridge. Set up the bridge - * according to the result of the scan. - * - * This function is the default scan_bus() method for PCI bridge devices. - * - * @param bus TODO - * @param min_devfn TODO - * @param max_devfn TODO - */ -static void hypertransport_scan_chain_x(struct bus *bus, - unsigned int min_devfn, unsigned int max_devfn) -{ - unsigned int ht_unitid_base[4]; - unsigned int offset_unitid = 1; - - unsigned int next_unitid = do_hypertransport_scan_chain(bus, min_devfn, max_devfn, - ht_unitid_base, offset_unitid); - - /* Now that nothing is overlapping it is safe to scan the children. */ - pci_scan_bus(bus, 0x00, ((next_unitid - 1) << 3) | 7); -} - -static void ht_scan_bridge(struct device *dev) -{ - do_pci_scan_bridge(dev, hypertransport_scan_chain_x); -} - -/** Default device operations for hypertransport bridges */ -static struct pci_operations ht_bus_ops_pci = { - .set_subsystem = 0, -}; - -struct device_operations default_ht_ops_bus = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .scan_bus = ht_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = &ht_bus_ops_pci, -}; diff --git a/src/device/pci_device.c b/src/device/pci_device.c index a00897736a..a7eb91d42d 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -862,19 +861,6 @@ static struct device_operations *get_pci_bridge_ops(struct device *dev) return &default_pcix_ops_bus; } #endif -#if CONFIG(HYPERTRANSPORT_PLUGIN_SUPPORT) - unsigned int htpos = 0; - while ((htpos = pci_find_next_capability(dev, PCI_CAP_ID_HT, htpos))) { - u16 flags; - flags = pci_read_config16(dev, htpos + PCI_CAP_FLAGS); - if ((flags >> 13) == 1) { - /* Host or Secondary Interface */ - printk(BIOS_DEBUG, "%s subordinate bus HT\n", - dev_path(dev)); - return &default_ht_ops_bus; - } - } -#endif #if CONFIG(PCIEXP_PLUGIN_SUPPORT) unsigned int pciexpos; pciexpos = pci_find_capability(dev, PCI_CAP_ID_PCIE); diff --git a/src/include/device/hypertransport.h b/src/include/device/hypertransport.h deleted file mode 100644 index 382731fe86..0000000000 --- a/src/include/device/hypertransport.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef DEVICE_HYPERTRANSPORT_H -#define DEVICE_HYPERTRANSPORT_H - -#include - -extern struct device_operations default_ht_ops_bus; - -#define HT_IO_HOST_ALIGN 4096 -#define HT_MEM_HOST_ALIGN (1024*1024) - -#endif /* DEVICE_HYPERTRANSPORT_H */ diff --git a/src/include/device/hypertransport_def.h b/src/include/device/hypertransport_def.h deleted file mode 100644 index 3cbd90b39c..0000000000 --- a/src/include/device/hypertransport_def.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef DEVICE_HYPERTRANSPORT_DEF_H -#define DEVICE_HYPERTRANSPORT_DEF_H - -#define HT_FREQ_200Mhz 0 -#define HT_FREQ_300Mhz 1 -#define HT_FREQ_400Mhz 2 -#define HT_FREQ_500Mhz 3 -#define HT_FREQ_600Mhz 4 -#define HT_FREQ_800Mhz 5 -#define HT_FREQ_1000Mhz 6 -#define HT_FREQ_1200Mhz 7 -#define HT_FREQ_1400Mhz 8 -#define HT_FREQ_1600Mhz 9 -#define HT_FREQ_1800Mhz 10 -#define HT_FREQ_2000Mhz 11 -#define HT_FREQ_2200Mhz 12 -#define HT_FREQ_2400Mhz 13 -#define HT_FREQ_2600Mhz 14 -#define HT_FREQ_VENDOR 15 /* AMD defines this to be 100Mhz */ - -static inline bool offset_unit_id(bool is_sb_ht_chain) -{ - bool need_offset = (CONFIG_HT_CHAIN_UNITID_BASE != 1) - || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20); - return need_offset && is_sb_ht_chain; -} - -#endif /* DEVICE_HYPERTRANSPORT_DEF_H */ diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index c1e342cde9..7c37ff8d71 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 207bec2d37..2d5234dde9 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index cedc7dae06..addd40f3c6 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/amd/agesa/nb_common.h b/src/northbridge/amd/agesa/nb_common.h index 31cee3ce79..66fbf92694 100644 --- a/src/northbridge/amd/agesa/nb_common.h +++ b/src/northbridge/amd/agesa/nb_common.h @@ -3,6 +3,9 @@ #ifndef __AMD_NB_COMMON_H__ #define __AMD_NB_COMMON_H__ +#define HT_IO_HOST_ALIGN 4096 +#define HT_MEM_HOST_ALIGN (1024 * 1024) + #define DEV_CDB 0x18 #endif diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 90d5603ca4..110dc84001 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 75e1f02c16..41554b84eb 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/amd/pi/nb_common.h b/src/northbridge/amd/pi/nb_common.h index a6daba3f9d..bee75c7109 100644 --- a/src/northbridge/amd/pi/nb_common.h +++ b/src/northbridge/amd/pi/nb_common.h @@ -3,6 +3,9 @@ #ifndef __AMD_NB_COMMON_H__ #define __AMD_NB_COMMON_H__ +#define HT_IO_HOST_ALIGN 4096 +#define HT_MEM_HOST_ALIGN (1024 * 1024) + #define DEV_CDB 0x18 #define IO_APIC2_ADDR 0xfec20000 From ec5cf1504e3bc31f308b18763eb256eeeb74dc7d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 10 Nov 2020 20:42:07 +0100 Subject: [PATCH 19/34] nb/amd: Deduplicate nb_common.h Save for the IO_APIC2_ADDR definition, they are equivalent. Change-Id: I14da3d9aeefcc725428957ce0c9ac164eabacec6 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47408 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/mainboard/pcengines/apu2/mptable.c | 2 +- src/northbridge/amd/agesa/family14/northbridge.c | 2 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 2 +- src/northbridge/amd/agesa/family16kb/northbridge.c | 2 +- src/northbridge/amd/agesa/nb_common.h | 11 ----------- src/northbridge/amd/{pi => }/nb_common.h | 0 src/northbridge/amd/pi/00630F01/northbridge.c | 2 +- src/northbridge/amd/pi/00730F01/northbridge.c | 2 +- src/northbridge/amd/pi/00730F01/state_machine.c | 2 +- 9 files changed, 7 insertions(+), 18 deletions(-) delete mode 100644 src/northbridge/amd/agesa/nb_common.h rename src/northbridge/amd/{pi => }/nb_common.h (100%) diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c index b52c8ccf49..a24863f5e3 100644 --- a/src/mainboard/pcengines/apu2/mptable.c +++ b/src/mainboard/pcengines/apu2/mptable.c @@ -3,7 +3,7 @@ #include #include #include -#include +#include #include static void *smp_write_config_table(void *v) diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 7c37ff8d71..020c9c6491 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 2d5234dde9..e345b50cf7 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index addd40f3c6..b600bc921c 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include diff --git a/src/northbridge/amd/agesa/nb_common.h b/src/northbridge/amd/agesa/nb_common.h deleted file mode 100644 index 66fbf92694..0000000000 --- a/src/northbridge/amd/agesa/nb_common.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __AMD_NB_COMMON_H__ -#define __AMD_NB_COMMON_H__ - -#define HT_IO_HOST_ALIGN 4096 -#define HT_MEM_HOST_ALIGN (1024 * 1024) - -#define DEV_CDB 0x18 - -#endif diff --git a/src/northbridge/amd/pi/nb_common.h b/src/northbridge/amd/nb_common.h similarity index 100% rename from src/northbridge/amd/pi/nb_common.h rename to src/northbridge/amd/nb_common.h diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 110dc84001..5242cd0deb 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #define MAX_NODE_NUMS MAX_NODES diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 41554b84eb..2019fae4cd 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include diff --git a/src/northbridge/amd/pi/00730F01/state_machine.c b/src/northbridge/amd/pi/00730F01/state_machine.c index af1198a001..ba34dabde9 100644 --- a/src/northbridge/amd/pi/00730F01/state_machine.c +++ b/src/northbridge/amd/pi/00730F01/state_machine.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { From eb8036b591b97145338cfd5ae4b7c9122ed55bef Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Mon, 23 Nov 2020 09:06:51 +0800 Subject: [PATCH 20/34] mb/google/volteer/var/elemi: Add H5ANAG6NCJR-XNC Add H5ANAG6NCJR-XNC. BUG=b:165461530 BRANCH=volteer TEST=emerge-volteer coreboot Change-Id: I827158ce0abe764f1e3b5de46abf50dc148a6ff0 Signed-off-by: Wisley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/47855 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/volteer/variants/elemi/memory/Makefile.inc | 1 + .../google/volteer/variants/elemi/memory/dram_id.generated.txt | 1 + .../google/volteer/variants/elemi/memory/mem_list_variant.txt | 1 + 3 files changed, 3 insertions(+) diff --git a/src/mainboard/google/volteer/variants/elemi/memory/Makefile.inc b/src/mainboard/google/volteer/variants/elemi/memory/Makefile.inc index 2685fcddd1..0a9e3f90d3 100644 --- a/src/mainboard/google/volteer/variants/elemi/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/elemi/memory/Makefile.inc @@ -5,3 +5,4 @@ SPD_SOURCES = SPD_SOURCES += ddr4-spd-2.hex # ID = 0(0b0000) Parts = H5ANAG6NCMR-XNC SPD_SOURCES += ddr4-spd-7.hex # ID = 1(0b0001) Parts = MT40A1G16KD-062E:E, K4AAG165WA-BCWE SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = H5AN8G6NDJR-XNC, MT40A512M16TB-062E:J, K4A8G165WC-BCWE +SPD_SOURCES += ddr4-spd-9.hex # ID = 3(0b0011) Parts = H5ANAG6NCJR-XNC diff --git a/src/mainboard/google/volteer/variants/elemi/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/elemi/memory/dram_id.generated.txt index c892d9b58a..e85149b345 100644 --- a/src/mainboard/google/volteer/variants/elemi/memory/dram_id.generated.txt +++ b/src/mainboard/google/volteer/variants/elemi/memory/dram_id.generated.txt @@ -5,3 +5,4 @@ K4AAG165WA-BCWE 1 (0001) H5AN8G6NDJR-XNC 2 (0010) MT40A512M16TB-062E:J 2 (0010) K4A8G165WC-BCWE 2 (0010) +H5ANAG6NCJR-XNC 3 (0011) diff --git a/src/mainboard/google/volteer/variants/elemi/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/elemi/memory/mem_list_variant.txt index 939d85fd06..b110e929ac 100644 --- a/src/mainboard/google/volteer/variants/elemi/memory/mem_list_variant.txt +++ b/src/mainboard/google/volteer/variants/elemi/memory/mem_list_variant.txt @@ -4,3 +4,4 @@ K4AAG165WA-BCWE H5AN8G6NDJR-XNC MT40A512M16TB-062E:J K4A8G165WC-BCWE +H5ANAG6NCJR-XNC From 6f32d80e1804de878dc750f649a15c24bd521a6f Mon Sep 17 00:00:00 2001 From: Nikolai Vyssotski Date: Wed, 11 Nov 2020 16:23:25 -0600 Subject: [PATCH 21/34] mb/amd/mandolin: Add decode range for LPC debug card Some LPC debug boards hard strap SIO address to be at 0x164e/0x164d vs 0x4e/0x4d. Add support for configurable SIO address to support these cards. BUG=b:159933344 TEST=boot with LPC debug card, verify serial output Change-Id: I103c61f21f13970dfa3b9a788b29964e478fb84c Signed-off-by: Nikolai Vyssotski Reviewed-on: https://review.coreboot.org/c/coreboot/+/47545 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/amd/mandolin/Kconfig | 18 ++++++++++++++++++ src/mainboard/amd/mandolin/bootblock.c | 9 +++++++-- 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index dde7ac8bed..b779630d56 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -29,6 +29,24 @@ config AMD_LPC_DEBUG_CARD PICASSO_CONSOLE_UART which selects the SoC's integrated memory-mapped UART for coreboot console output. +choice + prompt "SMSC/Microchip 1036 SuperIO config address" + depends on SUPERIO_SMSC_SIO1036 + default SMSC_SIO1036_BASE_164E + +config SMSC_SIO1036_BASE_4E + bool "0x4e/0x4d base address" + +config SMSC_SIO1036_BASE_164E + bool "0x164e/0x164d base address" + +endchoice + +config SUPERIO_ADDR_BASE + hex + default 0x4e if SMSC_SIO1036_BASE_4E + default 0x164e if SMSC_SIO1036_BASE_164E + config CBFS_SIZE hex default 0x7cf000 if BOARD_AMD_MANDOLIN # Maximum size for the Mandolin FMAP diff --git a/src/mainboard/amd/mandolin/bootblock.c b/src/mainboard/amd/mandolin/bootblock.c index 06da379d93..94a132938f 100644 --- a/src/mainboard/amd/mandolin/bootblock.c +++ b/src/mainboard/amd/mandolin/bootblock.c @@ -5,14 +5,19 @@ #include #include "gpio.h" -#define SERIAL_DEV PNP_DEV(0x4e, SIO1036_SP1) +#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_ADDR_BASE, SIO1036_SP1) void bootblock_mainboard_early_init(void) { mainboard_program_early_gpios(); if (CONFIG(SUPERIO_SMSC_SIO1036)) { - lpc_enable_sio_decode(LPC_SELECT_SIO_4E4F); + if (CONFIG_SUPERIO_ADDR_BASE == 0x4e) { + lpc_enable_sio_decode(LPC_SELECT_SIO_4E4F); + } else { + // set up 16 byte wide I/O range window for the super IO + lpc_set_wideio_range(CONFIG_SUPERIO_ADDR_BASE & ~0xF, 16); + } lpc_enable_decode(DECODE_ENABLE_SERIAL_PORT0 << CONFIG_UART_FOR_CONSOLE); sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } From 5a41b0db20348c6a6b83132d40f825daa2dedc9a Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Mon, 23 Nov 2020 20:20:38 +0000 Subject: [PATCH 22/34] MAINTAINERS: Add maintainers for kontron/mal10 Add Maxim Polyakov, Nico Huber and Felix Singer as maintainers for kontron/mal10. Change-Id: I2f4200708e4aec6d74916fb5e63efe2f20594882 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/47889 Reviewed-by: Maxim Polyakov Tested-by: build bot (Jenkins) --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index b4b685ce2a..4f643b2f3c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -288,6 +288,13 @@ M: Nico Huber S: Supported F: src/mainboard/kontron/bsl6/ +KONTRON MAL10 MAINBOARD +M: Maxim Polyakov +M: Nico Huber +M: Felix Singer +S: Supported +F: src/mainboard/kontron/mal10/ + LENOVO MAINBOARDS From ea378ccc8f61b64fcc8be603e5d1c76555086108 Mon Sep 17 00:00:00 2001 From: Jakub Czapiga Date: Thu, 12 Nov 2020 12:10:51 +0100 Subject: [PATCH 23/34] tests: Add lib/list-test test case Change-Id: If74f241b2bb788b3e2fd1b9062fc74819f7be31e Signed-off-by: Jakub Czapiga Reviewed-on: https://review.coreboot.org/c/coreboot/+/47507 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg --- tests/lib/Makefile.inc | 7 ++- tests/lib/list-test.c | 129 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 135 insertions(+), 1 deletion(-) create mode 100644 tests/lib/list-test.c diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index c49828962d..5783f18919 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -8,6 +8,7 @@ tests-y += timestamp-test tests-y += edid-test tests-y += cbmem_console-romstage-test tests-y += cbmem_console-ramstage-test +tests-y += list-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -38,4 +39,8 @@ cbmem_console-romstage-test-srcs += tests/stubs/console.c cbmem_console-ramstage-test-stage := ramstage cbmem_console-ramstage-test-srcs += tests/lib/cbmem_console-test.c -cbmem_console-ramstage-test-srcs += tests/stubs/console.c \ No newline at end of file +cbmem_console-ramstage-test-srcs += tests/stubs/console.c + +list-test-srcs += tests/lib/list-test.c +list-test-srcs += src/lib/list.c + diff --git a/tests/lib/list-test.c b/tests/lib/list-test.c new file mode 100644 index 0000000000..6688c4faeb --- /dev/null +++ b/tests/lib/list-test.c @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +struct test_container { + int value; + + struct list_node list_node; +}; + +void test_list_insert_after(void **state) +{ + int i = 0; + struct list_node root = { .prev = NULL, .next = NULL }; + struct test_container *c1 = (struct test_container *)malloc(sizeof(*c1)); + struct test_container *c2 = (struct test_container *)malloc(sizeof(*c2)); + struct test_container *c3 = (struct test_container *)malloc(sizeof(*c2)); + struct test_container *ptr; + const int values[] = { 5, 10, 13 }; /* Random values */ + + memset(c1, 0, sizeof(*c1)); + memset(c2, 0, sizeof(*c2)); + memset(c2, 0, sizeof(*c3)); + + c1->value = values[0]; + c2->value = values[1]; + c3->value = values[2]; + + list_insert_after(&c1->list_node, &root); + list_insert_after(&c2->list_node, &c1->list_node); + list_insert_after(&c3->list_node, &c2->list_node); + + list_for_each(ptr, root, list_node) { + assert_int_equal(values[i], ptr->value); + i++; + } + + assert_int_equal(3, i); + + free(c3); + free(c2); + free(c1); +} + +void test_list_insert_before(void **state) +{ + int i = 0; + struct list_node root = { .prev = NULL, .next = NULL }; + struct test_container *c1 = (struct test_container *)malloc(sizeof(*c1)); + struct test_container *c2 = (struct test_container *)malloc(sizeof(*c2)); + struct test_container *c3 = (struct test_container *)malloc(sizeof(*c2)); + struct test_container *ptr; + const int values[] = { 19, 71, 991 }; /* Random values */ + + memset(c1, 0, sizeof(*c1)); + memset(c2, 0, sizeof(*c2)); + memset(c2, 0, sizeof(*c3)); + + c1->value = values[0]; + c2->value = values[1]; + c3->value = values[2]; + + list_insert_after(&c3->list_node, &root); + list_insert_before(&c2->list_node, &c3->list_node); + list_insert_before(&c1->list_node, &c2->list_node); + + + list_for_each(ptr, root, list_node) { + assert_int_equal(values[i], ptr->value); + i++; + } + + assert_int_equal(3, i); + + free(c3); + free(c2); + free(c1); +} + +void test_list_remove(void **state) +{ + struct list_node root = { .prev = NULL, .next = NULL }; + struct test_container *c1 = (struct test_container *)malloc(sizeof(*c1)); + struct test_container *c2 = (struct test_container *)malloc(sizeof(*c2)); + struct test_container *ptr; + int len; + + list_insert_after(&c1->list_node, &root); + list_insert_after(&c2->list_node, &c1->list_node); + + len = 0; + list_for_each(ptr, root, list_node) { + len++; + } + assert_int_equal(2, len); + + list_remove(&c1->list_node); + + len = 0; + list_for_each(ptr, root, list_node) { + len++; + } + assert_int_equal(1, len); + + list_remove(&c2->list_node); + len = 0; + list_for_each(ptr, root, list_node) { + len++; + } + assert_int_equal(0, len); + + free(c2); + free(c1); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(test_list_insert_after), + cmocka_unit_test(test_list_insert_before), + cmocka_unit_test(test_list_remove), + }; + + + return cmocka_run_group_tests(tests, NULL, NULL); +} From 64f7bdf19a05b773eaf68acc9067bab8309cbefb Mon Sep 17 00:00:00 2001 From: Stanley Wu Date: Fri, 30 Oct 2020 12:01:20 +0800 Subject: [PATCH 24/34] mb/google/volteer/variant/lindar: change speaker smart amplifier to ALC1011 Lindar change amp to ALC1011 Add ALC1011 amp acpi info to devicetree BUG=b:171771736 BRANCH=firmware-volteer-13521.B TEST=build and verify ALC1011 can be recognized. Change-Id: I4d83a19b3baa87cc926bb7c3a2cb96bf3165d2f4 Signed-off-by: Stanley Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/47009 Tested-by: build bot (Jenkins) Reviewed-by: Zhuohao Lee Reviewed-by: Caveh Jalali --- src/mainboard/google/volteer/Kconfig.name | 2 ++ src/mainboard/google/volteer/fw_config.c | 3 ++- .../volteer/variants/baseboard/devicetree.cb | 1 + .../volteer/variants/lindar/overridetree.cb | 20 ++++++++++++++++++- 4 files changed, 24 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index b651430ddd..0f9b6e287c 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -22,6 +22,8 @@ config BOARD_GOOGLE_LINDAR select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU select INTEL_CAR_NEM + select CHROMEOS_DSM_CALIB + select DRIVERS_I2C_RT1011 config BOARD_GOOGLE_MALEFOR bool "-> Malefor" diff --git a/src/mainboard/google/volteer/fw_config.c b/src/mainboard/google/volteer/fw_config.c index 50e8f93080..5080d9b27d 100644 --- a/src/mainboard/google/volteer/fw_config.c +++ b/src/mainboard/google/volteer/fw_config.c @@ -86,7 +86,8 @@ static void fw_config_handle(void *unused) } if (fw_config_probe(FW_CONFIG(AUDIO, MAX98357_ALC5682I_I2S)) || fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682I_I2S)) || - fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))) { + fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S)) || + fw_config_probe(FW_CONFIG(AUDIO, RT1011_ALC5682I_I2S))) { printk(BIOS_INFO, "Configure GPIOs for I2S audio on UP3.\n"); gpio_configure_pads(i2s_up3_enable_pads, ARRAY_SIZE(i2s_up3_enable_pads)); gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 7964885ffa..bc1febb18f 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -16,6 +16,7 @@ fw_config option MAX98373_ALC5682_SNDW 3 option MAX98373_ALC5682I_I2S_UP4 4 option MAX98360_ALC5682I_I2S 5 + option RT1011_ALC5682I_I2S 6 end field TABLETMODE 11 option TABLETMODE_DISABLED 0 diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index 64f5ab9910..2e61071c9d 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -35,7 +35,25 @@ chip soc/intel/tigerlake register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" - device i2c 1a on end + device i2c 1a on + probe AUDIO RT1011_ALC5682I_I2S + end + end + chip drivers/i2c/rt1011 + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "0" + register "name" = ""RTL"" + device i2c 38 on + probe AUDIO RT1011_ALC5682I_I2S + end + end + chip drivers/i2c/rt1011 + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + register "name" = ""RTR"" + device i2c 39 on + probe AUDIO RT1011_ALC5682I_I2S + end end end device ref i2c1 on From f106b3b430aca26d09ffdf315dbed4a86650c743 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 14 Oct 2020 10:52:08 +0200 Subject: [PATCH 25/34] crossgcc: Upgrade LLVM to version 11.0.0 Change-Id: I1cc02355e3fea7eb9ad98be6396a492dbbdc47b2 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/46379 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- util/crossgcc/buildgcc | 2 +- util/crossgcc/sum/clang-10.0.1.src.tar.xz.cksum | 1 - util/crossgcc/sum/clang-11.0.0.src.tar.xz.cksum | 1 + util/crossgcc/sum/clang-tools-extra-10.0.1.src.tar.xz.cksum | 1 - util/crossgcc/sum/clang-tools-extra-11.0.0.src.tar.xz.cksum | 1 + util/crossgcc/sum/compiler-rt-10.0.1.src.tar.xz.cksum | 1 - util/crossgcc/sum/compiler-rt-11.0.0.src.tar.xz.cksum | 1 + util/crossgcc/sum/llvm-10.0.1.src.tar.xz.cksum | 1 - util/crossgcc/sum/llvm-11.0.0.src.tar.xz.cksum | 1 + 9 files changed, 5 insertions(+), 5 deletions(-) delete mode 100644 util/crossgcc/sum/clang-10.0.1.src.tar.xz.cksum create mode 100644 util/crossgcc/sum/clang-11.0.0.src.tar.xz.cksum delete mode 100644 util/crossgcc/sum/clang-tools-extra-10.0.1.src.tar.xz.cksum create mode 100644 util/crossgcc/sum/clang-tools-extra-11.0.0.src.tar.xz.cksum delete mode 100644 util/crossgcc/sum/compiler-rt-10.0.1.src.tar.xz.cksum create mode 100644 util/crossgcc/sum/compiler-rt-11.0.0.src.tar.xz.cksum delete mode 100644 util/crossgcc/sum/llvm-10.0.1.src.tar.xz.cksum create mode 100644 util/crossgcc/sum/llvm-11.0.0.src.tar.xz.cksum diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index bba8ac71a3..2ba26802ff 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -44,7 +44,7 @@ IASL_VERSION=20200925 PYTHON_VERSION=3.8.5 EXPAT_VERSION=2.2.9 # CLANG version number -CLANG_VERSION=10.0.1 +CLANG_VERSION=11.0.0 CMAKE_VERSION=3.18.1 NASM_VERSION=2.15.05 diff --git a/util/crossgcc/sum/clang-10.0.1.src.tar.xz.cksum b/util/crossgcc/sum/clang-10.0.1.src.tar.xz.cksum deleted file mode 100644 index 6e0d86371d..0000000000 --- a/util/crossgcc/sum/clang-10.0.1.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -0e61e92b22a620fe7f833fa8b2a56f2db96f7335 tarballs/clang-10.0.1.src.tar.xz diff --git a/util/crossgcc/sum/clang-11.0.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-11.0.0.src.tar.xz.cksum new file mode 100644 index 0000000000..817234f50b --- /dev/null +++ b/util/crossgcc/sum/clang-11.0.0.src.tar.xz.cksum @@ -0,0 +1 @@ +02c87f5e07f2a1c1e2dbb8ce8328f0106d70b10d tarballs/clang-11.0.0.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-10.0.1.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-10.0.1.src.tar.xz.cksum deleted file mode 100644 index 1b880c7ce4..0000000000 --- a/util/crossgcc/sum/clang-tools-extra-10.0.1.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -26c996da082677aca1016bcf2141dbff01dc7300 tarballs/clang-tools-extra-10.0.1.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-11.0.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-11.0.0.src.tar.xz.cksum new file mode 100644 index 0000000000..f6b260faa3 --- /dev/null +++ b/util/crossgcc/sum/clang-tools-extra-11.0.0.src.tar.xz.cksum @@ -0,0 +1 @@ +b77dc0494894b997c8f4012debbf0bf469462386 tarballs/clang-tools-extra-11.0.0.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-10.0.1.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-10.0.1.src.tar.xz.cksum deleted file mode 100644 index 2efb4136b1..0000000000 --- a/util/crossgcc/sum/compiler-rt-10.0.1.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -ee6077b4728b3c750e476938cead11cea45b49ff tarballs/compiler-rt-10.0.1.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-11.0.0.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-11.0.0.src.tar.xz.cksum new file mode 100644 index 0000000000..fe447bf748 --- /dev/null +++ b/util/crossgcc/sum/compiler-rt-11.0.0.src.tar.xz.cksum @@ -0,0 +1 @@ +be3e79fb93cd99135643a191f27c49449bf9c0ee tarballs/compiler-rt-11.0.0.src.tar.xz diff --git a/util/crossgcc/sum/llvm-10.0.1.src.tar.xz.cksum b/util/crossgcc/sum/llvm-10.0.1.src.tar.xz.cksum deleted file mode 100644 index a6919e89ad..0000000000 --- a/util/crossgcc/sum/llvm-10.0.1.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -25d07260f3b7bf4f647e115c4a663fdeda130fbd tarballs/llvm-10.0.1.src.tar.xz diff --git a/util/crossgcc/sum/llvm-11.0.0.src.tar.xz.cksum b/util/crossgcc/sum/llvm-11.0.0.src.tar.xz.cksum new file mode 100644 index 0000000000..c95d6a5d5d --- /dev/null +++ b/util/crossgcc/sum/llvm-11.0.0.src.tar.xz.cksum @@ -0,0 +1 @@ +5723ae20d1e6e9ccfda208cb9a8cf2f87c3a6107 tarballs/llvm-11.0.0.src.tar.xz From 794a9b7b9c53c615cd642b9c9537b009ce3274f2 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 19 Sep 2020 13:57:36 +0200 Subject: [PATCH 26/34] crossgcc: Upgrade binutils to 2.35.1 Change-Id: I8694a154d48c5a718b27d4beb858942db0feb997 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/45550 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- util/crossgcc/buildgcc | 2 +- ...inutils-2.35_as-ipxe.patch => binutils-2.35.1_as-ipxe.patch} | 0 ...ils-2.35_mips-gold.patch => binutils-2.35.1_mips-gold.patch} | 0 ...s-2.35_no-bfd-doc.patch => binutils-2.35.1_no-bfd-doc.patch} | 0 ...2.35_no-makeinfo.patch => binutils-2.35.1_no-makeinfo.patch} | 0 util/crossgcc/sum/binutils-2.35.1.tar.xz.cksum | 1 + util/crossgcc/sum/binutils-2.35.tar.xz.cksum | 1 - 7 files changed, 2 insertions(+), 2 deletions(-) rename util/crossgcc/patches/{binutils-2.35_as-ipxe.patch => binutils-2.35.1_as-ipxe.patch} (100%) rename util/crossgcc/patches/{binutils-2.35_mips-gold.patch => binutils-2.35.1_mips-gold.patch} (100%) rename util/crossgcc/patches/{binutils-2.35_no-bfd-doc.patch => binutils-2.35.1_no-bfd-doc.patch} (100%) rename util/crossgcc/patches/{binutils-2.35_no-makeinfo.patch => binutils-2.35.1_no-makeinfo.patch} (100%) create mode 100644 util/crossgcc/sum/binutils-2.35.1.tar.xz.cksum delete mode 100644 util/crossgcc/sum/binutils-2.35.tar.xz.cksum diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 2ba26802ff..b55ecb22ee 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -38,7 +38,7 @@ MPFR_VERSION=4.1.0 MPC_VERSION=1.2.0 GCC_VERSION=8.3.0 GCC_AUTOCONF_VERSION=2.69 -BINUTILS_VERSION=2.35 +BINUTILS_VERSION=2.35.1 GDB_VERSION=9.2 IASL_VERSION=20200925 PYTHON_VERSION=3.8.5 diff --git a/util/crossgcc/patches/binutils-2.35_as-ipxe.patch b/util/crossgcc/patches/binutils-2.35.1_as-ipxe.patch similarity index 100% rename from util/crossgcc/patches/binutils-2.35_as-ipxe.patch rename to util/crossgcc/patches/binutils-2.35.1_as-ipxe.patch diff --git a/util/crossgcc/patches/binutils-2.35_mips-gold.patch b/util/crossgcc/patches/binutils-2.35.1_mips-gold.patch similarity index 100% rename from util/crossgcc/patches/binutils-2.35_mips-gold.patch rename to util/crossgcc/patches/binutils-2.35.1_mips-gold.patch diff --git a/util/crossgcc/patches/binutils-2.35_no-bfd-doc.patch b/util/crossgcc/patches/binutils-2.35.1_no-bfd-doc.patch similarity index 100% rename from util/crossgcc/patches/binutils-2.35_no-bfd-doc.patch rename to util/crossgcc/patches/binutils-2.35.1_no-bfd-doc.patch diff --git a/util/crossgcc/patches/binutils-2.35_no-makeinfo.patch b/util/crossgcc/patches/binutils-2.35.1_no-makeinfo.patch similarity index 100% rename from util/crossgcc/patches/binutils-2.35_no-makeinfo.patch rename to util/crossgcc/patches/binutils-2.35.1_no-makeinfo.patch diff --git a/util/crossgcc/sum/binutils-2.35.1.tar.xz.cksum b/util/crossgcc/sum/binutils-2.35.1.tar.xz.cksum new file mode 100644 index 0000000000..b1abda8073 --- /dev/null +++ b/util/crossgcc/sum/binutils-2.35.1.tar.xz.cksum @@ -0,0 +1 @@ +45f7a96a2580a422f44b78317f0abf13935fecb6 tarballs/binutils-2.35.1.tar.xz diff --git a/util/crossgcc/sum/binutils-2.35.tar.xz.cksum b/util/crossgcc/sum/binutils-2.35.tar.xz.cksum deleted file mode 100644 index 06c29b0b3e..0000000000 --- a/util/crossgcc/sum/binutils-2.35.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -6bdd090ce268b6d6c3442516021c4e4b5019e303 tarballs/binutils-2.35.tar.xz From d87a84830e7ef3d9d2e2f6df614bef03d5becd55 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 30 Oct 2020 00:06:11 +0100 Subject: [PATCH 27/34] soc/intel/{broadwell,quark}: Drop `PEI_DATA` typedef It is not used. Change-Id: I3ef0878811bf2ec406ded03aac6c5dfeb5bf45a2 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47001 Reviewed-by: Frans Hendriks Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/include/soc/pei_data.h | 2 -- src/soc/intel/quark/include/soc/pei_wrapper.h | 2 -- 2 files changed, 4 deletions(-) diff --git a/src/soc/intel/broadwell/include/soc/pei_data.h b/src/soc/intel/broadwell/include/soc/pei_data.h index bc9f220af7..67d73d9dbf 100644 --- a/src/soc/intel/broadwell/include/soc/pei_data.h +++ b/src/soc/intel/broadwell/include/soc/pei_data.h @@ -246,6 +246,4 @@ struct pei_data { struct pei_memory_info meminfo; } __packed; -typedef struct pei_data PEI_DATA; - #endif diff --git a/src/soc/intel/quark/include/soc/pei_wrapper.h b/src/soc/intel/quark/include/soc/pei_wrapper.h index a14da63efb..5c52d3b39b 100644 --- a/src/soc/intel/quark/include/soc/pei_wrapper.h +++ b/src/soc/intel/quark/include/soc/pei_wrapper.h @@ -28,6 +28,4 @@ struct pei_data { int data_to_save_size; } __packed; -typedef struct pei_data PEI_DATA; - #endif /* _PEI_WRAPPER_H_ */ From 105cdf562567e935d318673556b0e9f7b1ce9cf3 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Fri, 23 Oct 2020 19:19:32 -0700 Subject: [PATCH 28/34] cbfstool: Don't add compression attribute for uncompressed files Our current cbfstool has always added a compression attribute to the CBFS file header for all files that used the cbfstool_convert_raw() function (basically anything other than a stage or payload), even if the compression type was NONE. This was likely some sort of oversight, since coreboot CBFS reading code has always accepted the absence of a compression attribute to mean "no compression". This patch fixes the behavior to avoid adding the attribute in these cases. Change-Id: Ic4a41152db9df66376fa26096d6f3a53baea51de Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46835 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- util/cbfstool/cbfstool.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index d2df1cc008..c7a6079333 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -595,6 +595,9 @@ static int cbfstool_convert_raw(struct buffer *buffer, return -1; memcpy(compressed, buffer->data + 8, compressed_size); } else { + if (param.compression == CBFS_COMPRESS_NONE) + goto out; + compress = compression_function(param.compression); if (!compress) return -1; @@ -606,7 +609,7 @@ static int cbfstool_convert_raw(struct buffer *buffer, compressed, &compressed_size)) { WARN("Compression failed - disabled\n"); free(compressed); - return 0; + goto out; } } @@ -626,6 +629,7 @@ static int cbfstool_convert_raw(struct buffer *buffer, buffer->data = compressed; buffer->size = compressed_size; +out: header->len = htonl(buffer->size); return 0; } From f7cdb8e3c6e7c59bb80497887d15c70e2b059804 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sat, 14 Nov 2020 14:58:48 -0600 Subject: [PATCH 29/34] mb/google/hatch: select SOC_INTEL_CSE_LITE_SKU only if CHROMEOS Selecting SOC_INTEL_CSE_LITE_SKU without conditioning on CHROMEOS force-selects CHROMEOS, per src/soc/intel/common/block/cse/Kconfig. Conditioning on CHROMEOS allows for non-ChromeOS targets to be built. Test: build wyvern variant with CONFIG_CHROMEOS=n Change-Id: I61c9c78a3b02d64bab2813b7a80915b7ecf7f934 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/47725 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Angel Pons --- src/mainboard/google/hatch/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 12e56384bd..20b71038d4 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -11,7 +11,7 @@ config BOARD_GOOGLE_BASEBOARD_PUFF select RT8168_SET_LED_MODE select ROMSTAGE_SPD_SMBUS select SPD_READ_BY_WORD - select SOC_INTEL_CSE_LITE_SKU + select SOC_INTEL_CSE_LITE_SKU if CHROMEOS select DRIVERS_INTEL_DPTF select DPTF_USE_EISA_HID From a96eaf870015d65eff3120d4e877febb6862088b Mon Sep 17 00:00:00 2001 From: Tim Chu Date: Thu, 12 Nov 2020 03:15:39 -0800 Subject: [PATCH 30/34] arch/x86/smbios: Update SMBIOS type 16 error correction type Add weak function for SMBIOS type 16 error correction type. Tested=Execute "dmidecode -t 16" to check if error correction type is correct. Signed-off-by: Tim Chu Change-Id: I85b37e9cfd22a78544d03e5506ff92b1f2404f8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/47508 Reviewed-by: Patrick Georgi Reviewed-by: Jonathan Zhang Tested-by: build bot (Jenkins) --- src/arch/x86/smbios.c | 9 +++++++-- src/include/smbios.h | 1 + 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index da77284d37..aabeb1046c 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -463,6 +463,12 @@ static int get_socket_type(void) return 0x02; /* Unknown */ } +unsigned int __weak smbios_memory_error_correction_type(struct memory_info *meminfo) +{ + return meminfo->ecc_capable ? + MEMORY_ARRAY_ECC_SINGLE_BIT : MEMORY_ARRAY_ECC_NONE; +} + unsigned int __weak smbios_processor_external_clock(void) { return 0; /* Unknown */ @@ -1035,8 +1041,7 @@ static int smbios_write_type16(unsigned long *current, int *handle) t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD; t->use = MEMORY_ARRAY_USE_SYSTEM; - t->memory_error_correction = meminfo->ecc_capable ? - MEMORY_ARRAY_ECC_SINGLE_BIT : MEMORY_ARRAY_ECC_NONE; + t->memory_error_correction = smbios_memory_error_correction_type(meminfo); /* no error information handle available */ t->memory_error_information_handle = 0xFFFE; diff --git a/src/include/smbios.h b/src/include/smbios.h index 4ddf4384dc..e451d17ef8 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -57,6 +57,7 @@ const char *smbios_processor_serial_number(void); void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision); +unsigned int smbios_memory_error_correction_type(struct memory_info *meminfo); unsigned int smbios_processor_external_clock(void); unsigned int smbios_processor_characteristics(void); struct cpuid_result; From 9b7dc7645db803d34dee314fcd46df77b2935f4f Mon Sep 17 00:00:00 2001 From: Tim Chu Date: Thu, 12 Nov 2020 04:16:34 -0800 Subject: [PATCH 31/34] mb/ocp/deltalake: Define SMBIOS type 16 error correction type by RasModesEnabled Use RasModesEnabled from SystemMemoryMapHob to define SMBIOS type 16 error correction type Tested=Execute "dmidecode -t 16" to check if error correction type is correct. Signed-off-by: Tim Chu Change-Id: I3636fcc4a874261cf484c10e2db15015ac5d7e68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47509 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Zhang --- src/mainboard/ocp/deltalake/ramstage.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 52c55b89b0..96b006020b 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -26,6 +26,31 @@ extern struct fru_info_str fru_strings; static char slot_id_str[SLOT_ID_LEN]; +/* Override SMBIOS type 16 error correction type. */ +unsigned int smbios_memory_error_correction_type(struct memory_info *meminfo) +{ + const struct SystemMemoryMapHob *hob; + + hob = get_system_memory_map(); + assert(hob != NULL); + + switch (hob->RasModesEnabled) { + case CH_INDEPENDENT: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + case FULL_MIRROR_1LM: + case PARTIAL_MIRROR_1LM: + case FULL_MIRROR_2LM: + case PARTIAL_MIRROR_2LM: + return MEMORY_ARRAY_ECC_MULTI_BIT; + case RK_SPARE: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + case CH_LOCKSTEP: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + default: + return MEMORY_ARRAY_ECC_MULTI_BIT; + } +} + /* * Update SMBIOS type 0 ec version. * In deltalake, BMC version is used to represent ec version. From 5190f42306b3e860c0fccec0f4ba933243c3a4fa Mon Sep 17 00:00:00 2001 From: Idwer Vollering Date: Tue, 24 Nov 2020 15:13:16 +0100 Subject: [PATCH 32/34] util/crossgcc: ensure curl writes downloaded bytes to a file Commit 82a30a134c (util/crossgcc: Retry package downloads on failure) caused a regression for curl users. Signed-off-by: Idwer Vollering Change-Id: I0d946b86baad3f6409a5042701808da307e5bcb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47911 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Angel Pons --- util/crossgcc/buildgcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index b55ecb22ee..5af3d5aadf 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -1066,7 +1066,7 @@ elif searchtool curl "^curl " > /dev/null; then download_showing_percentage() { url=$1 echo - curl --progress-bar --location --retry 3 "$url" + curl -O --progress-bar --location --retry 3 "$url" } fi From 2f1d686ba64a255dfde99d50f16f60805b31d7cc Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 24 Nov 2020 16:47:46 +0000 Subject: [PATCH 33/34] Update vboot submodule to upstream master Updating from commit id 9d4053d: 2020-11-20 01:51:08 +0000 - (Revert "Reland: Clean up implicit fall through.") to commit id 48195e5: 2020-11-24 10:23:45 +0000 - (Makefile: Test for warning flags before using them) This brings in 3 new commits. Change-Id: I64f27f346df264cb6eeeb4e3203fcca7d35f7e83 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/47906 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering --- 3rdparty/vboot | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/vboot b/3rdparty/vboot index 9d4053df76..48195e5878 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 9d4053df76c127f625a8571d3ef16e6a063c8de5 +Subproject commit 48195e5878006ac2cf74cb7f02953ab06c68202d From 1856effaf2397edc3e00b8c2cf2acdb9f6bd935e Mon Sep 17 00:00:00 2001 From: Nick Chen Date: Mon, 23 Nov 2020 15:40:57 +0800 Subject: [PATCH 34/34] mb/google/volteer: Update Eldrid USB2 port settings in overridetree 1. Disable M.2 WWAN and Type-A Port A1 2. Change register 4 to 3 and tuning USB2 Port1 eye diagram 3. Lower camera driving BUG=b:169105751 Signed-off-by: Nick Chen Change-Id: I6b8a5c0d5e814de232d79a43354f5ec0220fc5ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/47863 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../volteer/variants/eldrid/overridetree.cb | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 72571c039a..51bc99159b 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -58,12 +58,22 @@ chip soc/intel/tigerlake }, }, }" - #These settings improve the USB2 Port1 eye diagram + + #Disable Type-A Port A1 + register "usb2_ports[1]" = "USB2_PORT_EMPTY" + + #Disable M.2 WWAN + register "usb2_ports[2]" = "USB2_PORT_EMPTY" + + #improve the USB2 Port1 eye diagram + register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" + + #lower camera driving register "usb2_ports[4]" = "{ .enable = 1, - .tx_bias = 7, - .tx_emp_enable = 7, - .pre_emp_bias = 3, + .tx_bias = 0, + .tx_emp_enable = 0, + .pre_emp_bias = 0, .pre_emp_bit = 0, }"