soc/intel/apollolake: Add GPE routing code

This patch adds the basic framework for SCI to GPE routing code.

BUG = chrome-os-partner:53438
TEST = Toogle pch_sci_l from ec console using gpioset command and
	see that the sci counter increases in /sys/firmware/acpi/interrupt
	and also 9 in /proc/interrupts.

Change-Id: I3b3198276530bf6513d94e9bea02ab9751212adf
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15324
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

src/soc/intel/apollolake/chip.h

@@ -21,6 +21,7 @@
 #include <soc/gpio.h>
 #include <soc/intel/common/lpss_i2c.h>
 #include <device/i2c.h>
+#include <soc/pm.h>
 
 #define CLKREQ_DISABLED		0xf
 #define APOLLOLAKE_I2C_DEV_MAX	8
@@ -96,6 +97,10 @@ struct soc_intel_apollolake_config {
 
 	/* I2C bus configuration */
 	struct apollolake_i2c_config i2c[APOLLOLAKE_I2C_DEV_MAX];
+
+	uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */
+	uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */
+	uint8_t gpe0_dw3; /* GPE0_127_96 STS/EN */
 };
 
 #endif	/* _SOC_APOLLOLAKE_CHIP_H_ */