Now that the VIA code is run above 1Meg (like other boards), it should

cache that range instead of the first 1Meg.  This reduces boot time by
about 1 second on epia-cn.

This patch also adds a MTRRphysMaskValid bit definition.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/cpu/x86/mtrr/mtrr.c

@@ -62,7 +62,7 @@ static void enable_var_mtrr(void)
 	msr_t msr;
 
 	msr = rdmsr(MTRRdefType_MSR);
-	msr.lo |= 0x800;
+	msr.lo |= MTRRdefTypeEn;
 	wrmsr(MTRRdefType_MSR, msr);
 }
 
@@ -115,7 +115,7 @@ static void set_var_mtrr(
 
 	/* Bit 32-35 of MTRRphysMask should be set to 1 */
 	base.lo |= type;
-	mask.lo |= 0x800;
+	mask.lo |= MTRRphysMaskValid;
 	wrmsr (MTRRphysBase_MSR(reg), base);
 	wrmsr (MTRRphysMask_MSR(reg), mask);