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Now that the VIA code is run above 1Meg (like other boards), it should

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cache that range instead of the first 1Meg.  This reduces boot time by
about 1 second on epia-cn.

This patch also adds a MTRRphysMaskValid bit definition.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Kevin O'Connor
2011-01-19 06:32:35 +00:00
committed by Stefan Reinauer
parent 4adc9eb600
commit 5bb9fd6e4d
3 changed files with 12 additions and 37 deletions
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2
src/include/cpu/x86/mtrr.h
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@@ -21,6 +21,8 @@
#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
#define MTRRphysMaskValid (1 << 11)
#define NUM_FIXED_RANGES 88
#define MTRRfix64K_00000_MSR 0x250
#define MTRRfix16K_80000_MSR 0x258