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mb/google/brox/jubilant: update overridetree for dptf settings

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Update dptf settings for EVT.

BUG=None
TEST=emerge-brox coreboot chromeos-bootiamge

Change-Id: Iadc95c14da6f879e25dac4804907e340dc16e47f
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83842
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Morris Hsu 2024-08-09 14:53:20 +08:00 committed by Felix Held
parent ffc1cbb8fc
commit 5bc6bd4c41
1 changed files with 4 additions and 3 deletions
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7
src/mainboard/google/brox/variants/jubilant/overridetree.cb
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@ -41,8 +41,9 @@ chip soc/intel/alderlake
device ref dtt on
chip drivers/intel/dptf
## sensor information
register "options.tsr[0].desc" = ""DRAM_SOC""
register "options.tsr[1].desc" = ""Fan-Inlet""
register "options.tsr[0].desc" = ""DRAM""
register "options.tsr[1].desc" = ""Soc""
register "options.tsr[2].desc" = ""Charger""
## Active Policy
register "policies.active" = "{
@ -101,7 +102,7 @@ chip soc/intel/alderlake
register "controls.power_limits" = "{
.pl1 = {
.min_power = 15000,
.max_power = 15000,
.max_power = 18000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200,