LUMPY: Add information to generate MPTABLE from devicetree.cb
Change-Id: If68888e87c5197328c59dafce1301eefe000e28e Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1462 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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@@ -12,12 +12,14 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select GFXUMA
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select GFXUMA
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_ACPI_TABLES
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select HAVE_MP_TABLE
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select HAVE_OPTION_TABLE
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select HAVE_OPTION_TABLE
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select HAVE_SMI_HANDLER
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select HAVE_SMI_HANDLER
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select MMCONF_SUPPORT
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select MMCONF_SUPPORT
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select SOUTHBRIDGE_INTEL_BD82X6X
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select SOUTHBRIDGE_INTEL_BD82X6X
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select SUPERIO_SMSC_MEC1308
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select SUPERIO_SMSC_MEC1308
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select DRIVERS_GENERIC_IOAPIC
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config MAINBOARD_DIR
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config MAINBOARD_DIR
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string
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string
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@@ -33,6 +33,10 @@ chip northbridge/intel/sandybridge
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end
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end
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device pci_domain 0 on
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device pci_domain 0 on
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ioapic_irq 4 INTA 0x10
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ioapic_irq 4 INTB 0x11
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ioapic_irq 4 INTC 0x12
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ioapic_irq 4 INTD 0x13
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subsystemid 0x1ae0 0xc000 inherit
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subsystemid 0x1ae0 0xc000 inherit
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device pci 00.0 on end # host bridge
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device pci 00.0 on end # host bridge
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device pci 02.0 on end # vga controller
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device pci 02.0 on end # vga controller
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@@ -68,19 +72,28 @@ chip northbridge/intel/sandybridge
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 16.3 off end # Management Engine KT
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device pci 19.0 off end # Intel Gigabit Ethernet
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device pci 19.0 off end # Intel Gigabit Ethernet
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device pci 1a.0 on end # USB2 EHCI #2
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device pci 1a.0 on # USB2 EHCI #2
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device pci 1b.0 on end # High Definition Audio
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ioapic_irq 4 INTA 0x11
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end
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device pci 1b.0 on # High Definition Audio
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ioapic_irq 4 INTA 0x16
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end
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device pci 1c.0 on end # PCIe Port #1 (WLAN)
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device pci 1c.0 on end # PCIe Port #1 (WLAN)
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device pci 1c.1 off end # PCIe Port #2
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device pci 1c.1 off end # PCIe Port #2
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device pci 1c.2 off end # PCIe Port #3
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device pci 1c.2 off end # PCIe Port #3
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device pci 1c.3 on end # PCIe Port #4 (LAN)
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device pci 1c.3 on # PCIe Port #4 (LAN)
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# ioapic_irq 4 INTA 0x13
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end
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device pci 1c.4 off end # PCIe Port #5
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device pci 1c.4 off end # PCIe Port #5
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device pci 1c.5 off end # PCIe Port #6
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device pci 1c.5 off end # PCIe Port #6
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device pci 1c.6 off end # PCIe Port #7
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device pci 1c.6 off end # PCIe Port #7
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device pci 1c.7 off end # PCIe Port #8
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device pci 1c.7 off end # PCIe Port #8
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device pci 1d.0 on end # USB2 EHCI #1
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device pci 1d.0 on # USB2 EHCI #1
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ioapic_irq 4 INTA 0x13
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end
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device pci 1e.0 off end # PCI bridge
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on # LPC bridge
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device pci 1f.0 on # LPC bridge
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ioapic_irq 4 INTA 0x10
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chip superio/smsc/mec1308
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chip superio/smsc/mec1308
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device pnp 2e.1 on # PM1
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device pnp 2e.1 on # PM1
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io 0x60 = 0xb00
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io 0x60 = 0xb00
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@@ -102,9 +115,21 @@ chip northbridge/intel/sandybridge
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register "mailbox_port" = "0xa00"
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register "mailbox_port" = "0xa00"
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device pnp ff.1 off end
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device pnp ff.1 off end
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end
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end
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chip drivers/generic/ioapic
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register "have_isa_interrupts" = "1"
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register "irq_on_fsb" = "1"
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register "enable_virtual_wire" = "1"
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register "base" = "0xfec00000"
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device ioapic 4 on end
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end
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end
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device pci 1f.2 on # SATA Controller 1
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ioapic_irq 4 INTA 0x10
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end
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device pci 1f.3 on # SMBus
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ioapic_irq 4 INTC 0x17
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end
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end
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device pci 1f.2 on end # SATA Controller 1
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device pci 1f.3 on end # SMBus
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device pci 1f.5 off end # SATA Controller 2
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device pci 1f.5 off end # SATA Controller 2
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device pci 1f.6 on end # Thermal
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device pci 1f.6 on end # Thermal
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end
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end
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