AGESA,binaryPI: Replace use of __PRE_RAM__

Change-Id: Id878fd33ec3d2de640d9a488058a805be3ccd223
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

src/drivers/amd/agesa/def_callouts.c

@@ -160,18 +160,19 @@ AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINTN FchData, VOID *ConfigPrt)
 
 AGESA_STATUS agesa_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
-	AGESA_STATUS Status = AGESA_UNSUPPORTED;
+	if (!ENV_ROMSTAGE)
-#ifdef __PRE_RAM__
+		return AGESA_UNSUPPORTED;
-	Status = AmdMemoryReadSPD (Func, Data, ConfigPtr);
+
-#endif
+	return AmdMemoryReadSPD (Func, Data, ConfigPtr);
-	return Status;
 }
 
 AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
-	AGESA_STATUS Status = AGESA_UNSUPPORTED;
-#ifdef __PRE_RAM__
 	AGESA_READ_SPD_PARAMS *info = ConfigPtr;
+
+	if (!ENV_ROMSTAGE)
+		return AGESA_UNSUPPORTED;
+
 	if (info->MemChannelId > 0)
 		return AGESA_UNSUPPORTED;
 	if (info->SocketId != 0)
@@ -183,9 +184,7 @@ AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 	if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, 0) < 0)
 		die("No SPD data\n");
 
-	Status = AGESA_SUCCESS;
+	return AGESA_SUCCESS;
-#endif
-	return Status;
 }
 
 #if HAS_AGESA_FCH_OEM_CALLOUT

src/mainboard/amd/bettong/BiosCallOuts.c

@@ -117,9 +117,11 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
 
 static AGESA_STATUS board_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
-#ifdef __PRE_RAM__
-	int spdAddress;
 	AGESA_READ_SPD_PARAMS *info = ConfigPtr;
+	int spdAddress;
+
+	if (!ENV_ROMSTAGE)
+		return AGESA_UNSUPPORTED;
 
 	DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2);
 
@@ -154,6 +156,6 @@ static AGESA_STATUS board_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 	int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128);
 	if (err)
 		return AGESA_ERROR;
-#endif
+
 	return AGESA_SUCCESS;
 }

src/mainboard/bap/ode_e20XX/BiosCallOuts.c

@@ -191,11 +191,12 @@ void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
 
 static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
-	AGESA_STATUS Status = AGESA_UNSUPPORTED;
-#ifdef __PRE_RAM__
 	AGESA_READ_SPD_PARAMS *info = ConfigPtr;
 	u8 index;
 
+	if (!ENV_ROMSTAGE)
+		return AGESA_UNSUPPORTED;
+
 	if (CONFIG(BAP_E20_DDR3_1066))
 		index = 1;
 	else	/* CONFIG_BAP_E20_DDR3_800 */
@@ -212,7 +213,5 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi
 	if (read_ddr3_spd_from_cbfs((u8 *)info->Buffer, index) < 0)
 		die("No SPD data\n");
 
-	Status = AGESA_SUCCESS;
+	return AGESA_SUCCESS;
-#endif
-	return Status;
 }

src/mainboard/bap/ode_e21XX/BiosCallOuts.c

@@ -299,11 +299,12 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
 
 static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
-	AGESA_STATUS Status = AGESA_UNSUPPORTED;
-#ifdef __PRE_RAM__
 	AGESA_READ_SPD_PARAMS *info = ConfigPtr;
 	u8 index;
 
+	if (!ENV_ROMSTAGE)
+		return AGESA_UNSUPPORTED;
+
 	if (CONFIG(BAP_E21_DDR3_1066))
 		index = 1;
 	else if (CONFIG(BAP_E21_DDR3_1333))
@@ -322,7 +323,5 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi
 	if (read_ddr3_spd_from_cbfs((u8 *)info->Buffer, index) < 0)
 		die("No SPD data\n");
 
-	Status = AGESA_SUCCESS;
+	return AGESA_SUCCESS;
-#endif
-	return Status;
 }

src/mainboard/pcengines/apu1/BiosCallOuts.c

@@ -50,9 +50,11 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
 
 static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
-	AGESA_STATUS Status = AGESA_UNSUPPORTED;
-#ifdef __PRE_RAM__
 	AGESA_READ_SPD_PARAMS *info = ConfigPtr;
+
+	if (!ENV_ROMSTAGE)
+		return AGESA_UNSUPPORTED;
+
 	u8 index = get_spd_offset();
 
 	if (info->MemChannelId > 0)
@@ -66,7 +68,5 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi
 	if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, index) < 0)
 		die("No SPD data\n");
 
-	Status = AGESA_SUCCESS;
+	return AGESA_SUCCESS;
-#endif
-	return Status;
 }

src/mainboard/pcengines/apu2/BiosCallOuts.c

@@ -130,9 +130,11 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
 
 static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
-	AGESA_STATUS Status = AGESA_UNSUPPORTED;
-#ifdef __PRE_RAM__
 	AGESA_READ_SPD_PARAMS	*info = ConfigPtr;
+
+	if (!ENV_ROMSTAGE)
+		return AGESA_UNSUPPORTED;
+
 	u8 index = get_spd_offset();
 
 	if (info->MemChannelId > 0)
@@ -146,7 +148,5 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi
 	if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, index) < 0)
 		die("No SPD data\n");
 
-	Status = AGESA_SUCCESS;
+	return AGESA_SUCCESS;
-#endif
-	return Status;
 }

src/northbridge/amd/agesa/family12/northbridge.c

@@ -54,11 +54,7 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
 {
 	struct device *dev;
 	struct dram_base_mask_t d;
-#if defined(__PRE_RAM__)
-	dev = PCI_DEV(0, DEV_CDB, 1);
-#else
 	dev = __f1_dev[0];
-#endif	// defined(__PRE_RAM__)
 
 	u32 temp;
 	temp = pci_read_config32(dev, 0x44); //[39:24] at [31:16]

src/northbridge/amd/agesa/family14/northbridge.c

@@ -52,11 +52,7 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
 {
 	struct device *dev;
 	struct dram_base_mask_t d;
-#if defined(__PRE_RAM__)
-	dev = PCI_DEV(0, DEV_CDB, 1);
-#else
 	dev = __f1_dev[0];
-#endif	// defined(__PRE_RAM__)
 
 	u32 temp;
 	temp = pci_read_config32(dev, 0x44); //[39:24] at [31:16]

src/northbridge/amd/pi/agesawrapper.c

@@ -248,13 +248,15 @@ AGESA_STATUS agesawrapper_amdinitmid(void)
 	return status;
 }
 
-#ifndef __PRE_RAM__
 AGESA_STATUS agesawrapper_amdinitlate(void)
 {
 	AGESA_STATUS Status;
 	AMD_INTERFACE_PARAMS AmdParamStruct;
 	AMD_LATE_PARAMS *AmdLateParams;
 
+	if (!ENV_RAMSTAGE)
+		return AGESA_UNSUPPORTED;
+
 	LibAmdMemFill (&AmdParamStruct,
 		       0,
 		       sizeof(AMD_INTERFACE_PARAMS),
@@ -289,7 +291,6 @@ AGESA_STATUS agesawrapper_amdinitlate(void)
 	/* No AmdReleaseStruct(&AmdParamStruct), we need AmdLateParams later. */
 	return Status;
 }
-#endif /* #ifndef __PRE_RAM__ */
 
 const void *agesawrapper_locate_module (const CHAR8 name[8])
 {

src/southbridge/amd/agesa/hudson/hudson.h

@@ -61,14 +61,11 @@ static inline int hudson_ide_enable(void)
 	return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3);
 }
 
-#ifndef __SMM__
-
 void pm_write8(u8 reg, u8 value);
 u8 pm_read8(u8 reg);
 void pm_write16(u8 reg, u16 value);
 u16 pm_read16(u16 reg);
 
-#ifdef __SIMPLE_DEVICE__
 void hudson_lpc_port80(void);
 void hudson_pci_port80(void);
 void hudson_clk_output_48Mhz(void);
@@ -76,10 +73,6 @@ void hudson_clk_output_48Mhz(void);
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 
-#else
 void hudson_enable(struct device *dev);
 
-#endif /* __PRE_RAM__ */
-#endif /* __SMM__ */
-
 #endif /* HUDSON_H */

src/southbridge/amd/agesa/hudson/imc.c

@@ -54,7 +54,6 @@ void imc_reg_init(void)
 #endif
 }
 
-#ifndef __PRE_RAM__
 void enable_imc_thermal_zone(void)
 {
 	AMD_CONFIG_PARAMS StdHeader;
@@ -83,4 +82,3 @@ void enable_imc_thermal_zone(void)
 	WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader);     // function number
 	WaitForEcLDN9MailboxCmdAck(&StdHeader);
 }
-#endif

src/southbridge/amd/cimx/sb800/fan.h

@@ -16,10 +16,10 @@
 #ifndef _SB800_FAN_H_
 #define _SB800_FAN_H_
 
-#ifndef __PRE_RAM__
+#include <device/device.h>
+
 void init_sb800_IMC_fans(struct device *dev);
 void init_sb800_MANUAL_fans(struct device *dev);
-#endif
 
 /* Fan Register Definitions */
 #define FAN_0_OFFSET				0x00

src/southbridge/amd/cimx/sb900/cfg.c

@@ -243,15 +243,13 @@ void sb900_cimx_config(AMDSBCFG *sb_config)
 	sb_config->PciClks								= SB_PCI_CLOCK_RESERVED;
 	sb_config->hwm.hwmEnable						= 0x0;
 
-#ifndef __PRE_RAM__
 	/* ramstage cimx config here */
-	if (!sb_config->StdHeader.CALLBACK.CalloutPtr) {
+	if (ENV_RAMSTAGE && !sb_config->StdHeader.CALLBACK.CalloutPtr) {
 		sb_config->StdHeader.CALLBACK.CalloutPtr = sb900_callout_entry;
 	}
 
 	//sb_config->
-#endif //!__PRE_RAM__
+	printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n");
-    printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n");
 }
 
 void SbPowerOnInit_Config(AMDSBCFG *sb_config)

src/southbridge/amd/common/amd_pci_util.c

@@ -22,8 +22,6 @@
 #include "amd_pci_int_defs.h"
 #include "amd_pci_int_types.h"
 
-#ifndef __PRE_RAM__
-
 const struct pirq_struct * pirq_data_ptr = NULL;
 u32 pirq_data_size = 0;
 const u8 *intr_data_ptr = NULL;
@@ -195,4 +193,3 @@ void write_pci_cfg_irqs(void)
 	}	/* for (dev = all_devices) */
 	printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n");
 }
-#endif /* __PRE_RAM__ */

src/southbridge/amd/common/amd_pci_util.h

@@ -23,8 +23,6 @@
 #define PCI_INTR_INDEX	0xc00
 #define PCI_INTR_DATA	0xc01
 
-#ifndef __PRE_RAM__
-
 struct pirq_struct {
 	u8 devfn;
 	u8 PIN[4];	/* PINA/B/C/D are index 0/1/2/3 */
@@ -39,6 +37,5 @@ u8 read_pci_int_idx(u8 index, int mode);
 void write_pci_int_idx(u8 index, int mode, u8 data);
 void write_pci_cfg_irqs(void);
 void write_pci_int_table (void);
-#endif /* __PRE_RAM */
 
 #endif /* AMD_PCI_UTIL_H */

src/southbridge/amd/pi/hudson/hudson.h

@@ -169,14 +169,11 @@ static inline int hudson_ide_enable(void)
 	return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3);
 }
 
-#ifndef __SMM__
-
 void pm_write8(u8 reg, u8 value);
 u8 pm_read8(u8 reg);
 void pm_write16(u8 reg, u16 value);
 u16 pm_read16(u16 reg);
 
-#ifdef __PRE_RAM__
 void hudson_lpc_port80(void);
 void hudson_lpc_decode(void);
 void hudson_pci_port80(void);
@@ -190,15 +187,9 @@ void lpc_wideio_16_window(uint16_t base);
 void hudson_tpm_decode_spi(void);
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
-#if CONFIG(HUDSON_UART)
 void configure_hudson_uart(void);
-#endif
 
-#else
 void hudson_enable(struct device *dev);
 void s3_resume_init_data(void *FchParams);
 
-#endif /* __PRE_RAM__ */
-#endif /* __SMM__ */
-
 #endif /* HUDSON_H */

src/southbridge/amd/pi/hudson/imc.c

@@ -51,7 +51,6 @@ void imc_reg_init(void)
 	pci_write_config8(PCI_DEV(0, 0x18, 0x3), 0x1E4, reg8);
 }
 
-#ifndef __PRE_RAM__
 void enable_imc_thermal_zone(void)
 {
 	AMD_CONFIG_PARAMS StdHeader;
@@ -80,4 +79,3 @@ void enable_imc_thermal_zone(void)
 	WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader);
 	WaitForEcLDN9MailboxCmdAck(&StdHeader);
 }
-#endif

src/vendorcode/amd/agesa/common/agesa-entry-cfg.h

@@ -2,7 +2,7 @@
 #define AGESA_ENTRY_CFG_H
 
 
-#if defined(__PRE_RAM__)
+#if ENV_ROMSTAGE
 
 #define AGESA_ENTRY_INIT_RESET		TRUE
 #define AGESA_ENTRY_INIT_EARLY		TRUE