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Clean up some comments and white space in gx2/northbridgeinit.c

Browse Source 
and gx2/raminit.c.

This is Abuild and boot tested.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Nils Jacobs 2010-11-03 13:19:50 +00:00 committed by Uwe Hermann
parent b54585244b
commit 5beac7f996
2 changed files with 212 additions and 270 deletions
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231
src/northbridge/amd/gx2/northbridgeinit.c
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@ -32,7 +32,6 @@ struct gliutable gliu0table[] = {
{.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0}, {.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
}; };
struct gliutable gliu1table[] = { struct gliutable gliu1table[] = {
{.desc_name=MSR_GLIU1_BASE1,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ {.desc_name=MSR_GLIU1_BASE1,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */
{.desc_name=MSR_GLIU1_BASE2,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0}, /* 80000-9ffff to Mc */ {.desc_name=MSR_GLIU1_BASE2,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0}, /* 80000-9ffff to Mc */
@ -87,9 +86,8 @@ struct msrinit ClockGatingPerformance[] = {
{GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}},
{0xffffffff, {0xffffffff, 0xffffffff}}, {0xffffffff, {0xffffffff, 0xffffffff}},
}; };
/* */
/* SET GeodeLink PRIORITY */ /* SET GeodeLink PRIORITY */
/* */
struct msrinit GeodeLinkPriorityTable [] = { struct msrinit GeodeLinkPriorityTable [] = {
{CPU_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0220}}, /* CPU Priority. */ {CPU_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0220}}, /* CPU Priority. */
{DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}}, /* DF Priority. */ {DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}}, /* DF Priority. */
@ -111,7 +109,7 @@ writeglmsr(struct gliutable *gl){
msr.lo = gl->lo; msr.lo = gl->lo;
msr.hi = gl->hi; msr.hi = gl->hi;
wrmsr(gl->desc_name, msr); // MSR - see table above wrmsr(gl->desc_name, msr); /* MSR - see table above */
printk(BIOS_DEBUG, "%s: write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); printk(BIOS_DEBUG, "%s: write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
/* they do this, so we do this */ /* they do this, so we do this */
msr = rdmsr(gl->desc_name); msr = rdmsr(gl->desc_name);
@ -133,8 +131,7 @@ ShadowInit(struct gliutable *gl)
/* NOTE: transcribed from assembly code. There is the usual redundant assembly nonsense in here. /* NOTE: transcribed from assembly code. There is the usual redundant assembly nonsense in here.
* CLEAN ME UP * CLEAN ME UP
*/ */
/* yes, this duplicates later code, but it seems that is how they want it done. /* yes, this duplicates later code, but it seems that is how they want it done. */
*/
static void static void
SysmemInit(struct gliutable *gl) SysmemInit(struct gliutable *gl)
{ {
@ -161,12 +158,12 @@ SysmemInit(struct gliutable *gl)
sizebytes &= 0xfff00000; sizebytes &= 0xfff00000;
sizebytes |= 0x100; sizebytes |= 0x100;
msr.lo = sizebytes; msr.lo = sizebytes;
wrmsr(gl->desc_name, msr); // MSR - see table above wrmsr(gl->desc_name, msr); /* MSR - see table above */
msr = rdmsr(gl->desc_name); msr = rdmsr(gl->desc_name);
printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__,
gl->desc_name, msr.hi, msr.lo); gl->desc_name, msr.hi, msr.lo);
} }
static void static void
DMMGL0Init(struct gliutable *gl) { DMMGL0Init(struct gliutable *gl) {
msr_t msr; msr_t msr;
@ -189,11 +186,11 @@ DMMGL0Init(struct gliutable *gl) {
msr.lo = DMM_OFFSET << 8; msr.lo = DMM_OFFSET << 8;
msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff; msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff;
wrmsr(gl->desc_name, msr); // MSR - See table above wrmsr(gl->desc_name, msr); /* MSR - See table above */
msr = rdmsr(gl->desc_name); msr = rdmsr(gl->desc_name);
printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
} }
static void static void
DMMGL1Init(struct gliutable *gl) { DMMGL1Init(struct gliutable *gl) {
msr_t msr; msr_t msr;
@ -212,10 +209,11 @@ DMMGL1Init(struct gliutable *gl) {
printk(BIOS_ERR, "%s: warning, using DMM_SIZE even though AMD used SMM_SIZE\n", __func__); printk(BIOS_ERR, "%s: warning, using DMM_SIZE even though AMD used SMM_SIZE\n", __func__);
msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff; msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff;
wrmsr(gl->desc_name, msr); // MSR - See table above wrmsr(gl->desc_name, msr); /* MSR - See table above */
msr = rdmsr(gl->desc_name); msr = rdmsr(gl->desc_name);
printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
} }
static void static void
SMMGL0Init(struct gliutable *gl) { SMMGL0Init(struct gliutable *gl) {
msr_t msr; msr_t msr;
@ -239,10 +237,11 @@ SMMGL0Init(struct gliutable *gl) {
msr.lo = SMM_OFFSET << 8; msr.lo = SMM_OFFSET << 8;
msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff; msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff;
wrmsr(gl->desc_name, msr); // MSR - See table above wrmsr(gl->desc_name, msr); /* MSR - See table above */
msr = rdmsr(gl->desc_name); msr = rdmsr(gl->desc_name);
printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
} }
static void static void
SMMGL1Init(struct gliutable *gl) { SMMGL1Init(struct gliutable *gl) {
msr_t msr; msr_t msr;
@ -255,7 +254,7 @@ SMMGL1Init(struct gliutable *gl) {
msr.lo = SMM_OFFSET << 8; msr.lo = SMM_OFFSET << 8;
msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff; msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff;
wrmsr(gl->desc_name, msr); // MSR - See table above wrmsr(gl->desc_name, msr); /* MSR - See table above */
msr = rdmsr(gl->desc_name); msr = rdmsr(gl->desc_name);
printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
} }
@ -294,42 +293,31 @@ GLIUInit(struct gliutable *gl){
} }
gl++; gl++;
} }
} }
/* ***************************************************************************/
/* **/ /*
/* * GLPCIInit*/ * Set up GLPCI settings for reads/write into memory.
/* **/ *
/* * Set up GLPCI settings for reads/write into memory*/ * R0: 0-640KB,
/* * R0: 0-640KB,*/ * R1: 1MB - Top of System Memory
/* * R1: 1MB - Top of System Memory*/ * R2: SMM Memory
/* * R2: SMM Memory*/ * R3: Framebuffer? - not set up yet
/* * R3: Framebuffer? - not set up yet*/ * R4: ??
/* * R4: ??*/ */
/* **/
/* * Entry:*/
/* * Exit:*/
/* * Modified:*/
/* **/
/* ***************************************************************************/
static void GLPCIInit(void){ static void GLPCIInit(void){
struct gliutable *gl = 0; struct gliutable *gl = 0;
int i; int i;
msr_t msr; msr_t msr;
int msrnum; int msrnum;
/* */
/* R0 - GLPCI settings for Conventional Memory space. */ /* R0 - GLPCI settings for Conventional Memory space. */
/* */ msr.hi = (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT; /* 640 */
msr.hi = (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT /* 640*/; msr.lo = 0; /* 0 */
msr.lo = 0 /* 0*/;
msr.lo |= GLPCI_RC_LOWER_EN_SET+ GLPCI_RC_LOWER_PF_SET + GLPCI_RC_LOWER_WC_SET; msr.lo |= GLPCI_RC_LOWER_EN_SET+ GLPCI_RC_LOWER_PF_SET + GLPCI_RC_LOWER_WC_SET;
msrnum = GLPCI_RC0; msrnum = GLPCI_RC0;
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
/* */
/* R1 - GLPCI settings for SysMem space. */ /* R1 - GLPCI settings for SysMem space. */
/* */
/* Get systop from GLIU0 SYSTOP Descriptor */ /* Get systop from GLIU0 SYSTOP Descriptor */
for(i = 0; gliu0table[i].desc_name != GL_END; i++) { for(i = 0; gliu0table[i].desc_name != GL_END; i++) {
if (gliu0table[i].desc_type == R_SYSMEM) { if (gliu0table[i].desc_type == R_SYSMEM) {
@ -345,8 +333,8 @@ static void GLPCIInit(void){
* translates to a base of 0x00100000 and top of 0xffbf0000 * translates to a base of 0x00100000 and top of 0xffbf0000
* base of 1M and top of around 256M * base of 1M and top of around 256M
*/ */
/* we have to create a page-aligned (4KB page) address for base and top */ /* we have to create a page-aligned (4KB page) address for base and top
/* So we need a high page aligned addresss (pah) and low page aligned address (pal) * So we need a high page aligned addresss (pah) and low page aligned address (pal)
* pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12 * pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12
*/ */
printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi); printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
@ -363,9 +351,7 @@ static void GLPCIInit(void){
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
} }
/* */
/* R2 - GLPCI settings for SMM space. */ /* R2 - GLPCI settings for SMM space. */
/* */
msr.hi = ((SMM_OFFSET+(SMM_SIZE*1024-1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT; msr.hi = ((SMM_OFFSET+(SMM_SIZE*1024-1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;
msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT; msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT;
msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET; msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET;
@ -374,8 +360,8 @@ static void GLPCIInit(void){
/* this is done elsewhere already, but it does no harm to do it more than once */ /* this is done elsewhere already, but it does no harm to do it more than once */
/* write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility. */ /* write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility. */
msr.lo = 0x021212121 /* cache disabled and write serialized*/; msr.lo = 0x021212121; /* cache disabled and write serialized */
msr.hi = 0x021212121 /* cache disabled and write serialized*/; msr.hi = 0x021212121; /* cache disabled and write serialized */
msrnum = CPU_RCONF_A0_BF; msrnum = CPU_RCONF_A0_BF;
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
@ -411,16 +397,13 @@ static void GLPCIInit(void){
/* we are ignoring the 5530 case for now, and perhaps forever. */ /* we are ignoring the 5530 case for now, and perhaps forever. */
/* */
/* 5535 NB Init */ /* 5535 NB Init */
/* */
msrnum = GLPCI_ARB; msrnum = GLPCI_ARB;
msr = rdmsr(msrnum); msr = rdmsr(msrnum);
msr.hi |= GLPCI_ARB_UPPER_PRE0_SET | GLPCI_ARB_UPPER_PRE1_SET; msr.hi |= GLPCI_ARB_UPPER_PRE0_SET | GLPCI_ARB_UPPER_PRE1_SET;
msr.lo |= GLPCI_ARB_LOWER_IIE_SET; msr.lo |= GLPCI_ARB_LOWER_IIE_SET;
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
msrnum = GLPCI_CTRL; msrnum = GLPCI_CTRL;
msr = rdmsr(msrnum); msr = rdmsr(msrnum);
@ -449,7 +432,6 @@ static void GLPCIInit(void){
msr.hi |= 0x00 << GLPCI_CTRL_UPPER_ILTO_SHIFT; msr.hi |= 0x00 << GLPCI_CTRL_UPPER_ILTO_SHIFT;
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
/* Set GLPCI Latency Timer. */ /* Set GLPCI Latency Timer. */
msrnum = GLPCI_CTRL; msrnum = GLPCI_CTRL;
msr = rdmsr(msrnum); msr = rdmsr(msrnum);
@ -462,24 +444,11 @@ static void GLPCIInit(void){
msr.lo &= ~ 0x7; msr.lo &= ~ 0x7;
msr.lo |= GLPCI_SPARE_LOWER_AILTO_SET | GLPCI_SPARE_LOWER_PPD_SET | GLPCI_SPARE_LOWER_PPC_SET | GLPCI_SPARE_LOWER_MPC_SET | GLPCI_SPARE_LOWER_NSE_SET | GLPCI_SPARE_LOWER_SUPO_SET; msr.lo |= GLPCI_SPARE_LOWER_AILTO_SET | GLPCI_SPARE_LOWER_PPD_SET | GLPCI_SPARE_LOWER_PPC_SET | GLPCI_SPARE_LOWER_MPC_SET | GLPCI_SPARE_LOWER_NSE_SET | GLPCI_SPARE_LOWER_SUPO_SET;
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
} }
/* Enable Clock Gating. */
static void ClockGatingInit (void)
/* ***************************************************************************/ {
/* **/
/* * ClockGatingInit*/
/* **/
/* * Enable Clock Gating.*/
/* **/
/* * Entry:*/
/* * Exit:*/
/* * Modified:*/
/* **/
/* ***************************************************************************/
static void
ClockGatingInit (void){
msr_t msr; msr_t msr;
struct msrinit *gating = ClockGatingDefault; struct msrinit *gating = ClockGatingDefault;
int i; int i;
@ -511,14 +480,13 @@ performance:
msr.lo |= gating->msr.lo; msr.lo |= gating->msr.lo;
printk(BIOS_DEBUG, "%s: MSR 0x%08lx will be set to 0x%08x:0x%08x\n", __func__, printk(BIOS_DEBUG, "%s: MSR 0x%08lx will be set to 0x%08x:0x%08x\n", __func__,
gating->msrnum, msr.hi, msr.lo); gating->msrnum, msr.hi, msr.lo);
wrmsr(gating->msrnum, msr); // MSR - See the table above wrmsr(gating->msrnum, msr); /* MSR - See the table above */
gating +=1; gating +=1;
} }
} }
static void static void GeodeLinkPriority(void)
GeodeLinkPriority(void){ {
msr_t msr; msr_t msr;
struct msrinit *prio = GeodeLinkPriorityTable; struct msrinit *prio = GeodeLinkPriorityTable;
int i; int i;
@ -531,15 +499,14 @@ GeodeLinkPriority(void){
msr.lo |= prio->msr.lo; msr.lo |= prio->msr.lo;
printk(BIOS_DEBUG, "%s: MSR 0x%08lx will be set to 0x%08x:0x%08x\n", __func__, printk(BIOS_DEBUG, "%s: MSR 0x%08lx will be set to 0x%08x:0x%08x\n", __func__,
prio->msrnum, msr.hi, msr.lo); prio->msrnum, msr.hi, msr.lo);
wrmsr(prio->msrnum, msr); // MSR - See the table above wrmsr(prio->msrnum, msr); /* MSR - See the table above */
prio +=1; prio +=1;
} }
} }
/* /*
* Get the GLIU0 shadow register settings * Get the GLIU0 shadow register settings.
*
* If the setShadow function is used then all shadow descriptors * If the setShadow function is used then all shadow descriptors
* will stay sync'ed. * will stay sync'ed.
*/ */
@ -550,61 +517,61 @@ static uint64_t getShadow(void)
return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo; return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo;
} }
/* /*
* Set the cache RConf registers for the memory hole. * Set the cache RConf registers for the memory hole.
*
* Keeps all cache shadow descriptors sync'ed. * Keeps all cache shadow descriptors sync'ed.
* This is part of the PCI lockup solution * This is part of the PCI lockup solution.
* Entry: EDX:EAX is the shadow settings *
* Entry: EDX:EAX is the shadow settings.
*/ */
static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo) static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
{ {
// ok this is whacky bit translation time. /* ok this is whacky bit translation time. */
int bit; int bit;
uint8_t shadowByte; uint8_t shadowByte;
msr_t msr; msr_t msr;
shadowByte = (uint8_t) (shadowLo >> 16); shadowByte = (uint8_t) (shadowLo >> 16);
// load up D000 settings in edx. /* load up D000 settings in edx. */
for (bit = 8; (bit > 4); bit--) { for (bit = 8; (bit > 4); bit--) {
msr.hi <<= 8; msr.hi <<= 8;
msr.hi |= 1; // cache disable PCI/Shadow memory msr.hi |= 1; /* cache disable PCI/Shadow memory */
if (shadowByte && (1 << bit)) if (shadowByte && (1 << bit))
msr.hi |= 0x20; // write serialize PCI memory msr.hi |= 0x20; /* write serialize PCI memory */
} }
// load up C000 settings in eax. /* load up C000 settings in eax. */
for ( ; bit; bit--) { for ( ; bit; bit--) {
msr.lo <<= 8; msr.lo <<= 8;
msr.lo |= 1; // cache disable PCI/Shadow memory msr.lo |= 1; /* cache disable PCI/Shadow memory */
if (shadowByte && (1 << bit)) if (shadowByte && (1 << bit))
msr.lo |= 0x20; // write serialize PCI memory msr.lo |= 0x20; /* write serialize PCI memory */
} }
wrmsr(CPU_RCONF_C0_DF, msr); wrmsr(CPU_RCONF_C0_DF, msr);
shadowByte = (uint8_t) (shadowLo >> 24); shadowByte = (uint8_t) (shadowLo >> 24);
// load up F000 settings in edx. /* load up F000 settings in edx. */
for (bit = 8; (bit > 4); bit--) { for (bit = 8; (bit > 4); bit--) {
msr.hi <<= 8; msr.hi <<= 8;
msr.hi |= 1; // cache disable PCI/Shadow memory msr.hi |= 1; /* cache disable PCI/Shadow memory */
if (shadowByte && (1 << bit)) if (shadowByte && (1 << bit))
msr.hi |= 0x20; // write serialize PCI memory msr.hi |= 0x20; /* write serialize PCI memory */
} }
// load up E000 settings in eax. /* load up E000 settings in eax. */
for ( ; bit; bit--) { for ( ; bit; bit--) {
msr.lo <<= 8; msr.lo <<= 8;
msr.lo |= 1; // cache disable PCI/Shadow memory msr.lo |= 1; /* cache disable PCI/Shadow memory */
if (shadowByte && (1 << bit)) if (shadowByte && (1 << bit))
msr.lo |= 0x20; // write serialize PCI memory msr.lo |= 0x20; /* write serialize PCI memory */
} }
wrmsr(CPU_RCONF_E0_FF, msr); wrmsr(CPU_RCONF_E0_FF, msr);
} }
/* /*
* Set the GLPCI registers for the memory hole. * Set the GLPCI registers for the memory hole.
* Keeps all cache shadow descriptors sync'ed. * Keeps all cache shadow descriptors sync'ed.
@ -614,15 +581,13 @@ static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo)
{ {
msr_t msr; msr_t msr;
// Set the Enable Register. /* Set the Enable Register. */
msr = rdmsr(GLPCI_REN); msr = rdmsr(GLPCI_REN);
msr.lo &= 0xFFFF00FF; msr.lo &= 0xFFFF00FF;
msr.lo |= ( (shadowLo & 0xFFFF0000) >> 8); msr.lo |= ( (shadowLo & 0xFFFF0000) >> 8);
wrmsr(GLPCI_REN, msr); wrmsr(GLPCI_REN, msr);
} }
/* /*
* Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW. * Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW.
* Keeps all shadow descriptors sync'ed. * Keeps all shadow descriptors sync'ed.
@ -647,41 +612,26 @@ static void setShadow(uint64_t shadowSettings)
msr = rdmsr(pTable->desc_name); msr = rdmsr(pTable->desc_name);
msr.lo = (uint32_t) shadowSettings; msr.lo = (uint32_t) shadowSettings;
msr.hi &= 0xFFFF0000; // maintain PDID in upper EDX msr.hi &= 0xFFFF0000; /* maintain PDID in upper EDX */
msr.hi |= ((uint32_t) (shadowSettings >> 32)) & 0x0000FFFF; msr.hi |= ((uint32_t) (shadowSettings >> 32)) & 0x0000FFFF;
wrmsr(pTable->desc_name, msr); // MSR - See the table above wrmsr(pTable->desc_name, msr); /* MSR - See the table above */
} }
} }
} }
} }
/************************************************************************** /* Set up a stack for ease of further testing. */
* static void shadowRom(void)
* shadowRom
*
* Set up a stack for ease of further testing
*
* Entry:
* Exit:
* Destroys:
*
**************************************************************************/
static void
shadowRom(void)
{ {
uint64_t shadowSettings = getShadow(); uint64_t shadowSettings = getShadow();
shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL; // Disable read & writes shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL; /* Disable read & writes */
shadowSettings |= (uint64_t) 0x0000FFFFFFFF0000ULL; // Enable reads for C0000-FFFFF shadowSettings |= (uint64_t) 0x0000FFFFFFFF0000ULL; /* Enable reads for C0000-FFFFF */
setShadow(shadowSettings); setShadow(shadowSettings);
} }
/*
* Set up RCONF_DEFAULT and any other RCONF registers needed.
/***************************************************************************
*
* RCONFInit
* Set up RCONF_DEFAULT and any other RCONF registers needed
* *
* DEVRC_RCONF_DEFAULT: * DEVRC_RCONF_DEFAULT:
* ROMRC(63:56) = 04h ; write protect ROMBASE * ROMRC(63:56) = 04h ; write protect ROMBASE
@ -689,8 +639,7 @@ shadowRom(void)
* DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst. * DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst.
* SYSTOP(27:8) = top of system memory * SYSTOP(27:8) = top of system memory
* SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough
* */
***************************************************************************/
#define SYSMEM_RCONF_WRITETHROUGH 8 #define SYSMEM_RCONF_WRITETHROUGH 8
#define DEVRC_RCONF_DEFAULT 0x21 #define DEVRC_RCONF_DEFAULT 0x21
#define ROMBASE_RCONF_DEFAULT 0xFFFC0000 #define ROMBASE_RCONF_DEFAULT 0xFFFC0000
@ -716,7 +665,7 @@ RCONFInit(void)
while (1); while (1);
} }
// sysdescfound: /* sysdescfound: */
/* found the descriptor... get its contents */ /* found the descriptor... get its contents */
msr = rdmsr(gl->desc_name); msr = rdmsr(gl->desc_name);
@ -725,26 +674,26 @@ RCONFInit(void)
*/ */
msr.lo = (msr.lo & 0xFFFFFF00) | (msr.hi & 0xFF); msr.lo = (msr.lo & 0xFFFFFF00) | (msr.hi & 0xFF);
msr.lo = ((msr.lo << 12) | (msr.lo >> 20)) & 0x000FFFFF; msr.lo = ((msr.lo << 12) | (msr.lo >> 20)) & 0x000FFFFF;
msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT; // 8 msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT; /* 8 */
// Set Default SYSMEM region properties /* Set Default SYSMEM region properties */
msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH; // 8 (or ~8) msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH; /* 8 (or ~8) */
// Set PCI space cache properties /* Set PCI space cache properties */
msr.hi = (DEVRC_RCONF_DEFAULT >> 4); // only need the bottom bits and lets clean the rest of edx msr.hi = (DEVRC_RCONF_DEFAULT >> 4); /* only need the bottom bits and lets clean the rest of edx */
msr.lo |= (DEVRC_RCONF_DEFAULT << 28); msr.lo |= (DEVRC_RCONF_DEFAULT << 28);
// Set the ROMBASE. This is usually FFFC0000h /* Set the ROMBASE. This is usually FFFC0000h */
msr.hi |= (ROMBASE_RCONF_DEFAULT >> 12) << RCONF_DEFAULT_UPPER_ROMBASE_SHIFT; msr.hi |= (ROMBASE_RCONF_DEFAULT >> 12) << RCONF_DEFAULT_UPPER_ROMBASE_SHIFT;
// Set ROMBASE cache properties. /* Set ROMBASE cache properties. */
msr.hi |= ((ROMRC_RCONF_DEFAULT >> 8) | (ROMRC_RCONF_DEFAULT << 24)); msr.hi |= ((ROMRC_RCONF_DEFAULT >> 8) | (ROMRC_RCONF_DEFAULT << 24));
// now program RCONF_DEFAULT /* now program RCONF_DEFAULT */
wrmsr(CPU_RCONF_DEFAULT, msr); wrmsr(CPU_RCONF_DEFAULT, msr);
// RCONF_BYPASS: Cache tablewalk properties and SMM/DMM header access properties. /* RCONF_BYPASS: Cache tablewalk properties and SMM/DMM header access properties. */
// Set to match system memory cache properties. /* Set to match system memory cache properties. */
msr = rdmsr(CPU_RCONF_DEFAULT); msr = rdmsr(CPU_RCONF_DEFAULT);
SysMemCacheProp = (uint8_t) (msr.lo & 0xFF); SysMemCacheProp = (uint8_t) (msr.lo & 0xFF);
msr = rdmsr(CPU_RCONF_BYPASS); msr = rdmsr(CPU_RCONF_BYPASS);
@ -752,21 +701,8 @@ RCONFInit(void)
wrmsr(CPU_RCONF_BYPASS, msr); wrmsr(CPU_RCONF_BYPASS, msr);
} }
/* Core Logic initialization: Host bridge. */
/* ***************************************************************************/ void northbridgeinit(void)
/* **/
/* * northBridgeInit*/
/* **/
/* * Core Logic initialization: Host bridge*/
/* **/
/* * Entry:*/
/* * Exit:*/
/* * Modified:*/
/* **/
/* ***************************************************************************/
void
northbridgeinit(void)
{ {
msr_t msr; msr_t msr;
int i; int i;
@ -779,16 +715,17 @@ northbridgeinit(void)
shadowRom(); shadowRom();
// GeodeROM ensures that the BIOS waits the required 1 second before /* GeodeROM ensures that the BIOS waits the required 1 second before */
// allowing anything to access PCI /* allowing anything to access PCI */
// PCIDelay(); // PCIDelay();
RCONFInit(); RCONFInit();
// The cacheInit function in GeodeROM tests cache and, among other things, /* The cacheInit function in GeodeROM tests cache and, among other things,
// makes sure all INVD instructions are treated as WBINVD. We do this * makes sure all INVD instructions are treated as WBINVD. We do this
// because we've found some programs which require this behavior. * because we've found some programs which require this behavior.
// That subset of cacheInit() is implemented here: * That subset of cacheInit() is implemented here:
*/
msr = rdmsr(CPU_DM_CONFIG0); msr = rdmsr(CPU_DM_CONFIG0);
msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET; msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET;
wrmsr(CPU_DM_CONFIG0, msr); wrmsr(CPU_DM_CONFIG0, msr);

105
src/northbridge/amd/gx2/raminit.c
View File

@ -80,12 +80,13 @@ static void auto_size_dimm(unsigned int dimm)
dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT; dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
banner("SPDNUMROWS"); banner("SPDNUMROWS");
/*; Field: DIMM size /* Field: DIMM size
*; EEPROM byte usage: (3) Number of Row Addresses * EEPROM byte usage:
*; (4) Number of Column Addresses * (3) Number of Row Addresses
*; (5) Number of DIMM Banks * (4) Number of Column Addresses
*; (31) Module Bank Density * (5) Number of DIMM Banks
*; Size = Module Density * Module Banks * (31) Module Bank Density
* Size = Module Density * Module Banks
*/ */
if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0) if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
|| (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) { || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
@ -113,27 +114,32 @@ static void auto_size_dimm(unsigned int dimm)
dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT; dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
banner("PAGESIZE"); banner("PAGESIZE");
/*; Field: PAGE size /*
*; EEPROM byte usage: (4) Number of Column Addresses * Field: PAGE size
*; PageSize = 2^# Column Addresses * Data width in bytes (should be 8bytes for a normal DIMM) * EEPROM byte usage: (4) Number of Column Addresses
* PageSize = 2^# Column Addresses * Data width in bytes
* (should be 8bytes for a normal DIMM)
* *
*; But this really works by magic. * But this really works by magic.
*; If ma[11:0] is the memory address pins, and pa[13:0] is the physical column address * If ma[11:0] is the memory address pins, and pa[13:0] is the physical column
*; that MC generates, here is how the MC assigns the pa onto the ma pins: * address that MC generates, here is how the MC assigns the pa onto the
* ma pins:
* *
*;ma 11 10 09 08 07 06 05 04 03 02 01 00 * ma 11 10 09 08 07 06 05 04 03 02 01 00
*;-------------------------------------------------------------------------------------------------------------------------------------- * ---------------------------------------
*;pa 09 08 07 06 05 04 03 (7 col addr bits = 1K page size) * pa 09 08 07 06 05 04 03 (7 col addr bits = 1K page size)
*;pa 10 09 08 07 06 05 04 03 (8 col addr bits = 2K page size) * pa 10 09 08 07 06 05 04 03 (8 col addr bits = 2K page size)
*;pa 11 10 09 08 07 06 05 04 03 (9 col addr bits = 4K page size) * pa 11 10 09 08 07 06 05 04 03 (9 col addr bits = 4K page size)
*;pa 12 11 10 09 08 07 06 05 04 03 (10 col addr bits = 8K page size) * pa 12 11 10 09 08 07 06 05 04 03 (10 col addr bits = 8K page size)
*;pa 13 AP 12 11 10 09 08 07 06 05 04 03 (11 col addr bits = 16K page size) * pa 13 AP 12 11 10 09 08 07 06 05 04 03 (11 col addr bits = 16K page size)
*; *AP=autoprecharge bit
* *
*; Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes), * (AP = autoprecharge bit)
*; so lower 3 address bits are dont_cares.So from the table above, *
*; it's easier to see what the old code is doing: if for example,#col_addr_bits=7(06h), * Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes),
*; it adds 3 to get 10, then does 2^10=1K. Get it?*/ * so lower 3 address bits are dont_cares. So from the table above,
* it's easier to see what the old code is doing: if for example,
* #col_addr_bits=7(06h), it adds 3 to get 10, then does 2^10=1K.
*/
spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF]; spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
banner("MAXCOLADDR"); banner("MAXCOLADDR");
@ -269,26 +275,25 @@ static u8 getcasmap(u32 dimm, u16 glspeed)
static void setCAS(void) static void setCAS(void)
{ {
/*;***************************************************************************** /*
;* * setCAS
;* setCAS * EEPROM byte usage: (18) SDRAM device attributes - CAS latency
;* EEPROM byte usage: (18) SDRAM device attributes - CAS latency * EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5
;* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5 * EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1
;* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1 *
;* * The CAS setting is based on the information provided in each DIMMs SPD.
;* The CAS setting is based on the information provided in each DIMMs SPD. * The speed at which a DIMM can run is described relative to the slowest
;* The speed at which a DIMM can run is described relative to the slowest * CAS the DIMM supports. Each speed for the relative CAS settings is
;* CAS the DIMM supports. Each speed for the relative CAS settings is * checked that it is within the GeodeLink speed. If it isn't within the GeodeLink
;* checked that it is within the GeodeLink speed. If it isn't within the GeodeLink * speed, the CAS setting is removed from the list of good settings for
;* speed, the CAS setting is removed from the list of good settings for * the DIMM. This is done for both DIMMs and the lists are compared to
;* the DIMM. This is done for both DIMMs and the lists are compared to * find the lowest common CAS latency setting. If there are no CAS settings
;* find the lowest common CAS latency setting. If there are no CAS settings * in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt.
;* in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt. *
;* * Entry:
;* Entry: * Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information.
;* Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information. * Destroys: We really use everything !
;* Destroys: We really use everything ! */
;*****************************************************************************/
uint16_t glspeed; uint16_t glspeed;
uint8_t spd_byte, casmap0, casmap1; uint8_t spd_byte, casmap0, casmap1;
msr_t msr; msr_t msr;
@ -298,7 +303,7 @@ static void setCAS(void)
casmap0 = getcasmap(DIMM0, glspeed); casmap0 = getcasmap(DIMM0, glspeed);
casmap1 = getcasmap(DIMM1, glspeed); casmap1 = getcasmap(DIMM1, glspeed);
/********************* CAS_LAT MAP COMPARE ***************************/ /* CAS_LAT MAP COMPARE */
if (casmap0 == 0) { if (casmap0 == 0) {
spd_byte = CASDDR[__builtin_ctz(casmap1)]; spd_byte = CASDDR[__builtin_ctz(casmap1)];
} else if (casmap1 == 0) { } else if (casmap1 == 0) {
@ -468,7 +473,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
uint8_t spd_byte; uint8_t spd_byte;
banner("sdram_set_spd_register"); banner("sdram_set_spd_register");
post_code(POST_MEM_SETUP); // post_70h post_code(POST_MEM_SETUP); /* post_70h */
spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES); spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES);
banner("Check DIMM 0"); banner("Check DIMM 0");
@ -486,23 +491,23 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
hcf(); hcf();
} }
post_code(POST_MEM_SETUP2); // post_72h post_code(POST_MEM_SETUP2); /* post_72h */
banner("Check DDR MAX"); banner("Check DDR MAX");
/* Check that the memory is not overclocked. */ /* Check that the memory is not overclocked. */
checkDDRMax(); checkDDRMax();
/* Size the DIMMS */ /* Size the DIMMS */
post_code(POST_MEM_SETUP3); // post_73h post_code(POST_MEM_SETUP3); /* post_73h */
banner("AUTOSIZE DIMM 0"); banner("AUTOSIZE DIMM 0");
auto_size_dimm(DIMM0); auto_size_dimm(DIMM0);
post_code(POST_MEM_SETUP4); // post_74h post_code(POST_MEM_SETUP4); /* post_74h */
banner("AUTOSIZE DIMM 1"); banner("AUTOSIZE DIMM 1");
auto_size_dimm(DIMM1); auto_size_dimm(DIMM1);
/* Set CAS latency */ /* Set CAS latency */
banner("set cas latency"); banner("set cas latency");
post_code(POST_MEM_SETUP5); // post_75h post_code(POST_MEM_SETUP5); /* post_75h */
setCAS(); setCAS();
/* Set all the other latencies here (tRAS, tRP....) */ /* Set all the other latencies here (tRAS, tRP....) */