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mainboard/amd/torpedo: Improve code formatting

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Change-Id: I18de4740e0d3512ec81e10b32d13d07a35791b57
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16846
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS
2016-10-01 15:10:11 +02:00
committed by Kyösti Mälkki
parent 738a3b043e
commit 5c22825c19
8 changed files with 868 additions and 871 deletions
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4
src/mainboard/amd/torpedo/BiosCallOuts.c
View File

@@ -141,7 +141,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
//DE-Assert ALL PCIE RESET //DE-Assert ALL PCIE RESET
// APU GPP0 (Dev 4) // APU GPP0 (Dev 4)
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 |= BIT6 ; Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);
// APU GPP1 (Dev 5) // APU GPP1 (Dev 5)
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01);
@@ -165,7 +165,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
} }
// Travis // Travis
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24);
Data8 &= ~(UINT8)BIT6 ; Data8 &= ~(UINT8)BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8); Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8);
//Assert ALL PCIE RESET //Assert ALL PCIE RESET
// APU GPP0 (Dev 4) // APU GPP0 (Dev 4)

1
src/mainboard/amd/torpedo/acpi_tables.c
View File

@@ -29,7 +29,6 @@ extern u32 apicid_sb900;
unsigned long acpi_fill_madt(unsigned long current) unsigned long acpi_fill_madt(unsigned long current)
{ {
/* create all subtables for processors */ /* create all subtables for processors */
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0); current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1); current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1);

8
src/mainboard/amd/torpedo/buildOpts.c
View File

@@ -104,9 +104,11 @@
// This string MUST be exactly 12 characters long // This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '0', ' ', ' ', ' ', ' '} #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '0', ' ', ' ', ' ', ' '}
// The following definitions specify the default values for various parameters in which there are /* The following definitions specify the default values for various parameters
// no clearly defined defaults to be used in the common file. The values below are based on product * in which there are no clearly defined defaults to be used in the common file.
// and BKDG content, please consult the AGESA Memory team for consultation. * The values below are based on product and BKDG content, please consult the
* AGESA Memory team for consultation.
*/
#define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_DRAM_RATE (0)
#define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L2_RATE (0)
#define DFLT_SCRUB_L3_RATE (0) #define DFLT_SCRUB_L3_RATE (0)

66
src/mainboard/amd/torpedo/gpio.c
View File

@@ -40,11 +40,7 @@
#define SB_GPIO_REG27 27 #define SB_GPIO_REG27 27
#endif #endif
void void gpioEarlyInit(void) {
gpioEarlyInit(
void
)
{
u8 Flags; u8 Flags;
u8 Data8 = 0; u8 Data8 = 0;
u8 StripInfo = 0; u8 StripInfo = 0;
@@ -109,32 +105,32 @@ gpioEarlyInit(
andMask32 = ~(1 << (Index - GEVENT_00)); andMask32 = ~(1 << (Index - GEVENT_00));
//EventEnable: 0-Disable, 1-Enable //EventEnable: 0-Disable, 1-Enable
Mmio32_And_Or (SmiMmioAddr, SMIREG_EVENT_ENABLE, andMask32, (gevent_table[Index - GEVENT_00].EventEnable << (Index - GEVENT_00))); Mmio32_And_Or(SmiMmioAddr, SMIREG_EVENT_ENABLE, andMask32, (gevent_table[Index - GEVENT_00].EventEnable << (Index - GEVENT_00)));
//SciTrig: 0-Falling Edge, 1-Rising Edge //SciTrig: 0-Falling Edge, 1-Rising Edge
Mmio32_And_Or (SmiMmioAddr, SMIREG_SCITRIG, andMask32, (gevent_table[Index - GEVENT_00].SciTrig << (Index - GEVENT_00))); Mmio32_And_Or(SmiMmioAddr, SMIREG_SCITRIG, andMask32, (gevent_table[Index - GEVENT_00].SciTrig << (Index - GEVENT_00)));
//SciLevl: 0-Edge trigger, 1-Level Trigger //SciLevl: 0-Edge trigger, 1-Level Trigger
Mmio32_And_Or (SmiMmioAddr, SMIREG_SCILEVEL, andMask32, (gevent_table[Index - GEVENT_00].SciLevl << (Index - GEVENT_00))); Mmio32_And_Or(SmiMmioAddr, SMIREG_SCILEVEL, andMask32, (gevent_table[Index - GEVENT_00].SciLevl << (Index - GEVENT_00)));
//SmiSciEn: 0-Not send SMI, 1-Send SMI //SmiSciEn: 0-Not send SMI, 1-Send SMI
Mmio32_And_Or (SmiMmioAddr, SMIREG_SMISCIEN, andMask32, (gevent_table[Index - GEVENT_00].SmiSciEn << (Index - GEVENT_00))); Mmio32_And_Or(SmiMmioAddr, SMIREG_SMISCIEN, andMask32, (gevent_table[Index - GEVENT_00].SmiSciEn << (Index - GEVENT_00)));
//SciS0En: 0-Disable, 1-Enable //SciS0En: 0-Disable, 1-Enable
Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIS0EN, andMask32, (gevent_table[Index - GEVENT_00].SciS0En << (Index - GEVENT_00))); Mmio32_And_Or(SmiMmioAddr, SMIREG_SCIS0EN, andMask32, (gevent_table[Index - GEVENT_00].SciS0En << (Index - GEVENT_00)));
//SciMap: 00000b ~ 11111b //SciMap: 00000b ~ 11111b
RegIndex8=(u8)((Index - GEVENT_00) >> 2); RegIndex8 = (u8)((Index - GEVENT_00) >> 2);
Data8=(u8)(((Index - GEVENT_00) & 0x3) * 8); Data8 = (u8)(((Index - GEVENT_00) & 0x3) * 8);
Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8)); Mmio32_And_Or(SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8));
//SmiTrig: 0-Active Low, 1-Active High //SmiTrig: 0-Active Low, 1-Active High
Mmio32_And_Or (SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00))); Mmio32_And_Or(SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)));
//SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13 //SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13
RegIndex8=(u8)((Index - GEVENT_00) >> 4); RegIndex8 = (u8)((Index - GEVENT_00) >> 4);
Data8=(u8)(((Index - GEVENT_00) & 0xF) * 2); Data8 = (u8)(((Index - GEVENT_00) & 0xF) * 2);
Mmio32_And_Or (SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8)); Mmio32_And_Or(SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8));
} }
} }
@@ -205,7 +201,7 @@ gpioEarlyInit(
Flags = 1; Flags = 1;
} }
} }
if ( Flags ) if (Flags)
{ {
// [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467 // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467
RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0); RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0);
@@ -228,7 +224,7 @@ gpioEarlyInit(
ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
} }
// [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset
// RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6); //RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6);
} }
else else
{ {
@@ -407,41 +403,41 @@ gpioEarlyInit(
// amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE // amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE
// GPIO07: BT_ON, 0 - OFF, 1 - ON // GPIO07: BT_ON, 0 - OFF, 1 - ON
// //
if (!CONFIG_ONBOARD_BLUETOOTH) { if (!CONFIG_ONBOARD_BLUETOOTH) {
//- if (SystemConfiguration.amdBlueTooth == 1) { //- if (SystemConfiguration.amdBlueTooth == 1) {
RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0); RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0);
//- } //- }
} }
// //
// WebCam control: // WebCam control:
// amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE // amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE
// GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF // GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF
// //
if (!CONFIG_ONBOARD_WEBCAM) { if (!CONFIG_ONBOARD_WEBCAM) {
//- if (SystemConfiguration.amdWebCam == 1) { //- if (SystemConfiguration.amdWebCam == 1) {
RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6); RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6);
//- } //- }
} }
// //
// Travis enable: // Travis enable:
// amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE // amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE
// GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE // GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE
// //
if (!CONFIG_ONBOARD_TRAVIS) { if (!CONFIG_ONBOARD_TRAVIS) {
//- if (SystemConfiguration.amdTravisCtrl == 0) { //- if (SystemConfiguration.amdTravisCtrl == 0) {
RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6); RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6);
//- } //- }
} }
// //
// Disable Light Sensor if needed // Disable Light Sensor if needed
// //
if (CONFIG_ONBOARD_LIGHTSENSOR) { if (CONFIG_ONBOARD_LIGHTSENSOR) {
//- if (SystemConfiguration.amdLightSensor == 1) { //- if (SystemConfiguration.amdLightSensor == 1) {
RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1); RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1);
//- } //- }
} }
} }