soc/amd/picasso: Add generic SMU service request

Add a new feature that allows messages to be sent to the SMU.  The
offsets of the PCI config index/data indirect registers have been
documented for prior generation devices.

The index/data pair is used to access a command register, a response,
and six argument values.

BUG=b:153264473
TEST=Verify service can be used to take the system into S3

Change-Id: Ide431aa976cb2f8bdc248cb08aa0724a9596ac5a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://chromium-review.googlesource.com/2161796
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

src/soc/amd/picasso/Makefile.inc

@@ -72,6 +72,7 @@ smm-y += tsc_freq.c
 smm-$(CONFIG_DEBUG_SMI) += uart.c
 smm-y += gpio.c
 smm-y += psp.c
+smm-y += smu.c
 smm-y += config.c
 
 CPPFLAGS_common += -I$(src)/soc/amd/picasso

src/soc/amd/picasso/include/soc/smu.h

@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __PICASSO_SMU_H__
+#define __PICASSO_SMU_H__
+
+#include <types.h>
+
+/* SMU registers accessed indirectly using an index/data pair in D0F00 config space */
+#define SMU_INDEX_ADDR		0xb8 /* 32 bit */
+#define SMU_DATA_ADDR		0xbc /* 32 bit */
+
+#define REG_ADDR_MESG_ID	0x3b10528
+#define REG_ADDR_MESG_RESP	0x3b10564
+#define REG_ADDR_MESG_ARGS_BASE	0x0b10998
+
+/* Argument 0-5 indexed locations are contiguous */
+#define SMU_NUM_ARGS		6
+#define REG_ADDR_MESG_ARG(x)	(REG_ADDR_MESG_ARGS_BASE + ((x) * sizeof(uint32_t)))
+
+enum smu_message_id {
+	SMC_MSG_S3ENTRY = 0x0c,
+};
+
+struct smu_payload {
+	uint32_t msg[SMU_NUM_ARGS];
+};
+
+/*
+ * Send a message and bi-directional payload to the SMU.  SMU response, if
+ * any, is returned via arg.  Returns 0 if success or -1 on failure.
+ */
+enum cb_err send_smu_message(enum smu_message_id id, struct smu_payload *arg);
+
+/*
+ * Request the SMU put system into S3, S4, or S5.  On entry, SlpTyp determines
+ * S-State and SlpTypeEn is clear.  Function does not return if successful.
+ */
+void smu_sx_entry(void);
+
+#endif /* __PICASSO_SMU_H__ */

src/soc/amd/picasso/smu.c

@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <timer.h>
+#include <console/console.h>
+#include <device/pci_ops.h>
+#include <soc/pci_devs.h>
+#include <soc/smu.h>
+#include <types.h>
+
+static uint32_t smu_read32(uint32_t reg)
+{
+	pci_write_config32(SOC_GNB_DEV, SMU_INDEX_ADDR, reg);
+	return pci_read_config32(SOC_GNB_DEV, SMU_DATA_ADDR);
+}
+
+static void smu_write32(uint32_t reg, uint32_t val)
+{
+	pci_write_config32(SOC_GNB_DEV, SMU_INDEX_ADDR, reg);
+	pci_write_config32(SOC_GNB_DEV, SMU_DATA_ADDR, val);
+}
+
+#define SMU_MESG_RESP_TIMEOUT	0x00
+#define SMU_MESG_RESP_OK	0x01
+
+/* returns SMU_MESG_RESP_OK, SMU_MESG_RESP_TIMEOUT or a negative number */
+static int32_t smu_poll_response(void)
+{
+	struct stopwatch sw;
+	const long timeout_ms = 10 * MSECS_PER_SEC;
+	int32_t result;
+
+	stopwatch_init_msecs_expire(&sw, timeout_ms);
+
+	do {
+		result = smu_read32(REG_ADDR_MESG_RESP);
+		if (result) {
+			printk(BIOS_SPEW, "SMU command consumed %ld msecs\n",
+					stopwatch_duration_usecs(&sw));
+			return result;
+		}
+	} while (!stopwatch_expired(&sw));
+
+	printk(BIOS_ERR, "Error: timeout sending SMU message\n");
+	return SMU_MESG_RESP_TIMEOUT;
+}
+
+/*
+ * Send a message and bi-directional payload to the SMU. SMU response, if any, is returned via
+ * arg.
+ */
+enum cb_err send_smu_message(enum smu_message_id id, struct smu_payload *arg)
+{
+	size_t i;
+
+	/* wait until SMU can process a new request; don't care if an old request failed */
+	if (smu_poll_response() == SMU_MESG_RESP_TIMEOUT)
+		return CB_ERR;
+
+	/* clear response register */
+	smu_write32(REG_ADDR_MESG_RESP, 0);
+
+	/* populate arguments */
+	for (i = 0 ; i < SMU_NUM_ARGS ; i++)
+		smu_write32(REG_ADDR_MESG_ARG(i), arg->msg[i]);
+
+	/* send message to SMU */
+	smu_write32(REG_ADDR_MESG_ID, id);
+
+	/* wait until SMU has processed the message and check if it was successful */
+	if (smu_poll_response() != SMU_MESG_RESP_OK)
+		return CB_ERR;
+
+	/* copy returned values */
+	for (i = 0 ; i < SMU_NUM_ARGS ; i++)
+		arg->msg[i] = smu_read32(REG_ADDR_MESG_ARG(i));
+
+	return CB_SUCCESS;
+}
+
+/*
+ * Request the SMU to put system into S3, S4, or S5. On entry, SlpTyp determines S-State and
+ * SlpTypeEn is clear. Function does not return if successful.
+ */
+void smu_sx_entry(void)
+{
+	struct smu_payload msg = { 0 }; /* Unused for SMC_MSG_S3ENTRY */
+
+	printk(BIOS_DEBUG, "SMU: Put system into S3/S4/S5\n");
+	send_smu_message(SMC_MSG_S3ENTRY, &msg);
+}