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Skylake: Only support UART2 as debug port, clean up the rest

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On Skylake, only UART2 is supported as debug port and the macros
INTEL_PCH_UART_CONSOLE_NUMBER, INTEL_PCH_UART_CONSOLE and the partial
code for UART0, 1 are cleaned up for Skylake and Sklrvp, Kunimitsu and
Glados boards.

BRANCH=none
BUG=chrome-os-partner:40857
TEST=Built for kunimitsu, checked the coreboot logs on LPSS UART2

Change-Id: I2fbcfb1d1ca6f59309a77c67d022cf4f5da7f7c0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e714c18d462bc7bdd7068309fb6be77da6973642
Original-Change-Id: I9343abd90ce685ea2d676047dccbefad7457b69f
Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/285793
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/10994
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Naveen Krishna Chatradhi
2015-07-15 16:02:25 +05:30
committed by Patrick Georgi
parent bbbfbf2e0f
commit 5c56ce13f4
7 changed files with 10 additions and 59 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
src/soc/intel/skylake/uart.c
View File

@@ -28,18 +28,7 @@
static int pch_uart_is_debug(struct device *dev)
{
if (!IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE))
return 0;
switch (dev->path.pci.devfn) {
case PCH_DEVFN_UART0:
return CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 0;
case PCH_DEVFN_UART1:
return CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 1;
case PCH_DEVFN_UART2:
return CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 2;
}
return 0;
return dev->path.pci.devfn == PCH_DEVFN_UART2;
}
static void pch_uart_read_resources(struct device *dev)