util/msrtool: Fix formatting issues reported by checkpatch
Change-Id: I487a9e6a6416bbe874ddadeaf464f54c02cacb0a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38635 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Georgi
@@ -22,7 +22,7 @@ int intel_core2_later_probe(const struct targetdef *target, const struct cpuid_t
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}
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const struct msrdef intel_core2_later_msrs[] = {
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{0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID Register",
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{0x17, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PLATFORM_ID Register",
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"Model Specific Platform ID", {
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/* The OS can use this MSR to determine "slot" information for the
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* processor and the proper microcode update to load. */
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@@ -46,7 +46,7 @@ const struct msrdef intel_core2_later_msrs[] = {
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{ 7, 8, RESERVED },
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{ BITS_EOT }
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}},
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{ 0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBL_CR_POWERON Register",
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{ 0x2a, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EBL_CR_POWERON Register",
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"Processor Hard Power-On Configuration", {
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{ 63, 41, RESERVED },
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{ 26, 5, "Integer Bus Frequency Ratio:", "R/O", PRESENT_DEC, {
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@@ -125,7 +125,7 @@ const struct msrdef intel_core2_later_msrs[] = {
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{ 0, 1, RESERVED },
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{ BITS_EOT }
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}},
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{0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scalable Bus Speed", {
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{0xcd, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_FSB_FREQ", "Scalable Bus Speed", {
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/* This field indicates the intended scalable bus clock speed */
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{ 63, 61, RESERVED },
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{ 2, 3, "Speed", "R/O", PRESENT_BIN, {
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@@ -140,7 +140,7 @@ const struct msrdef intel_core2_later_msrs[] = {
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}},
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{ BITS_EOT }
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}},
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{0x11e, MSRTYPE_RDWR, MSR2(0,0), "MSR_BBL_CR_CTL3", "", {
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{0x11e, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BBL_CR_CTL3", "", {
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{ 63, 40, RESERVED },
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{ 23, 1, "L2 Present", "R/O", PRESENT_BIN, {
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{ MSR1(0), "L2 Present" },
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@@ -164,27 +164,27 @@ const struct msrdef intel_core2_later_msrs[] = {
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}},
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{ BITS_EOT }
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}},
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{0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", {
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{0x198, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_STATUS", "", {
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{ BITS_EOT }
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}},
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// Per core msrs
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{0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "Pentium Processor\
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Machine-Check Exception Address", {
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{0x0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_ADDR",
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"Pentium Processor Machine-Check Exception Address", {
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{ BITS_EOT }
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}},
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{0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "Pentium Processor\
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Machine-Check Exception Type", {
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{0x1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_TYPE",
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"Pentium Processor Machine-Check Exception Type", {
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{ BITS_EOT }
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}},
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{0x6, MSRTYPE_RDWR, MSR2(0,0), "IA32_MONITOR_FILTER_SIZE", "", {
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{0x6, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MONITOR_FILTER_SIZE", "", {
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{ BITS_EOT }
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}},
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{0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STEP_COUNTER", "TSC", {
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{0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STEP_COUNTER", "TSC", {
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{ BITS_EOT }
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}},
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{0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "APIC BASE", {
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{0x1b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APIC_BASE", "APIC BASE", {
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/* In Intel's manual there is MAXPHYWID,
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* which determine index of highest bit of
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* APIC Base itself, so marking it as
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@@ -202,7 +202,7 @@ const struct msrdef intel_core2_later_msrs[] = {
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{ 7, 8, RESERVED },
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{ BITS_EOT }
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}},
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{0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL",
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{0x3a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FEATURE_CONTROL",
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"Control features in Intel 64Processor", {
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{ 63, 48, RESERVED },
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/* if CPUID.01H: ECX[6] = 1 */
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@@ -257,57 +257,57 @@ const struct msrdef intel_core2_later_msrs[] = {
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}},
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{ BITS_EOT }
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}},
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{0x40, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_FROM_IP", "", {
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{0x40, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_0_FROM_IP", "", {
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{ BITS_EOT }
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}},
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{0x41, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_FROM_IP", "", {
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{0x41, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_1_FROM_IP", "", {
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{ BITS_EOT }
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}},
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{0x42, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_FROM_IP", "", {
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{0x42, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_2_FROM_IP", "", {
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{ BITS_EOT }
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}},
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{0x43, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_FROM_IP", "", {
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{0x43, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_3_FROM_IP", "", {
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{ BITS_EOT }
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}},
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{0x60, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_TO_LIP", "", {
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{0x60, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_0_TO_LIP", "", {
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{ BITS_EOT }
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}},
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{0x61, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_TO_LIP", "", {
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{0x61, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_1_TO_LIP", "", {
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{ BITS_EOT }
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}},
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{0x62, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_TO_LIP", "", {
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{0x62, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_2_TO_LIP", "", {
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{ BITS_EOT }
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}},
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{0x63, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_TO_LIP", "", {
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{0x63, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_3_TO_LIP", "", {
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{ BITS_EOT }
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}},
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{0x79, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_UPDT_TRIG",
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{0x79, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_UPDT_TRIG",
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"BIOS Update Trigger Register (W)", {
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{ BITS_EOT }
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}},
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{0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID",
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{0x8b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_SIGN_ID",
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"BIOS Update Signature ID (RO)", {
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{ BITS_EOT }
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}},
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{0xa0, MSRTYPE_RDWR, MSR2(0,0), "MSR_SMRR_PHYS_BASE", "", {
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{0xa0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SMRR_PHYS_BASE", "", {
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{ BITS_EOT }
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}},
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{0xa1, MSRTYPE_RDWR, MSR2(0,0), "MSR_SMRR_PHYS_MASK", "", {
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{0xa1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SMRR_PHYS_MASK", "", {
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{ BITS_EOT }
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}},
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{0xc1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC0", "", {
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{0xc1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PMC0", "", {
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{ BITS_EOT }
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}},
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{0xc2, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC1", "", {
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{0xc2, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PMC1", "", {
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{ BITS_EOT }
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}},
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{0xe7, MSRTYPE_RDWR, MSR2(0,0), "IA32_MPERF", "", {
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{0xe7, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MPERF", "", {
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{ BITS_EOT }
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}},
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{0xe8, MSRTYPE_RDWR, MSR2(0,0), "IA32_APERF", "", {
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{0xe8, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APERF", "", {
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{ BITS_EOT }
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}},
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{0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", {
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{0xfe, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRRCAP", "", {
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{ 63, 52, RESERVED },
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{ 11, 1, "SMRR Capability Using MSR 0xa0 and 0xa1", "R/O", PRESENT_BIN, {
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{ BITVAL_EOT }
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@@ -315,19 +315,19 @@ const struct msrdef intel_core2_later_msrs[] = {
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{ 10, 11, RESERVED },
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{ BITS_EOT }
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}},
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{0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", {
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{0x174, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_CS", "", {
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{ BITS_EOT }
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}},
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{0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", {
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{0x175, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_ESP", "", {
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{ BITS_EOT }
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}},
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{0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", {
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{0x176, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_EIP", "", {
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{ BITS_EOT }
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}},
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{0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", {
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{0x179, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CAP", "", {
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{ BITS_EOT }
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}},
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{0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", {
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{0x17a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_STATUS", "", {
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{ 63, 61, RESERVED },
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{ 2, 1, "MCIP", "R/W", PRESENT_BIN, {
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/* When set, bit indicates that a machine check has been
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@@ -363,7 +363,7 @@ const struct msrdef intel_core2_later_msrs[] = {
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{ BITS_EOT }
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}},
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/* if CPUID.0AH: EAX[15:8] > 0 */
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{0x186, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL0",
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{0x186, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERFEVTSEL0",
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"Performance Event Select Register 0", {
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{ 63, 32, RESERVED },
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{ 31, 8, "CMASK", "R/W", PRESENT_HEX, {
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@@ -423,7 +423,7 @@ const struct msrdef intel_core2_later_msrs[] = {
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{ BITS_EOT }
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}},
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/* if CPUID.0AH: EAX[15:8] > 0 */
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{0x187, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL1",
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{0x187, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERFEVTSEL1",
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"Performance Event Select Register 1", {
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{ 63, 32, RESERVED },
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{ 31, 8, "CMASK", "R/W", PRESENT_HEX, {
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@@ -482,13 +482,13 @@ const struct msrdef intel_core2_later_msrs[] = {
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}},
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{ BITS_EOT }
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}},
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{0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", {
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{0x198, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_STATUS", "", {
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{ BITS_EOT }
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}},
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{0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CTL", "", {
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{0x199, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_CTL", "", {
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{ BITS_EOT }
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}},
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{0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION",
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{0x19a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_CLOCK_MODULATION",
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"Clock Modulation", {
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{ 63, 59, RESERVED },
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{ 4, 1, "On demand Clock Modulation", "R/W", PRESENT_BIN, {
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@@ -502,18 +502,18 @@ const struct msrdef intel_core2_later_msrs[] = {
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{ 0, 1, RESERVED },
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{ BITS_EOT }
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}},
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{0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT",
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{0x19b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_INTERRUPT",
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"Thermal Interrupt Control", {
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{ BITS_EOT }
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}},
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{0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS",
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{0x19c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_STATUS",
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"Thermal Monitor Status", {
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{ BITS_EOT }
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}},
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{0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", {
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{0x19d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_THERM2_CTL", "", {
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{ BITS_EOT }
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}},
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{0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE",
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{0x1a0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MISC_ENABLE",
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"Enable miscellaneous processor features", {
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{ 63, 24, RESERVED },
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{ 39, 1, "IP Prefetcher Disable", "R/W", PRESENT_BIN, {
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@@ -562,18 +562,18 @@ const struct msrdef intel_core2_later_msrs[] = {
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{ 21, 1, RESERVED },
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{ 20, 1, "Enhanced Intel SpeedStep Select Lock", "R/W",
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PRESENT_BIN, {
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{ MSR1(0), "Enhanced Intel SpeedStep Select\
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and Enable bits are writeable" },
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{ MSR1(1), "Enhanced Intel SpeedStep Select\
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and Enable bits are locked and R/O" },
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{ MSR1(0), "Enhanced Intel SpeedStep Select "
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"and Enable bits are writeable" },
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{ MSR1(1), "Enhanced Intel SpeedStep Select "
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"and Enable bits are locked and R/O" },
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{ BITVAL_EOT }
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}},
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{ 19, 1, "Adjacent Cache Line Prefetch Disable", "R/W",
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PRESENT_BIN, {
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{ MSR1(0), "Fetching cache lines that comprise a cache\
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line pair (128 bytes)" },
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{ MSR1(1), "Fetching cache line that contains data\
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currently required by the processor" },
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{ MSR1(0), "Fetching cache lines that comprise a cache "
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"line pair (128 bytes)" },
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{ MSR1(1), "Fetching cache line that contains data "
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"currently required by the processor" },
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{ BITVAL_EOT }
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}},
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{ 18, 1, "Enable Monitor FSM", "R/W", PRESENT_BIN, {
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@@ -603,8 +603,8 @@ const struct msrdef intel_core2_later_msrs[] = {
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}},
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{ 10, 1, "FERR# Multiplexing Enable", "R/W", PRESENT_BIN, {
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{ MSR1(0), "FERR# signaling compatible behaviour" },
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{ MSR1(1), "FERR# asserted by the processor to indicate\
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a pending break event within the processor" },
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{ MSR1(1), "FERR# asserted by the processor to indicate "
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"a pending break event within the processor" },
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{ BITVAL_EOT }
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}},
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{ 9, 1, "Hardware Prefetcher Disable", "R/W", PRESENT_BIN, {
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@@ -627,100 +627,100 @@ const struct msrdef intel_core2_later_msrs[] = {
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}},
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{ BITS_EOT }
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}},
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{0x1c9, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_TOS", "", {
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{0x1c9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_TOS", "", {
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{ BITS_EOT }
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}},
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{0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", {
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{0x1d9, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DEBUGCTL", "", {
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{ BITS_EOT }
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}},
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{0x1dd, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_FROM_LIP", "", {
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{0x1dd, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LER_FROM_LIP", "", {
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{ BITS_EOT }
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}},
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{0x1de, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_TO_LIP", "", {
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{0x1de, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LER_TO_LIP", "", {
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{ BITS_EOT }
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}},
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{0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE0", "", {
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{0x200, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE0", "", {
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{ BITS_EOT }
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}},
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{0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK0", "", {
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{0x201, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK0", "", {
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{ BITS_EOT }
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}},
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{0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE1", "", {
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{0x202, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE1", "", {
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{ BITS_EOT }
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}},
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{0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK1", "", {
|
||||
{0x203, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK1", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE2", "", {
|
||||
{0x204, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE2", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK2", "", {
|
||||
{0x205, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK2", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE3", "", {
|
||||
{0x206, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE3", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK3", "", {
|
||||
{0x207, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK3", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE4", "", {
|
||||
{0x208, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE4", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK4", "", {
|
||||
{0x209, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK4", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE5", "", {
|
||||
{0x20a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE5", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK5", "", {
|
||||
{0x20b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK5", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE6", "", {
|
||||
{0x20c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE6", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK6", "", {
|
||||
{0x20d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK6", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE7", "", {
|
||||
{0x20e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE7", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK7", "", {
|
||||
{0x20f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK7", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", {
|
||||
{0x250, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX64K_00000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", {
|
||||
{0x258, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_80000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", {
|
||||
{0x259, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_A0000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", {
|
||||
{0x268, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C0000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", {
|
||||
{0x269, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C8000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", {
|
||||
{0x26a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D0000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", {
|
||||
{0x26b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D8000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", {
|
||||
{0x26c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E0000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", {
|
||||
{0x26d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E8000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", {
|
||||
{0x26e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F0000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", {
|
||||
{0x26f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F8000", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x277, MSRTYPE_RDWR, MSR2(0,0), "IA32_PAT", "IA32_PAT", {
|
||||
{0x277, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PAT", "IA32_PAT", {
|
||||
{ 63, 5, RESERVED },
|
||||
{ 58, 3, "PA7", "R/W", PRESENT_BIN, {
|
||||
{ BITVAL_EOT }
|
||||
@@ -755,7 +755,7 @@ const struct msrdef intel_core2_later_msrs[] = {
|
||||
}},
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE",
|
||||
{0x2ff, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_DEF_TYPE",
|
||||
"Default Memory Types", {
|
||||
{ 63, 52, RESERVED },
|
||||
{ 11, 1, "MTRR Enable", "R/W", PRESENT_BIN, {
|
||||
@@ -771,24 +771,24 @@ const struct msrdef intel_core2_later_msrs[] = {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
/* if CPUID.0AH: EDX[4:0] > 0 */
|
||||
{0x309, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR0", "Fixed-Function \
|
||||
Performance Counter Register 0: Counts Instr_Retired.Any", {
|
||||
{0x309, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR0", "Fixed-Function "
|
||||
"Performance Counter Register 0: Counts Instr_Retired.Any", {
|
||||
/* Also known as MSR_PERF_FIXED_CTR0 */
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
/* if CPUID.0AH: EDX[4:0] > 1 */
|
||||
{0x30a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR1", "Fixed-Function \
|
||||
Performance Counter Register 1: Counts CPU_CLK_Unhalted.Core ", {
|
||||
{0x30a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR1", "Fixed-Function "
|
||||
"Performance Counter Register 1: Counts CPU_CLK_Unhalted.Core ", {
|
||||
/* Also known as MSR_PERF_FIXED_CTR1 */
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
/* if CPUID.0AH: EDX[4:0] > 2 */
|
||||
{0x30b, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR2", "Fixed-Function \
|
||||
Performance Counter Register 2: Counts CPU_CLK_Unhalted.Ref", {
|
||||
{0x30b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR2", "Fixed-Function "
|
||||
"Performance Counter Register 2: Counts CPU_CLK_Unhalted.Ref", {
|
||||
/* Also known as MSR_PERF_FIXED_CTR2 */
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x345, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", {
|
||||
{0x345, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PERF_CAPABILITIES", "", {
|
||||
/* Additional info available at Section 17.4.1 of
|
||||
* Intel 64 and IA-32 Architectures Software Developer's
|
||||
* Manual, Volume 3.
|
||||
@@ -806,7 +806,7 @@ const struct msrdef intel_core2_later_msrs[] = {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
/* if CPUID.0AH: EAX[7:0] > 1*/
|
||||
{0x38d, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR_CTRL",
|
||||
{0x38d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR_CTRL",
|
||||
"Fixed-Function-Counter Control Register", {
|
||||
/* Also known as MSR_PERF_FIXED_CTR_CTRL.
|
||||
* Counter increments while the results of ANDing respective enable bit
|
||||
@@ -820,10 +820,12 @@ const struct msrdef intel_core2_later_msrs[] = {
|
||||
}},
|
||||
/* if CPUID.0AH EAX[7:0] > 2 */
|
||||
{ 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, {
|
||||
{ MSR1(0), "Counter only increments the associated event \
|
||||
conditions occurring in the logical processor which programmed the MSR" },
|
||||
{ MSR1(1), "Counting the associated event conditions \
|
||||
occurring across all logical processors sharing a processor core" },
|
||||
{ MSR1(0), "Counter only increments the associated event "
|
||||
"conditions occurring in the logical processor "
|
||||
"which programmed the MSR" },
|
||||
{ MSR1(1), "Counting the associated event conditions "
|
||||
"occurring across all logical processors sharing "
|
||||
"a processor core" },
|
||||
{ BITVAL_EOT }
|
||||
}},
|
||||
{ 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, {
|
||||
@@ -843,10 +845,12 @@ const struct msrdef intel_core2_later_msrs[] = {
|
||||
}},
|
||||
/* if CPUID.0AH: EAX[7:0] > 2 */
|
||||
{ 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, {
|
||||
{ MSR1(0), "Counter only increments the associated event \
|
||||
conditions occurring in the logical processor which programmed the MSR" },
|
||||
{ MSR1(1), "Counting the associated event conditions \
|
||||
occurring across all logical processors sharing a processor core" },
|
||||
{ MSR1(0), "Counter only increments the associated event "
|
||||
"conditions occurring in the logical processor "
|
||||
"which programmed the MSR" },
|
||||
{ MSR1(1), "Counting the associated event conditions "
|
||||
"occurring across all logical processors sharing "
|
||||
"a processor core" },
|
||||
{ BITVAL_EOT }
|
||||
}},
|
||||
{ 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, {
|
||||
@@ -866,10 +870,12 @@ const struct msrdef intel_core2_later_msrs[] = {
|
||||
}},
|
||||
/* if CPUID.0AH: EAX[7:0] > 2 */
|
||||
{ 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, {
|
||||
{ MSR1(0), "Counter only increments the associated event \
|
||||
conditions occurring in the logical processor which programmed the MSR" },
|
||||
{ MSR1(1), "Counting the associated event conditions \
|
||||
occurring across all logical processors sharing a processor core" },
|
||||
{ MSR1(0), "Counter only increments the associated event "
|
||||
"conditions occurring in the logical processor "
|
||||
"which programmed the MSR" },
|
||||
{ MSR1(1), "Counting the associated event conditions "
|
||||
"occurring across all logical processors sharing "
|
||||
"a processor core" },
|
||||
{ BITVAL_EOT }
|
||||
}},
|
||||
{ 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, {
|
||||
@@ -885,7 +891,7 @@ const struct msrdef intel_core2_later_msrs[] = {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
/* if CPUID.0AH: EAX[7:0] > 0 */
|
||||
{0x38e, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_GLOBAL_STATUS",
|
||||
{0x38e, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PERF_GLOBAL_STATUS",
|
||||
"Global Performance Counter Status", {
|
||||
/* Also known as MSR_PERF_GLOBAL_STATUS */
|
||||
/* if CPUID.0AH: EAX[7:0] > 0 */
|
||||
@@ -939,7 +945,7 @@ const struct msrdef intel_core2_later_msrs[] = {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
/* if CPUID.0AH: EAX[7:0] > 0 */
|
||||
{0x38f, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_CTL",
|
||||
{0x38f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_GLOBAL_CTL",
|
||||
"Global Performance Counter Control", {
|
||||
/* Counter increments while the result of ANDing respective
|
||||
* enable bit in this MSR with corresponding OS or USR bits
|
||||
@@ -970,7 +976,7 @@ const struct msrdef intel_core2_later_msrs[] = {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
/* if CPUID.0AH: EAX[7:0] > 0 */
|
||||
{0x390, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_OVF_CTL",
|
||||
{0x390, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_GLOBAL_OVF_CTL",
|
||||
"Global Performance Counter Overflow Control", {
|
||||
/* if CPUID.0AH: EAX[7:0] > 0 */
|
||||
{ 63, 1, "Clear CondChg bit", "R/W", PRESENT_BIN, {
|
||||
@@ -1012,7 +1018,7 @@ const struct msrdef intel_core2_later_msrs[] = {
|
||||
* Software Developer's Manual, Volume 3,
|
||||
* "Precise Event Based Sampling (PEBS)".
|
||||
*/
|
||||
{0x3f1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PEBS_ENABLE", "PEBS Control", {
|
||||
{0x3f1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PEBS_ENABLE", "PEBS Control", {
|
||||
{ 63, 28, RESERVED },
|
||||
{ 35, 1, "Load Latency on IA32_PMC3", "R/W", PRESENT_BIN, {
|
||||
{ MSR1(0), "Disabled" },
|
||||
@@ -1057,85 +1063,85 @@ const struct msrdef intel_core2_later_msrs[] = {
|
||||
}},
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", {
|
||||
{0x400, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", {
|
||||
{0x401, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
|
||||
{0x402, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_ADDR", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", {
|
||||
{0x403, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_MISC", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", {
|
||||
{0x404, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", {
|
||||
{0x405, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", {
|
||||
{0x406, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_ADDR", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x407, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_MISC", "", {
|
||||
{0x407, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_MISC", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", {
|
||||
{0x408, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", {
|
||||
{0x409, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", {
|
||||
{0x40a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_ADDR", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", {
|
||||
{0x40b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_MISC", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
|
||||
{0x40c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
|
||||
{0x40d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
|
||||
{0x40e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_ADDR", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", {
|
||||
{0x40f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_MISC", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
|
||||
{0x410, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
|
||||
{0x411, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
|
||||
{0x412, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_ADDR", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", {
|
||||
{0x413, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_MISC", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x414, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_CTL", "", {
|
||||
{0x414, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC5_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x415, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_STATUS", "", {
|
||||
{0x415, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC5_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x416, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_ADDR", "", {
|
||||
{0x416, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC5_ADDR", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x417, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_MISC", "", {
|
||||
{0x417, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC5_MISC", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x418, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_CTL", "", {
|
||||
{0x418, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC6_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x419, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_STATUS", "", {
|
||||
{0x419, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC6_STATUS", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x480, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_BASIC",
|
||||
{0x480, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_BASIC",
|
||||
"Reporting Register of Basic VMX Capabilities", {
|
||||
/* Additional info available at
|
||||
* Appendix A.1, "Basic VMX Information" */
|
||||
@@ -1159,76 +1165,76 @@ const struct msrdef intel_core2_later_msrs[] = {
|
||||
}},
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x481, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PINBASED_CTLS",
|
||||
"Capability Reporting Register of \
|
||||
Pin-based VM-execution Controls", {
|
||||
{0x481, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PINBASED_CTLS",
|
||||
"Capability Reporting Register of "
|
||||
"Pin-based VM-execution Controls", {
|
||||
/* Additional info available at Appendix A.3,
|
||||
* "VM-Execution Controls" */
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x482, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PROCBASED_CTLS",
|
||||
"Capability Reporting Register of \
|
||||
Primary Processor-based VM-execution Controls", {
|
||||
{0x482, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PROCBASED_CTLS",
|
||||
"Capability Reporting Register of "
|
||||
"Primary Processor-based VM-execution Controls", {
|
||||
/* Additional info available at Appendix A.3,
|
||||
* "VM-Execution Controls" */
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x483, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_EXIT_CTLS",
|
||||
{0x483, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_EXIT_CTLS",
|
||||
"Capability Reporting Register of VM-exit Controls", {
|
||||
/* Additional info available at Appendix A.4,
|
||||
* "VM-Exit Controls" */
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x484, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_ENTRY_CTLS",
|
||||
{0x484, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_ENTRY_CTLS",
|
||||
"Capability Reporting Register of VM-entry Controls", {
|
||||
/* Additional info available at Appendix A.5,
|
||||
* "VM-Entry Controls" */
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x485, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_MISC",
|
||||
{0x485, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_MISC",
|
||||
"Reporting Register of Miscellaneous VMX Capabilities", {
|
||||
/* Additional info available at Appendix A.6,
|
||||
* "Miscellaneous Data" */
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x486, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR0_FIXED0",
|
||||
{0x486, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR0_FIXED0",
|
||||
"Capability Reporting Register of CR0 Bits Fixed to 0", {
|
||||
/* Additional info available at Appendix A.7,
|
||||
* "VMX-Fixed Bits in CR0" */
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x487, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR0_FIXED1",
|
||||
{0x487, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR0_FIXED1",
|
||||
"Capability Reporting Register of CR0 Bits Fixed to 1", {
|
||||
/* Additional info available at Appendix A.7,
|
||||
* "VMX-Fixed Bits in CR0" */
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x488, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR4_FIXED0",
|
||||
{0x488, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR4_FIXED0",
|
||||
"Capability Reporting Register of CR4 Bits Fixed to 0", {
|
||||
/* Additional info available at Appendix A.8,
|
||||
* "VMX-Fixed Bits in CR4" */
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x489, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR4_FIXED1",
|
||||
{0x489, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR4_FIXED1",
|
||||
"Capability Reporting Register of CR4 Bits Fixed to 1", {
|
||||
/* Additional info available at Appendix A.8,
|
||||
* "VMX-Fixed Bits in CR4" */
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x48a, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_VMCS_ENUM",
|
||||
{0x48a, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_VMCS_ENUM",
|
||||
"Capability Reporting Register of VMCS Field Enumeration", {
|
||||
/* Additional info available at Appendix A.9,
|
||||
* "VMCS Enumeration" */
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x48b, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_PROCBASED_CTLS2",
|
||||
"Capability Reporting Register of Secondary \
|
||||
Processor-based VM-execution Controls", {
|
||||
{0x48b, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_PROCBASED_CTLS2",
|
||||
"Capability Reporting Register of Secondary "
|
||||
"Processor-based VM-execution Controls", {
|
||||
/* Additional info available at Appendix A.3,
|
||||
* "VM-Execution Controls" */
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x600, MSRTYPE_RDWR, MSR2(0,0), "IA32_DS_AREA", "DS Save Area", {
|
||||
{0x600, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DS_AREA", "DS Save Area", {
|
||||
/* Additional info available at Section 18.10.4 of Intel 64
|
||||
* and IA-32 Architectures Software Developer's Manual,
|
||||
* "Debug Store (DS) Mechanism".
|
||||
@@ -1240,52 +1246,52 @@ const struct msrdef intel_core2_later_msrs[] = {
|
||||
}},
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x107cc, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL0", "", {
|
||||
{0x107cc, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL0", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x107cd, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL1", "", {
|
||||
{0x107cd, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL1", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x107ce, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL2", "", {
|
||||
{0x107ce, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL2", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x107cf, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL3", "", {
|
||||
{0x107cf, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL3", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x107d0, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL4", "", {
|
||||
{0x107d0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL4", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x107d1, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL5", "", {
|
||||
{0x107d1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL5", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x107d2, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL6", "", {
|
||||
{0x107d2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL6", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x107d3, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL7", "", {
|
||||
{0x107d3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL7", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0x107d8, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_GL_CTL", "", {
|
||||
{0x107d8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_GL_CTL", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0xc0000080, MSRTYPE_RDWR, MSR2(0,0), "IA32_EFER", "", {
|
||||
{0xc0000080, MSRTYPE_RDWR, MSR2(0, 0), "IA32_EFER", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0xc0000081, MSRTYPE_RDWR, MSR2(0,0), "IA32_STAR", "", {
|
||||
{0xc0000081, MSRTYPE_RDWR, MSR2(0, 0), "IA32_STAR", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0xc0000082, MSRTYPE_RDWR, MSR2(0,0), "IA32_LSTAR", "", {
|
||||
{0xc0000082, MSRTYPE_RDWR, MSR2(0, 0), "IA32_LSTAR", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0xc0000084, MSRTYPE_RDWR, MSR2(0,0), "IA32_FMASK", "", {
|
||||
{0xc0000084, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FMASK", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0xc0000100, MSRTYPE_RDWR, MSR2(0,0), "IA32_FS_BASE", "", {
|
||||
{0xc0000100, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FS_BASE", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0xc0000101, MSRTYPE_RDWR, MSR2(0,0), "IA32_GS_BASE", "", {
|
||||
{0xc0000101, MSRTYPE_RDWR, MSR2(0, 0), "IA32_GS_BASE", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{0xc0000102, MSRTYPE_RDWR, MSR2(0,0), "IA32_KERNEL_GS_BASE", "", {
|
||||
{0xc0000102, MSRTYPE_RDWR, MSR2(0, 0), "IA32_KERNEL_GS_BASE", "", {
|
||||
{ BITS_EOT }
|
||||
}},
|
||||
{ MSR_EOT }
|
||||
|
||||
Reference in New Issue
Block a user