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util/msrtool: Fix formatting issues reported by checkpatch

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Change-Id: I487a9e6a6416bbe874ddadeaf464f54c02cacb0a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38635
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Georgi 2020-01-29 13:45:45 +01:00
parent fbbef02f06
commit 5c65d00ef2
10 changed files with 1377 additions and 1359 deletions
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90
util/msrtool/intel_atom.c
View File

@ -22,12 +22,12 @@ int intel_atom_probe(const struct targetdef *target, const struct cpuid_t *id) {
} }
const struct msrdef intel_atom_msrs[] = { const struct msrdef intel_atom_msrs[] = {
{0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "Pentium Processor\ {0x0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_ADDR",
Machine-Check Exception Address", { "Pentium Processor Machine-Check Exception Address", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "Pentium Processor\ {0x1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_TYPE",
Machine-Check Exception Type", { "Pentium Processor Machine-Check Exception Type", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STEP_COUNTER", "TSC", { {0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STEP_COUNTER", "TSC", {
@ -651,15 +651,15 @@ const struct msrdef intel_atom_msrs[] = {
}}, }},
{ 13, 1, "ENABLE_UNCORE_PMI", "R/O", PRESENT_BIN, { { 13, 1, "ENABLE_UNCORE_PMI", "R/O", PRESENT_BIN, {
{ MSR1(0), "Nothing" }, { MSR1(0), "Nothing" },
{ MSR1(1), "Logical processor can receive and generate PMI \ { MSR1(1), "Logical processor can receive and generate PMI "
on behalf of the uncore" }, "on behalf of the uncore" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
/* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */ /* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */
{ 12, 1, "FREEZE_PERFMON_ON_PMI", "R/O", PRESENT_BIN, { { 12, 1, "FREEZE_PERFMON_ON_PMI", "R/O", PRESENT_BIN, {
{ MSR1(0), "Nothing" }, { MSR1(0), "Nothing" },
{ MSR1(1), "Each ENABLE bit of the global counter control MSR \ { MSR1(1), "Each ENABLE bit of the global counter control MSR "
are frozen (address 0x3bf) on PMI request" }, "are frozen (address 0x3bf) on PMI request" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
/* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */ /* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */
@ -680,15 +680,15 @@ const struct msrdef intel_atom_msrs[] = {
}}, }},
{ 8, 1, "BTINT", "R/O", PRESENT_BIN, { { 8, 1, "BTINT", "R/O", PRESENT_BIN, {
{ MSR1(0), "BTMs are logged in a BTS buffer in circular fashion" }, { MSR1(0), "BTMs are logged in a BTS buffer in circular fashion" },
{ MSR1(1), "An interrupt is generated by the BTS facility \ { MSR1(1), "An interrupt is generated by the BTS facility "
when the BTS buffer is full" }, "when the BTS buffer is full" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ 7, 1, "BTS", "R/O", PRESENT_BIN, { { 7, 1, "BTS", "R/O", PRESENT_BIN, {
{ MSR1(0), "Logging of BTMs (branch trace messages) \ { MSR1(0), "Logging of BTMs (branch trace messages) "
in BTS buffer is disabled" }, "in BTS buffer is disabled" },
{ MSR1(1), "Logging of BTMs (branch trace messages) \ { MSR1(1), "Logging of BTMs (branch trace messages) "
in BTS buffer is enabled" }, "in BTS buffer is enabled" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ 6, 1, "TR", "R/O", PRESENT_BIN, { { 6, 1, "TR", "R/O", PRESENT_BIN, {
@ -699,14 +699,14 @@ const struct msrdef intel_atom_msrs[] = {
{ 5, 4, RESERVED }, { 5, 4, RESERVED },
{ 1, 1, "BTF", "R/O", PRESENT_BIN, { { 1, 1, "BTF", "R/O", PRESENT_BIN, {
{ MSR1(0), "Nothing" }, { MSR1(0), "Nothing" },
{ MSR1(1), "Enabled treating EFLAGS.TF as single-step on \ { MSR1(1), "Enabled treating EFLAGS.TF as single-step on "
branches instead of single-step on instructions" }, "branches instead of single-step on instructions" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ 0, 1, "LBR", "R/O", PRESENT_BIN, { { 0, 1, "LBR", "R/O", PRESENT_BIN, {
{ MSR1(0), "Nothing" }, { MSR1(0), "Nothing" },
{ MSR1(1), "Enabled recording a running trace of the most \ { MSR1(1), "Enabled recording a running trace of the most "
recent branches taken by the processor in the LBR stack" }, "recent branches taken by the processor in the LBR stack" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ BITS_EOT } { BITS_EOT }
@ -764,20 +764,20 @@ const struct msrdef intel_atom_msrs[] = {
{ BITS_EOT } { BITS_EOT }
}}, }},
/* if CPUID.0AH: EDX[4:0] > 0 */ /* if CPUID.0AH: EDX[4:0] > 0 */
{0x309, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR0", "Fixed-Function \ {0x309, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR0", "Fixed-Function "
Performance Counter Register 0: Counts Instr_Retired.Any", { "Performance Counter Register 0: Counts Instr_Retired.Any", {
/* Also known as MSR_PERF_FIXED_CTR0 */ /* Also known as MSR_PERF_FIXED_CTR0 */
{ BITS_EOT } { BITS_EOT }
}}, }},
/* if CPUID.0AH: EDX[4:0] > 1 */ /* if CPUID.0AH: EDX[4:0] > 1 */
{0x30a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR1", "Fixed-Function \ {0x30a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR1", "Fixed-Function "
Performance Counter Register 1: Counts CPU_CLK_Unhalted.Core ", { "Performance Counter Register 1: Counts CPU_CLK_Unhalted.Core ", {
/* Also known as MSR_PERF_FIXED_CTR1 */ /* Also known as MSR_PERF_FIXED_CTR1 */
{ BITS_EOT } { BITS_EOT }
}}, }},
/* if CPUID.0AH: EDX[4:0] > 2 */ /* if CPUID.0AH: EDX[4:0] > 2 */
{0x30b, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR2", "Fixed-Function \ {0x30b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR2", "Fixed-Function "
Performance Counter Register 2: Counts CPU_CLK_Unhalted.Ref", { "Performance Counter Register 2: Counts CPU_CLK_Unhalted.Ref", {
/* Also known as MSR_PERF_FIXED_CTR2 */ /* Also known as MSR_PERF_FIXED_CTR2 */
{ BITS_EOT } { BITS_EOT }
}}, }},
@ -796,10 +796,12 @@ const struct msrdef intel_atom_msrs[] = {
}}, }},
/* if CPUID.0AH EAX[7:0] > 2 */ /* if CPUID.0AH EAX[7:0] > 2 */
{ 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, { { 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, {
{ MSR1(0), "Counter only increments the associated event \ { MSR1(0), "Counter only increments the associated event "
conditions occurring in the logical processor which programmed the MSR" }, "conditions occurring in the logical processor "
{ MSR1(1), "Counting the associated event conditions \ "which programmed the MSR" },
occurring across all logical processors sharing a processor core" }, { MSR1(1), "Counting the associated event conditions "
"occurring across all logical processors sharing "
"a processor core" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, { { 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, {
@ -819,10 +821,12 @@ const struct msrdef intel_atom_msrs[] = {
}}, }},
/* if CPUID.0AH: EAX[7:0] > 2 */ /* if CPUID.0AH: EAX[7:0] > 2 */
{ 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, { { 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, {
{ MSR1(0), "Counter only increments the associated event \ { MSR1(0), "Counter only increments the associated event "
conditions occurring in the logical processor which programmed the MSR" }, "conditions occurring in the logical processor "
{ MSR1(1), "Counting the associated event conditions \ "which programmed the MSR" },
occurring across all logical processors sharing a processor core" }, { MSR1(1), "Counting the associated event conditions "
"occurring across all logical processors sharing "
"a processor core" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, { { 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, {
@ -842,10 +846,12 @@ const struct msrdef intel_atom_msrs[] = {
}}, }},
/* if CPUID.0AH: EAX[7:0] > 2 */ /* if CPUID.0AH: EAX[7:0] > 2 */
{ 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, { { 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, {
{ MSR1(0), "Counter only increments the associated event \ { MSR1(0), "Counter only increments the associated event "
conditions occurring in the logical processor which programmed the MSR" }, "conditions occurring in the logical processor "
{ MSR1(1), "Counting the associated event conditions \ "which programmed the MSR" },
occurring across all logical processors sharing a processor core" }, { MSR1(1), "Counting the associated event conditions "
"occurring across all logical processors sharing "
"a processor core" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, { { 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, {
@ -1059,15 +1065,15 @@ const struct msrdef intel_atom_msrs[] = {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x481, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PINBASED_CTLS", {0x481, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PINBASED_CTLS",
"Capability Reporting Register of \ "Capability Reporting Register of "
Pin-based VM-execution Controls", { "Pin-based VM-execution Controls", {
/* Additional info available at Appendix A.3, /* Additional info available at Appendix A.3,
* "VM-Execution Controls" */ * "VM-Execution Controls" */
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x482, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PROCBASED_CTLS", {0x482, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PROCBASED_CTLS",
"Capability Reporting Register of \ "Capability Reporting Register of "
Primary Processor-based VM-execution Controls", { "Primary Processor-based VM-execution Controls", {
/* Additional info available at Appendix A.3, /* Additional info available at Appendix A.3,
* "VM-Execution Controls" */ * "VM-Execution Controls" */
{ BITS_EOT } { BITS_EOT }
@ -1121,8 +1127,8 @@ const struct msrdef intel_atom_msrs[] = {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x48b, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_PROCBASED_CTLS2", {0x48b, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_PROCBASED_CTLS2",
"Capability Reporting Register of Secondary \ "Capability Reporting Register of Secondary "
Processor-based VM-execution Controls", { "Processor-based VM-execution Controls", {
/* Additional info available at Appendix A.3, /* Additional info available at Appendix A.3,
* "VM-Execution Controls" */ * "VM-Execution Controls" */
{ BITS_EOT } { BITS_EOT }

82
util/msrtool/intel_core2_later.c
View File

@ -170,12 +170,12 @@ const struct msrdef intel_core2_later_msrs[] = {
// Per core msrs // Per core msrs
{0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "Pentium Processor\ {0x0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_ADDR",
Machine-Check Exception Address", { "Pentium Processor Machine-Check Exception Address", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "Pentium Processor\ {0x1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_TYPE",
Machine-Check Exception Type", { "Pentium Processor Machine-Check Exception Type", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x6, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MONITOR_FILTER_SIZE", "", { {0x6, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MONITOR_FILTER_SIZE", "", {
@ -562,18 +562,18 @@ const struct msrdef intel_core2_later_msrs[] = {
{ 21, 1, RESERVED }, { 21, 1, RESERVED },
{ 20, 1, "Enhanced Intel SpeedStep Select Lock", "R/W", { 20, 1, "Enhanced Intel SpeedStep Select Lock", "R/W",
PRESENT_BIN, { PRESENT_BIN, {
{ MSR1(0), "Enhanced Intel SpeedStep Select\ { MSR1(0), "Enhanced Intel SpeedStep Select "
and Enable bits are writeable" }, "and Enable bits are writeable" },
{ MSR1(1), "Enhanced Intel SpeedStep Select\ { MSR1(1), "Enhanced Intel SpeedStep Select "
and Enable bits are locked and R/O" }, "and Enable bits are locked and R/O" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ 19, 1, "Adjacent Cache Line Prefetch Disable", "R/W", { 19, 1, "Adjacent Cache Line Prefetch Disable", "R/W",
PRESENT_BIN, { PRESENT_BIN, {
{ MSR1(0), "Fetching cache lines that comprise a cache\ { MSR1(0), "Fetching cache lines that comprise a cache "
line pair (128 bytes)" }, "line pair (128 bytes)" },
{ MSR1(1), "Fetching cache line that contains data\ { MSR1(1), "Fetching cache line that contains data "
currently required by the processor" }, "currently required by the processor" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ 18, 1, "Enable Monitor FSM", "R/W", PRESENT_BIN, { { 18, 1, "Enable Monitor FSM", "R/W", PRESENT_BIN, {
@ -603,8 +603,8 @@ const struct msrdef intel_core2_later_msrs[] = {
}}, }},
{ 10, 1, "FERR# Multiplexing Enable", "R/W", PRESENT_BIN, { { 10, 1, "FERR# Multiplexing Enable", "R/W", PRESENT_BIN, {
{ MSR1(0), "FERR# signaling compatible behaviour" }, { MSR1(0), "FERR# signaling compatible behaviour" },
{ MSR1(1), "FERR# asserted by the processor to indicate\ { MSR1(1), "FERR# asserted by the processor to indicate "
a pending break event within the processor" }, "a pending break event within the processor" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ 9, 1, "Hardware Prefetcher Disable", "R/W", PRESENT_BIN, { { 9, 1, "Hardware Prefetcher Disable", "R/W", PRESENT_BIN, {
@ -771,20 +771,20 @@ const struct msrdef intel_core2_later_msrs[] = {
{ BITS_EOT } { BITS_EOT }
}}, }},
/* if CPUID.0AH: EDX[4:0] > 0 */ /* if CPUID.0AH: EDX[4:0] > 0 */
{0x309, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR0", "Fixed-Function \ {0x309, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR0", "Fixed-Function "
Performance Counter Register 0: Counts Instr_Retired.Any", { "Performance Counter Register 0: Counts Instr_Retired.Any", {
/* Also known as MSR_PERF_FIXED_CTR0 */ /* Also known as MSR_PERF_FIXED_CTR0 */
{ BITS_EOT } { BITS_EOT }
}}, }},
/* if CPUID.0AH: EDX[4:0] > 1 */ /* if CPUID.0AH: EDX[4:0] > 1 */
{0x30a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR1", "Fixed-Function \ {0x30a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR1", "Fixed-Function "
Performance Counter Register 1: Counts CPU_CLK_Unhalted.Core ", { "Performance Counter Register 1: Counts CPU_CLK_Unhalted.Core ", {
/* Also known as MSR_PERF_FIXED_CTR1 */ /* Also known as MSR_PERF_FIXED_CTR1 */
{ BITS_EOT } { BITS_EOT }
}}, }},
/* if CPUID.0AH: EDX[4:0] > 2 */ /* if CPUID.0AH: EDX[4:0] > 2 */
{0x30b, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR2", "Fixed-Function \ {0x30b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR2", "Fixed-Function "
Performance Counter Register 2: Counts CPU_CLK_Unhalted.Ref", { "Performance Counter Register 2: Counts CPU_CLK_Unhalted.Ref", {
/* Also known as MSR_PERF_FIXED_CTR2 */ /* Also known as MSR_PERF_FIXED_CTR2 */
{ BITS_EOT } { BITS_EOT }
}}, }},
@ -820,10 +820,12 @@ const struct msrdef intel_core2_later_msrs[] = {
}}, }},
/* if CPUID.0AH EAX[7:0] > 2 */ /* if CPUID.0AH EAX[7:0] > 2 */
{ 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, { { 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, {
{ MSR1(0), "Counter only increments the associated event \ { MSR1(0), "Counter only increments the associated event "
conditions occurring in the logical processor which programmed the MSR" }, "conditions occurring in the logical processor "
{ MSR1(1), "Counting the associated event conditions \ "which programmed the MSR" },
occurring across all logical processors sharing a processor core" }, { MSR1(1), "Counting the associated event conditions "
"occurring across all logical processors sharing "
"a processor core" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, { { 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, {
@ -843,10 +845,12 @@ const struct msrdef intel_core2_later_msrs[] = {
}}, }},
/* if CPUID.0AH: EAX[7:0] > 2 */ /* if CPUID.0AH: EAX[7:0] > 2 */
{ 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, { { 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, {
{ MSR1(0), "Counter only increments the associated event \ { MSR1(0), "Counter only increments the associated event "
conditions occurring in the logical processor which programmed the MSR" }, "conditions occurring in the logical processor "
{ MSR1(1), "Counting the associated event conditions \ "which programmed the MSR" },
occurring across all logical processors sharing a processor core" }, { MSR1(1), "Counting the associated event conditions "
"occurring across all logical processors sharing "
"a processor core" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, { { 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, {
@ -866,10 +870,12 @@ const struct msrdef intel_core2_later_msrs[] = {
}}, }},
/* if CPUID.0AH: EAX[7:0] > 2 */ /* if CPUID.0AH: EAX[7:0] > 2 */
{ 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, { { 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, {
{ MSR1(0), "Counter only increments the associated event \ { MSR1(0), "Counter only increments the associated event "
conditions occurring in the logical processor which programmed the MSR" }, "conditions occurring in the logical processor "
{ MSR1(1), "Counting the associated event conditions \ "which programmed the MSR" },
occurring across all logical processors sharing a processor core" }, { MSR1(1), "Counting the associated event conditions "
"occurring across all logical processors sharing "
"a processor core" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, { { 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, {
@ -1160,15 +1166,15 @@ const struct msrdef intel_core2_later_msrs[] = {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x481, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PINBASED_CTLS", {0x481, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PINBASED_CTLS",
"Capability Reporting Register of \ "Capability Reporting Register of "
Pin-based VM-execution Controls", { "Pin-based VM-execution Controls", {
/* Additional info available at Appendix A.3, /* Additional info available at Appendix A.3,
* "VM-Execution Controls" */ * "VM-Execution Controls" */
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x482, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PROCBASED_CTLS", {0x482, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PROCBASED_CTLS",
"Capability Reporting Register of \ "Capability Reporting Register of "
Primary Processor-based VM-execution Controls", { "Primary Processor-based VM-execution Controls", {
/* Additional info available at Appendix A.3, /* Additional info available at Appendix A.3,
* "VM-Execution Controls" */ * "VM-Execution Controls" */
{ BITS_EOT } { BITS_EOT }
@ -1222,8 +1228,8 @@ const struct msrdef intel_core2_later_msrs[] = {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x48b, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_PROCBASED_CTLS2", {0x48b, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_PROCBASED_CTLS2",
"Capability Reporting Register of Secondary \ "Capability Reporting Register of Secondary "
Processor-based VM-execution Controls", { "Processor-based VM-execution Controls", {
/* Additional info available at Appendix A.3, /* Additional info available at Appendix A.3,
* "VM-Execution Controls" */ * "VM-Execution Controls" */
{ BITS_EOT } { BITS_EOT }

138
util/msrtool/intel_nehalem.c
View File

@ -238,12 +238,12 @@ const struct msrdef intel_nehalem_msrs[] = {
* ========================================================================== * ==========================================================================
*/ */
{0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "Pentium Processor\ {0x0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_ADDR",
Machine-Check Exception Address", { "Pentium Processor Machine-Check Exception Address", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "Pentium Processor\ {0x1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_TYPE",
Machine-Check Exception Type", { "Pentium Processor Machine-Check Exception Type", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x6, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MONITOR_FILTER_SIZE", "", { {0x6, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MONITOR_FILTER_SIZE", "", {
@ -400,26 +400,26 @@ const struct msrdef intel_nehalem_msrs[] = {
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ 24, 1, "Interrupt filtering enabled/disabled", "R/W", PRESENT_DEC, { { 24, 1, "Interrupt filtering enabled/disabled", "R/W", PRESENT_DEC, {
{ MSR1(0), "All CPU cores in deep C-State will wake for an \ { MSR1(0), "All CPU cores in deep C-State will wake for an "
event message" }, "event message" },
{ MSR1(1), "CPU in deep C-State will wake only when the event \ { MSR1(1), "CPU in deep C-State will wake only when the event "
message is destined for that core" }, "message is destined for that core" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ 23, 8, RESERVED }, { 23, 8, RESERVED },
{ 15, 1, "CFG Lock", "R/WO", PRESENT_DEC, { { 15, 1, "CFG Lock", "R/WO", PRESENT_DEC, {
{ MSR1(0), "[15:0] bits of MSR_PKG_CST_CONFIG_CONTROL(0xe2) \ { MSR1(0), "[15:0] bits of MSR_PKG_CST_CONFIG_CONTROL(0xe2) "
are writeable" }, "are writeable" },
{ MSR1(1), "[15:0] bits of MSR_PKG_CST_CONFIG_CONTROL(0xe2) \ { MSR1(1), "[15:0] bits of MSR_PKG_CST_CONFIG_CONTROL(0xe2) "
are locked until reset" }, "are locked until reset" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ 14, 4, RESERVED }, { 14, 4, RESERVED },
{ 10, 1, "I/O MWAIT Redirection", "R/W", PRESENT_DEC, { { 10, 1, "I/O MWAIT Redirection", "R/W", PRESENT_DEC, {
{ MSR1(0), "I/O MWAIT Redirection disabled" }, { MSR1(0), "I/O MWAIT Redirection disabled" },
{ MSR1(1), "CPU will map IO_read instructions sent to \ { MSR1(1), "CPU will map IO_read instructions sent to "
IO register specified by MSR_PMG_IO_CAPTURE_BASE \ "IO register specified by MSR_PMG_IO_CAPTURE_BASE "
to MWAIT instructions" }, "to MWAIT instructions" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ 9, 7, RESERVED }, { 9, 7, RESERVED },
@ -893,17 +893,17 @@ const struct msrdef intel_nehalem_msrs[] = {
/* This bit status is also reflected /* This bit status is also reflected
* by CPUID.(EAX=06h):ECX[3] * by CPUID.(EAX=06h):ECX[3]
*/ */
{ MSR1(0), "IA32_ENERGY_PERF_BIAS (0x1b0) is invisible \ { MSR1(0), "IA32_ENERGY_PERF_BIAS (0x1b0) is invisible "
for Ring 0 software" }, "for Ring 0 software" },
{ MSR1(1), "IA32_ENERGY_PERF_BIAS (0x1b0) accessible \ { MSR1(1), "IA32_ENERGY_PERF_BIAS (0x1b0) accessible "
by Ring 0 software" }, "by Ring 0 software" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ 0, 1, "EIST Hardware Coordination Disable", "R/W", PRESENT_BIN, { { 0, 1, "EIST Hardware Coordination Disable", "R/W", PRESENT_BIN, {
{ MSR1(0), "Hardware Coordination of EIST request \ { MSR1(0), "Hardware Coordination of EIST request "
from processor cores is enabled" }, "from processor cores is enabled" },
{ MSR1(1), "Hardware Coordination of EIST request \ { MSR1(1), "Hardware Coordination of EIST request "
from processor cores is disabled" }, "from processor cores is disabled" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ BITS_EOT } { BITS_EOT }
@ -939,15 +939,15 @@ const struct msrdef intel_nehalem_msrs[] = {
}}, }},
{ 13, 1, "ENABLE_UNCORE_PMI", "R/O", PRESENT_BIN, { { 13, 1, "ENABLE_UNCORE_PMI", "R/O", PRESENT_BIN, {
{ MSR1(0), "Nothing" }, { MSR1(0), "Nothing" },
{ MSR1(1), "Logical processor can receive and generate PMI \ { MSR1(1), "Logical processor can receive and generate PMI "
on behalf of the uncore" }, "on behalf of the uncore" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
/* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */ /* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */
{ 12, 1, "FREEZE_PERFMON_ON_PMI", "R/O", PRESENT_BIN, { { 12, 1, "FREEZE_PERFMON_ON_PMI", "R/O", PRESENT_BIN, {
{ MSR1(0), "Nothing" }, { MSR1(0), "Nothing" },
{ MSR1(1), "Each ENABLE bit of the global counter control MSR \ { MSR1(1), "Each ENABLE bit of the global counter control MSR "
are frozen (address 0x3bf) on PMI request" }, "are frozen (address 0x3bf) on PMI request" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
/* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */ /* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */
@ -968,15 +968,15 @@ const struct msrdef intel_nehalem_msrs[] = {
}}, }},
{ 8, 1, "BTINT", "R/O", PRESENT_BIN, { { 8, 1, "BTINT", "R/O", PRESENT_BIN, {
{ MSR1(0), "BTMs are logged in a BTS buffer in circular fashion" }, { MSR1(0), "BTMs are logged in a BTS buffer in circular fashion" },
{ MSR1(1), "An interrupt is generated by the BTS facility \ { MSR1(1), "An interrupt is generated by the BTS facility "
when the BTS buffer is full" }, "when the BTS buffer is full" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ 7, 1, "BTS", "R/O", PRESENT_BIN, { { 7, 1, "BTS", "R/O", PRESENT_BIN, {
{ MSR1(0), "Logging of BTMs (branch trace messages) \ { MSR1(0), "Logging of BTMs (branch trace messages) "
in BTS buffer is disabled" }, "in BTS buffer is disabled" },
{ MSR1(1), "Logging of BTMs (branch trace messages) \ { MSR1(1), "Logging of BTMs (branch trace messages) "
in BTS buffer is enabled" }, "in BTS buffer is enabled" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ 6, 1, "TR", "R/O", PRESENT_BIN, { { 6, 1, "TR", "R/O", PRESENT_BIN, {
@ -987,14 +987,14 @@ const struct msrdef intel_nehalem_msrs[] = {
{ 5, 4, RESERVED }, { 5, 4, RESERVED },
{ 1, 1, "BTF", "R/O", PRESENT_BIN, { { 1, 1, "BTF", "R/O", PRESENT_BIN, {
{ MSR1(0), "Nothing" }, { MSR1(0), "Nothing" },
{ MSR1(1), "Enabled treating EFLAGS.TF as single-step on \ { MSR1(1), "Enabled treating EFLAGS.TF as single-step on "
branches instead of single-step on instructions" }, "branches instead of single-step on instructions" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ 0, 1, "LBR", "R/O", PRESENT_BIN, { { 0, 1, "LBR", "R/O", PRESENT_BIN, {
{ MSR1(0), "Nothing" }, { MSR1(0), "Nothing" },
{ MSR1(1), "Enabled recording a running trace of the most \ { MSR1(1), "Enabled recording a running trace of the most "
recent branches taken by the processor in the LBR stack" }, "recent branches taken by the processor in the LBR stack" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ BITS_EOT } { BITS_EOT }
@ -1109,9 +1109,9 @@ const struct msrdef intel_nehalem_msrs[] = {
/* Whole package bit */ /* Whole package bit */
{ 1, 1, "C1E Enable", "R/W", PRESENT_BIN, { { 1, 1, "C1E Enable", "R/W", PRESENT_BIN, {
{ MSR1(0), "Nothing" }, { MSR1(0), "Nothing" },
{ MSR1(1), "CPU switch to the Minimum Enhanced Intel \ { MSR1(1), "CPU switch to the Minimum Enhanced Intel "
SpeedStep Technology operating point when all \ "SpeedStep Technology operating point when all "
execution cores enter MWAIT (C1)" }, "execution cores enter MWAIT (C1)" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ 0, 1, RESERVED }, { 0, 1, RESERVED },
@ -1309,20 +1309,20 @@ const struct msrdef intel_nehalem_msrs[] = {
{ BITS_EOT } { BITS_EOT }
}}, }},
/* if CPUID.0AH: EDX[4:0] > 0 */ /* if CPUID.0AH: EDX[4:0] > 0 */
{0x309, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR0", "Fixed-Function \ {0x309, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR0", "Fixed-Function "
Performance Counter Register 0: Counts Instr_Retired.Any", { "Performance Counter Register 0: Counts Instr_Retired.Any", {
/* Also known as MSR_PERF_FIXED_CTR0 */ /* Also known as MSR_PERF_FIXED_CTR0 */
{ BITS_EOT } { BITS_EOT }
}}, }},
/* if CPUID.0AH: EDX[4:0] > 1 */ /* if CPUID.0AH: EDX[4:0] > 1 */
{0x30a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR1", "Fixed-Function \ {0x30a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR1", "Fixed-Function "
Performance Counter Register 1: Counts CPU_CLK_Unhalted.Core ", { "Performance Counter Register 1: Counts CPU_CLK_Unhalted.Core ", {
/* Also known as MSR_PERF_FIXED_CTR1 */ /* Also known as MSR_PERF_FIXED_CTR1 */
{ BITS_EOT } { BITS_EOT }
}}, }},
/* if CPUID.0AH: EDX[4:0] > 2 */ /* if CPUID.0AH: EDX[4:0] > 2 */
{0x30b, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR2", "Fixed-Function \ {0x30b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR2", "Fixed-Function "
Performance Counter Register 2: Counts CPU_CLK_Unhalted.Ref", { "Performance Counter Register 2: Counts CPU_CLK_Unhalted.Ref", {
/* Also known as MSR_PERF_FIXED_CTR2 */ /* Also known as MSR_PERF_FIXED_CTR2 */
{ BITS_EOT } { BITS_EOT }
}}, }},
@ -1372,10 +1372,12 @@ const struct msrdef intel_nehalem_msrs[] = {
}}, }},
/* if CPUID.0AH EAX[7:0] > 2 */ /* if CPUID.0AH EAX[7:0] > 2 */
{ 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, { { 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, {
{ MSR1(0), "Counter only increments the associated event \ { MSR1(0), "Counter only increments the associated event "
conditions occurring in the logical processor which programmed the MSR" }, "conditions occurring in the logical processor "
{ MSR1(1), "Counting the associated event conditions \ "which programmed the MSR" },
occurring across all logical processors sharing a processor core" }, { MSR1(1), "Counting the associated event conditions "
"occurring across all logical processors sharing "
"a processor core" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, { { 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, {
@ -1395,10 +1397,12 @@ const struct msrdef intel_nehalem_msrs[] = {
}}, }},
/* if CPUID.0AH: EAX[7:0] > 2 */ /* if CPUID.0AH: EAX[7:0] > 2 */
{ 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, { { 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, {
{ MSR1(0), "Counter only increments the associated event \ { MSR1(0), "Counter only increments the associated event "
conditions occurring in the logical processor which programmed the MSR" }, "conditions occurring in the logical processor "
{ MSR1(1), "Counting the associated event conditions \ "which programmed the MSR" },
occurring across all logical processors sharing a processor core" }, { MSR1(1), "Counting the associated event conditions "
"occurring across all logical processors sharing "
"a processor core" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, { { 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, {
@ -1418,10 +1422,12 @@ const struct msrdef intel_nehalem_msrs[] = {
}}, }},
/* if CPUID.0AH: EAX[7:0] > 2 */ /* if CPUID.0AH: EAX[7:0] > 2 */
{ 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, { { 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, {
{ MSR1(0), "Counter only increments the associated event \ { MSR1(0), "Counter only increments the associated event "
conditions occurring in the logical processor which programmed the MSR" }, "conditions occurring in the logical processor "
{ MSR1(1), "Counting the associated event conditions \ "which programmed the MSR" },
occurring across all logical processors sharing a processor core" }, { MSR1(1), "Counting the associated event conditions "
"occurring across all logical processors sharing "
"a processor core" },
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, { { 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, {
@ -1615,8 +1621,8 @@ const struct msrdef intel_nehalem_msrs[] = {
*/ */
{ 63, 28, RESERVED }, { 63, 28, RESERVED },
{ 35, 20, RESERVED }, { 35, 20, RESERVED },
{ 15, 16, "Minimum threshold latency value of tagged \ { 15, 16, "Minimum threshold latency value of tagged "
load operation that will be counted", "R/W", PRESENT_DEC, { "load operation that will be counted", "R/W", PRESENT_DEC, {
{ BITVAL_EOT } { BITVAL_EOT }
}}, }},
{ BITS_EOT } { BITS_EOT }
@ -1718,15 +1724,15 @@ const struct msrdef intel_nehalem_msrs[] = {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x481, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PINBASED_CTLS", {0x481, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PINBASED_CTLS",
"Capability Reporting Register of \ "Capability Reporting Register of "
Pin-based VM-execution Controls", { "Pin-based VM-execution Controls", {
/* Additional info available at Appendix A.3, /* Additional info available at Appendix A.3,
* "VM-Execution Controls" */ * "VM-Execution Controls" */
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x482, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PROCBASED_CTLS", {0x482, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PROCBASED_CTLS",
"Capability Reporting Register of \ "Capability Reporting Register of "
Primary Processor-based VM-execution Controls", { "Primary Processor-based VM-execution Controls", {
/* Additional info available at Appendix A.3, /* Additional info available at Appendix A.3,
* "VM-Execution Controls" */ * "VM-Execution Controls" */
{ BITS_EOT } { BITS_EOT }
@ -1780,8 +1786,8 @@ const struct msrdef intel_nehalem_msrs[] = {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x48b, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_PROCBASED_CTLS2", {0x48b, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_PROCBASED_CTLS2",
"Capability Reporting Register of Secondary \ "Capability Reporting Register of Secondary "
Processor-based VM-execution Controls", { "Processor-based VM-execution Controls", {
/* Additional info available at Appendix A.3, /* Additional info available at Appendix A.3,
* "VM-Execution Controls" */ * "VM-Execution Controls" */
{ BITS_EOT } { BITS_EOT }