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- Moved hlt() to it's own header.

Browse Source 
- Reworked pnp superio device support.  Now complete superio support is less than 100 lines.
- Added support for hard coding resource assignments in Config.lb
- Minor bug fixes to romcc
- Initial support for catching the x86 processor BIST error codes.  I've only seen
  this trigger once in production during a very suspcious reset but...
- added raminit_test to test the code paths in raminit.c for the Opteron
- Removed the IORESOURCE_SET bit and added IORESOURCE_ASSIGNED and IORESOURCE_STORED
  so we can tell what we have really done.
- Added generic AGP/IOMMU setting code to x86
- Added an implementation of memmove and removed reserved identifiers from memcpy
- Added minimal support for booting on pre b3 stepping K8 cores
- Moved the checksum on amd8111 boards because our default location was on top of
  extended RTC registers
- On the Hdama added support for enabling i2c hub so we can get at the temperature
  sensors.  Not that i2c bus was implemented well enough to make that useful.
- Redid the Opteron port so we should only need one reset and most of memory initialization
  is done in cpu_fixup.  This is much, much faster.
- Attempted to make the VGA IO region assigment work.  The code seems to work now...
- Redid the error handling in amdk8/raminit.c to distinguish between a bad value
  and a smbus error, and moved memory clearing out to cpufixup.
- Removed CONFIG_KEYBOARD as it was useless.  See pc87360/superio.c for how to
  setup a legacy keyboard properly.
- Reworked the register values for standard hardware, moving the defintions from
  chip.h into the headers of the initialization routines.  This is much saner
  and is actually implemented.
- Made the hdama port an under clockers BIOS.  I debuged so many interesting problems.
- On amd8111_lpc added setup of architectural/legacy hardware
- Enabled PCI error reporting as much as possible.
- Enhanded build_opt_tbl to generate a header of the cmos option locations so
  that romcc compiled code can query the cmos options.
- In romcc gracefully handle function names that degenerate into function pointers
- Bumped the version to 1.1.6 as we are getting closer to 2.0

  TODO finish optimizing the HT links of non dual boards
  TODO make all Opteron board work again
  TODO convert all superio devices to use the new helpers
  TODO convert the via/epia to freebios2 conventions
  TODO cpu fixup/setup by cpu type


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
2004-03-11 15:01:31 +00:00
parent f31d5542f6
commit 5cd81730ec
101 changed files with 4046 additions and 1869 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
src/mainboard/amd/quartet/Config.lb
View File

@@ -251,19 +251,29 @@ northbridge amd/amdk8 "mc0"
pci 1:0.2 on
pci 1:1.0 on
superio NSC/pc87360 link 1
pnp 2e.0
pnp 2e.1
pnp 2e.2
pnp 2e.3
pnp 2e.4
pnp 2e.5
pnp 2e.6
pnp 2e.7
pnp 2e.8
pnp 2e.9
pnp 2e.a
register "com1" = "{1, 0, 0x3f8, 4}"
register "lpt" = "{1}"
pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
pnp 2e.2 off # Com 2
io 0x60 = 0x2f8
irq 0x70 = 3
pnp 2e.3 on # Com 1
io 0x60 = 0x3f8
irq 0x70 = 4
pnp 2e.4 off # SWC
pnp 2e.5 off # Mouse
pnp 2e.6 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
pnp 2e.7 off # GPIO
pnp 2e.8 off # ACB
pnp 2e.9 off # FSCM
pnp 2e.a off # WDT
end
end
end

81
src/mainboard/amd/solo/Config.lb
View File

@@ -23,6 +23,12 @@ uses XIP_ROM_BASE
uses STACK_SIZE
uses HEAP_SIZE
uses USE_OPTION_TABLE
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE=262144
@@ -59,7 +65,14 @@ default HAVE_MP_TABLE=1
default HAVE_OPTION_TABLE=1
##
## AMD Solo is a 1cpu board
## Move the default LinuxBIOS cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default LB_CKS_LOC=123
##
## AMD Solo is a 1cpu board
##
default CONFIG_SMP=1
default CONFIG_MAX_CPUS=1
@@ -152,7 +165,7 @@ object reset.o
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
end
@@ -161,13 +174,13 @@ makerule ./failover.inc
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h "
action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
end
makerule ./auto.inc
makerule ./auto.inc
depends "./auto.E ./romcc"
action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
end
##
@@ -175,18 +188,19 @@ end
##
mainboardinit cpu/i386/entry16.inc
mainboardinit cpu/i386/entry32.inc
#mainboardinit cpu/i386/bist32.inc
ldscript /cpu/i386/entry16.lds
ldscript /cpu/i386/entry32.lds
##
## Build our reset vector (This is where linuxBIOS is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/i386/reset16.inc
ldscript /cpu/i386/reset16.lds
if USE_FALLBACK_IMAGE
mainboardinit cpu/i386/reset16.inc
ldscript /cpu/i386/reset16.lds
else
mainboardinit cpu/i386/reset32.inc
ldscript /cpu/i386/reset32.lds
mainboardinit cpu/i386/reset32.inc
ldscript /cpu/i386/reset32.lds
end
### Should this be in the northbridge code?
@@ -204,12 +218,12 @@ ldscript /arch/i386/lib/id.lds
mainboardinit cpu/k8/earlymtrr.inc
###
### This is the early phase of linuxBIOS startup
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
@@ -225,7 +239,7 @@ mainboardinit ./auto.inc
mainboardinit cpu/k8/disable_mmx_sse.inc
##
## Include the secondary Configuration files
## Include the secondary Configuration files
##
dir /pc80
config chip.h
@@ -254,19 +268,29 @@ northbridge amd/amdk8 "mc0"
pci 1:0.2 on
# pci 1:1.0 off
superio NSC/pc87360 link 1
pnp 2e.0
pnp 2e.1
pnp 2e.2
pnp 2e.3
pnp 2e.4
pnp 2e.5
pnp 2e.6
pnp 2e.7
pnp 2e.8
pnp 2e.9
pnp 2e.a
register "com1" = "{1, 0, 0x3f8, 4}"
register "lpt" = "{1}"
pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
pnp 2e.2 off # Com 2
io 0x60 = 0x2f8
irq 0x70 = 3
pnp 2e.3 on # Com 1
io 0x60 = 0x3f8
irq 0x70 = 4
pnp 2e.4 off # SWC
pnp 2e.5 off # Mouse
pnp 2e.6 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
pnp 2e.7 off # GPIO
pnp 2e.8 off # ACB
pnp 2e.9 off # FSCM
pnp 2e.a off # WDT
end
end
end
@@ -279,4 +303,5 @@ end
##
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
#mainboardinit cpu/i386/bist32_fail.inc

104
src/mainboard/amd/solo/auto.c
View File

@@ -1,14 +1,16 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <cpu/p6/apic.h>
#include <arch/io.h>
#include <device/pnp.h>
#include <arch/romcc_io.h>
#include <arch/smp/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/k8/apic_timer.c"
@@ -17,9 +19,26 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include "debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/NSC/pc87360/pc87360_early_serial.c"
#define SIO_BASE 0x2e
static void hard_reset(void)
{
set_bios_reset();
/* enable cf9 */
pci_write_config8(PCI_DEV(0, 0x05, 3), 0x41, 0xf1);
/* reset */
outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
set_bios_reset();
pci_write_config8(PCI_DEV(0, 0x05, 0), 0x47, 1);
}
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
@@ -54,7 +73,7 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing here */
/* nothing to do */
}
static inline int spd_read_byte(unsigned device, unsigned address)
@@ -62,69 +81,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
/* no specific code here. this should go away completely */
static void coherent_ht_mainboard(unsigned cpus)
{
}
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
static void enable_lapic(void)
{
msr_t msr;
msr = rdmsr(0x1b);
msr.hi &= 0xffffff00;
msr.lo &= 0x000007ff;
msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
wrmsr(0x1b, msr);
}
static void stop_this_cpu(void)
{
unsigned apicid;
apicid = apic_read(APIC_ID) >> 24;
/* Send an APIC INIT to myself */
apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
/* Wait for the ipi send to finish */
apic_wait_icr_idle();
/* Deassert the APIC INIT */
apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
/* Wait for the ipi send to finish */
apic_wait_icr_idle();
/* If I haven't halted spin forever */
for(;;) {
hlt();
}
}
#define PC87360_FDC 0x00
#define PC87360_PP 0x01
#define PC87360_SP2 0x02
#define PC87360_SP1 0x03
#define PC87360_SWC 0x04
#define PC87360_KBCM 0x05
#define PC87360_KBCK 0x06
#define PC87360_GPIO 0x07
#define PC87360_ACB 0x08
#define PC87360_FSCM 0x09
#define PC87360_WDT 0x0A
/* FIXME: Do we really need this on Solo boards? */
static void pc87360_enable_serial(void)
{
pnp_set_logical_device(SIO_BASE, PC87360_SP1);
pnp_set_enable(SIO_BASE, 1);
pnp_set_iobase0(SIO_BASE, 0x3f8);
}
static void main(void)
{
static const struct mem_controller cpu[] = {
@@ -138,26 +99,29 @@ static void main(void)
.channel1 = { 0, 0, 0, 0 },
}
};
int needs_reset;
enable_lapic();
init_timer();
if (cpu_init_detected()) {
asm("jmp __cpu_reset");
}
enable_lapic();
init_timer();
#if 0
/* Enabling this will make romcc segfault - 2003/10/13 */
distinguish_cpu_resets();
if (!boot_cpu()) {
print_err("This LinuxBIOS image is built for UP only.\n");
stop_this_cpu();
}
#endif
pc87360_enable_serial();
pc87360_enable_serial(SIO_BASE, TTYS0_BASE);
uart_init();
console_init();
setup_default_resource_map();
setup_coherent_ht_domain();
enumerate_ht_chain(0);
distinguish_cpu_resets(0);
needs_reset = setup_coherent_ht_domain();
needs_reset = ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) {
print_info("ht reset -");
soft_reset();
}
#if 0
print_pci_devices();
#endif

26
src/mainboard/amd/solo/cmos.layout
View File

@@ -29,6 +29,9 @@ entries
386 1 e 1 ECC_memory
388 4 r 0 reboot_bits
392 3 e 5 baud_rate
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
416 4 e 7 boot_first
@@ -36,7 +39,14 @@ entries
424 4 e 7 boot_third
428 4 h 0 boot_index
432 8 h 0 boot_countdown
1008 16 h 0 check_sum
440 4 e 9 slow_cpu
444 1 e 1 nmi
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
enumerations
@@ -66,9 +76,21 @@ enumerations
7 9 Fallback_HDD
7 10 Fallback_Floppy
#7 3 ROM
8 0 200Mhz
8 1 166Mhz
8 2 133Mhz
8 3 100Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums
checksum 392 1007 1008
checksum 392 983 984

72
src/mainboard/amd/solo/failover.c
View File

@@ -3,40 +3,78 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include "arch/romcc_io.h"
#include <arch/romcc_io.h>
#include <arch/smp/lapic.h>
#include "pc80/mc146818rtc_early.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "cpu/p6/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#define HAVE_REGPARM_SUPPORT 0
#if HAVE_REGPARM_SUPPORT
static unsigned long main(unsigned long bist)
{
#else
static void main(void)
{
unsigned long bist = 0;
#endif
/* Make cerain my local apic is useable */
enable_lapic();
/* Is this a cpu only reset? */
if (cpu_init_detected()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto cpu_reset;
}
}
/* Is this a secondary cpu? */
if (!boot_cpu()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain(0);
/* Setup the 8111 */
amd8111_enable_rom();
/* Is this a cpu reset? */
if (cpu_init_detected()) {
if (last_boot_normal()) {
asm("jmp __normal_image");
} else {
asm("jmp __cpu_reset");
}
}
/* Is this a deliberate reset by the bios */
else if (bios_reset_detected() && last_boot_normal()) {
asm("jmp __normal_image");
}
/* Is this a secondary cpu? */
else if (!boot_cpu() && last_boot_normal()) {
asm("jmp __normal_image");
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
asm("jmp __normal_image");
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
asm("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
#if HAVE_REGPARM_SUPPORT
return bist;
#else
return;
#endif
}

1
src/mainboard/amd/solo/mptable.c
View File

@@ -178,7 +178,6 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
1, (5<<2)|1, 0x02, 0x11);
/* There is no extension information... */
/* Compute the checksums */

61
src/mainboard/arima/hdama/Config.lb
View File

@@ -23,6 +23,12 @@ uses XIP_ROM_BASE
uses STACK_SIZE
uses HEAP_SIZE
uses USE_OPTION_TABLE
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE=524288
@@ -58,6 +64,13 @@ default HAVE_MP_TABLE=1
##
default HAVE_OPTION_TABLE=1
##
## Move the default LinuxBIOS cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default LB_CKS_LOC=123
##
## Build code for SMP support
## Only worry about 2 micro processors
@@ -73,8 +86,8 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
#default MAINBOARD_PART_NUMBER="HDAMA"
#default MAINBOARD_VENDOR="ARIMA"
default MAINBOARD_PART_NUMBER="HDAMA"
default MAINBOARD_VENDOR="ARIMA"
###
### LinuxBIOS layout values
@@ -144,9 +157,7 @@ arch i386 end
## Build the objects we have code for in this directory.
##
#object mainboard.o
driver mainboard.o
#object static_devices.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
object reset.o
@@ -165,8 +176,8 @@ makerule ./failover.inc
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
depends "$(MAINBOARD)/auto.c option_table.h "
action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
end
makerule ./auto.inc
depends "./auto.E ./romcc"
@@ -178,6 +189,7 @@ end
##
mainboardinit cpu/i386/entry16.inc
mainboardinit cpu/i386/entry32.inc
mainboardinit cpu/i386/bist32.inc
ldscript /cpu/i386/entry16.lds
ldscript /cpu/i386/entry32.lds
@@ -259,19 +271,29 @@ northbridge amd/amdk8 "mc0"
pci 1:0.2 on
pci 1:1.0 off
superio NSC/pc87360 link 1
pnp 2e.0
pnp 2e.1
pnp 2e.2
pnp 2e.3
pnp 2e.4
pnp 2e.5
pnp 2e.6
pnp 2e.7
pnp 2e.8
pnp 2e.9
pnp 2e.a
register "com1" = "{1, 0, 0x3f8, 4}"
register "lpt" = "{1}"
pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
pnp 2e.2 off # Com 2
io 0x60 = 0x2f8
irq 0x70 = 3
pnp 2e.3 on # Com 1
io 0x60 = 0x3f8
irq 0x70 = 4
pnp 2e.4 off # SWC
pnp 2e.5 off # Mouse
pnp 2e.6 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
pnp 2e.7 off # GPIO
pnp 2e.8 off # ACB
pnp 2e.9 off # FSCM
pnp 2e.a off # WDT
end
end
end
@@ -297,4 +319,5 @@ end
##
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
mainboardinit cpu/i386/bist32_fail.inc

134
src/mainboard/arima/hdama/auto.c
View File

@@ -1,14 +1,16 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <cpu/p6/apic.h>
#include <arch/io.h>
#include <device/pnp.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/smp/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/k8/apic_timer.c"
@@ -17,8 +19,25 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include "debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/NSC/pc87360/pc87360_early_serial.c"
#define SIO_BASE 0x2e
#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
static void hard_reset(void)
{
set_bios_reset();
/* enable cf9 */
pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
/* reset */
outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
set_bios_reset();
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
}
static void memreset_setup(void)
{
@@ -75,13 +94,13 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
{ 0x00010404, 0x00050101 }
};
if(maxnodes>2) {
if(maxnodes > 2) {
print_debug("this mainboard is only designed for 2 cpus\r\n");
maxnodes=2;
}
if (!(node>=maxnodes || row>=maxnodes)) {
if (!(node >= maxnodes || row >= maxnodes)) {
ret=rows_2p[node][row];
}
@@ -98,67 +117,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
/* no specific code here. this should go away completely */
static void coherent_ht_mainboard(unsigned cpus)
{
}
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
static void enable_lapic(void)
{
msr_t msr;
msr = rdmsr(0x1b);
msr.hi &= 0xffffff00;
msr.lo &= 0x000007ff;
msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
wrmsr(0x1b, msr);
}
static void stop_this_cpu(void)
{
unsigned apicid;
apicid = apic_read(APIC_ID) >> 24;
/* Send an APIC INIT to myself */
apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
/* Wait for the ipi send to finish */
apic_wait_icr_idle();
/* Deassert the APIC INIT */
apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
/* Wait for the ipi send to finish */
apic_wait_icr_idle();
/* If I haven't halted spin forever */
for(;;) {
hlt();
}
}
#define PC87360_FDC 0x00
#define PC87360_PP 0x01
#define PC87360_SP2 0x02
#define PC87360_SP1 0x03
#define PC87360_SWC 0x04
#define PC87360_KBCM 0x05
#define PC87360_KBCK 0x06
#define PC87360_GPIO 0x07
#define PC87360_ACB 0x08
#define PC87360_FSCM 0x09
#define PC87360_WDT 0x0A
static void pc87360_enable_serial(void)
{
pnp_set_logical_device(SIO_BASE, PC87360_SP1);
pnp_set_enable(SIO_BASE, 1);
pnp_set_iobase0(SIO_BASE, 0x3f8);
}
#define FIRST_CPU 1
#define SECOND_CPU 1
@@ -193,22 +157,26 @@ static void main(void)
},
#endif
};
int needs_reset;
enable_lapic();
init_timer();
if (cpu_init_detected()) {
asm("jmp __cpu_reset");
}
enable_lapic();
init_timer();
distinguish_cpu_resets();
if (!boot_cpu()) {
stop_this_cpu();
}
pc87360_enable_serial();
pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
setup_default_resource_map();
setup_coherent_ht_domain();
enumerate_ht_chain(0);
distinguish_cpu_resets(0);
needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) {
print_info("ht reset -");
soft_reset();
}
#if 0
print_pci_devices();
#endif
@@ -219,39 +187,15 @@ static void main(void)
memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
#if 1
#if 0
dump_pci_devices();
#endif
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 2));
#endif
/* Check all of memory */
#if 0
msr_t msr;
msr = rdmsr(TOP_MEM);
print_debug("TOP_MEM: ");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
print_debug("\r\n");
#endif
#if 0
ram_check(0x00000000, msr.lo);
#endif
#if 0
static const struct {
unsigned long lo, hi;
} check_addrs[] = {
/* Check 16MB of memory @ 0*/
{ 0x00000000, 0x01000000 },
#if TOTAL_CPUS > 1
/* Check 16MB of memory @ 2GB */
{ 0x80000000, 0x81000000 },
#endif
};
int i;
for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
ram_check(check_addrs[i].lo, check_addrs[i].hi);
}
/* Check the first 1M */
ram_check(0x00000000, 0x000100000);
#endif
}

26
src/mainboard/arima/hdama/cmos.layout
View File

@@ -29,6 +29,9 @@ entries
386 1 e 1 ECC_memory
388 4 r 0 reboot_bits
392 3 e 5 baud_rate
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
416 4 e 7 boot_first
@@ -36,7 +39,14 @@ entries
424 4 e 7 boot_third
428 4 h 0 boot_index
432 8 h 0 boot_countdown
1008 16 h 0 check_sum
440 4 e 9 slow_cpu
444 1 e 1 nmi
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
enumerations
@@ -66,9 +76,21 @@ enumerations
7 9 Fallback_HDD
7 10 Fallback_Floppy
#7 3 ROM
8 0 200Mhz
8 1 166Mhz
8 2 133Mhz
8 3 100Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums
checksum 392 1007 1008
checksum 392 983 984

74
src/mainboard/arima/hdama/failover.c
View File

@@ -3,40 +3,78 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include "arch/romcc_io.h"
#include <arch/romcc_io.h>
#include <arch/smp/lapic.h>
#include "pc80/mc146818rtc_early.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "cpu/p6/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#define HAVE_REGPARM_SUPPORT 0
#if HAVE_REGPARM_SUPPORT
static unsigned long main(unsigned long bist)
{
#else
static void main(void)
{
unsigned long bist = 0;
#endif
/* Make cerain my local apic is useable */
enable_lapic();
/* Is this a cpu only reset? */
if (cpu_init_detected()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto cpu_reset;
}
}
/* Is this a secondary cpu? */
if (!boot_cpu()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain(0);
enumerate_ht_chain();
/* Setup the 8111 */
amd8111_enable_rom();
/* Is this a cpu reset? */
if (cpu_init_detected()) {
if (last_boot_normal()) {
asm("jmp __normal_image");
} else {
asm("jmp __cpu_reset");
}
}
/* Is this a deliberate reset by the bios */
else if (bios_reset_detected() && last_boot_normal()) {
asm("jmp __normal_image");
}
/* Is this a secondary cpu? */
else if (!boot_cpu() && last_boot_normal()) {
asm("jmp __normal_image");
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
asm("jmp __normal_image");
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
asm("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
#if HAVE_REGPARM_SUPPORT
return bist;
#else
return;
#endif
}

36
src/mainboard/arima/hdama/irq_tables.c
View File

@@ -17,36 +17,28 @@
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32+16*IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT
* devices on the bus */
PIRQ_VERSION, /* u16 version */
32+16*IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT table entries */
IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */
IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */
0x00, /* IRQs devoted exclusively to PCI usage */
IRQ_ROUTER_VENDOR, /* Vendor */
IRQ_ROUTER_DEVICE, /* Device */
0x00, /* Crap (miniport) */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x00, /* u8 checksum , mod 256 checksum must give
* zero, will be corrected later
*/
{
/* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0xb0, /* u8 checksum , mod 256 checksum must give zero */
{ /* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */
/* PCI Slot 1-6 */
IRQ_SLOT (1, 3,1,0, 2,3,4,1 ),
IRQ_SLOT (2, 3,2,0, 3,4,1,2 ),
IRQ_SLOT (3, 2,1,0, 2,3,4,1 ),
IRQ_SLOT (4, 2,2,0, 3,4,1,2 ),
IRQ_SLOT (5, 4,5,0, 2,3,4,1 ),
IRQ_SLOT (6, 4,4,0, 1,2,3,4 ),
IRQ_SLOT(1, 3,1,0, 2,3,4,1 ),
IRQ_SLOT(2, 3,2,0, 3,4,1,2 ),
IRQ_SLOT(3, 2,1,0, 2,3,4,1 ),
IRQ_SLOT(4, 2,2,0, 3,4,1,2 ),
IRQ_SLOT(5, 4,5,0, 2,3,4,1 ),
IRQ_SLOT(6, 4,4,0, 1,2,3,4 ),
/* Onboard NICs */
IRQ_SLOT (0, 2,3,0, 4,0,0,0 ),
IRQ_SLOT (0, 2,4,0, 4,0,0,0 ),
IRQ_SLOT(0, 2,3,0, 4,0,0,0 ),
IRQ_SLOT(0, 2,4,0, 4,0,0,0 ),
/* Let Linux know about bus 1 */
IRQ_SLOT (0, 1,4,3, 0,0,0,0 ),
IRQ_SLOT(0, 1,4,3, 0,0,0,0 ),
}
};

247
src/mainboard/arima/hdama/mainboard.c
View File

@@ -3,23 +3,268 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <cpu/p6/msr.h>
#include <arch/io.h>
#include <device/chip.h>
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
#include "pc80/mc146818rtc.h"
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{
0, 1,
};
#define SMBGSTATUS 0xe0
#define SMBGCTL 0xe2
#define SMBHSTADDR 0xe4
#define SMBHSTDAT 0xe6
#define SMBHSTCMD 0xe8
#define SMBHSTFIFO 0xe9
#define SMBUS_TIMEOUT (100*1000*10)
static inline void smbus_delay(void)
{
outb(0x80, 0x80);
}
static int smbus_wait_until_ready(unsigned smbus_io_base)
{
unsigned long loops;
loops = SMBUS_TIMEOUT;
do {
unsigned short val;
smbus_delay();
val = inw(smbus_io_base + SMBGSTATUS);
if ((val & 0x800) == 0) {
break;
}
if(loops == (SMBUS_TIMEOUT / 2)) {
outw(inw(smbus_io_base + SMBGSTATUS),
smbus_io_base + SMBGSTATUS);
}
} while(--loops);
return loops?0:-2;
}
static int smbus_wait_until_done(unsigned smbus_io_base)
{
unsigned long loops;
loops = SMBUS_TIMEOUT;
do {
unsigned short val;
smbus_delay();
val = inw(smbus_io_base + SMBGSTATUS);
if (((val & 0x8) == 0) | ((val & 0x437) != 0)) {
break;
}
} while(--loops);
return loops?0:-3;
}
static int smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned value)
{
unsigned char global_status_register;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return -2;
}
/* setup transaction */
/* disable interrupts */
outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
/* set the device I'm talking too */
outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
/* set the command/address... */
outb(0, smbus_io_base + SMBHSTCMD);
/* set up for a send byte */
outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x1), smbus_io_base + SMBGCTL);
/* clear any lingering errors, so the transaction will run */
/* Do I need to write the bits to a 1 to clear an error? */
outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS);
/* set the data word...*/
outw(value, smbus_io_base + SMBHSTDAT);
/* start the command */
outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL);
/* poll for transaction completion */
if (smbus_wait_until_done(smbus_io_base) < 0) {
return -3;
}
global_status_register = inw(smbus_io_base + SMBGSTATUS);
if (global_status_register != (1 << 4)) {
return -1;
}
return 0;
}
static int smbus_recv_byte(unsigned smbus_io_base, unsigned device)
{
unsigned char global_status_register;
unsigned char byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return -2;
}
/* setup transaction */
/* disable interrupts */
outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
/* set the device I'm talking too */
outw(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
/* set the command/address... */
outb(0, smbus_io_base + SMBHSTCMD);
/* set up for a send byte */
outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x1), smbus_io_base + SMBGCTL);
/* clear any lingering errors, so the transaction will run */
/* Do I need to write the bits to a 1 to clear an error? */
outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS);
/* set the data word...*/
outw(0, smbus_io_base + SMBHSTDAT);
/* start the command */
outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL);
/* poll for transaction completion */
if (smbus_wait_until_done(smbus_io_base) < 0) {
return -3;
}
global_status_register = inw(smbus_io_base + SMBGSTATUS);
/* read results of transaction */
byte = inw(smbus_io_base + SMBHSTDAT) & 0xff;
if (global_status_register != (1 << 4)) {
return -1;
}
return byte;
}
#if 0
static int smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
{
unsigned char global_status_register;
unsigned char byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return -2;
}
/* setup transaction */
/* disable interrupts */
outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
/* set the device I'm talking too */
outw(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
/* set the command/address... */
outb(address & 0xFF, smbus_io_base + SMBHSTCMD);
/* set up for a byte data read */
outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x2), smbus_io_base + SMBGCTL);
/* clear any lingering errors, so the transaction will run */
/* Do I need to write the bits to a 1 to clear an error? */
outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS);
/* clear the data word...*/
outw(0, smbus_io_base + SMBHSTDAT);
/* start the command */
outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL);
/* poll for transaction completion */
if (smbus_wait_until_done(smbus_io_base) < 0) {
return -3;
}
global_status_register = inw(smbus_io_base + SMBGSTATUS);
/* read results of transaction */
byte = inw(smbus_io_base + SMBHSTDAT) & 0xff;
if (global_status_register != (1 << 4)) {
return -1;
}
return byte;
}
static int smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val)
{
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return -2;
}
/* setup transaction */
/* disable interrupts */
outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)),
smbus_io_base + SMBGCTL);
/* set the device I'm talking too */
outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
outb(address & 0xFF, smbus_io_base + SMBHSTCMD);
/* set up for a byte data write */ /* FIXME */
outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x1), smbus_io_base + SMBGCTL);
/* clear any lingering errors, so the transaction will run */
/* Do I need to write the bits to a 1 to clear an error? */
outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS);
/* clear the data word...*/
outw(val, smbus_io_base + SMBHSTDAT);
/* start the command */
outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL);
/* poll for transaction completion */
if (smbus_wait_until_done(smbus_io_base) < 0) {
return -3;
}
return 0;
}
#endif
#define SMBUS_MUX 0x70
static void mainboard_init(device_t dev)
{
/* Set the mux to see the temperature sensors */
dev = dev_find_device(0x1022, 0x746b, 0);
if (dev) {
unsigned smbus_io_base;
unsigned device;
int result;
int mux_setting;
device = SMBUS_MUX;
mux_setting = 1;
smbus_io_base = pci_read_config32(dev, 0x58) & ~1;;
result = smbus_send_byte(smbus_io_base, device, mux_setting);
if ((result < 0) ||
(smbus_recv_byte(smbus_io_base, device) != mux_setting)) {
printk_err("SMBUS mux would not set to %d\n", mux_setting);
}
}
else {
printk_err("SMBUS_controller not found\n");
}
}
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.init = mainboard_init,
.scan_bus = amdk8_scan_root_bus,
.enable = 0,
};

36
src/mainboard/newisys/khepri/Config.lb
View File

@@ -252,19 +252,29 @@ northbridge amd/amdk8 "mc0"
pci 1:0.2 on
pci 1:1.0 on
superio NSC/pc87360 link 1
pnp 2e.0
pnp 2e.1
pnp 2e.2
pnp 2e.3
pnp 2e.4
pnp 2e.5
pnp 2e.6
pnp 2e.7
pnp 2e.8
pnp 2e.9
pnp 2e.a
register "com1" = "{1, 0, 0x3f8, 4}"
register "lpt" = "{1}"
pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
pnp 2e.2 off # Com 2
io 0x60 = 0x2f8
irq 0x70 = 3
pnp 2e.3 on # Com 1
io 0x60 = 0x3f8
irq 0x70 = 4
pnp 2e.4 off # SWC
pnp 2e.5 off # Mouse
pnp 2e.6 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
pnp 2e.7 off # GPIO
pnp 2e.8 off # ACB
pnp 2e.9 off # FSCM
pnp 2e.a off # WDT
end
end
end

127
src/mainboard/newisys/khepri/auto.c
View File

@@ -2,17 +2,19 @@
#define MAXIMUM_CONSOLE_LOGLEVEL 9
#define DEFAULT_CONSOLE_LOGLEVEL 9
#include <stdint.h>
#include <device/pci_def.h>
#include <cpu/p6/apic.h>
#include <arch/io.h>
#include <device/pnp.h>
#include <arch/romcc_io.h>
#include <arch/smp/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/k8/apic_timer.c"
@@ -21,8 +23,25 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include "debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/NSC/pc87360/pc87360_early_serial.c"
#define SIO_BASE 0x2e
#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
static void hard_reset(void)
{
set_bios_reset();
/* enable cf9 */
pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
/* reset */
outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
set_bios_reset();
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
}
static void memreset_setup(void)
{
@@ -102,11 +121,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
/* no specific code here. this should go away completely */
static void coherent_ht_mainboard(unsigned cpus)
{
}
#include "northbridge/amd/amdk8/raminit.c"
#define CONNECTION_0_1 DOWN
@@ -116,59 +130,6 @@ static void coherent_ht_mainboard(unsigned cpus)
#include "resourcemap.c" /* newisys khepri does not want the default */
static void enable_lapic(void)
{
msr_t msr;
msr = rdmsr(0x1b);
msr.hi &= 0xffffff00;
msr.lo &= 0x000007ff;
msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
wrmsr(0x1b, msr);
}
static void stop_this_cpu(void)
{
unsigned apicid;
apicid = apic_read(APIC_ID) >> 24;
/* Send an APIC INIT to myself */
apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
/* Wait for the ipi send to finish */
apic_wait_icr_idle();
/* Deassert the APIC INIT */
apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
/* Wait for the ipi send to finish */
apic_wait_icr_idle();
/* If I haven't halted spin forever */
for(;;) {
hlt();
}
}
#define PC87360_FDC 0x00
#define PC87360_PP 0x01
#define PC87360_SP2 0x02
#define PC87360_SP1 0x03
#define PC87360_SWC 0x04
#define PC87360_KBCM 0x05
#define PC87360_KBCK 0x06
#define PC87360_GPIO 0x07
#define PC87360_ACB 0x08
#define PC87360_FSCM 0x09
#define PC87360_WDT 0x0A
static void pc87360_enable_serial(void)
{
pnp_set_logical_device(SIO_BASE, PC87360_SP1);
pnp_set_enable(SIO_BASE, 1);
pnp_set_iobase0(SIO_BASE, 0x3f8);
}
static void main(void)
{
/*
@@ -195,21 +156,26 @@ static void main(void)
.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
},
};
int needs_reset;
enable_lapic();
init_timer();
if (cpu_init_detected()) {
asm("jmp __cpu_reset");
}
enable_lapic();
init_timer();
distinguish_cpu_resets();
if (!boot_cpu()) {
stop_this_cpu();
}
pc87360_enable_serial();
pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
setup_khepri_resource_map();
setup_coherent_ht_domain();
enumerate_ht_chain(0);
distinguish_cpu_resets(0);
needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) {
print_info("ht reset -");
soft_reset();
}
#if 0
print_pci_devices();
@@ -230,30 +196,7 @@ static void main(void)
/* Check all of memory */
#if 0
msr_t msr;
msr = rdmsr(TOP_MEM);
print_debug("TOP_MEM: ");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
print_debug("\r\n");
#endif
#if 0
ram_check(0x00000000, msr.lo);
#endif
#if 0
static const struct {
unsigned long lo, hi;
} check_addrs[] = {
/* Check 16MB of memory @ 0*/
{ 0x00000000, 0x01000000 },
#if TOTAL_CPUS > 1
/* Check 16MB of memory @ 2GB */
{ 0x80000000, 0x81000000 },
#endif
};
int i;
for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
ram_check(check_addrs[i].lo, check_addrs[i].hi);
}
/* Check the first 1M */
ram_check(0x00000000, 0x000100000);
#endif
}