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Add darp7

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Change-Id: I8c47a18095ad19f907c9018952dec551865e27fe
This commit is contained in:
Jeremy Soller
2020-12-22 11:32:42 -07:00
parent 6690cc7c7a
commit 5cf1e853cc
15 changed files with 899 additions and 2 deletions
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72
src/mainboard/system76/darp7/Kconfig Normal file
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if BOARD_SYSTEM76_DARP7
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_16384
select DRIVERS_I2C_HID
select DRIVERS_INTEL_PMC
select DRIVERS_INTEL_USB4_RETIMER
select EC_SYSTEM76_EC
select EC_SYSTEM76_EC_BAT_THRESHOLDS
select HAVE_ACPI_TABLES
select HAVE_SMI_HANDLER
select INTEL_GMA_HAVE_VBT
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_LPC_TPM
select MAINBOARD_HAS_TPM2
select NO_UART_ON_SUPERIO
select PCIEXP_HOTPLUG
select SOC_INTEL_TIGERLAKE
select SOC_INTEL_COMMON_BLOCK_HDA
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SPD_READ_BY_WORD
select SYSTEM_TYPE_LAPTOP
select TPM_RDRESP_NEED_DELAY
config MAINBOARD_DIR
string
default "system76/darp7"
config MAINBOARD_PART_NUMBER
string
default "darp7"
config MAINBOARD_SMBIOS_PRODUCT_NAME
string
default "Darter Pro"
config MAINBOARD_VERSION
string
default "darp7"
#TODO: subsystem IDs
config CBFS_SIZE
hex
default 0xA00000
config CONSOLE_POST
bool
default y
config DIMM_MAX
int
default 4 # Hack to make soc code work
config DIMM_SPD_SIZE
int
default 512
config MAX_CPUS
int
default 8
config POST_DEVICE
bool
default n
config UART_FOR_CONSOLE
int
default 2
endif

2
src/mainboard/system76/darp7/Kconfig.name Normal file
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config BOARD_SYSTEM76_DARP7
bool "darp7"

3
src/mainboard/system76/darp7/Makefile.inc Normal file
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bootblock-y += bootblock.c
ramstage-y += ramstage.c
ramstage-y += hda_verb.c

30
src/mainboard/system76/darp7/acpi/backlight.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/intel/gma/acpi/gma.asl>
Scope (GFX0) {
Name (BRIG, Package (22) {
40, /* default AC */
40, /* default Battery */
5,
10,
15,
20,
25,
30,
35,
40,
45,
50,
55,
60,
65,
70,
75,
80,
85,
90,
95,
100
})
}

12
src/mainboard/system76/darp7/acpi/mainboard.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#define EC_GPE_SCI 0x6E
#define EC_GPE_SWI 0x6E
#include <ec/system76/ec/acpi/ec.asl>
Scope (\_SB) {
#include "sleep.asl"
Scope (PCI0) {
#include "backlight.asl"
}
}

46
src/mainboard/system76/darp7/acpi/sleep.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <intelblocks/gpio.h>
Method (PGPM, 1, Serialized)
{
For (Local0 = 0, Local0 < 6, Local0++)
{
\_SB.PCI0.CGPM (Local0, Arg0)
}
}
/*
* Method called from _PTS prior to system sleep state entry
* Enables dynamic clock gating for all 5 GPIO communities
*/
Method (MPTS, 1, Serialized)
{
\_SB.PCI0.LPCB.EC0.PTS (Arg0)
PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
}
/*
* Method called from _WAK prior to system sleep state wakeup
* Disables dynamic clock gating for all 5 GPIO communities
*/
Method (MWAK, 1, Serialized)
{
PGPM (0)
\_SB.PCI0.LPCB.EC0.WAK (Arg0)
}
/*
* S0ix Entry/Exit Notifications
* Called from \_SB.PEPD._DSM
*/
Method (MS0X, 1, Serialized)
{
If (Arg0 == 1) {
/* S0ix Entry */
PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
} Else {
/* S0ix Exit */
PGPM (0)
}
}

8
src/mainboard/system76/darp7/board_info.txt Normal file
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Vendor name: System76
Board name: darp7
Category: laptop
Release year: 2021
ROM package: SOIC-8
ROM protocol: SPI
ROM socketed: n
Flashrom support: y

9
src/mainboard/system76/darp7/bootblock.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <gpio.h>
#include "gpio.h"
void bootblock_mainboard_init(void) {
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}

369
src/mainboard/system76/darp7/devicetree.cb Normal file
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chip soc/intel/tigerlake
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
// Touchpad I2C bus
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 80,
.fall_time_ns = 110,
},
}"
# ACPI (soc/intel/tigerlake/acpi.c)
# Disable DPTF
register "dptf_enable" = "0"
# Enable Enhanced Intel SpeedStep
register "eist_enable" = "1"
# Enable s0ix, required for TGL-U
register "s0ix_enable" = "1"
# CPU (soc/intel/tigerlake/cpu.c)
# Power limits
register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
.tdp_pl1_override = 28,
// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
.tdp_pl2_override = 51,
}"
register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
.tdp_pl1_override = 28,
// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
.tdp_pl2_override = 51,
}"
# Finalize (soc/intel/tigerlake/finalize.c)
# PM Timer Disabled, saves power
register "PmTimerDisabled" = "1"
# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
# Enable C6 DRAM
register "enable_c6dram" = "1"
# System Agent dynamic frequency support
register "SaGv" = "SaGv_Enabled"
# FSP Silicon (soc/intel/tigerlake/fsp_params.c)
# Acoustic settings
register "AcousticNoiseMitigation" = "1"
register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8"
register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8"
register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1"
register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1"
# FIVR configuration
# Read EXT_RAIL_CONFIG to determine bitmaps
# sudo devmem2 0xfe0011b8
# 0x0
# Read EXT_V1P05_VR_CONFIG
# sudo devmem2 0xfe0011c0
# 0x1a42000
# Read EXT_VNN_VR_CONFIG0
# sudo devmem2 0xfe0011c4
# 0x1a42000
# TODO: v1p05 voltage and vnn icc max?
register "ext_fivr_settings" = "{
.configure_ext_fivr = 1,
.v1p05_enable_bitmap = 0,
.vnn_enable_bitmap = 0,
.v1p05_supported_voltage_bitmap = 0,
.vnn_supported_voltage_bitmap = 0,
.v1p05_icc_max_ma = 500,
.vnn_sx_voltage_mv = 1050,
}"
# Read LPM_EN, make sure to invert the bits
# sudo devmem2 0xfe001c78
# 0x9
register "LpmStateDisableMask" = "
LPM_S0i2_1 |
LPM_S0i2_2 |
LPM_S0i3_1 |
LPM_S0i3_2 |
LPM_S0i3_3 |
LPM_S0i3_4
"
# Thermal
# rdmsr --bitfield 31:24 --decimal 0x1A2
register "tcc_offset" = "12"
# PM Util (soc/intel/tigerlake/pmutil.c)
# GPE configuration
# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
# 0x432
register "pmc_gpe0_dw0" = "PMC_GPP_A"
register "pmc_gpe0_dw1" = "PMC_GPP_R"
register "pmc_gpe0_dw2" = "PMC_GPD"
# Actual device tree
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
#From CPU EDS(575683)
device ref system_agent on end
device ref igpu on
# DDIA is eDP
register "DdiPortAConfig" = "1"
register "DdiPortAHpd" = "1"
register "DdiPortADdc" = "0"
# DDIB is HDMI
register "DdiPortBConfig" = "0"
register "DdiPortBHpd" = "1"
register "DdiPortBDdc" = "1"
register "gfx" = "GMA_STATIC_DISPLAYS(0)"
end
device ref dptf on
register "Device4Enable" = "1"
end
device ref peg on
# PCIe PEG0 x4, Clock 0 (SSD1)
register "PcieClkSrcUsage[0]" = "0x40"
register "PcieClkSrcClkReq[0]" = "0"
#TODO: causes failure on resume
# chip soc/intel/common/block/pcie/rtd3
# register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" # SSD1_PWR_EN
# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D13)" # GPP_D13_SSD1_PLT_RST#
# #TODO: Support disable/enable CPU RP clock
# register "srcclk_pin" = "-1" # SSD1_CLKREQ#
# device generic 0 on end
# end
#TODO: Hybrid storage mode?
register "HybridStorageMode" = "0"
end
device ref tbt_pcie_rp0 on end # J_TYPEC2
device ref gna on end
device ref north_xhci on # J_TYPEC2
register "TcssXhciEn" = "1"
chip drivers/usb/acpi
device ref tcss_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB3 J_TYPEC2""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(1, 1)"
device ref tcss_usb3_port1 on end
end
end
end
end
device ref tbt_dma0 on # J_TYPEC2
chip drivers/intel/usb4/retimer
register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)"
device generic 0 on end
end
end
# From PCH EDS(576591)
device ref cnvi_bt on end
device ref south_xhci on
# USB2
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # UJ_USB1
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_1
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
# USB3
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH0
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_1
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH1
# ACPI
chip drivers/usb/acpi
device ref xhci_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB2 UJ_USB1""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(1, 2)"
device ref usb2_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 J_TYPEC1""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(2, 1)"
device ref usb2_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 J_USB3_1""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(2, 2)"
device ref usb2_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Fingerprint""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port5 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 J_TYPEC2""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(1, 1)"
device ref usb2_port6 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Camera""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port7 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port10 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 J_TYPEC1 CH0""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(2, 1)"
device ref usb3_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 J_USB3_1""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(2, 2)"
device ref usb3_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 J_TYPEC1 CH1""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(2, 1)"
device ref usb3_port4 on end
end
end
end
end
device ref shared_ram on end
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
end
device ref i2c0 on
# Touchpad I2C bus
register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
chip drivers/i2c/hid
register "generic.hid" = ""PNP0C50""
register "generic.desc" = ""FocalTech Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B3)"
register "generic.probed" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 38 on end
end
end
device ref i2c1 on
#TODO: USB-PD?
register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
end
device ref heci1 on
#TODO Disable ME and HECI
register "HeciEnabled" = "1"
end
device ref uart2 on
# Debug console
register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
end
device ref sata on
# SATA1 (SSD0)
register "SataPortsEnable[1]" = "1"
register "SataPortsDevSlp[1]" = "1"
register "SataPortsEnableDitoConfig[1]" = "1"
register "SataSalpSupport" = "1"
end
device ref pcie_rp6 on
# PCIe root port #6 x1, Clock 2 (CARD)
register "PcieRpEnable[5]" = "1"
register "PcieRpLtrEnable[5]" = "1"
register "PcieClkSrcUsage[2]" = "5"
register "PcieClkSrcClkReq[2]" = "2"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_U4)" # GPIO_SDCARD_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D2)" # GPP_D2_SDCARD_RST#
register "srcclk_pin" = "2"
device generic 0 on end
end
end
device ref pcie_rp7 on
# PCIe root port #7 x1, Clock 3 (GLAN)
register "PcieRpEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
register "PcieClkSrcUsage[3]" = "6"
register "PcieClkSrcClkReq[3]" = "3"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # GPIO_LAN_EN
#TODO: should this be GPIO_LANRTD3 or LAN_PLT_RST# ?
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)" # LAN_PLT_RST#
register "srcclk_pin" = "3" # GLAN_CLKREQ#
device generic 0 on end
end
end
device ref pcie_rp8 on
# PCIe root port #8 x1, Clock 1 (WLAN)
register "PcieRpEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "1"
register "PcieClkSrcUsage[1]" = "7"
register "PcieClkSrcClkReq[1]" = "1"
end
device ref pcie_rp9 on
# PCIe root port #9 x4, Clock 4 (SSD0)
register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[4]" = "8"
register "PcieClkSrcClkReq[4]" = "4"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD_PWR_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3
register "srcclk_pin" = "4"
device generic 0 on end
end
end
device ref pch_espi on
# LPC configuration from lspci -s 1f.0 -xxx
# Address 0x84: Decode 0x80 - 0x8F (Port 80)
register "gen1_dec" = "0x000c0081"
# Address 0x88: Decode 0x68 - 0x6F (PMC)
register "gen2_dec" = "0x00040069"
# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
register "gen3_dec" = "0x00fc0E01"
# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
register "gen4_dec" = "0x00fc0F01"
# LPC TPM
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
end
device ref p2sb on end
device ref pmc hidden
# The pmc_mux chip driver is a placeholder for the
# PMC.MUX device in the ACPI hierarchy.
chip drivers/intel/pmc_mux
device generic 0 on
chip drivers/intel/pmc_mux/conn
# J_TYPEC2
register "usb2_port_number" = "6"
register "usb3_port_number" = "1"
# SBU & HSL follow CC
device generic 0 alias conn0 on end
end
end
end
end
device ref hda on
register "PchHdaAudioLinkHdaEnable" = "1"
end
device ref smbus on
register "SmbusEnable" = "1"
end
device ref fast_spi on end
end
end

41
src/mainboard/system76/darp7/dsdt.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
//TODO: cleaner solution for ACPI brightness
#define SYSTEM76_ACPI_NO_GFX0
#include <acpi/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20110725 // OEM revision
)
{
#include <soc/intel/common/block/acpi/acpi/platform.asl>
// global NVS and variables
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
// CPU
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)
{
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/tigerlake/acpi/southbridge.asl>
#include <soc/intel/tigerlake/acpi/tcss.asl>
}
}
Scope (\_SB.PCI0.LPCB) {
#include <drivers/pc80/pc/ps2_controller.asl>
}
#include <southbridge/intel/common/acpi/sleepstates.asl>
#include "acpi/mainboard.asl"
}

226
src/mainboard/system76/darp7/gpio.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H
#ifndef __ACPI__
#include <soc/gpe.h>
#include <soc/gpio.h>
/* Pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = {
// UART2_RXD
PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1),
// UART2_TXD
PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1),
};
/* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
PAD_CFG_GPI(GPD2, NONE, PWROK),
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
PAD_CFG_TERM_GPO(GPD7, 1, NONE, PWROK),
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
PAD_CFG_TERM_GPO(GPD9, 0, NONE, PWROK),
PAD_CFG_NF(GPD10, UP_20K, DEEP, NF1),
PAD_CFG_GPI(GPD11, UP_20K, DEEP),
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
PAD_NC(GPP_A7, NONE),
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2),
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3),
PAD_NC(GPP_A10, NONE),
PAD_NC(GPP_A11, NONE),
PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1),
PAD_CFG_TERM_GPO(GPP_A13, 1, NONE, PLTRST),
PAD_NC(GPP_A14, NONE),
PAD_NC(GPP_A15, NONE),
PAD_NC(GPP_A16, NONE),
PAD_NC(GPP_A17, NONE),
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
PAD_NC(GPP_A19, NONE),
PAD_NC(GPP_A20, NONE),
PAD_NC(GPP_A21, NONE),
PAD_NC(GPP_A22, NONE),
PAD_CFG_TERM_GPO(GPP_A23, 0, NONE, PLTRST),
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
PAD_CFG_GPI(GPP_B2, UP_20K, DEEP),
// GPP_B3 - touchpad interrupt
PAD_CFG_GPI_INT(GPP_B3, NONE, PLTRST, LEVEL),
PAD_NC(GPP_B4, NONE),
PAD_NC(GPP_B5, NONE),
PAD_NC(GPP_B6, NONE),
PAD_NC(GPP_B7, NONE),
PAD_CFG_TERM_GPO(GPP_B8, 1, NONE, DEEP),
PAD_NC(GPP_B9, NONE),
PAD_NC(GPP_B10, NONE),
PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1),
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
PAD_CFG_TERM_GPO(GPP_B14, 0, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_B15, 1, NONE, DEEP),
_PAD_CFG_STRUCT(GPP_B16, 0x44000301, 0x0000),
PAD_NC(GPP_B17, NONE),
PAD_NC(GPP_B18, NONE),
PAD_NC(GPP_B19, NONE),
PAD_NC(GPP_B20, NONE),
PAD_NC(GPP_B21, NONE),
PAD_NC(GPP_B22, NONE),
PAD_CFG_TERM_GPO(GPP_B23, 0, NONE, DEEP),
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
PAD_NC(GPP_C2, NONE),
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
PAD_NC(GPP_C5, NONE),
PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1),
PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1),
PAD_NC(GPP_C8, NONE),
PAD_NC(GPP_C9, NONE),
PAD_NC(GPP_C10, NONE),
PAD_NC(GPP_C11, NONE),
PAD_NC(GPP_C12, NONE),
PAD_NC(GPP_C13, NONE),
_PAD_CFG_STRUCT(GPP_C14, 0x40100100, 0x3000),
PAD_NC(GPP_C15, NONE),
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
// UART2_RXD
PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1),
// UART2_TXD
PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1),
PAD_CFG_TERM_GPO(GPP_C22, 1, NONE, PLTRST),
_PAD_CFG_STRUCT(GPP_C23, 0x40880100, 0x0000),
PAD_CFG_GPI(GPP_D0, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_D1, 1, NONE, PLTRST),
PAD_CFG_GPI(GPP_D2, NONE, PLTRST),
PAD_CFG_GPI(GPP_D3, NONE, PLTRST),
PAD_NC(GPP_D4, NONE),
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
PAD_NC(GPP_D9, NONE),
PAD_NC(GPP_D10, NONE),
PAD_CFG_GPI(GPP_D11, DN_20K, DEEP),
PAD_CFG_GPI(GPP_D12, DN_20K, DEEP),
PAD_CFG_TERM_GPO(GPP_D13, 1, NONE, PLTRST),
PAD_CFG_TERM_GPO(GPP_D14, 1, NONE, PLTRST),
PAD_NC(GPP_D15, NONE),
PAD_NC(GPP_D16, NONE),
PAD_NC(GPP_D17, NONE),
PAD_NC(GPP_D18, NONE),
PAD_NC(GPP_D19, NONE),
PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1),
PAD_CFG_TERM_GPO(GPP_E1, 0, NONE, PLTRST),
_PAD_CFG_STRUCT(GPP_E2, 0x40880100, 0x0000),
PAD_CFG_GPI(GPP_E3, DN_20K, DEEP),
PAD_NC(GPP_E4, NONE),
PAD_NC(GPP_E5, NONE),
PAD_NC(GPP_E6, NONE),
_PAD_CFG_STRUCT(GPP_E7, 0x82840100, 0x0000),
PAD_NC(GPP_E8, NONE),
PAD_NC(GPP_E9, NONE),
PAD_NC(GPP_E10, NONE),
PAD_NC(GPP_E11, NONE),
PAD_NC(GPP_E12, NONE),
PAD_NC(GPP_E13, NONE),
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
PAD_NC(GPP_E15, NONE),
PAD_CFG_GPI(GPP_E16, DN_20K, DEEP),
PAD_NC(GPP_E17, NONE),
// GPP_E18_TBT_LSX0_TXD - programmed by FSP, see Intel document 617016
PAD_NC(GPP_E18, NATIVE),
// GPP_E19_TBT_LSX0_RXD - programmed by FSP, see Intel document 617016
PAD_NC(GPP_E19, NATIVE),
PAD_NC(GPP_E20, NONE),
PAD_NC(GPP_E21, NONE),
PAD_NC(GPP_E22, NONE),
PAD_NC(GPP_E23, NONE),
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
PAD_NC(GPP_F4, NONE),
PAD_NC(GPP_F5, NONE),
PAD_NC(GPP_F6, NONE),
PAD_CFG_TERM_GPO(GPP_F7, 1, NONE, DEEP),
PAD_NC(GPP_F8, NONE),
PAD_CFG_TERM_GPO(GPP_F9, 1, NONE, DEEP),
PAD_NC(GPP_F10, NONE),
PAD_NC(GPP_F11, NONE),
PAD_NC(GPP_F12, NONE),
PAD_NC(GPP_F13, NONE),
PAD_NC(GPP_F14, NONE),
PAD_NC(GPP_F15, NONE),
PAD_NC(GPP_F16, NONE),
PAD_CFG_GPI(GPP_F17, NONE, PLTRST),
PAD_NC(GPP_F18, NONE),
PAD_NC(GPP_F19, NONE),
PAD_NC(GPP_F20, NONE),
PAD_CFG_GPI(GPP_F21, DN_20K, DEEP),
PAD_NC(GPP_F22, NONE),
PAD_NC(GPP_F23, NONE),
PAD_CFG_TERM_GPO(GPP_H0, 1, NONE, PLTRST),
PAD_NC(GPP_H1, NONE),
PAD_NC(GPP_H2, NONE),
PAD_CFG_GPI(GPP_H3, DN_20K, DEEP),
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
PAD_NC(GPP_H6, NONE),
PAD_NC(GPP_H7, NONE),
PAD_CFG_GPI(GPP_H8, DN_20K, DEEP),
PAD_CFG_GPI(GPP_H9, DN_20K, DEEP),
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
PAD_NC(GPP_H11, NONE),
PAD_NC(GPP_H12, NONE),
PAD_NC(GPP_H13, NONE),
PAD_NC(GPP_H14, NONE),
PAD_NC(GPP_H15, NONE),
PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
PAD_NC(GPP_H19, NONE),
PAD_NC(GPP_H20, NONE),
PAD_NC(GPP_H21, NONE),
PAD_NC(GPP_H22, NONE),
PAD_NC(GPP_H23, NONE),
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
PAD_NC(GPP_R5, NONE),
PAD_NC(GPP_R6, NONE),
PAD_NC(GPP_R7, NONE),
PAD_NC(GPP_S0, NONE),
PAD_NC(GPP_S1, NONE),
PAD_NC(GPP_S2, NONE),
PAD_NC(GPP_S3, NONE),
PAD_NC(GPP_S4, NONE),
PAD_NC(GPP_S5, NONE),
PAD_NC(GPP_S6, NONE),
PAD_NC(GPP_S7, NONE),
PAD_NC(GPP_T2, NONE),
PAD_NC(GPP_T3, NONE),
PAD_CFG_TERM_GPO(GPP_U4, 0, NONE, PLTRST),
PAD_CFG_TERM_GPO(GPP_U5, 1, NONE, PLTRST),
};
#endif
#endif

26
src/mainboard/system76/darp7/hda_verb.c Normal file
View File

@@ -0,0 +1,26 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* Realtek, ALC293 */
0x10ec0293, /* Vendor ID */
0x155851a1, /* Subsystem ID */
12, /* Number of entries */
AZALIA_SUBVENDOR(0, 0x155851a1),
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
AZALIA_PIN_CFG(0, 0x15, 0x02211020),
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1d, 0x40738205),
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
};
const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES;

18
src/mainboard/system76/darp7/ramstage.c Normal file
View File

@@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/ramstage.h>
#include "gpio.h"
void mainboard_silicon_init_params(FSP_S_CONFIG *params) {
// CPU RP Config
params->CpuPcieRpAdvancedErrorReporting[0] = 0;
params->CpuPcieRpLtrEnable[0] = 1;
params->CpuPcieRpPtmEnabled[0] = 0;
// IOM config
params->PchUsbOverCurrentEnable = 0;
params->PortResetMessageEnable[5] = 1; // J_TYPEC2
params->UsbTcPortEn = 1;
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}

35
src/mainboard/system76/darp7/romstage.c Normal file
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@@ -0,0 +1,35 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <fsp/util.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
static const struct mb_ddr4_cfg board_cfg = {
// dq_map unused on DDR4
// dqs_map unused on DDR4
// TGL-U does not support interleaved memory
.dq_pins_interleaved = 0,
//TODO: can we use early command training?
.ect = 0,
};
static const struct spd_info spd = {
.topology = SODIMM,
.smbus_info[0] = {
.addr_dimm0 = 0x50,
},
.smbus_info[1] = {
.addr_dimm0 = 0x52,
},
};
void mainboard_memory_init_params(FSPM_UPD *mupd) {
//TODO: Allow memory clocks higher than 2933 MHz
mupd->FspmConfig.SaOcSupport = 1;
//TODO: what is this for?
const bool half_populated = false;
meminit_ddr4(&mupd->FspmConfig, &board_cfg, &spd, half_populated);
}

4
src/mainboard/system76/galp5/devicetree.cb
View File

@@ -177,9 +177,9 @@ chip soc/intel/tigerlake
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
# USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_2
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 Channel 0
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH0
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_1
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 Channel 0
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH1
# ACPI
chip drivers/usb/acpi
device ref xhci_root_hub on