arch/riscv: Remove typedefs

typedefs violate our coding-style

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Id51eda53b6b53ed2cc66c0339c03c855c12c1bd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81124
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>

src/arch/riscv/include/arch/exception.h

@@ -5,29 +5,29 @@
 
 #include <stdint.h>
 
-typedef struct {
+struct trapframe {
 	uintptr_t gpr[32];
 	uintptr_t status;
 	uintptr_t epc;
 	uintptr_t badvaddr;
 	uintptr_t cause;
 	uintptr_t insn;
-} trapframe;
+};
 
 typedef uint32_t insn_t;
 
-typedef struct {
+struct insn_fetch {
 	uintptr_t error;
 	insn_t insn;
-} insn_fetch_t;
+};
 
 static inline void exception_init(void)
 {
 }
 
 void redirect_trap(void);
-void default_trap_handler(trapframe *tf);
-void handle_supervisor_call(trapframe *tf);
-void handle_misaligned(trapframe *tf);
+void default_trap_handler(struct trapframe *tf);
+void handle_supervisor_call(struct trapframe *tf);
+void handle_misaligned(struct trapframe *tf);
 
 #endif

src/arch/riscv/include/mcall.h

@@ -3,7 +3,7 @@
 #ifndef _MCALL_H
 #define _MCALL_H
 
-// NOTE: this is the size of hls_t below. A static_assert would be
+// NOTE: this is the size of struct hls below. A static_assert would be
 // nice to have.
 #if __riscv_xlen == 64
 #define HLS_SIZE 88
@@ -22,12 +22,12 @@
 #include <arch/smp/atomic.h>
 #include <stdint.h>
 
-typedef struct {
+struct sbi_device_message {
 	unsigned long dev;
 	unsigned long cmd;
 	unsigned long data;
 	unsigned long sbi_private_data;
-} sbi_device_message;
+};
 
 struct blocker {
 	void *arg;
@@ -36,11 +36,11 @@ struct blocker {
 	atomic_t sync_b;
 };
 
-typedef struct {
-	sbi_device_message *device_request_queue_head;
+struct hls {
+	struct sbi_device_message *device_request_queue_head;
 	unsigned long device_request_queue_size;
-	sbi_device_message *device_response_queue_head;
-	sbi_device_message *device_response_queue_tail;
+	struct sbi_device_message *device_response_queue_head;
+	struct sbi_device_message *device_response_queue_tail;
 
 	int hart_id;
 	int ipi_pending;
@@ -48,11 +48,11 @@ typedef struct {
 	uint64_t *time;
 	void *fdt;
 	struct blocker entry;
-} hls_t;
+};
 
 _Static_assert(
-	sizeof(hls_t) == HLS_SIZE,
-	"HLS_SIZE must equal to sizeof(hls_t)");
+	sizeof(struct hls) == HLS_SIZE,
+	"HLS_SIZE must equal to sizeof(struct hls)");
 
 register uintptr_t current_stack_pointer asm("sp");
 
@@ -60,8 +60,8 @@ register uintptr_t current_stack_pointer asm("sp");
 	(void *)((current_stack_pointer + RISCV_PGSIZE) & -RISCV_PGSIZE); })
 
 // hart-local storage, at top of stack
-#define HLS() ((hls_t*)(MACHINE_STACK_TOP() - HLS_SIZE))
-#define OTHER_HLS(id) ((hls_t*)((void*)HLS() + RISCV_PGSIZE * ((id) - HLS()->hart_id)))
+#define HLS() ((struct hls *)(MACHINE_STACK_TOP() - HLS_SIZE))
+#define OTHER_HLS(id) ((struct hls *)((void *)HLS() + RISCV_PGSIZE * ((id) - HLS()->hart_id)))
 
 #define MACHINE_STACK_SIZE RISCV_PGSIZE
 

src/arch/riscv/include/sbi.h

@@ -21,6 +21,6 @@
 #define IPI_SFENCE_VMA_ASID 8
 #define IPI_SHUTDOWN        16
 
-void handle_sbi(trapframe *tf);
+void handle_sbi(struct trapframe *tf);
 
 #endif /* RISCV_SBI_H */

src/arch/riscv/misaligned.c

@@ -156,7 +156,7 @@ static enum cb_err fetch_32bit_instruction(uintptr_t vaddr, uintptr_t *insn, int
 	return CB_ERR;
 }
 
-void handle_misaligned(trapframe *tf)
+void handle_misaligned(struct trapframe *tf)
 {
 	uintptr_t insn = 0;
 	union endian_buf buff;

src/arch/riscv/pmp.c

@@ -12,7 +12,7 @@
  * This structure is used to temporarily record PMP
  * configuration information.
  */
-typedef struct {
+struct pmpcfg {
 	/* used to record the value of pmpcfg[i] */
 	uintptr_t cfg;
 	/*
@@ -23,7 +23,7 @@ typedef struct {
 	uintptr_t previous_address;
 	/* used to record the value of pmpaddr[i] */
 	uintptr_t address;
-} pmpcfg_t;
+};
 
 /* This variable is used to record which entries have been used. */
 static uintptr_t pmp_entry_used_mask;
@@ -207,10 +207,10 @@ static void write_pmpaddr(int idx, uintptr_t val)
 }
 
 /* Generate a PMP configuration of type NA4/NAPOT */
-static pmpcfg_t generate_pmp_napot(
+static struct pmpcfg generate_pmp_napot(
 		uintptr_t base, uintptr_t size, uintptr_t flags)
 {
-	pmpcfg_t p;
+	struct pmpcfg p;
 	flags = flags & (PMP_R | PMP_W | PMP_X | PMP_L);
 	p.cfg = flags | (size > GRANULE ? PMP_NAPOT : PMP_NA4);
 	p.previous_address = 0;
@@ -219,10 +219,10 @@ static pmpcfg_t generate_pmp_napot(
 }
 
 /* Generate a PMP configuration of type TOR */
-static pmpcfg_t generate_pmp_range(
+static struct pmpcfg generate_pmp_range(
 		uintptr_t base, uintptr_t size, uintptr_t flags)
 {
-	pmpcfg_t p;
+	struct pmpcfg p;
 	flags = flags & (PMP_R | PMP_W | PMP_X | PMP_L);
 	p.cfg = flags | PMP_TOR;
 	p.previous_address = base >> PMP_SHIFT;
@@ -231,7 +231,7 @@ static pmpcfg_t generate_pmp_range(
 }
 
 /* Generate a PMP configuration */
-static pmpcfg_t generate_pmp(uintptr_t base, uintptr_t size, uintptr_t flags)
+static struct pmpcfg generate_pmp(uintptr_t base, uintptr_t size, uintptr_t flags)
 {
 	if (IS_POWER_OF_2(size) && (size >= 4) && ((base & (size - 1)) == 0))
 		return generate_pmp_napot(base, size, flags);
@@ -289,7 +289,7 @@ void reset_pmp(void)
 /* set up PMP record */
 void setup_pmp(uintptr_t base, uintptr_t size, uintptr_t flags)
 {
-	pmpcfg_t p;
+	struct pmpcfg p;
 	int is_range, n;
 
 	p = generate_pmp(base, size, flags);

src/arch/riscv/ramdetect.c

@@ -13,7 +13,7 @@ static enum {
 	ABORT_CHECKER_TRIGGERED,
 } abort_state = ABORT_CHECKER_NOT_TRIGGERED;
 
-extern void (*trap_handler)(trapframe *tf);
+extern void (*trap_handler)(struct trapframe *tf);
 
 static int get_instruction_len(uintptr_t addr)
 {
@@ -31,7 +31,7 @@ static int get_instruction_len(uintptr_t addr)
 	die("Not a 16bit or 32bit instruction 0x%x\n", ins);
 }
 
-static void ramcheck_trap_handler(trapframe *tf)
+static void ramcheck_trap_handler(struct trapframe *tf)
 {
 	abort_state = ABORT_CHECKER_TRIGGERED;
 

src/arch/riscv/sbi.c

@@ -55,7 +55,7 @@ static uintptr_t sbi_clear_ipi(void)
  * function  : register a7
  * return    : register a0
  */
-void handle_sbi(trapframe *tf)
+void handle_sbi(struct trapframe *tf)
 {
 	uintptr_t ret = 0;
 	uintptr_t arg0 = tf->gpr[10];

src/arch/riscv/trap_handler.c

@@ -46,7 +46,7 @@ static const char *mstatus_to_previous_mode(uintptr_t ms)
 	return "unknown";
 }
 
-static void print_trap_information(const trapframe *tf)
+static void print_trap_information(const struct trapframe *tf)
 {
 	const char *previous_mode;
 	bool mprv = !!(tf->status & MSTATUS_MPRV);
@@ -69,7 +69,7 @@ static void print_trap_information(const trapframe *tf)
 	printk(BIOS_DEBUG, "Stored sp:          %p\n", (void *)tf->gpr[2]);
 }
 
-static void interrupt_handler(trapframe *tf)
+static void interrupt_handler(struct trapframe *tf)
 {
 	uint64_t cause = tf->cause & ~0x8000000000000000ULL;
 
@@ -109,9 +109,9 @@ static void interrupt_handler(trapframe *tf)
 	}
 }
 
-void (*trap_handler)(trapframe *tf) = default_trap_handler;
+void (*trap_handler)(struct trapframe *tf) = default_trap_handler;
 
-void default_trap_handler(trapframe *tf)
+void default_trap_handler(struct trapframe *tf)
 {
 	if (tf->cause & 0x8000000000000000ULL) {
 		interrupt_handler(tf);