soc/intel/alderlake: Drop unused PrmrrSize from devicetree

The `PrmrrSize` FSP-M UPD is set using `get_valid_prmrr_size()`. As the
devicetree option's value is not used anywhere, drop it.

Change-Id: Ib6fb77b03a4648adbd8b23c160cfba94d142a2d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>

src/mainboard/intel/adlrvp/devicetree.cb

@@ -52,8 +52,6 @@ chip soc/intel/alderlake
 	register "gpio_pm[COMM_4]" = "0"
 	register "gpio_pm[COMM_5]" = "0"
 
-	register "PrmrrSize" = "0"
-
 	# Enable PCH PCIE RP 5 using CLK 2
 	register "pch_pcie_rp[PCH_RP(5)]" = "{
 		.clk_src = 2,

src/mainboard/intel/adlrvp/devicetree_m.cb

@@ -35,8 +35,6 @@ chip soc/intel/alderlake
 	# EC memory map range is 0x900-0x9ff
 	register "gen3_dec" = "0x00fc0901"
 
-	register "PrmrrSize" = "0"
-
 	#Enable PCH PCIE RP 4 using CLK 5
 	register "pch_pcie_rp[PCH_RP(4)]" = "{
 		.clk_src = 5,

src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb

@@ -47,7 +47,6 @@ chip soc/intel/alderlake
 	register "gen2_dec" = "0x000c0201"
 	# EC memory map range is 0x900-0x9ff
 	register "gen3_dec" = "0x00fc0901"
-	register "PrmrrSize" = "0"
 
 	# Enable PCH PCIE RP 5 using CLK 1
 	register "pch_pcie_rp[PCH_RP(5)]" = "{

src/soc/intel/alderlake/chip.h

@@ -165,16 +165,6 @@ struct soc_intel_alderlake_config {
 
 	/* Enable C6 DRAM */
 	uint8_t enable_c6dram;
-	/*
-	 * PRMRR size setting with below options
-	 * Disable: 0x0
-	 * 32MB: 0x2000000
-	 * 64MB: 0x4000000
-	 * 128 MB: 0x8000000
-	 * 256 MB: 0x10000000
-	 * 512 MB: 0x20000000
-	 */
-	uint32_t PrmrrSize;
 	uint8_t PmTimerDisabled;
 	/*
 	 * SerialIO device mode selection: