soc/intel/alderlake: Drop unused PrmrrSize from devicetree

The `PrmrrSize` FSP-M UPD is set using `get_valid_prmrr_size()`. As the
devicetree option's value is not used anywhere, drop it.

Change-Id: Ib6fb77b03a4648adbd8b23c160cfba94d142a2d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Angel Pons
2021-04-05 13:05:54 +02:00
parent 0c0d49229d
commit 5d13e7fdcd
4 changed files with 0 additions and 15 deletions

View File

@@ -35,8 +35,6 @@ chip soc/intel/alderlake
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
register "PrmrrSize" = "0"
#Enable PCH PCIE RP 4 using CLK 5
register "pch_pcie_rp[PCH_RP(4)]" = "{
.clk_src = 5,