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Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX)

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This patch cleans up remaining uses of raw boolean Kconfig values I
could find by wrapping them with CONFIG(). The remaining naked config
value warnings in the code should all be false positives now (although
the process was semi-manual and involved some eyeballing so I may have
missed a few).

Change-Id: Ifa0573a535addc3354a74e944c0920befb0666be
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Julius Werner
2019-03-07 17:07:26 -08:00
committed by Patrick Georgi
parent 2de19038be
commit 5d1f9a0096
31 changed files with 51 additions and 51 deletions
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2
src/southbridge/amd/cimx/sb800/cfg.c
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@@ -101,7 +101,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
#endif
/* LPC */
/* SuperIO hardware monitor register access */
sb_config->SioHwmPortEnable = CONFIG_SB_SUPERIO_HWM;
sb_config->SioHwmPortEnable = CONFIG(SB_SUPERIO_HWM);
/*
* GPP. default configure only enable port0 with 4 lanes,

2
src/southbridge/amd/cimx/sb900/early.c
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@@ -40,7 +40,7 @@ void sb_poweron_init(void)
outb(0xEA, 0xCD6);
data = inb(0xCD7);
data &= !BIT0;
if (!CONFIG_PCIB_ENABLE) {
if (!CONFIG(PCIB_ENABLE)) {
data |= BIT0;
}
outb(data, 0xCD7);

2
src/southbridge/intel/bd82x6x/lpc.c
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@@ -418,7 +418,7 @@ static void enable_clock_gating(struct device *dev)
static void pch_set_acpi_mode(void)
{
if (!acpi_is_wakeup_s3() && CONFIG_HAVE_SMI_HANDLER) {
if (!acpi_is_wakeup_s3() && CONFIG(HAVE_SMI_HANDLER)) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode

2
src/southbridge/intel/ibexpeak/lpc.c
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@@ -433,7 +433,7 @@ static void enable_clock_gating(struct device *dev)
static void pch_set_acpi_mode(void)
{
if (!acpi_is_wakeup_s3() && CONFIG_HAVE_SMI_HANDLER) {
if (!acpi_is_wakeup_s3() && CONFIG(HAVE_SMI_HANDLER)) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode

2
src/southbridge/nvidia/ck804/ck804.h
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@@ -24,7 +24,7 @@
#endif
#define CK804B_BUSN 0x80
#define CK804B_DEVN_BASE (!CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY ? CK804_DEVN_BASE : 1)
#define CK804B_DEVN_BASE (!CONFIG(SB_HT_CHAIN_UNITID_OFFSET_ONLY) ? CK804_DEVN_BASE : 1)
#ifdef __PRE_RAM__
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);