drop quite a lot of dead code that did nothing but produce warnings and make
the rest of the code unreadable. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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committed by
Stefan Reinauer
parent
4154c668f2
commit
5d3dee8334
@@ -1,97 +0,0 @@
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#ifndef AMD_EARLYMTRR_C
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#define AMD_EARLYMTRR_C
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/mtrr.h>
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#include "cpu/x86/mtrr/earlymtrr.c"
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/* the fixed and variable MTTRs are power-up with random values,
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* clear them to MTRR_TYPE_UNCACHEABLE for safty.
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*/
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static void do_amd_early_mtrr_init(const unsigned long *mtrr_msrs)
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{
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/* Precondition:
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* The cache is not enabled in cr0 nor in MTRRdefType_MSR
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* entry32.inc ensures the cache is not enabled in cr0
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*/
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msr_t msr;
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const unsigned long *msr_addr;
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#if 0
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/* Enable the access to AMD RdDram and WrDram extension bits */
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msr = rdmsr(SYSCFG_MSR);
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msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
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wrmsr(SYSCFG_MSR, msr);
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#endif
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/* Inialize all of the relevant msrs to 0 */
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msr.lo = 0;
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msr.hi = 0;
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unsigned long msr_nr;
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for(msr_addr = mtrr_msrs; (msr_nr = *msr_addr); msr_addr++) {
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wrmsr(msr_nr, msr);
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}
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#if 0
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/* Disable the access to AMD RdDram and WrDram extension bits */
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msr = rdmsr(SYSCFG_MSR);
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msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
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wrmsr(SYSCFG_MSR, msr);
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#endif
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/* Enable memory access for 0 - 1MB using top_mem */
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msr.hi = 0;
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msr.lo = (((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK);
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wrmsr(TOP_MEM, msr);
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#if defined(CONFIG_XIP_ROM_SIZE)
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/* enable write through caching so we can do execute in place
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* on the flash rom.
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*/
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set_var_mtrr(1, REAL_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
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#endif
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/* Set the default memory type and enable fixed and variable MTRRs
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*/
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/* Enable Variable MTRRs */
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msr.hi = 0x00000000;
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msr.lo = 0x00000800;
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wrmsr(MTRRdefType_MSR, msr);
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/* Enable the MTRRs in SYSCFG */
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msr = rdmsr(SYSCFG_MSR);
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msr.lo |= SYSCFG_MSR_MtrrVarDramEn;
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wrmsr(SYSCFG_MSR, msr);
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}
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static void amd_early_mtrr_init(void)
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{
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static const unsigned long mtrr_msrs[] = {
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/* fixed mtrr */
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0x250, 0x258, 0x259,
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0x268, 0x269, 0x26A,
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0x26B, 0x26C, 0x26D,
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0x26E, 0x26F,
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/* var mtrr */
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0x200, 0x201, 0x202, 0x203,
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0x204, 0x205, 0x206, 0x207,
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0x208, 0x209, 0x20A, 0x20B,
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0x20C, 0x20D, 0x20E, 0x20F,
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/* var iorr */
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0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019,
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/* mem top */
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0xC001001A, 0xC001001D,
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/* NULL end of table */
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0
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};
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/* wbinvd which is called in disable_cache() causes hangs on Opterons
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* if there is no data in the cache.
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* At this point we should not have the cache enabled so don't bother
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* disabling it.
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*/
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/* disable_cache(); */
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do_amd_early_mtrr_init(mtrr_msrs);
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enable_cache();
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}
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#endif /* AMD_EARLYMTRR_C */
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@@ -2,6 +2,7 @@
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#define EARLYMTRR_C
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#include <cpu/x86/cache.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/mtrr.h>
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#include <cpu/x86/msr.h>
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#if 0
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