mb/google/guybrush: Enable ACPI tables
BUG=b:180419454 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I1e724e78b5ef378d474063417aa2b7e57a00886f Reviewed-on: https://review.coreboot.org/c/coreboot/+/50814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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committed by
Patrick Georgi
parent
40f53f4b87
commit
5d47887965
@@ -1,5 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <boot/coreboot_tables.h>
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#include <boot/coreboot_tables.h>
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#include <gpio.h>
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#include <gpio.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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@@ -12,3 +13,13 @@ void fill_lb_gpios(struct lb_gpios *gpios)
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};
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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}
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static const struct cros_gpio cros_gpios[] = {
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CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME),
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CROS_GPIO_WP_AL(CROS_WP_GPIO, GPIO_DEVICE_NAME),
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};
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void mainboard_chromeos_acpi_generate(void)
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{
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chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
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}
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@@ -2,6 +2,7 @@
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#include <baseboard/variants.h>
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#include <baseboard/variants.h>
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#include <device/device.h>
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#include <device/device.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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static void mainboard_configure_gpios(void)
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static void mainboard_configure_gpios(void)
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{
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{
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@@ -22,7 +23,9 @@ static void mainboard_init(void *chip_info)
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static void mainboard_enable(struct device *dev)
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static void mainboard_enable(struct device *dev)
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{
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{
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/* TODO: Enable mainboard */
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printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
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dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
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}
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}
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struct chip_operations mainboard_ops = {
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struct chip_operations mainboard_ops = {
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@@ -3,4 +3,7 @@
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#ifndef __BASEBOARD_GPIO_H__
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#ifndef __BASEBOARD_GPIO_H__
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#define __BASEBOARD_GPIO_H__
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#define __BASEBOARD_GPIO_H__
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/* SPI Write protect */
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#define CROS_WP_GPIO GPIO_67
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#endif /* __BASEBOARD_GPIO_H__ */
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#endif /* __BASEBOARD_GPIO_H__ */
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